mirror of
https://github.com/holub/mame
synced 2025-04-19 15:11:37 +03:00
added new 7200 FIFO chip device
This commit is contained in:
Michaël Banaan Ananas
parent
c36db85b5d
commit
552d0d0fc2
2
.gitattributes
vendored
2
.gitattributes
vendored
@ -1148,6 +1148,8 @@ src/emu/machine/6850acia.c svneol=native#text/plain
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src/emu/machine/6850acia.h svneol=native#text/plain
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src/emu/machine/68681.c svneol=native#text/plain
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src/emu/machine/68681.h svneol=native#text/plain
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src/emu/machine/7200fifo.c svneol=native#text/plain
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src/emu/machine/7200fifo.h svneol=native#text/plain
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src/emu/machine/74123.c svneol=native#text/plain
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src/emu/machine/74123.h svneol=native#text/plain
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src/emu/machine/74145.c svneol=native#text/plain
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@ -152,6 +152,7 @@ EMUMACHINEOBJS = \
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$(EMUMACHINE)/6840ptm.o \
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$(EMUMACHINE)/6850acia.o \
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$(EMUMACHINE)/68681.o \
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$(EMUMACHINE)/7200fifo.o \
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$(EMUMACHINE)/74123.o \
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$(EMUMACHINE)/74145.o \
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$(EMUMACHINE)/74148.o \
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130
src/emu/machine/7200fifo.c
Normal file
130
src/emu/machine/7200fifo.c
Normal file
@ -0,0 +1,130 @@
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/**********************************************************************
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IDT7200 series 9-bit Asynchronous FIFO Emulation
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TODO:
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- retransmit (RT pin)
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**********************************************************************/
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#include "emu.h"
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#include "machine/7200fifo.h"
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const device_type FIFO7200 = &device_creator<fifo7200_device>;
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//-------------------------------------------------
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// fifo7200_device - constructor
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//-------------------------------------------------
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fifo7200_device::fifo7200_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
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: device_t(mconfig, FIFO7200, "IDT7200 Asynchronous FIFO", tag, owner, clock),
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m_ram_size(0),
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m_ef_handler(*this),
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m_ff_handler(*this),
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m_hf_handler(*this)
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{
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}
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//-------------------------------------------------
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// device_start - device-specific startup
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//-------------------------------------------------
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void fifo7200_device::device_start()
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{
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assert(m_ram_size > 1 && ~m_ram_size & 1);
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m_buffer = auto_alloc_array(machine(), UINT16, m_ram_size);
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// resolve callbacks
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m_ef_handler.resolve();
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m_ff_handler.resolve();
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m_hf_handler.resolve();
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// state save
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save_item(NAME(m_read_ptr));
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save_item(NAME(m_write_ptr));
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save_item(NAME(m_ef));
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save_item(NAME(m_ff));
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save_item(NAME(m_hf));
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}
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//-------------------------------------------------
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// device_reset - device-specific reset
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//-------------------------------------------------
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void fifo7200_device::device_reset()
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{
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// master reset
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memset(m_buffer, 0, m_ram_size * sizeof(UINT16));
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m_read_ptr = 0;
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m_write_ptr = 0;
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m_ef = 1;
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m_ff = 0;
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m_hf = 0;
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if (!m_ef_handler.isnull()) m_ef_handler(m_ef);
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if (!m_ff_handler.isnull()) m_ff_handler(m_ff);
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if (!m_hf_handler.isnull()) m_hf_handler(m_hf);
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}
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void fifo7200_device::fifo_write(UINT32 data)
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{
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if (m_ff)
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return;
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m_buffer[m_write_ptr] = data;
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m_write_ptr = (m_write_ptr + 1) % m_ram_size;
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// update flags
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if (m_ef)
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{
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m_ef = 0;
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if (!m_ef_handler.isnull()) m_ef_handler(m_ef);
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}
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else if (m_read_ptr == m_write_ptr)
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{
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m_ff = 1;
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if (!m_ff_handler.isnull()) m_ff_handler(m_ff);
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}
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else if (((m_read_ptr + 1 + m_ram_size / 2) % m_ram_size) == m_write_ptr)
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{
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m_hf = 1;
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if (!m_hf_handler.isnull()) m_hf_handler(m_hf);
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}
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}
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UINT32 fifo7200_device::fifo_read()
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{
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if (m_ef)
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return ~0;
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UINT16 ret = m_buffer[m_read_ptr];
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m_read_ptr = (m_read_ptr + 1) % m_ram_size;
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// update flags
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if (m_ff)
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{
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m_ff = 0;
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if (!m_ff_handler.isnull()) m_ff_handler(m_ff);
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}
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else if (m_read_ptr == m_write_ptr)
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{
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m_ef = 1;
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if (!m_ef_handler.isnull()) m_ef_handler(m_ef);
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}
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else if (((m_read_ptr + m_ram_size / 2) % m_ram_size) == m_write_ptr)
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{
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m_hf = 0;
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if (!m_hf_handler.isnull()) m_hf_handler(m_hf);
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}
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return ret;
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}
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137
src/emu/machine/7200fifo.h
Normal file
137
src/emu/machine/7200fifo.h
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@ -0,0 +1,137 @@
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/**********************************************************************
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IDT7200 series 9-bit Asynchronous FIFO Emulation
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Copyright MAME Team.
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Visit http://mamedev.org for licensing and usage restrictions.
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**********************************************************************
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_____ _____
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_W 1 |* \_/ | 28 Vcc
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D8 2 | | 27 D4
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D3 3 | | 26 D5
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D2 4 | | 25 D6
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D1 5 | | 24 D7
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D0 6 | | 23 _FL/_RT
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_XI 7 | 7200 | 22 _MR
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_FF 8 | | 21 _EF
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Q0 9 | | 20 _XO/_HF
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Q1 10 | | 19 Q7
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Q2 11 | | 18 Q6
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Q3 12 | | 17 Q5
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Q8 13 | | 16 Q4
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GND 14 |_____________| 15 _R
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Known chips and buffer sizes are listed below. Note that in width or depth
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expansion mode (using more than one chip and XO/XI), it may be increased more.
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256x9 512x9 1Kx9 2Kx9 4Kx9 8Kx9 16Kx9 32Kx9 64Kx9
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-------------------------------------------------------------------------------------------
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IDT7200 IDT7201 IDT7202 IDT7203 IDT7204 IDT7205 IDT7206 IDT7207 IDT7208
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The following chips are functionally equivalent and pin-compatible.
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AM7200 AM7201 AM7202 AM7203 AM7204
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MS7200 MS7201 MS7202 MS7203 MS7204
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LH5495 LH5496 LH5497 LH5498 LH5499
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LH540201 LH540202 LH540203 LH540204 LH540205 LH540206
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CY7C419 CY7C420 CY7C424 CY7C428 CY7C432
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CY7C421 CY7C425 CY7C429 CY7C433
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32-pin PLCC/LCC or TQFP configurations are also available.
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**********************************************************************/
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#pragma once
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#ifndef _7200FIFO_H
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#define _7200FIFO_H
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#include "emu.h"
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//**************************************************************************
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// INTERFACE CONFIGURATION MACROS
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//**************************************************************************
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#define MCFG_FIFO7200_ADD(_tag, _ramsize) \
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MCFG_DEVICE_ADD(_tag, FIFO7200, 0) \
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fifo7200_device::set_ram_size(*device, _ramsize);
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#define MCFG_FIFO7200_EF_HANDLER(_devcb) \
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devcb = &fifo7200_device::set_ef_handler(*device, DEVCB2_##_devcb);
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#define MCFG_FIFO7200_FF_HANDLER(_devcb) \
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devcb = &fifo7200_device::set_ff_handler(*device, DEVCB2_##_devcb);
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#define MCFG_FIFO7200_HF_HANDLER(_devcb) \
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devcb = &fifo7200_device::set_hf_handler(*device, DEVCB2_##_devcb);
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//**************************************************************************
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// TYPE DEFINITIONS
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//**************************************************************************
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// ======================> fifo7200_device
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class fifo7200_device : public device_t
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{
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public:
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fifo7200_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
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// static configuration helpers
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template<class _Object> static devcb2_base &set_ef_handler(device_t &device, _Object object) { return downcast<fifo7200_device &>(device).m_ef_handler.set_callback(object); }
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template<class _Object> static devcb2_base &set_ff_handler(device_t &device, _Object object) { return downcast<fifo7200_device &>(device).m_ff_handler.set_callback(object); }
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template<class _Object> static devcb2_base &set_hf_handler(device_t &device, _Object object) { return downcast<fifo7200_device &>(device).m_hf_handler.set_callback(object); }
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static void set_ram_size(device_t &device, int size) { downcast<fifo7200_device &>(device).m_ram_size = size; }
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DECLARE_READ_LINE_MEMBER( ef_r ) { return m_ef; }
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DECLARE_READ_LINE_MEMBER( ff_r ) { return m_ff; }
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DECLARE_READ_LINE_MEMBER( hf_r ) { return m_hf; }
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// normal configuration
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DECLARE_WRITE16_MEMBER( data_word_w ) { fifo_write(data); }
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DECLARE_READ16_MEMBER( data_word_r ) { return (UINT16)fifo_read(); }
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// use these for simple configurations that don't have d8/q8 connected
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DECLARE_WRITE8_MEMBER( data_byte_w ) { fifo_write(data); }
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DECLARE_READ8_MEMBER( data_byte_r ) { return (UINT8)fifo_read(); }
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// use these for configurations in cascaded width expansion mode using more than 16 bits
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DECLARE_WRITE32_MEMBER( data_dword_w ) { fifo_write(data); }
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DECLARE_READ32_MEMBER( data_dword_r ) { return (UINT16)fifo_read(); }
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protected:
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// device-level overrides
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virtual void device_start();
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virtual void device_reset();
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private:
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void fifo_write(UINT32 data);
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UINT32 fifo_read();
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UINT16* m_buffer;
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int m_ram_size;
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int m_read_ptr;
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int m_write_ptr;
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int m_ef; // empty flag
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int m_ff; // full flag
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int m_hf; // half-full flag
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devcb2_write_line m_ef_handler;
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devcb2_write_line m_ff_handler;
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devcb2_write_line m_hf_handler;
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};
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// device type definition
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extern const device_type FIFO7200;
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#endif /* _7200FIFO_H */
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@ -16,6 +16,7 @@
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#include "machine/at28c16.h"
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#include "machine/nvram.h"
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#include "machine/mb3773.h"
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#include "machine/7200fifo.h"
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#include "machine/znsec.h"
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#include "machine/zndip.h"
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#include "machine/idectrl.h"
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@ -40,7 +41,9 @@ public:
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m_zndip(*this,"maincpu:sio0:zndip"),
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m_maincpu(*this, "maincpu"),
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m_audiocpu(*this, "audiocpu"),
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m_ram(*this, "maincpu:ram")
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m_ram(*this, "maincpu:ram"),
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m_cbaj_fifo1(*this, "cbaj_fifo1"),
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m_cbaj_fifo2(*this, "cbaj_fifo2")
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{
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}
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@ -75,12 +78,8 @@ public:
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DECLARE_WRITE_LINE_MEMBER(coh1001l_ymz_irq);
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DECLARE_WRITE8_MEMBER(coh1002v_bank_w);
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DECLARE_WRITE8_MEMBER(coh1002m_bank_w);
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DECLARE_READ8_MEMBER(cbaj_from_z80_latch_r);
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DECLARE_WRITE8_MEMBER(cbaj_to_z80_latch_w);
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DECLARE_READ8_MEMBER(cbaj_from_z80_status_r);
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DECLARE_READ8_MEMBER(cbaj_to_z80_latch_r);
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DECLARE_WRITE8_MEMBER(cbaj_from_z80_latch_w);
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DECLARE_READ8_MEMBER(cbaj_to_z80_status_r);
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DECLARE_READ8_MEMBER(cbaj_sound_main_status_r);
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DECLARE_READ8_MEMBER(cbaj_sound_z80_status_r);
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DECLARE_READ8_MEMBER(jdredd_idestat_r);
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DECLARE_READ16_MEMBER(jdredd_ide_r);
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DECLARE_WRITE16_MEMBER(jdredd_ide_w);
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@ -97,7 +96,6 @@ public:
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DECLARE_MACHINE_RESET(coh1001l);
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DECLARE_MACHINE_RESET(coh1002v);
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DECLARE_MACHINE_RESET(coh1002m);
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DECLARE_MACHINE_RESET(coh1002msnd);
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DECLARE_WRITE_LINE_MEMBER(irqhandler);
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INTERRUPT_GEN_MEMBER(qsound_interrupt);
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void atpsx_dma_read(UINT32 *p_n_psxram, UINT32 n_address, INT32 n_size );
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@ -120,10 +118,6 @@ private:
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size_t m_nbajamex_eeprom_size;
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UINT8 *m_nbajamex_eeprom;
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UINT8 m_cbaj_fifo_buffer[2][0x400];
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int m_cbaj_fifo_main_ptr[2];
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int m_cbaj_fifo_z80_ptr[2];
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required_device<psxgpu_device> m_gpu;
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required_device<znsec_device> m_znsec0;
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required_device<znsec_device> m_znsec1;
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@ -131,6 +125,8 @@ private:
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required_device<cpu_device> m_maincpu;
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optional_device<cpu_device> m_audiocpu;
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required_device<ram_device> m_ram;
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optional_device<fifo7200_device> m_cbaj_fifo1;
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optional_device<fifo7200_device> m_cbaj_fifo2;
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};
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inline void ATTR_PRINTF(3,4) zn_state::verboselog( int n_level, const char *s_fmt, ... )
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@ -2422,47 +2418,23 @@ static MACHINE_CONFIG_DERIVED( coh1002m, zn1_2mb_vram )
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MCFG_MACHINE_RESET_OVERRIDE(zn_state, coh1002m)
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MACHINE_CONFIG_END
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READ8_MEMBER(zn_state::cbaj_from_z80_latch_r)
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READ8_MEMBER(zn_state::cbaj_sound_main_status_r)
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{
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UINT8 ret = m_cbaj_fifo_buffer[1][m_cbaj_fifo_main_ptr[1]];
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m_cbaj_fifo_main_ptr[1] = (m_cbaj_fifo_main_ptr[1] + 1) & 0x3ff;
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return ret;
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}
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WRITE8_MEMBER(zn_state::cbaj_to_z80_latch_w)
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{
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m_cbaj_fifo_buffer[0][m_cbaj_fifo_main_ptr[0]] = data;
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m_cbaj_fifo_main_ptr[0] = (m_cbaj_fifo_main_ptr[0] + 1) & 0x3ff;
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}
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READ8_MEMBER(zn_state::cbaj_from_z80_status_r)
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{
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return (m_cbaj_fifo_main_ptr[1] != m_cbaj_fifo_z80_ptr[1]) ? 0x02 : 0x00;
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// d1: fifo empty flag, other bits: unused(?)
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return ~(m_cbaj_fifo2->ef_r() << 1);
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}
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static ADDRESS_MAP_START(coh1002msnd_map, AS_PROGRAM, 32, zn_state)
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AM_RANGE(0x1fb00000, 0x1fb00003) AM_READWRITE8(cbaj_from_z80_latch_r, cbaj_to_z80_latch_w, 0x000000ff)
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AM_RANGE(0x1fb00000, 0x1fb00003) AM_READ8(cbaj_from_z80_status_r, 0xff000000)
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AM_RANGE(0x1fb00000, 0x1fb00003) AM_DEVREAD8("cbaj_fifo2", fifo7200_device, data_byte_r, 0x000000ff) AM_DEVWRITE8("cbaj_fifo1", fifo7200_device, data_byte_w, 0x000000ff)
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AM_RANGE(0x1fb00000, 0x1fb00003) AM_READ8(cbaj_sound_main_status_r, 0xff000000)
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AM_IMPORT_FROM(coh1002m_map)
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ADDRESS_MAP_END
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READ8_MEMBER(zn_state::cbaj_to_z80_latch_r)
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READ8_MEMBER(zn_state::cbaj_sound_z80_status_r)
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{
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UINT8 ret = m_cbaj_fifo_buffer[0][m_cbaj_fifo_z80_ptr[0]];
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m_cbaj_fifo_z80_ptr[0] = (m_cbaj_fifo_z80_ptr[0] + 1) & 0x3ff;
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return ret;
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}
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WRITE8_MEMBER(zn_state::cbaj_from_z80_latch_w)
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{
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m_cbaj_fifo_buffer[1][m_cbaj_fifo_z80_ptr[1]] = data;
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m_cbaj_fifo_z80_ptr[1] = (m_cbaj_fifo_z80_ptr[1] + 1) & 0x3ff;
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}
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READ8_MEMBER(zn_state::cbaj_to_z80_status_r)
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{
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return (m_cbaj_fifo_main_ptr[0] != m_cbaj_fifo_z80_ptr[0]) ? 0x02 : 0x00;
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// d1: fifo empty flag, other bits: unused
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return ~(m_cbaj_fifo1->ef_r() << 1);
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}
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static ADDRESS_MAP_START( cbaj_z80_map, AS_PROGRAM, 8, zn_state )
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@ -2473,18 +2445,10 @@ ADDRESS_MAP_END
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static ADDRESS_MAP_START( cbaj_z80_port_map, AS_IO, 8, zn_state )
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ADDRESS_MAP_GLOBAL_MASK(0xff)
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AM_RANGE(0x84, 0x85) AM_DEVREADWRITE("ymz", ymz280b_device, read, write)
|
||||
AM_RANGE(0x90, 0x90) AM_READWRITE(cbaj_to_z80_latch_r, cbaj_from_z80_latch_w)
|
||||
AM_RANGE(0x91, 0x91) AM_READ(cbaj_to_z80_status_r)
|
||||
AM_RANGE(0x90, 0x90) AM_DEVREAD("cbaj_fifo1", fifo7200_device, data_byte_r) AM_DEVWRITE("cbaj_fifo2", fifo7200_device, data_byte_w)
|
||||
AM_RANGE(0x91, 0x91) AM_READ(cbaj_sound_z80_status_r)
|
||||
ADDRESS_MAP_END
|
||||
|
||||
MACHINE_RESET_MEMBER(zn_state,coh1002msnd)
|
||||
{
|
||||
m_cbaj_fifo_main_ptr[0] = m_cbaj_fifo_main_ptr[1] = 0;
|
||||
m_cbaj_fifo_z80_ptr[0] = m_cbaj_fifo_z80_ptr[1] = 0;
|
||||
|
||||
MACHINE_RESET_CALL_MEMBER(coh1002m);
|
||||
}
|
||||
|
||||
static MACHINE_CONFIG_DERIVED( coh1002msnd, coh1002m )
|
||||
MCFG_CPU_MODIFY("maincpu")
|
||||
MCFG_CPU_PROGRAM_MAP(coh1002msnd_map)
|
||||
@ -2492,9 +2456,11 @@ static MACHINE_CONFIG_DERIVED( coh1002msnd, coh1002m )
|
||||
MCFG_CPU_ADD("audiocpu", Z80, XTAL_32MHz/8)
|
||||
MCFG_CPU_PROGRAM_MAP(cbaj_z80_map)
|
||||
MCFG_CPU_IO_MAP(cbaj_z80_port_map)
|
||||
|
||||
MCFG_FIFO7200_ADD("cbaj_fifo1", 0x400) // LH540202
|
||||
MCFG_FIFO7200_ADD("cbaj_fifo2", 0x400) // LH540202
|
||||
|
||||
MCFG_QUANTUM_TIME(attotime::from_hz(6000))
|
||||
MCFG_MACHINE_RESET_OVERRIDE(zn_state, coh1002msnd)
|
||||
|
||||
MCFG_SOUND_ADD("ymz", YMZ280B, XTAL_16_9344MHz)
|
||||
MCFG_SOUND_ROUTE(0, "lspeaker", 0.35)
|
||||
|
||||
Loading…
Reference in New Issue
Block a user