idectrl/atahle.c: call routine fill_buffer using a timer to avoid reentering read_data and losing data with ultra dma (nw)

Also small comment changes.
This commit is contained in:
yz70s 2015-10-19 21:55:49 +02:00
parent 53348ed1df
commit 5c880f47f1
3 changed files with 16 additions and 6 deletions

View File

@ -110,6 +110,7 @@ void ata_hle_device::device_start()
save_item(NAME(m_identify_buffer)); save_item(NAME(m_identify_buffer));
m_busy_timer = timer_alloc(TID_BUSY); m_busy_timer = timer_alloc(TID_BUSY);
m_buffer_empty_timer = timer_alloc(TID_BUFFER_EMPTY);
} }
void ata_hle_device::device_reset() void ata_hle_device::device_reset()
@ -158,6 +159,10 @@ void ata_hle_device::device_timer(emu_timer &timer, device_timer_id id, int para
finished_busy(param); finished_busy(param);
break; break;
case TID_BUFFER_EMPTY:
m_buffer_empty_timer->enable(false);
fill_buffer();
break;
} }
} }
@ -465,7 +470,8 @@ void ata_hle_device::read_buffer_empty()
if ((multi_word_dma_mode() >= 0) || (ultra_dma_mode() >= 0)) if ((multi_word_dma_mode() >= 0) || (ultra_dma_mode() >= 0))
set_dmarq(CLEAR_LINE); set_dmarq(CLEAR_LINE);
fill_buffer(); m_buffer_empty_timer->enable(true);
m_buffer_empty_timer->adjust(attotime::zero);
} }
void ata_hle_device::write_buffer_full() void ata_hle_device::write_buffer_full()

View File

@ -34,6 +34,8 @@ public:
virtual DECLARE_WRITE_LINE_MEMBER(write_dmack); virtual DECLARE_WRITE_LINE_MEMBER(write_dmack);
virtual DECLARE_WRITE_LINE_MEMBER(write_pdiag); virtual DECLARE_WRITE_LINE_MEMBER(write_pdiag);
TIMER_CALLBACK_MEMBER(buffer_empty_timer_work);
protected: protected:
virtual void device_start(); virtual void device_start();
virtual void device_reset(); virtual void device_reset();
@ -160,7 +162,8 @@ protected:
enum enum
{ {
TID_BUSY TID_BUSY,
TID_BUFFER_EMPTY
}; };
enum enum
@ -213,6 +216,7 @@ private:
bool m_resetting; bool m_resetting;
emu_timer *m_busy_timer; emu_timer *m_busy_timer;
emu_timer *m_buffer_empty_timer;
}; };
#endif #endif

View File

@ -274,11 +274,11 @@ WRITE32_MEMBER( bus_master_ide_controller_device::bmdma_w )
case 0: case 0:
if( ACCESSING_BITS_0_7 ) if( ACCESSING_BITS_0_7 )
{ {
/* command register */ /* Bus Master IDE Command register */
UINT8 old = m_bus_master_command; UINT8 old = m_bus_master_command;
UINT8 val = data & 0xff; UINT8 val = data & 0xff;
/* save the read/write bit and the start/stop bit */ /* save the "Read or Write Control" bit 3 and the "Start/Stop Bus Master" bit 0 */
m_bus_master_command = (old & 0xf6) | (val & 0x09); m_bus_master_command = (old & 0xf6) | (val & 0x09);
if ((old ^ m_bus_master_command) & 1) if ((old ^ m_bus_master_command) & 1)
@ -306,7 +306,7 @@ WRITE32_MEMBER( bus_master_ide_controller_device::bmdma_w )
if( ACCESSING_BITS_16_23 ) if( ACCESSING_BITS_16_23 )
{ {
/* status register */ /* Bus Master IDE Status register */
UINT8 old = m_bus_master_status; UINT8 old = m_bus_master_status;
UINT8 val = data >> 16; UINT8 val = data >> 16;
@ -334,7 +334,7 @@ void bus_master_ide_controller_device::execute_dma()
while (m_dmarq && (m_bus_master_status & IDE_BUSMASTER_STATUS_ACTIVE)) while (m_dmarq && (m_bus_master_status & IDE_BUSMASTER_STATUS_ACTIVE))
{ {
/* if we're out of space, grab the next descriptor */ /* if we're out of space, grab the next Physical Region Descriptor */
if (m_dma_bytes_left == 0) if (m_dma_bytes_left == 0)
{ {
/* fetch the address */ /* fetch the address */