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https://github.com/holub/mame
synced 2025-07-05 09:57:47 +03:00
idectrl/atahle.c: call routine fill_buffer using a timer to avoid reentering read_data and losing data with ultra dma (nw)
Also small comment changes.
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53348ed1df
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@ -110,6 +110,7 @@ void ata_hle_device::device_start()
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save_item(NAME(m_identify_buffer));
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save_item(NAME(m_identify_buffer));
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m_busy_timer = timer_alloc(TID_BUSY);
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m_busy_timer = timer_alloc(TID_BUSY);
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m_buffer_empty_timer = timer_alloc(TID_BUFFER_EMPTY);
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}
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}
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void ata_hle_device::device_reset()
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void ata_hle_device::device_reset()
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@ -158,6 +159,10 @@ void ata_hle_device::device_timer(emu_timer &timer, device_timer_id id, int para
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finished_busy(param);
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finished_busy(param);
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break;
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break;
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case TID_BUFFER_EMPTY:
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m_buffer_empty_timer->enable(false);
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fill_buffer();
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break;
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}
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}
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}
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}
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@ -465,7 +470,8 @@ void ata_hle_device::read_buffer_empty()
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if ((multi_word_dma_mode() >= 0) || (ultra_dma_mode() >= 0))
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if ((multi_word_dma_mode() >= 0) || (ultra_dma_mode() >= 0))
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set_dmarq(CLEAR_LINE);
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set_dmarq(CLEAR_LINE);
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fill_buffer();
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m_buffer_empty_timer->enable(true);
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m_buffer_empty_timer->adjust(attotime::zero);
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}
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}
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void ata_hle_device::write_buffer_full()
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void ata_hle_device::write_buffer_full()
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@ -34,6 +34,8 @@ public:
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virtual DECLARE_WRITE_LINE_MEMBER(write_dmack);
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virtual DECLARE_WRITE_LINE_MEMBER(write_dmack);
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virtual DECLARE_WRITE_LINE_MEMBER(write_pdiag);
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virtual DECLARE_WRITE_LINE_MEMBER(write_pdiag);
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TIMER_CALLBACK_MEMBER(buffer_empty_timer_work);
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protected:
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protected:
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virtual void device_start();
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virtual void device_start();
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virtual void device_reset();
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virtual void device_reset();
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@ -160,7 +162,8 @@ protected:
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enum
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enum
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{
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{
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TID_BUSY
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TID_BUSY,
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TID_BUFFER_EMPTY
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};
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};
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enum
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enum
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@ -213,6 +216,7 @@ private:
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bool m_resetting;
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bool m_resetting;
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emu_timer *m_busy_timer;
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emu_timer *m_busy_timer;
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emu_timer *m_buffer_empty_timer;
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};
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};
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#endif
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#endif
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@ -274,11 +274,11 @@ WRITE32_MEMBER( bus_master_ide_controller_device::bmdma_w )
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case 0:
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case 0:
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if( ACCESSING_BITS_0_7 )
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if( ACCESSING_BITS_0_7 )
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{
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{
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/* command register */
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/* Bus Master IDE Command register */
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UINT8 old = m_bus_master_command;
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UINT8 old = m_bus_master_command;
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UINT8 val = data & 0xff;
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UINT8 val = data & 0xff;
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/* save the read/write bit and the start/stop bit */
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/* save the "Read or Write Control" bit 3 and the "Start/Stop Bus Master" bit 0 */
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m_bus_master_command = (old & 0xf6) | (val & 0x09);
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m_bus_master_command = (old & 0xf6) | (val & 0x09);
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if ((old ^ m_bus_master_command) & 1)
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if ((old ^ m_bus_master_command) & 1)
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@ -306,7 +306,7 @@ WRITE32_MEMBER( bus_master_ide_controller_device::bmdma_w )
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if( ACCESSING_BITS_16_23 )
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if( ACCESSING_BITS_16_23 )
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{
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{
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/* status register */
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/* Bus Master IDE Status register */
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UINT8 old = m_bus_master_status;
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UINT8 old = m_bus_master_status;
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UINT8 val = data >> 16;
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UINT8 val = data >> 16;
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@ -334,7 +334,7 @@ void bus_master_ide_controller_device::execute_dma()
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while (m_dmarq && (m_bus_master_status & IDE_BUSMASTER_STATUS_ACTIVE))
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while (m_dmarq && (m_bus_master_status & IDE_BUSMASTER_STATUS_ACTIVE))
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{
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{
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/* if we're out of space, grab the next descriptor */
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/* if we're out of space, grab the next Physical Region Descriptor */
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if (m_dma_bytes_left == 0)
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if (m_dma_bytes_left == 0)
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{
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{
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/* fetch the address */
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/* fetch the address */
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