mirror of
https://github.com/holub/mame
synced 2025-05-21 13:18:56 +03:00
Normalized m37710 local CPU state pointers to to 'cpustate'.
Removed need for cpunum in the timers.
This commit is contained in:
Aaron Giles
parent
593e334f08
commit
5cfad18a84
@ -57,7 +57,7 @@
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#define M37710_DEBUG (0) // enables verbose logging for peripherals, etc.
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static void m37710_set_irq_line(m37710i_cpu_struct *m37710i_cpu, int line, int state);
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static void m37710_set_irq_line(m37710i_cpu_struct *cpustate, int line, int state);
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/* interrupt control mapping */
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@ -260,20 +260,20 @@ static const char *const m37710_tnames[8] =
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static TIMER_CALLBACK( m37710_timer_cb )
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{
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m37710i_cpu_struct *m37710i_cpu = ptr;
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m37710i_cpu_struct *cpustate = ptr;
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int which = param;
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int curirq = M37710_LINE_TIMERA0 - which;
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cpu_push_context(m37710i_cpu->device);
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timer_adjust_oneshot(m37710i_cpu->timers[which], m37710i_cpu->reload[which], param);
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cpu_push_context(cpustate->device);
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timer_adjust_oneshot(cpustate->timers[which], cpustate->reload[which], param);
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m37710i_cpu->m37710_regs[m37710_irq_levels[curirq]] |= 0x04;
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m37710_set_irq_line(m37710i_cpu, curirq, PULSE_LINE);
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cpu_triggerint(m37710i_cpu->device);
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cpustate->m37710_regs[m37710_irq_levels[curirq]] |= 0x04;
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m37710_set_irq_line(cpustate, curirq, PULSE_LINE);
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cpu_triggerint(cpustate->device);
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cpu_pop_context();
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}
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static void m37710_external_tick(m37710i_cpu_struct *m37710i_cpu, int timer, int state)
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static void m37710_external_tick(m37710i_cpu_struct *cpustate, int timer, int state)
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{
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// we only care if the state is "on"
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if (!state)
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@ -282,18 +282,18 @@ static void m37710_external_tick(m37710i_cpu_struct *m37710i_cpu, int timer, int
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}
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// check if enabled
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if (m37710i_cpu->m37710_regs[0x40] & (1<<timer))
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if (cpustate->m37710_regs[0x40] & (1<<timer))
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{
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if ((m37710i_cpu->m37710_regs[0x56+timer] & 0x3) == 1)
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if ((cpustate->m37710_regs[0x56+timer] & 0x3) == 1)
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{
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if (m37710i_cpu->m37710_regs[0x46+(timer*2)] == 0xff)
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if (cpustate->m37710_regs[0x46+(timer*2)] == 0xff)
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{
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m37710i_cpu->m37710_regs[0x46+(timer*2)] = 0;
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m37710i_cpu->m37710_regs[0x46+(timer*2)+1]++;
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cpustate->m37710_regs[0x46+(timer*2)] = 0;
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cpustate->m37710_regs[0x46+(timer*2)+1]++;
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}
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else
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{
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m37710i_cpu->m37710_regs[0x46+(timer*2)]++;
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cpustate->m37710_regs[0x46+(timer*2)]++;
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}
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}
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else
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@ -303,40 +303,39 @@ static void m37710_external_tick(m37710i_cpu_struct *m37710i_cpu, int timer, int
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}
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}
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static void m37710_recalc_timer(m37710i_cpu_struct *m37710i_cpu, running_machine *machine, int timer)
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static void m37710_recalc_timer(m37710i_cpu_struct *cpustate, running_machine *machine, int timer)
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{
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int cpunum = cpunum_get_active();
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int tval;
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static const int tcr[8] = { 0x56, 0x57, 0x58, 0x59, 0x5a, 0x5b, 0x5c, 0x5d };
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attotime time;
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static const int tscales[4] = { 2, 16, 64, 512 };
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// check if enabled
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if (m37710i_cpu->m37710_regs[0x40] & (1<<timer))
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if (cpustate->m37710_regs[0x40] & (1<<timer))
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{
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#if M37710_DEBUG
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mame_printf_debug("Timer %d (%s) is enabled\n", timer, m37710_tnames[timer]);
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#endif
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// set the timer's value
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tval = m37710i_cpu->m37710_regs[0x46+(timer*2)] | (m37710i_cpu->m37710_regs[0x47+(timer*2)]<<8);
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tval = cpustate->m37710_regs[0x46+(timer*2)] | (cpustate->m37710_regs[0x47+(timer*2)]<<8);
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// check timer's mode
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// modes are slightly different between timer groups A and B
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if (timer < 5)
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{
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switch (m37710i_cpu->m37710_regs[0x56+timer] & 0x3)
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switch (cpustate->m37710_regs[0x56+timer] & 0x3)
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{
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case 0: // timer mode
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time = attotime_mul(ATTOTIME_IN_HZ(cpu_get_clock(machine->activecpu)), tscales[m37710i_cpu->m37710_regs[tcr[timer]]>>6]);
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time = attotime_mul(ATTOTIME_IN_HZ(cpu_get_clock(machine->activecpu)), tscales[cpustate->m37710_regs[tcr[timer]]>>6]);
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time = attotime_mul(time, tval + 1);
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#if M37710_DEBUG
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mame_printf_debug("Timer %d in timer mode, %f Hz\n", timer, 1.0 / attotime_to_double(time));
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#endif
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timer_adjust_oneshot(m37710i_cpu->timers[timer], time, cpunum);
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m37710i_cpu->reload[timer] = time;
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timer_adjust_oneshot(cpustate->timers[timer], time, timer);
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cpustate->reload[timer] = time;
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break;
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case 1: // event counter mode
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@ -360,18 +359,18 @@ static void m37710_recalc_timer(m37710i_cpu_struct *m37710i_cpu, running_machine
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}
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else
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{
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switch (m37710i_cpu->m37710_regs[0x56+timer] & 0x3)
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switch (cpustate->m37710_regs[0x56+timer] & 0x3)
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{
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case 0: // timer mode
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time = attotime_mul(ATTOTIME_IN_HZ(cpu_get_clock(machine->activecpu)), tscales[m37710i_cpu->m37710_regs[tcr[timer]]>>6]);
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time = attotime_mul(ATTOTIME_IN_HZ(cpu_get_clock(machine->activecpu)), tscales[cpustate->m37710_regs[tcr[timer]]>>6]);
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time = attotime_mul(time, tval + 1);
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#if M37710_DEBUG
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mame_printf_debug("Timer %d in timer mode, %f Hz\n", timer, 1.0 / attotime_to_double(time));
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#endif
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timer_adjust_oneshot(m37710i_cpu->timers[timer], time, cpunum);
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m37710i_cpu->reload[timer] = time;
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timer_adjust_oneshot(cpustate->timers[timer], time, timer);
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cpustate->reload[timer] = time;
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break;
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case 1: // event counter mode
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@ -396,7 +395,7 @@ static void m37710_recalc_timer(m37710i_cpu_struct *m37710i_cpu, running_machine
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}
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}
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static UINT8 m37710_internal_r(m37710i_cpu_struct *m37710i_cpu, int offset)
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static UINT8 m37710_internal_r(m37710i_cpu_struct *cpustate, int offset)
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{
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#if M37710_DEBUG
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if (offset > 1)
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@ -406,147 +405,147 @@ static UINT8 m37710_internal_r(m37710i_cpu_struct *m37710i_cpu, int offset)
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switch (offset)
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{
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case 2: // p0
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return memory_read_byte_8le(m37710i_cpu->io, M37710_PORT0);
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return memory_read_byte_8le(cpustate->io, M37710_PORT0);
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break;
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case 3: // p1
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return memory_read_byte_8le(m37710i_cpu->io, M37710_PORT1);
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return memory_read_byte_8le(cpustate->io, M37710_PORT1);
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break;
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case 6: // p2
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return memory_read_byte_8le(m37710i_cpu->io, M37710_PORT2);
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return memory_read_byte_8le(cpustate->io, M37710_PORT2);
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break;
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case 7: // p3
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return memory_read_byte_8le(m37710i_cpu->io, M37710_PORT3);
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return memory_read_byte_8le(cpustate->io, M37710_PORT3);
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break;
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case 0xa: // p4
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return memory_read_byte_8le(m37710i_cpu->io, M37710_PORT4);
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return memory_read_byte_8le(cpustate->io, M37710_PORT4);
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break;
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case 0xb: // p5
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return memory_read_byte_8le(m37710i_cpu->io, M37710_PORT5);
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return memory_read_byte_8le(cpustate->io, M37710_PORT5);
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break;
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case 0xe: // p6
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return memory_read_byte_8le(m37710i_cpu->io, M37710_PORT6);
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return memory_read_byte_8le(cpustate->io, M37710_PORT6);
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break;
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case 0xf: // p7
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return memory_read_byte_8le(m37710i_cpu->io, M37710_PORT7);
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return memory_read_byte_8le(cpustate->io, M37710_PORT7);
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break;
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case 0x12: // p8
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return memory_read_byte_8le(m37710i_cpu->io, M37710_PORT8);
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return memory_read_byte_8le(cpustate->io, M37710_PORT8);
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break;
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case 0x20:
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return memory_read_byte_8le(m37710i_cpu->io, M37710_ADC0_L);
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return memory_read_byte_8le(cpustate->io, M37710_ADC0_L);
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break;
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case 0x21:
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return memory_read_byte_8le(m37710i_cpu->io, M37710_ADC0_H);
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return memory_read_byte_8le(cpustate->io, M37710_ADC0_H);
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break;
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case 0x22:
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return memory_read_byte_8le(m37710i_cpu->io, M37710_ADC1_L);
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return memory_read_byte_8le(cpustate->io, M37710_ADC1_L);
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break;
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case 0x23:
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return memory_read_byte_8le(m37710i_cpu->io, M37710_ADC1_H);
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return memory_read_byte_8le(cpustate->io, M37710_ADC1_H);
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break;
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case 0x24:
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return memory_read_byte_8le(m37710i_cpu->io, M37710_ADC2_L);
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return memory_read_byte_8le(cpustate->io, M37710_ADC2_L);
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break;
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case 0x25:
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return memory_read_byte_8le(m37710i_cpu->io, M37710_ADC2_H);
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return memory_read_byte_8le(cpustate->io, M37710_ADC2_H);
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break;
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case 0x26:
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return memory_read_byte_8le(m37710i_cpu->io, M37710_ADC3_L);
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return memory_read_byte_8le(cpustate->io, M37710_ADC3_L);
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break;
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case 0x27:
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return memory_read_byte_8le(m37710i_cpu->io, M37710_ADC3_H);
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return memory_read_byte_8le(cpustate->io, M37710_ADC3_H);
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break;
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case 0x28:
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return memory_read_byte_8le(m37710i_cpu->io, M37710_ADC4_L);
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return memory_read_byte_8le(cpustate->io, M37710_ADC4_L);
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break;
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case 0x29:
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return memory_read_byte_8le(m37710i_cpu->io, M37710_ADC4_H);
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return memory_read_byte_8le(cpustate->io, M37710_ADC4_H);
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break;
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case 0x2a:
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return memory_read_byte_8le(m37710i_cpu->io, M37710_ADC5_L);
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return memory_read_byte_8le(cpustate->io, M37710_ADC5_L);
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break;
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case 0x2b:
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return memory_read_byte_8le(m37710i_cpu->io, M37710_ADC5_H);
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return memory_read_byte_8le(cpustate->io, M37710_ADC5_H);
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break;
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case 0x2c:
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return memory_read_byte_8le(m37710i_cpu->io, M37710_ADC6_L);
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return memory_read_byte_8le(cpustate->io, M37710_ADC6_L);
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break;
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case 0x2d:
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return memory_read_byte_8le(m37710i_cpu->io, M37710_ADC6_H);
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return memory_read_byte_8le(cpustate->io, M37710_ADC6_H);
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break;
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case 0x2e:
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return memory_read_byte_8le(m37710i_cpu->io, M37710_ADC7_L);
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return memory_read_byte_8le(cpustate->io, M37710_ADC7_L);
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break;
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case 0x2f:
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return memory_read_byte_8le(m37710i_cpu->io, M37710_ADC7_H);
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return memory_read_byte_8le(cpustate->io, M37710_ADC7_H);
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break;
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case 0x35:
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return 0xff; // UART control
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break;
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case 0x70: // A/D IRQ control
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return m37710i_cpu->m37710_regs[offset] | 8;
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return cpustate->m37710_regs[offset] | 8;
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break;
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}
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return m37710i_cpu->m37710_regs[offset];
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return cpustate->m37710_regs[offset];
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}
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static void m37710_internal_w(m37710i_cpu_struct *m37710i_cpu, int offset, UINT8 data)
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static void m37710_internal_w(m37710i_cpu_struct *cpustate, int offset, UINT8 data)
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{
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int i;
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switch(offset)
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{
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case 2: // p0
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memory_write_byte_8le(m37710i_cpu->io, M37710_PORT0, data);
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memory_write_byte_8le(cpustate->io, M37710_PORT0, data);
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return;
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break;
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case 3: // p1
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memory_write_byte_8le(m37710i_cpu->io, M37710_PORT1, data);
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memory_write_byte_8le(cpustate->io, M37710_PORT1, data);
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return;
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break;
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case 6: // p2
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memory_write_byte_8le(m37710i_cpu->io, M37710_PORT2, data);
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memory_write_byte_8le(cpustate->io, M37710_PORT2, data);
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return;
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break;
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case 7: // p3
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memory_write_byte_8le(m37710i_cpu->io, M37710_PORT3, data);
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memory_write_byte_8le(cpustate->io, M37710_PORT3, data);
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return;
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break;
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case 0xa: // p4
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memory_write_byte_8le(m37710i_cpu->io, M37710_PORT4, data);
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memory_write_byte_8le(cpustate->io, M37710_PORT4, data);
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return;
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break;
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case 0xb: // p5
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memory_write_byte_8le(m37710i_cpu->io, M37710_PORT5, data);
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memory_write_byte_8le(cpustate->io, M37710_PORT5, data);
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return;
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break;
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case 0xe: // p6
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memory_write_byte_8le(m37710i_cpu->io, M37710_PORT6, data);
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memory_write_byte_8le(cpustate->io, M37710_PORT6, data);
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return;
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break;
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case 0xf: // p7
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memory_write_byte_8le(m37710i_cpu->io, M37710_PORT7, data);
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memory_write_byte_8le(cpustate->io, M37710_PORT7, data);
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return;
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break;
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case 0x12: // p8
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memory_write_byte_8le(m37710i_cpu->io, M37710_PORT8, data);
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memory_write_byte_8le(cpustate->io, M37710_PORT8, data);
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return;
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break;
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case 0x40: // count start
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for (i = 0; i < 8; i++)
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{
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if ((data & (1<<i)) && !(m37710i_cpu->m37710_regs[offset] & (1<<i)))
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if ((data & (1<<i)) && !(cpustate->m37710_regs[offset] & (1<<i)))
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{
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m37710i_cpu->m37710_regs[offset] |= (1<<i);
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m37710_recalc_timer(m37710i_cpu, m37710i_cpu->device->machine, i);
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cpustate->m37710_regs[offset] |= (1<<i);
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m37710_recalc_timer(cpustate, cpustate->device->machine, i);
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}
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}
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m37710i_cpu->m37710_regs[offset] = data;
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cpustate->m37710_regs[offset] = data;
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return;
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break;
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@ -556,29 +555,29 @@ static void m37710_internal_w(m37710i_cpu_struct *m37710i_cpu, int offset, UINT8
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break;
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}
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m37710i_cpu->m37710_regs[offset] = data;
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cpustate->m37710_regs[offset] = data;
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#if M37710_DEBUG
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if (offset >= 0x1e && offset <= 0x40)
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logerror("m37710_internal_w %x to %02x: %s = %x\n", data, (int)offset, m37710_rnames[(int)offset], m37710i_cpu->m37710_regs[offset]);
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logerror("m37710_internal_w %x to %02x: %s = %x\n", data, (int)offset, m37710_rnames[(int)offset], cpustate->m37710_regs[offset]);
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#endif
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}
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static READ16_HANDLER( m37710_internal_word_r )
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{
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m37710i_cpu_struct *m37710i_cpu = (m37710i_cpu_struct *)space->cpu->token;
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m37710i_cpu_struct *cpustate = (m37710i_cpu_struct *)space->cpu->token;
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if (mem_mask == 0xffff)
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{
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return (m37710_internal_r(m37710i_cpu, offset*2) | m37710_internal_r(m37710i_cpu, (offset*2)+1)<<8);
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return (m37710_internal_r(cpustate, offset*2) | m37710_internal_r(cpustate, (offset*2)+1)<<8);
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}
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else if (mem_mask == 0xff00)
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{
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return m37710_internal_r(m37710i_cpu, (offset*2)+1)<<8;
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return m37710_internal_r(cpustate, (offset*2)+1)<<8;
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}
|
||||
else if (mem_mask == 0x00ff)
|
||||
{
|
||||
return m37710_internal_r(m37710i_cpu, (offset*2));
|
||||
return m37710_internal_r(cpustate, (offset*2));
|
||||
}
|
||||
|
||||
return 0;
|
||||
@ -586,56 +585,56 @@ static READ16_HANDLER( m37710_internal_word_r )
|
||||
|
||||
static WRITE16_HANDLER( m37710_internal_word_w )
|
||||
{
|
||||
m37710i_cpu_struct *m37710i_cpu = (m37710i_cpu_struct *)space->cpu->token;
|
||||
m37710i_cpu_struct *cpustate = (m37710i_cpu_struct *)space->cpu->token;
|
||||
|
||||
if (mem_mask == 0xffff)
|
||||
{
|
||||
m37710_internal_w(m37710i_cpu, (offset*2), data & 0xff);
|
||||
m37710_internal_w(m37710i_cpu, (offset*2)+1, data>>8);
|
||||
m37710_internal_w(cpustate, (offset*2), data & 0xff);
|
||||
m37710_internal_w(cpustate, (offset*2)+1, data>>8);
|
||||
}
|
||||
else if (mem_mask == 0xff00)
|
||||
{
|
||||
m37710_internal_w(m37710i_cpu, (offset*2)+1, data>>8);
|
||||
m37710_internal_w(cpustate, (offset*2)+1, data>>8);
|
||||
}
|
||||
else if (mem_mask == 0x00ff)
|
||||
{
|
||||
m37710_internal_w(m37710i_cpu, (offset*2), data & 0xff);
|
||||
m37710_internal_w(cpustate, (offset*2), data & 0xff);
|
||||
}
|
||||
}
|
||||
|
||||
extern void (*const m37710i_opcodes_M0X0[])(m37710i_cpu_struct *m37710i_cpu);
|
||||
extern void (*const m37710i_opcodes42_M0X0[])(m37710i_cpu_struct *m37710i_cpu);
|
||||
extern void (*const m37710i_opcodes89_M0X0[])(m37710i_cpu_struct *m37710i_cpu);
|
||||
extern uint m37710i_get_reg_M0X0(m37710i_cpu_struct *m37710i_cpu, int regnum);
|
||||
extern void m37710i_set_reg_M0X0(m37710i_cpu_struct *m37710i_cpu, int regnum, uint val);
|
||||
extern void m37710i_set_line_M0X0(m37710i_cpu_struct *m37710i_cpu, int line, int state);
|
||||
extern int m37710i_execute_M0X0(m37710i_cpu_struct *m37710i_cpu, int cycles);
|
||||
extern void (*const m37710i_opcodes_M0X0[])(m37710i_cpu_struct *cpustate);
|
||||
extern void (*const m37710i_opcodes42_M0X0[])(m37710i_cpu_struct *cpustate);
|
||||
extern void (*const m37710i_opcodes89_M0X0[])(m37710i_cpu_struct *cpustate);
|
||||
extern uint m37710i_get_reg_M0X0(m37710i_cpu_struct *cpustate, int regnum);
|
||||
extern void m37710i_set_reg_M0X0(m37710i_cpu_struct *cpustate, int regnum, uint val);
|
||||
extern void m37710i_set_line_M0X0(m37710i_cpu_struct *cpustate, int line, int state);
|
||||
extern int m37710i_execute_M0X0(m37710i_cpu_struct *cpustate, int cycles);
|
||||
|
||||
extern void (*const m37710i_opcodes_M0X1[])(m37710i_cpu_struct *m37710i_cpu);
|
||||
extern void (*const m37710i_opcodes42_M0X1[])(m37710i_cpu_struct *m37710i_cpu);
|
||||
extern void (*const m37710i_opcodes89_M0X1[])(m37710i_cpu_struct *m37710i_cpu);
|
||||
extern uint m37710i_get_reg_M0X1(m37710i_cpu_struct *m37710i_cpu, int regnum);
|
||||
extern void m37710i_set_reg_M0X1(m37710i_cpu_struct *m37710i_cpu, int regnum, uint val);
|
||||
extern void m37710i_set_line_M0X1(m37710i_cpu_struct *m37710i_cpu, int line, int state);
|
||||
extern int m37710i_execute_M0X1(m37710i_cpu_struct *m37710i_cpu, int cycles);
|
||||
extern void (*const m37710i_opcodes_M0X1[])(m37710i_cpu_struct *cpustate);
|
||||
extern void (*const m37710i_opcodes42_M0X1[])(m37710i_cpu_struct *cpustate);
|
||||
extern void (*const m37710i_opcodes89_M0X1[])(m37710i_cpu_struct *cpustate);
|
||||
extern uint m37710i_get_reg_M0X1(m37710i_cpu_struct *cpustate, int regnum);
|
||||
extern void m37710i_set_reg_M0X1(m37710i_cpu_struct *cpustate, int regnum, uint val);
|
||||
extern void m37710i_set_line_M0X1(m37710i_cpu_struct *cpustate, int line, int state);
|
||||
extern int m37710i_execute_M0X1(m37710i_cpu_struct *cpustate, int cycles);
|
||||
|
||||
extern void (*const m37710i_opcodes_M1X0[])(m37710i_cpu_struct *m37710i_cpu);
|
||||
extern void (*const m37710i_opcodes42_M1X0[])(m37710i_cpu_struct *m37710i_cpu);
|
||||
extern void (*const m37710i_opcodes89_M1X0[])(m37710i_cpu_struct *m37710i_cpu);
|
||||
extern uint m37710i_get_reg_M1X0(m37710i_cpu_struct *m37710i_cpu, int regnum);
|
||||
extern void m37710i_set_reg_M1X0(m37710i_cpu_struct *m37710i_cpu, int regnum, uint val);
|
||||
extern void m37710i_set_line_M1X0(m37710i_cpu_struct *m37710i_cpu, int line, int state);
|
||||
extern int m37710i_execute_M1X0(m37710i_cpu_struct *m37710i_cpu, int cycles);
|
||||
extern void (*const m37710i_opcodes_M1X0[])(m37710i_cpu_struct *cpustate);
|
||||
extern void (*const m37710i_opcodes42_M1X0[])(m37710i_cpu_struct *cpustate);
|
||||
extern void (*const m37710i_opcodes89_M1X0[])(m37710i_cpu_struct *cpustate);
|
||||
extern uint m37710i_get_reg_M1X0(m37710i_cpu_struct *cpustate, int regnum);
|
||||
extern void m37710i_set_reg_M1X0(m37710i_cpu_struct *cpustate, int regnum, uint val);
|
||||
extern void m37710i_set_line_M1X0(m37710i_cpu_struct *cpustate, int line, int state);
|
||||
extern int m37710i_execute_M1X0(m37710i_cpu_struct *cpustate, int cycles);
|
||||
|
||||
extern void (*const m37710i_opcodes_M1X1[])(m37710i_cpu_struct *m37710i_cpu);
|
||||
extern void (*const m37710i_opcodes42_M1X1[])(m37710i_cpu_struct *m37710i_cpu);
|
||||
extern void (*const m37710i_opcodes89_M1X1[])(m37710i_cpu_struct *m37710i_cpu);
|
||||
extern uint m37710i_get_reg_M1X1(m37710i_cpu_struct *m37710i_cpu, int regnum);
|
||||
extern void m37710i_set_reg_M1X1(m37710i_cpu_struct *m37710i_cpu, int regnum, uint val);
|
||||
extern void m37710i_set_line_M1X1(m37710i_cpu_struct *m37710i_cpu, int line, int state);
|
||||
extern int m37710i_execute_M1X1(m37710i_cpu_struct *m37710i_cpu, int cycles);
|
||||
extern void (*const m37710i_opcodes_M1X1[])(m37710i_cpu_struct *cpustate);
|
||||
extern void (*const m37710i_opcodes42_M1X1[])(m37710i_cpu_struct *cpustate);
|
||||
extern void (*const m37710i_opcodes89_M1X1[])(m37710i_cpu_struct *cpustate);
|
||||
extern uint m37710i_get_reg_M1X1(m37710i_cpu_struct *cpustate, int regnum);
|
||||
extern void m37710i_set_reg_M1X1(m37710i_cpu_struct *cpustate, int regnum, uint val);
|
||||
extern void m37710i_set_line_M1X1(m37710i_cpu_struct *cpustate, int line, int state);
|
||||
extern int m37710i_execute_M1X1(m37710i_cpu_struct *cpustate, int cycles);
|
||||
|
||||
void (*const *const m37710i_opcodes[4])(m37710i_cpu_struct *m37710i_cpu) =
|
||||
void (*const *const m37710i_opcodes[4])(m37710i_cpu_struct *cpustate) =
|
||||
{
|
||||
m37710i_opcodes_M0X0,
|
||||
m37710i_opcodes_M0X1,
|
||||
@ -643,7 +642,7 @@ void (*const *const m37710i_opcodes[4])(m37710i_cpu_struct *m37710i_cpu) =
|
||||
m37710i_opcodes_M1X1,
|
||||
};
|
||||
|
||||
void (*const *const m37710i_opcodes2[4])(m37710i_cpu_struct *m37710i_cpu) =
|
||||
void (*const *const m37710i_opcodes2[4])(m37710i_cpu_struct *cpustate) =
|
||||
{
|
||||
m37710i_opcodes42_M0X0,
|
||||
m37710i_opcodes42_M0X1,
|
||||
@ -651,7 +650,7 @@ void (*const *const m37710i_opcodes2[4])(m37710i_cpu_struct *m37710i_cpu) =
|
||||
m37710i_opcodes42_M1X1,
|
||||
};
|
||||
|
||||
void (*const *const m37710i_opcodes3[4])(m37710i_cpu_struct *m37710i_cpu) =
|
||||
void (*const *const m37710i_opcodes3[4])(m37710i_cpu_struct *cpustate) =
|
||||
{
|
||||
m37710i_opcodes89_M0X0,
|
||||
m37710i_opcodes89_M0X1,
|
||||
@ -659,7 +658,7 @@ void (*const *const m37710i_opcodes3[4])(m37710i_cpu_struct *m37710i_cpu) =
|
||||
m37710i_opcodes89_M1X1,
|
||||
};
|
||||
|
||||
uint (*const m37710i_get_reg[4])(m37710i_cpu_struct *m37710i_cpu, int regnum) =
|
||||
uint (*const m37710i_get_reg[4])(m37710i_cpu_struct *cpustate, int regnum) =
|
||||
{
|
||||
m37710i_get_reg_M0X0,
|
||||
m37710i_get_reg_M0X1,
|
||||
@ -667,7 +666,7 @@ uint (*const m37710i_get_reg[4])(m37710i_cpu_struct *m37710i_cpu, int regnum) =
|
||||
m37710i_get_reg_M1X1,
|
||||
};
|
||||
|
||||
void (*const m37710i_set_reg[4])(m37710i_cpu_struct *m37710i_cpu, int regnum, uint val) =
|
||||
void (*const m37710i_set_reg[4])(m37710i_cpu_struct *cpustate, int regnum, uint val) =
|
||||
{
|
||||
m37710i_set_reg_M0X0,
|
||||
m37710i_set_reg_M0X1,
|
||||
@ -675,7 +674,7 @@ void (*const m37710i_set_reg[4])(m37710i_cpu_struct *m37710i_cpu, int regnum, ui
|
||||
m37710i_set_reg_M1X1,
|
||||
};
|
||||
|
||||
void (*const m37710i_set_line[4])(m37710i_cpu_struct *m37710i_cpu, int line, int state) =
|
||||
void (*const m37710i_set_line[4])(m37710i_cpu_struct *cpustate, int line, int state) =
|
||||
{
|
||||
m37710i_set_line_M0X0,
|
||||
m37710i_set_line_M0X1,
|
||||
@ -683,7 +682,7 @@ void (*const m37710i_set_line[4])(m37710i_cpu_struct *m37710i_cpu, int line, int
|
||||
m37710i_set_line_M1X1,
|
||||
};
|
||||
|
||||
int (*const m37710i_execute[4])(m37710i_cpu_struct *m37710i_cpu, int cycles) =
|
||||
int (*const m37710i_execute[4])(m37710i_cpu_struct *cpustate, int cycles) =
|
||||
{
|
||||
m37710i_execute_M0X0,
|
||||
m37710i_execute_M0X1,
|
||||
@ -693,19 +692,19 @@ int (*const m37710i_execute[4])(m37710i_cpu_struct *m37710i_cpu, int cycles) =
|
||||
|
||||
/* internal functions */
|
||||
|
||||
INLINE void m37710i_push_8(m37710i_cpu_struct *m37710i_cpu, uint value)
|
||||
INLINE void m37710i_push_8(m37710i_cpu_struct *cpustate, uint value)
|
||||
{
|
||||
m37710_write_8(REG_S, value);
|
||||
REG_S = MAKE_UINT_16(REG_S-1);
|
||||
}
|
||||
|
||||
INLINE void m37710i_push_16(m37710i_cpu_struct *m37710i_cpu, uint value)
|
||||
INLINE void m37710i_push_16(m37710i_cpu_struct *cpustate, uint value)
|
||||
{
|
||||
m37710i_push_8(m37710i_cpu, value>>8);
|
||||
m37710i_push_8(m37710i_cpu, value&0xff);
|
||||
m37710i_push_8(cpustate, value>>8);
|
||||
m37710i_push_8(cpustate, value&0xff);
|
||||
}
|
||||
|
||||
INLINE uint m37710i_get_reg_p(m37710i_cpu_struct *m37710i_cpu)
|
||||
INLINE uint m37710i_get_reg_p(m37710i_cpu_struct *cpustate)
|
||||
{
|
||||
return (FLAG_N&0x80) |
|
||||
((FLAG_V>>1)&0x40) |
|
||||
@ -717,7 +716,7 @@ INLINE uint m37710i_get_reg_p(m37710i_cpu_struct *m37710i_cpu)
|
||||
((FLAG_C>>8)&1);
|
||||
}
|
||||
|
||||
void m37710i_update_irqs(m37710i_cpu_struct *m37710i_cpu)
|
||||
void m37710i_update_irqs(m37710i_cpu_struct *cpustate)
|
||||
{
|
||||
int curirq, pending = LINE_IRQ;
|
||||
int wantedIRQ, curpri;
|
||||
@ -737,16 +736,16 @@ void m37710i_update_irqs(m37710i_cpu_struct *m37710i_cpu)
|
||||
// this IRQ is set
|
||||
if (m37710_irq_levels[curirq])
|
||||
{
|
||||
// logerror("line %d set, level %x curpri %x IPL %x\n", curirq, m37710i_cpu->m37710_regs[m37710_irq_levels[curirq]] & 7, curpri, m37710i_cpu->ipl);
|
||||
// logerror("line %d set, level %x curpri %x IPL %x\n", curirq, cpustate->m37710_regs[m37710_irq_levels[curirq]] & 7, curpri, cpustate->ipl);
|
||||
// it's maskable, check if the level works
|
||||
if ((m37710i_cpu->m37710_regs[m37710_irq_levels[curirq]] & 7) > curpri)
|
||||
if ((cpustate->m37710_regs[m37710_irq_levels[curirq]] & 7) > curpri)
|
||||
{
|
||||
// also make sure it's acceptable for the current CPU level
|
||||
if ((m37710i_cpu->m37710_regs[m37710_irq_levels[curirq]] & 7) > m37710i_cpu->ipl)
|
||||
if ((cpustate->m37710_regs[m37710_irq_levels[curirq]] & 7) > cpustate->ipl)
|
||||
{
|
||||
// mark us as the best candidate
|
||||
wantedIRQ = curirq;
|
||||
curpri = m37710i_cpu->m37710_regs[m37710_irq_levels[curirq]] & 7;
|
||||
curpri = cpustate->m37710_regs[m37710_irq_levels[curirq]] & 7;
|
||||
}
|
||||
}
|
||||
}
|
||||
@ -762,7 +761,7 @@ void m37710i_update_irqs(m37710i_cpu_struct *m37710i_cpu)
|
||||
|
||||
if (wantedIRQ != -1)
|
||||
{
|
||||
if (INT_ACK) INT_ACK(m37710i_cpu->device, wantedIRQ);
|
||||
if (INT_ACK) INT_ACK(cpustate->device, wantedIRQ);
|
||||
|
||||
// make sure we're running to service the interrupt
|
||||
CPU_STOPPED &= ~STOP_LEVEL_WAI;
|
||||
@ -770,27 +769,27 @@ void m37710i_update_irqs(m37710i_cpu_struct *m37710i_cpu)
|
||||
// indicate we're servicing it now
|
||||
if (m37710_irq_levels[wantedIRQ])
|
||||
{
|
||||
m37710i_cpu->m37710_regs[m37710_irq_levels[wantedIRQ]] &= ~8;
|
||||
cpustate->m37710_regs[m37710_irq_levels[wantedIRQ]] &= ~8;
|
||||
}
|
||||
|
||||
// auto-clear if it's an internal line
|
||||
if (wantedIRQ <= 12)
|
||||
{
|
||||
m37710_set_irq_line(m37710i_cpu, wantedIRQ, CLEAR_LINE);
|
||||
m37710_set_irq_line(cpustate, wantedIRQ, CLEAR_LINE);
|
||||
}
|
||||
|
||||
// let's do it...
|
||||
// push PB, then PC, then status
|
||||
CLK(8);
|
||||
// mame_printf_debug("taking IRQ %d: PC = %06x, SP = %04x, IPL %d\n", wantedIRQ, REG_PB | REG_PC, REG_S, m37710i_cpu->ipl);
|
||||
m37710i_push_8(m37710i_cpu, REG_PB>>16);
|
||||
m37710i_push_16(m37710i_cpu, REG_PC);
|
||||
m37710i_push_8(m37710i_cpu, m37710i_cpu->ipl);
|
||||
m37710i_push_8(m37710i_cpu, m37710i_get_reg_p(m37710i_cpu));
|
||||
// mame_printf_debug("taking IRQ %d: PC = %06x, SP = %04x, IPL %d\n", wantedIRQ, REG_PB | REG_PC, REG_S, cpustate->ipl);
|
||||
m37710i_push_8(cpustate, REG_PB>>16);
|
||||
m37710i_push_16(cpustate, REG_PC);
|
||||
m37710i_push_8(cpustate, cpustate->ipl);
|
||||
m37710i_push_8(cpustate, m37710i_get_reg_p(cpustate));
|
||||
|
||||
// set I to 1, set IPL to the interrupt we're taking
|
||||
FLAG_I = IFLAG_SET;
|
||||
m37710i_cpu->ipl = curpri;
|
||||
cpustate->ipl = curpri;
|
||||
// then PB=0, PC=(vector)
|
||||
REG_PB = 0;
|
||||
REG_PC = m37710_read_8(m37710_irq_vectors[wantedIRQ]) |
|
||||
@ -804,7 +803,7 @@ void m37710i_update_irqs(m37710i_cpu_struct *m37710i_cpu)
|
||||
|
||||
static CPU_RESET( m37710 )
|
||||
{
|
||||
m37710i_cpu_struct *m37710i_cpu = device->token;
|
||||
m37710i_cpu_struct *cpustate = device->token;
|
||||
|
||||
/* Start the CPU */
|
||||
CPU_STOPPED = 0;
|
||||
@ -833,7 +832,7 @@ static CPU_RESET( m37710 )
|
||||
IRQ_DELAY = 0;
|
||||
|
||||
/* Set the function tables to emulation mode */
|
||||
m37710i_set_execution_mode(m37710i_cpu, EXECUTION_MODE_M0X0);
|
||||
m37710i_set_execution_mode(cpustate, EXECUTION_MODE_M0X0);
|
||||
|
||||
FLAG_Z = ZFLAG_CLEAR;
|
||||
REG_S = 0x1ff;
|
||||
@ -871,34 +870,34 @@ static CPU_SET_CONTEXT( m37710 )
|
||||
}
|
||||
|
||||
/* Set the Program Counter */
|
||||
static void m37710_set_pc(m37710i_cpu_struct *m37710i_cpu, unsigned val)
|
||||
static void m37710_set_pc(m37710i_cpu_struct *cpustate, unsigned val)
|
||||
{
|
||||
REG_PC = MAKE_UINT_16(val);
|
||||
m37710_jumping(REG_PB | REG_PC);
|
||||
}
|
||||
|
||||
/* Get the current Stack Pointer */
|
||||
static unsigned m37710_get_sp(m37710i_cpu_struct *m37710i_cpu)
|
||||
static unsigned m37710_get_sp(m37710i_cpu_struct *cpustate)
|
||||
{
|
||||
return REG_S;
|
||||
}
|
||||
|
||||
/* Set the Stack Pointer */
|
||||
static void m37710_set_sp(m37710i_cpu_struct *m37710i_cpu, unsigned val)
|
||||
static void m37710_set_sp(m37710i_cpu_struct *cpustate, unsigned val)
|
||||
{
|
||||
REG_S = MAKE_UINT_16(val);
|
||||
}
|
||||
|
||||
/* Get a register */
|
||||
static unsigned m37710_get_reg(m37710i_cpu_struct *m37710i_cpu, int regnum)
|
||||
static unsigned m37710_get_reg(m37710i_cpu_struct *cpustate, int regnum)
|
||||
{
|
||||
return FTABLE_GET_REG(m37710i_cpu, regnum);
|
||||
return FTABLE_GET_REG(cpustate, regnum);
|
||||
}
|
||||
|
||||
/* Set a register */
|
||||
static void m37710_set_reg(m37710i_cpu_struct *m37710i_cpu, int regnum, unsigned value)
|
||||
static void m37710_set_reg(m37710i_cpu_struct *cpustate, int regnum, unsigned value)
|
||||
{
|
||||
FTABLE_SET_REG(m37710i_cpu, regnum, value);
|
||||
FTABLE_SET_REG(cpustate, regnum, value);
|
||||
}
|
||||
|
||||
/* Load a CPU state */
|
||||
@ -912,9 +911,9 @@ void m37710_state_save(void *file)
|
||||
}
|
||||
|
||||
/* Set an interrupt line */
|
||||
static void m37710_set_irq_line(m37710i_cpu_struct *m37710i_cpu, int line, int state)
|
||||
static void m37710_set_irq_line(m37710i_cpu_struct *cpustate, int line, int state)
|
||||
{
|
||||
FTABLE_SET_LINE(m37710i_cpu, line, state);
|
||||
FTABLE_SET_LINE(cpustate, line, state);
|
||||
}
|
||||
|
||||
/* Set the callback that is called when servicing an interrupt */
|
||||
@ -930,17 +929,17 @@ void m37710_set_irq_callback(cpu_irq_callback callback)
|
||||
|
||||
static CPU_DISASSEMBLE( m37710 )
|
||||
{
|
||||
m37710i_cpu_struct *m37710i_cpu = device->token;
|
||||
m37710i_cpu_struct *cpustate = device->token;
|
||||
|
||||
return m7700_disassemble(buffer, (pc&0xffff), pc>>16, oprom, FLAG_M, FLAG_X);
|
||||
}
|
||||
|
||||
static STATE_POSTLOAD( m37710_restore_state )
|
||||
{
|
||||
m37710i_cpu_struct *m37710i_cpu = (m37710i_cpu_struct *)param;
|
||||
m37710i_cpu_struct *cpustate = (m37710i_cpu_struct *)param;
|
||||
|
||||
// restore proper function pointers
|
||||
m37710i_set_execution_mode(m37710i_cpu, (FLAG_M>>4) | (FLAG_X>>4));
|
||||
m37710i_set_execution_mode(cpustate, (FLAG_M>>4) | (FLAG_X>>4));
|
||||
|
||||
// make sure the memory system can keep up
|
||||
m37710i_jumping(REG_PB | REG_PC);
|
||||
@ -948,74 +947,74 @@ static STATE_POSTLOAD( m37710_restore_state )
|
||||
|
||||
static CPU_INIT( m37710 )
|
||||
{
|
||||
m37710i_cpu_struct *m37710i_cpu = device->token;
|
||||
m37710i_cpu_struct *cpustate = device->token;
|
||||
int i;
|
||||
|
||||
memset(m37710i_cpu, 0, sizeof(m37710i_cpu));
|
||||
memset(cpustate, 0, sizeof(cpustate));
|
||||
|
||||
INT_ACK = irqcallback;
|
||||
m37710i_cpu->device = device;
|
||||
m37710i_cpu->program = memory_find_address_space(device, ADDRESS_SPACE_PROGRAM);
|
||||
m37710i_cpu->io = memory_find_address_space(device, ADDRESS_SPACE_IO);
|
||||
cpustate->device = device;
|
||||
cpustate->program = memory_find_address_space(device, ADDRESS_SPACE_PROGRAM);
|
||||
cpustate->io = memory_find_address_space(device, ADDRESS_SPACE_IO);
|
||||
|
||||
m37710i_cpu->ICount = 0;
|
||||
cpustate->ICount = 0;
|
||||
|
||||
m37710i_cpu->source = 0;
|
||||
m37710i_cpu->destination = 0;
|
||||
cpustate->source = 0;
|
||||
cpustate->destination = 0;
|
||||
|
||||
for (i = 0; i < 8; i++)
|
||||
m37710i_cpu->timers[0] = timer_alloc(device->machine, m37710_timer_cb, m37710i_cpu);
|
||||
cpustate->timers[i] = timer_alloc(device->machine, m37710_timer_cb, cpustate);
|
||||
|
||||
state_save_register_item("M377xx", device->tag, 0, m37710i_cpu->a);
|
||||
state_save_register_item("M377xx", device->tag, 0, m37710i_cpu->b);
|
||||
state_save_register_item("M377xx", device->tag, 0, m37710i_cpu->ba);
|
||||
state_save_register_item("M377xx", device->tag, 0, m37710i_cpu->bb);
|
||||
state_save_register_item("M377xx", device->tag, 0, m37710i_cpu->x);
|
||||
state_save_register_item("M377xx", device->tag, 0, m37710i_cpu->y);
|
||||
state_save_register_item("M377xx", device->tag, 0, m37710i_cpu->s);
|
||||
state_save_register_item("M377xx", device->tag, 0, m37710i_cpu->pc);
|
||||
state_save_register_item("M377xx", device->tag, 0, m37710i_cpu->ppc);
|
||||
state_save_register_item("M377xx", device->tag, 0, m37710i_cpu->pb);
|
||||
state_save_register_item("M377xx", device->tag, 0, m37710i_cpu->db);
|
||||
state_save_register_item("M377xx", device->tag, 0, m37710i_cpu->d);
|
||||
state_save_register_item("M377xx", device->tag, 0, m37710i_cpu->flag_e);
|
||||
state_save_register_item("M377xx", device->tag, 0, m37710i_cpu->flag_m);
|
||||
state_save_register_item("M377xx", device->tag, 0, m37710i_cpu->flag_x);
|
||||
state_save_register_item("M377xx", device->tag, 0, m37710i_cpu->flag_n);
|
||||
state_save_register_item("M377xx", device->tag, 0, m37710i_cpu->flag_v);
|
||||
state_save_register_item("M377xx", device->tag, 0, m37710i_cpu->flag_d);
|
||||
state_save_register_item("M377xx", device->tag, 0, m37710i_cpu->flag_i);
|
||||
state_save_register_item("M377xx", device->tag, 0, m37710i_cpu->flag_z);
|
||||
state_save_register_item("M377xx", device->tag, 0, m37710i_cpu->flag_c);
|
||||
state_save_register_item("M377xx", device->tag, 0, m37710i_cpu->line_irq);
|
||||
state_save_register_item("M377xx", device->tag, 0, m37710i_cpu->ipl);
|
||||
state_save_register_item("M377xx", device->tag, 0, m37710i_cpu->ir);
|
||||
state_save_register_item("M377xx", device->tag, 0, m37710i_cpu->im);
|
||||
state_save_register_item("M377xx", device->tag, 0, m37710i_cpu->im2);
|
||||
state_save_register_item("M377xx", device->tag, 0, m37710i_cpu->im3);
|
||||
state_save_register_item("M377xx", device->tag, 0, m37710i_cpu->im4);
|
||||
state_save_register_item("M377xx", device->tag, 0, m37710i_cpu->irq_delay);
|
||||
state_save_register_item("M377xx", device->tag, 0, m37710i_cpu->irq_level);
|
||||
state_save_register_item("M377xx", device->tag, 0, m37710i_cpu->stopped);
|
||||
state_save_register_item_array("M377xx", device->tag, 0, m37710i_cpu->m37710_regs);
|
||||
state_save_register_item("M377xx", device->tag, 0, m37710i_cpu->reload[0].seconds);
|
||||
state_save_register_item("M377xx", device->tag, 0, m37710i_cpu->reload[0].attoseconds);
|
||||
state_save_register_item("M377xx", device->tag, 0, m37710i_cpu->reload[1].seconds);
|
||||
state_save_register_item("M377xx", device->tag, 0, m37710i_cpu->reload[1].attoseconds);
|
||||
state_save_register_item("M377xx", device->tag, 0, m37710i_cpu->reload[2].seconds);
|
||||
state_save_register_item("M377xx", device->tag, 0, m37710i_cpu->reload[2].attoseconds);
|
||||
state_save_register_item("M377xx", device->tag, 0, m37710i_cpu->reload[3].seconds);
|
||||
state_save_register_item("M377xx", device->tag, 0, m37710i_cpu->reload[3].attoseconds);
|
||||
state_save_register_item("M377xx", device->tag, 0, m37710i_cpu->reload[4].seconds);
|
||||
state_save_register_item("M377xx", device->tag, 0, m37710i_cpu->reload[4].attoseconds);
|
||||
state_save_register_item("M377xx", device->tag, 0, m37710i_cpu->reload[5].seconds);
|
||||
state_save_register_item("M377xx", device->tag, 0, m37710i_cpu->reload[5].attoseconds);
|
||||
state_save_register_item("M377xx", device->tag, 0, m37710i_cpu->reload[6].seconds);
|
||||
state_save_register_item("M377xx", device->tag, 0, m37710i_cpu->reload[6].attoseconds);
|
||||
state_save_register_item("M377xx", device->tag, 0, m37710i_cpu->reload[7].seconds);
|
||||
state_save_register_item("M377xx", device->tag, 0, m37710i_cpu->reload[7].attoseconds);
|
||||
state_save_register_item("M377xx", device->tag, 0, cpustate->a);
|
||||
state_save_register_item("M377xx", device->tag, 0, cpustate->b);
|
||||
state_save_register_item("M377xx", device->tag, 0, cpustate->ba);
|
||||
state_save_register_item("M377xx", device->tag, 0, cpustate->bb);
|
||||
state_save_register_item("M377xx", device->tag, 0, cpustate->x);
|
||||
state_save_register_item("M377xx", device->tag, 0, cpustate->y);
|
||||
state_save_register_item("M377xx", device->tag, 0, cpustate->s);
|
||||
state_save_register_item("M377xx", device->tag, 0, cpustate->pc);
|
||||
state_save_register_item("M377xx", device->tag, 0, cpustate->ppc);
|
||||
state_save_register_item("M377xx", device->tag, 0, cpustate->pb);
|
||||
state_save_register_item("M377xx", device->tag, 0, cpustate->db);
|
||||
state_save_register_item("M377xx", device->tag, 0, cpustate->d);
|
||||
state_save_register_item("M377xx", device->tag, 0, cpustate->flag_e);
|
||||
state_save_register_item("M377xx", device->tag, 0, cpustate->flag_m);
|
||||
state_save_register_item("M377xx", device->tag, 0, cpustate->flag_x);
|
||||
state_save_register_item("M377xx", device->tag, 0, cpustate->flag_n);
|
||||
state_save_register_item("M377xx", device->tag, 0, cpustate->flag_v);
|
||||
state_save_register_item("M377xx", device->tag, 0, cpustate->flag_d);
|
||||
state_save_register_item("M377xx", device->tag, 0, cpustate->flag_i);
|
||||
state_save_register_item("M377xx", device->tag, 0, cpustate->flag_z);
|
||||
state_save_register_item("M377xx", device->tag, 0, cpustate->flag_c);
|
||||
state_save_register_item("M377xx", device->tag, 0, cpustate->line_irq);
|
||||
state_save_register_item("M377xx", device->tag, 0, cpustate->ipl);
|
||||
state_save_register_item("M377xx", device->tag, 0, cpustate->ir);
|
||||
state_save_register_item("M377xx", device->tag, 0, cpustate->im);
|
||||
state_save_register_item("M377xx", device->tag, 0, cpustate->im2);
|
||||
state_save_register_item("M377xx", device->tag, 0, cpustate->im3);
|
||||
state_save_register_item("M377xx", device->tag, 0, cpustate->im4);
|
||||
state_save_register_item("M377xx", device->tag, 0, cpustate->irq_delay);
|
||||
state_save_register_item("M377xx", device->tag, 0, cpustate->irq_level);
|
||||
state_save_register_item("M377xx", device->tag, 0, cpustate->stopped);
|
||||
state_save_register_item_array("M377xx", device->tag, 0, cpustate->m37710_regs);
|
||||
state_save_register_item("M377xx", device->tag, 0, cpustate->reload[0].seconds);
|
||||
state_save_register_item("M377xx", device->tag, 0, cpustate->reload[0].attoseconds);
|
||||
state_save_register_item("M377xx", device->tag, 0, cpustate->reload[1].seconds);
|
||||
state_save_register_item("M377xx", device->tag, 0, cpustate->reload[1].attoseconds);
|
||||
state_save_register_item("M377xx", device->tag, 0, cpustate->reload[2].seconds);
|
||||
state_save_register_item("M377xx", device->tag, 0, cpustate->reload[2].attoseconds);
|
||||
state_save_register_item("M377xx", device->tag, 0, cpustate->reload[3].seconds);
|
||||
state_save_register_item("M377xx", device->tag, 0, cpustate->reload[3].attoseconds);
|
||||
state_save_register_item("M377xx", device->tag, 0, cpustate->reload[4].seconds);
|
||||
state_save_register_item("M377xx", device->tag, 0, cpustate->reload[4].attoseconds);
|
||||
state_save_register_item("M377xx", device->tag, 0, cpustate->reload[5].seconds);
|
||||
state_save_register_item("M377xx", device->tag, 0, cpustate->reload[5].attoseconds);
|
||||
state_save_register_item("M377xx", device->tag, 0, cpustate->reload[6].seconds);
|
||||
state_save_register_item("M377xx", device->tag, 0, cpustate->reload[6].attoseconds);
|
||||
state_save_register_item("M377xx", device->tag, 0, cpustate->reload[7].seconds);
|
||||
state_save_register_item("M377xx", device->tag, 0, cpustate->reload[7].attoseconds);
|
||||
|
||||
state_save_register_postload(device->machine, m37710_restore_state, m37710i_cpu);
|
||||
state_save_register_postload(device->machine, m37710_restore_state, cpustate);
|
||||
}
|
||||
|
||||
/**************************************************************************
|
||||
@ -1024,40 +1023,40 @@ static CPU_INIT( m37710 )
|
||||
|
||||
static CPU_SET_INFO( m37710 )
|
||||
{
|
||||
m37710i_cpu_struct *m37710i_cpu = device->token;
|
||||
m37710i_cpu_struct *cpustate = device->token;
|
||||
|
||||
switch (state)
|
||||
{
|
||||
/* --- the following bits of info are set as 64-bit signed integers --- */
|
||||
case CPUINFO_INT_INPUT_STATE + M37710_LINE_ADC: m37710_set_irq_line(m37710i_cpu, M37710_LINE_ADC, info->i); break;
|
||||
case CPUINFO_INT_INPUT_STATE + M37710_LINE_IRQ0: m37710_set_irq_line(m37710i_cpu, M37710_LINE_IRQ0, info->i); break;
|
||||
case CPUINFO_INT_INPUT_STATE + M37710_LINE_IRQ1: m37710_set_irq_line(m37710i_cpu, M37710_LINE_IRQ1, info->i); break;
|
||||
case CPUINFO_INT_INPUT_STATE + M37710_LINE_IRQ2: m37710_set_irq_line(m37710i_cpu, M37710_LINE_IRQ2, info->i); break;
|
||||
case CPUINFO_INT_INPUT_STATE + M37710_LINE_ADC: m37710_set_irq_line(cpustate, M37710_LINE_ADC, info->i); break;
|
||||
case CPUINFO_INT_INPUT_STATE + M37710_LINE_IRQ0: m37710_set_irq_line(cpustate, M37710_LINE_IRQ0, info->i); break;
|
||||
case CPUINFO_INT_INPUT_STATE + M37710_LINE_IRQ1: m37710_set_irq_line(cpustate, M37710_LINE_IRQ1, info->i); break;
|
||||
case CPUINFO_INT_INPUT_STATE + M37710_LINE_IRQ2: m37710_set_irq_line(cpustate, M37710_LINE_IRQ2, info->i); break;
|
||||
|
||||
case CPUINFO_INT_INPUT_STATE + M37710_LINE_TIMERA0TICK: m37710_external_tick(m37710i_cpu, state - CPUINFO_INT_INPUT_STATE - M37710_LINE_TIMERA0TICK, info->i); break;
|
||||
case CPUINFO_INT_INPUT_STATE + M37710_LINE_TIMERA1TICK: m37710_external_tick(m37710i_cpu, state - CPUINFO_INT_INPUT_STATE - M37710_LINE_TIMERA0TICK, info->i); break;
|
||||
case CPUINFO_INT_INPUT_STATE + M37710_LINE_TIMERA2TICK: m37710_external_tick(m37710i_cpu, state - CPUINFO_INT_INPUT_STATE - M37710_LINE_TIMERA0TICK, info->i); break;
|
||||
case CPUINFO_INT_INPUT_STATE + M37710_LINE_TIMERA3TICK: m37710_external_tick(m37710i_cpu, state - CPUINFO_INT_INPUT_STATE - M37710_LINE_TIMERA0TICK, info->i); break;
|
||||
case CPUINFO_INT_INPUT_STATE + M37710_LINE_TIMERA4TICK: m37710_external_tick(m37710i_cpu, state - CPUINFO_INT_INPUT_STATE - M37710_LINE_TIMERA0TICK, info->i); break;
|
||||
case CPUINFO_INT_INPUT_STATE + M37710_LINE_TIMERB0TICK: m37710_external_tick(m37710i_cpu, state - CPUINFO_INT_INPUT_STATE - M37710_LINE_TIMERA0TICK, info->i); break;
|
||||
case CPUINFO_INT_INPUT_STATE + M37710_LINE_TIMERB1TICK: m37710_external_tick(m37710i_cpu, state - CPUINFO_INT_INPUT_STATE - M37710_LINE_TIMERA0TICK, info->i); break;
|
||||
case CPUINFO_INT_INPUT_STATE + M37710_LINE_TIMERB2TICK: m37710_external_tick(m37710i_cpu, state - CPUINFO_INT_INPUT_STATE - M37710_LINE_TIMERA0TICK, info->i); break;
|
||||
case CPUINFO_INT_INPUT_STATE + M37710_LINE_TIMERA0TICK: m37710_external_tick(cpustate, state - CPUINFO_INT_INPUT_STATE - M37710_LINE_TIMERA0TICK, info->i); break;
|
||||
case CPUINFO_INT_INPUT_STATE + M37710_LINE_TIMERA1TICK: m37710_external_tick(cpustate, state - CPUINFO_INT_INPUT_STATE - M37710_LINE_TIMERA0TICK, info->i); break;
|
||||
case CPUINFO_INT_INPUT_STATE + M37710_LINE_TIMERA2TICK: m37710_external_tick(cpustate, state - CPUINFO_INT_INPUT_STATE - M37710_LINE_TIMERA0TICK, info->i); break;
|
||||
case CPUINFO_INT_INPUT_STATE + M37710_LINE_TIMERA3TICK: m37710_external_tick(cpustate, state - CPUINFO_INT_INPUT_STATE - M37710_LINE_TIMERA0TICK, info->i); break;
|
||||
case CPUINFO_INT_INPUT_STATE + M37710_LINE_TIMERA4TICK: m37710_external_tick(cpustate, state - CPUINFO_INT_INPUT_STATE - M37710_LINE_TIMERA0TICK, info->i); break;
|
||||
case CPUINFO_INT_INPUT_STATE + M37710_LINE_TIMERB0TICK: m37710_external_tick(cpustate, state - CPUINFO_INT_INPUT_STATE - M37710_LINE_TIMERA0TICK, info->i); break;
|
||||
case CPUINFO_INT_INPUT_STATE + M37710_LINE_TIMERB1TICK: m37710_external_tick(cpustate, state - CPUINFO_INT_INPUT_STATE - M37710_LINE_TIMERA0TICK, info->i); break;
|
||||
case CPUINFO_INT_INPUT_STATE + M37710_LINE_TIMERB2TICK: m37710_external_tick(cpustate, state - CPUINFO_INT_INPUT_STATE - M37710_LINE_TIMERA0TICK, info->i); break;
|
||||
|
||||
case CPUINFO_INT_PC: REG_PB = info->i & 0xff0000; m37710_set_pc(m37710i_cpu, info->i & 0xffff); break;
|
||||
case CPUINFO_INT_SP: m37710_set_sp(m37710i_cpu, info->i); break;
|
||||
case CPUINFO_INT_PC: REG_PB = info->i & 0xff0000; m37710_set_pc(cpustate, info->i & 0xffff); break;
|
||||
case CPUINFO_INT_SP: m37710_set_sp(cpustate, info->i); break;
|
||||
|
||||
case CPUINFO_INT_REGISTER + M37710_PC: m37710_set_reg(m37710i_cpu, M37710_PC, info->i); break;
|
||||
case CPUINFO_INT_REGISTER + M37710_S: m37710_set_reg(m37710i_cpu, M37710_S, info->i); break;
|
||||
case CPUINFO_INT_REGISTER + M37710_P: m37710_set_reg(m37710i_cpu, M37710_P, info->i&0xff); m37710i_cpu->ipl = (info->i>>8)&0xff; break;
|
||||
case CPUINFO_INT_REGISTER + M37710_A: m37710_set_reg(m37710i_cpu, M37710_A, info->i); break;
|
||||
case CPUINFO_INT_REGISTER + M37710_X: m37710_set_reg(m37710i_cpu, M37710_X, info->i); break;
|
||||
case CPUINFO_INT_REGISTER + M37710_Y: m37710_set_reg(m37710i_cpu, M37710_Y, info->i); break;
|
||||
case CPUINFO_INT_REGISTER + M37710_PB: m37710_set_reg(m37710i_cpu, M37710_PB, info->i); break;
|
||||
case CPUINFO_INT_REGISTER + M37710_DB: m37710_set_reg(m37710i_cpu, M37710_DB, info->i); break;
|
||||
case CPUINFO_INT_REGISTER + M37710_D: m37710_set_reg(m37710i_cpu, M37710_D, info->i); break;
|
||||
case CPUINFO_INT_REGISTER + M37710_E: m37710_set_reg(m37710i_cpu, M37710_E, info->i); break;
|
||||
case CPUINFO_INT_REGISTER + M37710_NMI_STATE: m37710_set_reg(m37710i_cpu, M37710_NMI_STATE, info->i); break;
|
||||
case CPUINFO_INT_REGISTER + M37710_IRQ_STATE: m37710_set_reg(m37710i_cpu, M37710_IRQ_STATE, info->i); break;
|
||||
case CPUINFO_INT_REGISTER + M37710_PC: m37710_set_reg(cpustate, M37710_PC, info->i); break;
|
||||
case CPUINFO_INT_REGISTER + M37710_S: m37710_set_reg(cpustate, M37710_S, info->i); break;
|
||||
case CPUINFO_INT_REGISTER + M37710_P: m37710_set_reg(cpustate, M37710_P, info->i&0xff); cpustate->ipl = (info->i>>8)&0xff; break;
|
||||
case CPUINFO_INT_REGISTER + M37710_A: m37710_set_reg(cpustate, M37710_A, info->i); break;
|
||||
case CPUINFO_INT_REGISTER + M37710_X: m37710_set_reg(cpustate, M37710_X, info->i); break;
|
||||
case CPUINFO_INT_REGISTER + M37710_Y: m37710_set_reg(cpustate, M37710_Y, info->i); break;
|
||||
case CPUINFO_INT_REGISTER + M37710_PB: m37710_set_reg(cpustate, M37710_PB, info->i); break;
|
||||
case CPUINFO_INT_REGISTER + M37710_DB: m37710_set_reg(cpustate, M37710_DB, info->i); break;
|
||||
case CPUINFO_INT_REGISTER + M37710_D: m37710_set_reg(cpustate, M37710_D, info->i); break;
|
||||
case CPUINFO_INT_REGISTER + M37710_E: m37710_set_reg(cpustate, M37710_E, info->i); break;
|
||||
case CPUINFO_INT_REGISTER + M37710_NMI_STATE: m37710_set_reg(cpustate, M37710_NMI_STATE, info->i); break;
|
||||
case CPUINFO_INT_REGISTER + M37710_IRQ_STATE: m37710_set_reg(cpustate, M37710_IRQ_STATE, info->i); break;
|
||||
}
|
||||
}
|
||||
|
||||
@ -1073,7 +1072,7 @@ ADDRESS_MAP_END
|
||||
|
||||
CPU_GET_INFO( m37710 )
|
||||
{
|
||||
m37710i_cpu_struct *m37710i_cpu = (device != NULL) ? device->token : NULL;
|
||||
m37710i_cpu_struct *cpustate = (device != NULL) ? device->token : NULL;
|
||||
|
||||
switch (state)
|
||||
{
|
||||
@ -1106,21 +1105,21 @@ CPU_GET_INFO( m37710 )
|
||||
|
||||
case CPUINFO_INT_PREVIOUSPC: info->i = REG_PPC; break;
|
||||
case CPUINFO_INT_PC: info->i = (REG_PB | REG_PC); break;
|
||||
case CPUINFO_INT_SP: info->i = m37710_get_sp(m37710i_cpu); break;
|
||||
case CPUINFO_INT_SP: info->i = m37710_get_sp(cpustate); break;
|
||||
|
||||
case CPUINFO_INT_REGISTER + M37710_PC: info->i = m37710_get_reg(m37710i_cpu, M37710_PC); break;
|
||||
case CPUINFO_INT_REGISTER + M37710_S: info->i = m37710_get_reg(m37710i_cpu, M37710_S); break;
|
||||
case CPUINFO_INT_REGISTER + M37710_P: info->i = m37710_get_reg(m37710i_cpu, M37710_P) | (m37710i_cpu->ipl<<8); break;
|
||||
case CPUINFO_INT_REGISTER + M37710_A: info->i = m37710_get_reg(m37710i_cpu, M37710_A); break;
|
||||
case CPUINFO_INT_REGISTER + M37710_B: info->i = m37710_get_reg(m37710i_cpu, M37710_B); break;
|
||||
case CPUINFO_INT_REGISTER + M37710_X: info->i = m37710_get_reg(m37710i_cpu, M37710_X); break;
|
||||
case CPUINFO_INT_REGISTER + M37710_Y: info->i = m37710_get_reg(m37710i_cpu, M37710_Y); break;
|
||||
case CPUINFO_INT_REGISTER + M37710_PB: info->i = m37710_get_reg(m37710i_cpu, M37710_PB); break;
|
||||
case CPUINFO_INT_REGISTER + M37710_DB: info->i = m37710_get_reg(m37710i_cpu, M37710_DB); break;
|
||||
case CPUINFO_INT_REGISTER + M37710_D: info->i = m37710_get_reg(m37710i_cpu, M37710_D); break;
|
||||
case CPUINFO_INT_REGISTER + M37710_E: info->i = m37710_get_reg(m37710i_cpu, M37710_E); break;
|
||||
case CPUINFO_INT_REGISTER + M37710_NMI_STATE: info->i = m37710_get_reg(m37710i_cpu, M37710_NMI_STATE); break;
|
||||
case CPUINFO_INT_REGISTER + M37710_IRQ_STATE: info->i = m37710_get_reg(m37710i_cpu, M37710_IRQ_STATE); break;
|
||||
case CPUINFO_INT_REGISTER + M37710_PC: info->i = m37710_get_reg(cpustate, M37710_PC); break;
|
||||
case CPUINFO_INT_REGISTER + M37710_S: info->i = m37710_get_reg(cpustate, M37710_S); break;
|
||||
case CPUINFO_INT_REGISTER + M37710_P: info->i = m37710_get_reg(cpustate, M37710_P) | (cpustate->ipl<<8); break;
|
||||
case CPUINFO_INT_REGISTER + M37710_A: info->i = m37710_get_reg(cpustate, M37710_A); break;
|
||||
case CPUINFO_INT_REGISTER + M37710_B: info->i = m37710_get_reg(cpustate, M37710_B); break;
|
||||
case CPUINFO_INT_REGISTER + M37710_X: info->i = m37710_get_reg(cpustate, M37710_X); break;
|
||||
case CPUINFO_INT_REGISTER + M37710_Y: info->i = m37710_get_reg(cpustate, M37710_Y); break;
|
||||
case CPUINFO_INT_REGISTER + M37710_PB: info->i = m37710_get_reg(cpustate, M37710_PB); break;
|
||||
case CPUINFO_INT_REGISTER + M37710_DB: info->i = m37710_get_reg(cpustate, M37710_DB); break;
|
||||
case CPUINFO_INT_REGISTER + M37710_D: info->i = m37710_get_reg(cpustate, M37710_D); break;
|
||||
case CPUINFO_INT_REGISTER + M37710_E: info->i = m37710_get_reg(cpustate, M37710_E); break;
|
||||
case CPUINFO_INT_REGISTER + M37710_NMI_STATE: info->i = m37710_get_reg(cpustate, M37710_NMI_STATE); break;
|
||||
case CPUINFO_INT_REGISTER + M37710_IRQ_STATE: info->i = m37710_get_reg(cpustate, M37710_IRQ_STATE); break;
|
||||
|
||||
/* --- the following bits of info are returned as pointers to data or functions --- */
|
||||
case CPUINFO_PTR_SET_INFO: info->setinfo = CPU_SET_INFO_NAME(m37710); break;
|
||||
@ -1132,7 +1131,7 @@ CPU_GET_INFO( m37710 )
|
||||
case CPUINFO_PTR_EXECUTE: info->execute = CPU_EXECUTE_NAME(m37710); break;
|
||||
case CPUINFO_PTR_BURN: info->burn = NULL; break;
|
||||
case CPUINFO_PTR_DISASSEMBLE: info->disassemble = CPU_DISASSEMBLE_NAME(m37710); break;
|
||||
case CPUINFO_PTR_INSTRUCTION_COUNTER: info->icount = &m37710i_cpu->ICount; break;
|
||||
case CPUINFO_PTR_INSTRUCTION_COUNTER: info->icount = &cpustate->ICount; break;
|
||||
|
||||
case CPUINFO_PTR_INTERNAL_MEMORY_MAP + ADDRESS_SPACE_PROGRAM: info->internal_map16 = ADDRESS_MAP_NAME(m37710_internal_map); break;
|
||||
case CPUINFO_PTR_INTERNAL_MEMORY_MAP + ADDRESS_SPACE_DATA: info->internal_map16 = NULL; break;
|
||||
@ -1147,36 +1146,36 @@ CPU_GET_INFO( m37710 )
|
||||
|
||||
case CPUINFO_STR_FLAGS:
|
||||
sprintf(info->s, "%c%c%c%c%c%c%c%c",
|
||||
m37710i_cpu->flag_n & NFLAG_SET ? 'N':'.',
|
||||
m37710i_cpu->flag_v & VFLAG_SET ? 'V':'.',
|
||||
m37710i_cpu->flag_m & MFLAG_SET ? 'M':'.',
|
||||
m37710i_cpu->flag_x & XFLAG_SET ? 'X':'.',
|
||||
m37710i_cpu->flag_d & DFLAG_SET ? 'D':'.',
|
||||
m37710i_cpu->flag_i & IFLAG_SET ? 'I':'.',
|
||||
m37710i_cpu->flag_z == 0 ? 'Z':'.',
|
||||
m37710i_cpu->flag_c & CFLAG_SET ? 'C':'.');
|
||||
cpustate->flag_n & NFLAG_SET ? 'N':'.',
|
||||
cpustate->flag_v & VFLAG_SET ? 'V':'.',
|
||||
cpustate->flag_m & MFLAG_SET ? 'M':'.',
|
||||
cpustate->flag_x & XFLAG_SET ? 'X':'.',
|
||||
cpustate->flag_d & DFLAG_SET ? 'D':'.',
|
||||
cpustate->flag_i & IFLAG_SET ? 'I':'.',
|
||||
cpustate->flag_z == 0 ? 'Z':'.',
|
||||
cpustate->flag_c & CFLAG_SET ? 'C':'.');
|
||||
break;
|
||||
|
||||
case CPUINFO_STR_REGISTER + M37710_PC: sprintf(info->s, "PC:%04X", m37710i_cpu->pc); break;
|
||||
case CPUINFO_STR_REGISTER + M37710_PB: sprintf(info->s, "PB:%02X", m37710i_cpu->pb>>16); break;
|
||||
case CPUINFO_STR_REGISTER + M37710_DB: sprintf(info->s, "DB:%02X", m37710i_cpu->db>>16); break;
|
||||
case CPUINFO_STR_REGISTER + M37710_D: sprintf(info->s, "D:%04X", m37710i_cpu->d); break;
|
||||
case CPUINFO_STR_REGISTER + M37710_S: sprintf(info->s, "S:%04X", m37710i_cpu->s); break;
|
||||
case CPUINFO_STR_REGISTER + M37710_PC: sprintf(info->s, "PC:%04X", cpustate->pc); break;
|
||||
case CPUINFO_STR_REGISTER + M37710_PB: sprintf(info->s, "PB:%02X", cpustate->pb>>16); break;
|
||||
case CPUINFO_STR_REGISTER + M37710_DB: sprintf(info->s, "DB:%02X", cpustate->db>>16); break;
|
||||
case CPUINFO_STR_REGISTER + M37710_D: sprintf(info->s, "D:%04X", cpustate->d); break;
|
||||
case CPUINFO_STR_REGISTER + M37710_S: sprintf(info->s, "S:%04X", cpustate->s); break;
|
||||
case CPUINFO_STR_REGISTER + M37710_P: sprintf(info->s, "P:%04X",
|
||||
(m37710i_cpu->flag_n&0x80) |
|
||||
((m37710i_cpu->flag_v>>1)&0x40) |
|
||||
m37710i_cpu->flag_m |
|
||||
m37710i_cpu->flag_x |
|
||||
m37710i_cpu->flag_d |
|
||||
m37710i_cpu->flag_i |
|
||||
((!m37710i_cpu->flag_z)<<1) |
|
||||
((m37710i_cpu->flag_c>>8)&1) | (m37710i_cpu->ipl<<8)); break;
|
||||
case CPUINFO_STR_REGISTER + M37710_E: sprintf(info->s, "E:%d", m37710i_cpu->flag_e); break;
|
||||
case CPUINFO_STR_REGISTER + M37710_A: sprintf(info->s, "A:%04X", m37710i_cpu->a | m37710i_cpu->b); break;
|
||||
case CPUINFO_STR_REGISTER + M37710_B: sprintf(info->s, "B:%04X", m37710i_cpu->ba | m37710i_cpu->bb); break;
|
||||
case CPUINFO_STR_REGISTER + M37710_X: sprintf(info->s, "X:%04X", m37710i_cpu->x); break;
|
||||
case CPUINFO_STR_REGISTER + M37710_Y: sprintf(info->s, "Y:%04X", m37710i_cpu->y); break;
|
||||
case CPUINFO_STR_REGISTER + M37710_IRQ_STATE: sprintf(info->s, "IRQ:%X", m37710i_cpu->line_irq); break;
|
||||
(cpustate->flag_n&0x80) |
|
||||
((cpustate->flag_v>>1)&0x40) |
|
||||
cpustate->flag_m |
|
||||
cpustate->flag_x |
|
||||
cpustate->flag_d |
|
||||
cpustate->flag_i |
|
||||
((!cpustate->flag_z)<<1) |
|
||||
((cpustate->flag_c>>8)&1) | (cpustate->ipl<<8)); break;
|
||||
case CPUINFO_STR_REGISTER + M37710_E: sprintf(info->s, "E:%d", cpustate->flag_e); break;
|
||||
case CPUINFO_STR_REGISTER + M37710_A: sprintf(info->s, "A:%04X", cpustate->a | cpustate->b); break;
|
||||
case CPUINFO_STR_REGISTER + M37710_B: sprintf(info->s, "B:%04X", cpustate->ba | cpustate->bb); break;
|
||||
case CPUINFO_STR_REGISTER + M37710_X: sprintf(info->s, "X:%04X", cpustate->x); break;
|
||||
case CPUINFO_STR_REGISTER + M37710_Y: sprintf(info->s, "Y:%04X", cpustate->y); break;
|
||||
case CPUINFO_STR_REGISTER + M37710_IRQ_STATE: sprintf(info->s, "IRQ:%X", cpustate->line_irq); break;
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
@ -100,12 +100,12 @@ void m37710_state_load(void *file);
|
||||
|
||||
#undef M37710_CALL_DEBUGGER
|
||||
|
||||
#define M37710_CALL_DEBUGGER(x) debugger_instruction_hook(m37710i_cpu->device, x)
|
||||
#define m37710_read_8(addr) memory_read_byte_16le(m37710i_cpu->program, addr)
|
||||
#define m37710_write_8(addr,data) memory_write_byte_16le(m37710i_cpu->program, addr,data)
|
||||
#define m37710_read_8_immediate(A) memory_read_byte_16le(m37710i_cpu->program, A)
|
||||
#define m37710_read_16(addr) memory_read_word_16le(m37710i_cpu->program, addr)
|
||||
#define m37710_write_16(addr,data) memory_write_word_16le(m37710i_cpu->program, addr,data)
|
||||
#define M37710_CALL_DEBUGGER(x) debugger_instruction_hook(cpustate->device, x)
|
||||
#define m37710_read_8(addr) memory_read_byte_16le(cpustate->program, addr)
|
||||
#define m37710_write_8(addr,data) memory_write_byte_16le(cpustate->program, addr,data)
|
||||
#define m37710_read_8_immediate(A) memory_read_byte_16le(cpustate->program, A)
|
||||
#define m37710_read_16(addr) memory_read_word_16le(cpustate->program, addr)
|
||||
#define m37710_write_16(addr,data) memory_write_word_16le(cpustate->program, addr,data)
|
||||
#define m37710_jumping(A)
|
||||
#define m37710_branching(A)
|
||||
|
||||
|
||||
@ -104,13 +104,13 @@ struct _m37710i_cpu_struct
|
||||
const address_space *program;
|
||||
const address_space *io;
|
||||
uint stopped; /* Sets how the CPU is stopped */
|
||||
void (*const *opcodes)(m37710i_cpu_struct *m37710i_cpu); /* opcodes with no prefix */
|
||||
void (*const *opcodes42)(m37710i_cpu_struct *m37710i_cpu); /* opcodes with 0x42 prefix */
|
||||
void (*const *opcodes89)(m37710i_cpu_struct *m37710i_cpu); /* opcodes with 0x89 prefix */
|
||||
uint (*get_reg)(m37710i_cpu_struct *m37710i_cpu, int regnum);
|
||||
void (*set_reg)(m37710i_cpu_struct *m37710i_cpu, int regnum, uint val);
|
||||
void (*set_line)(m37710i_cpu_struct *m37710i_cpu, int line, int state);
|
||||
int (*execute)(m37710i_cpu_struct *m37710i_cpu, int cycles);
|
||||
void (*const *opcodes)(m37710i_cpu_struct *cpustate); /* opcodes with no prefix */
|
||||
void (*const *opcodes42)(m37710i_cpu_struct *cpustate); /* opcodes with 0x42 prefix */
|
||||
void (*const *opcodes89)(m37710i_cpu_struct *cpustate); /* opcodes with 0x89 prefix */
|
||||
uint (*get_reg)(m37710i_cpu_struct *cpustate, int regnum);
|
||||
void (*set_reg)(m37710i_cpu_struct *cpustate, int regnum, uint val);
|
||||
void (*set_line)(m37710i_cpu_struct *cpustate, int line, int state);
|
||||
int (*execute)(m37710i_cpu_struct *cpustate, int cycles);
|
||||
|
||||
// on-board peripheral stuff
|
||||
UINT8 m37710_regs[128];
|
||||
@ -122,51 +122,51 @@ struct _m37710i_cpu_struct
|
||||
extern uint m37710i_adc_tbl[];
|
||||
extern uint m37710i_sbc_tbl[];
|
||||
|
||||
extern void (*const *const m37710i_opcodes[])(m37710i_cpu_struct *m37710i_cpu);
|
||||
extern void (*const *const m37710i_opcodes2[])(m37710i_cpu_struct *m37710i_cpu);
|
||||
extern void (*const *const m37710i_opcodes3[])(m37710i_cpu_struct *m37710i_cpu);
|
||||
extern uint (*const m37710i_get_reg[])(m37710i_cpu_struct *m37710i_cpu,int regnum);
|
||||
extern void (*const m37710i_set_reg[])(m37710i_cpu_struct *m37710i_cpu,int regnum, uint val);
|
||||
extern void (*const m37710i_set_line[])(m37710i_cpu_struct *m37710i_cpu,int line, int state);
|
||||
extern int (*const m37710i_execute[])(m37710i_cpu_struct *m37710i_cpu, int cycles);
|
||||
extern void (*const *const m37710i_opcodes[])(m37710i_cpu_struct *cpustate);
|
||||
extern void (*const *const m37710i_opcodes2[])(m37710i_cpu_struct *cpustate);
|
||||
extern void (*const *const m37710i_opcodes3[])(m37710i_cpu_struct *cpustate);
|
||||
extern uint (*const m37710i_get_reg[])(m37710i_cpu_struct *cpustate,int regnum);
|
||||
extern void (*const m37710i_set_reg[])(m37710i_cpu_struct *cpustate,int regnum, uint val);
|
||||
extern void (*const m37710i_set_line[])(m37710i_cpu_struct *cpustate,int line, int state);
|
||||
extern int (*const m37710i_execute[])(m37710i_cpu_struct *cpustate, int cycles);
|
||||
|
||||
#define REG_A m37710i_cpu->a /* Accumulator */
|
||||
#define REG_B m37710i_cpu->b /* Accumulator hi byte */
|
||||
#define REG_BA m37710i_cpu->ba /* Secondary Accumulator */
|
||||
#define REG_BB m37710i_cpu->bb /* Secondary Accumulator hi byte */
|
||||
#define REG_X m37710i_cpu->x /* Index X Register */
|
||||
#define REG_Y m37710i_cpu->y /* Index Y Register */
|
||||
#define REG_S m37710i_cpu->s /* Stack Pointer */
|
||||
#define REG_PC m37710i_cpu->pc /* Program Counter */
|
||||
#define REG_PPC m37710i_cpu->ppc /* Previous Program Counter */
|
||||
#define REG_PB m37710i_cpu->pb /* Program Bank */
|
||||
#define REG_DB m37710i_cpu->db /* Data Bank */
|
||||
#define REG_D m37710i_cpu->d /* Direct Register */
|
||||
#define FLAG_M m37710i_cpu->flag_m /* Memory/Accumulator Select Flag */
|
||||
#define FLAG_X m37710i_cpu->flag_x /* Index Select Flag */
|
||||
#define FLAG_N m37710i_cpu->flag_n /* Negative Flag */
|
||||
#define FLAG_V m37710i_cpu->flag_v /* Overflow Flag */
|
||||
#define FLAG_D m37710i_cpu->flag_d /* Decimal Mode Flag */
|
||||
#define FLAG_I m37710i_cpu->flag_i /* Interrupt Mask Flag */
|
||||
#define FLAG_Z m37710i_cpu->flag_z /* Zero Flag (inverted) */
|
||||
#define FLAG_C m37710i_cpu->flag_c /* Carry Flag */
|
||||
#define LINE_IRQ m37710i_cpu->line_irq /* Status of the IRQ line */
|
||||
#define REG_IR m37710i_cpu->ir /* Instruction Register */
|
||||
#define REG_IM m37710i_cpu->im /* Immediate load value */
|
||||
#define REG_IM2 m37710i_cpu->im2 /* Immediate load target */
|
||||
#define REG_IM3 m37710i_cpu->im3 /* Immediate load target */
|
||||
#define REG_IM4 m37710i_cpu->im4 /* Immediate load target */
|
||||
#define INT_ACK m37710i_cpu->int_ack /* Interrupt Acknowledge function pointer */
|
||||
#define CLOCKS m37710i_cpu->ICount /* Clock cycles remaining */
|
||||
#define IRQ_DELAY m37710i_cpu->irq_delay /* Delay 1 instruction before checking IRQ */
|
||||
#define CPU_STOPPED m37710i_cpu->stopped /* Stopped status of the CPU */
|
||||
#define REG_A cpustate->a /* Accumulator */
|
||||
#define REG_B cpustate->b /* Accumulator hi byte */
|
||||
#define REG_BA cpustate->ba /* Secondary Accumulator */
|
||||
#define REG_BB cpustate->bb /* Secondary Accumulator hi byte */
|
||||
#define REG_X cpustate->x /* Index X Register */
|
||||
#define REG_Y cpustate->y /* Index Y Register */
|
||||
#define REG_S cpustate->s /* Stack Pointer */
|
||||
#define REG_PC cpustate->pc /* Program Counter */
|
||||
#define REG_PPC cpustate->ppc /* Previous Program Counter */
|
||||
#define REG_PB cpustate->pb /* Program Bank */
|
||||
#define REG_DB cpustate->db /* Data Bank */
|
||||
#define REG_D cpustate->d /* Direct Register */
|
||||
#define FLAG_M cpustate->flag_m /* Memory/Accumulator Select Flag */
|
||||
#define FLAG_X cpustate->flag_x /* Index Select Flag */
|
||||
#define FLAG_N cpustate->flag_n /* Negative Flag */
|
||||
#define FLAG_V cpustate->flag_v /* Overflow Flag */
|
||||
#define FLAG_D cpustate->flag_d /* Decimal Mode Flag */
|
||||
#define FLAG_I cpustate->flag_i /* Interrupt Mask Flag */
|
||||
#define FLAG_Z cpustate->flag_z /* Zero Flag (inverted) */
|
||||
#define FLAG_C cpustate->flag_c /* Carry Flag */
|
||||
#define LINE_IRQ cpustate->line_irq /* Status of the IRQ line */
|
||||
#define REG_IR cpustate->ir /* Instruction Register */
|
||||
#define REG_IM cpustate->im /* Immediate load value */
|
||||
#define REG_IM2 cpustate->im2 /* Immediate load target */
|
||||
#define REG_IM3 cpustate->im3 /* Immediate load target */
|
||||
#define REG_IM4 cpustate->im4 /* Immediate load target */
|
||||
#define INT_ACK cpustate->int_ack /* Interrupt Acknowledge function pointer */
|
||||
#define CLOCKS cpustate->ICount /* Clock cycles remaining */
|
||||
#define IRQ_DELAY cpustate->irq_delay /* Delay 1 instruction before checking IRQ */
|
||||
#define CPU_STOPPED cpustate->stopped /* Stopped status of the CPU */
|
||||
|
||||
#define FTABLE_GET_REG m37710i_cpu->get_reg
|
||||
#define FTABLE_SET_REG m37710i_cpu->set_reg
|
||||
#define FTABLE_SET_LINE m37710i_cpu->set_line
|
||||
#define FTABLE_GET_REG cpustate->get_reg
|
||||
#define FTABLE_SET_REG cpustate->set_reg
|
||||
#define FTABLE_SET_LINE cpustate->set_line
|
||||
|
||||
#define SRC m37710i_cpu->source /* Source Operand */
|
||||
#define DST m37710i_cpu->destination /* Destination Operand */
|
||||
#define SRC cpustate->source /* Source Operand */
|
||||
#define DST cpustate->destination /* Destination Operand */
|
||||
|
||||
#define STOP_LEVEL_WAI 1
|
||||
#define STOP_LEVEL_STOP 2
|
||||
@ -176,15 +176,15 @@ extern int (*const m37710i_execute[])(m37710i_cpu_struct *m37710i_cpu, int cycle
|
||||
#define EXECUTION_MODE_M1X0 2
|
||||
#define EXECUTION_MODE_M1X1 3
|
||||
|
||||
INLINE void m37710i_set_execution_mode(m37710i_cpu_struct *m37710i_cpu, uint mode)
|
||||
INLINE void m37710i_set_execution_mode(m37710i_cpu_struct *cpustate, uint mode)
|
||||
{
|
||||
m37710i_cpu->opcodes = m37710i_opcodes[mode];
|
||||
m37710i_cpu->opcodes42 = m37710i_opcodes2[mode];
|
||||
m37710i_cpu->opcodes89 = m37710i_opcodes3[mode];
|
||||
cpustate->opcodes = m37710i_opcodes[mode];
|
||||
cpustate->opcodes42 = m37710i_opcodes2[mode];
|
||||
cpustate->opcodes89 = m37710i_opcodes3[mode];
|
||||
FTABLE_GET_REG = m37710i_get_reg[mode];
|
||||
FTABLE_SET_REG = m37710i_set_reg[mode];
|
||||
FTABLE_SET_LINE = m37710i_set_line[mode];
|
||||
m37710i_cpu->execute = m37710i_execute[mode];
|
||||
cpustate->execute = m37710i_execute[mode];
|
||||
}
|
||||
|
||||
/* ======================================================================== */
|
||||
@ -312,7 +312,7 @@ INLINE void m37710i_set_execution_mode(m37710i_cpu_struct *m37710i_cpu, uint mod
|
||||
#define CFLAG_AS_1() ((FLAG_C>>8)&1)
|
||||
|
||||
/* update IRQ state (internal use only) */
|
||||
void m37710i_update_irqs(m37710i_cpu_struct *m37710i_cpu);
|
||||
void m37710i_update_irqs(m37710i_cpu_struct *cpustate);
|
||||
|
||||
/* ======================================================================== */
|
||||
/* ================================== CPU ================================= */
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
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Reference in New Issue
Block a user