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svga_s3: added CLKSYN test register (SR17), gets stock Trio64V2/DX BIOS to boot. (no whatsnew)
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@ -16,7 +16,7 @@ ROM_START( s3_764 )
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ROM_IGNORE( 0x8000 )
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// The following are from Trio64V2/DX based cards
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ROM_SYSTEM_BIOS( 1, "s3_9503", "PCI S3 9503-62 (S3 Trio64V2/DX)" )
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ROM_SYSTEM_BIOS( 1, "trio64v2", "PCI S3 86C765 v1.03-08N (S3 Trio64V2/DX)" )
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ROMX_LOAD("pci_9503-62_s3.bin", 0x00000, 0x8000, CRC(0e9d79d8) SHA1(274b5b98cc998f2783567000cdb12b14308bc290), ROM_BIOS(2) )
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ROM_SYSTEM_BIOS( 2, "winner1k", "PCI Elsa Winner 1000/T2D 6.01.00 (S3 Trio64V2/DX)" )
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@ -2005,6 +2005,8 @@ void s3_vga_device::device_reset()
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// Power-on strapping bits. Sampled at reset, but can be modified later.
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// These are just assumed defaults.
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s3.strapping = 0x000f0b1e;
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s3.sr10 = 0x42;
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s3.sr11 = 0x41;
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}
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READ8_MEMBER(vga_device::mem_r)
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@ -3241,6 +3243,10 @@ UINT8 s3_vga_device::s3_seq_reg_read(UINT8 index)
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case 0x15:
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res = s3.sr15;
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break;
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case 0x17:
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res = s3.sr17; // CLKSYN test register
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s3.sr17--; // who knows what it should return, docs only say it defaults to 0, and is reserved for testing of the clock synthesiser
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break;
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}
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}
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@ -584,6 +584,7 @@ protected:
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UINT8 sr12; // DCLK PLL
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UINT8 sr13; // DCLK PLL
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UINT8 sr15; // CLKSYN control 2
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UINT8 sr17; // CLKSYN test
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UINT8 clk_pll_r; // individual DCLK PLL values
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UINT8 clk_pll_m;
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UINT8 clk_pll_n;
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