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svga_s3: added CLKSYN test register (SR17), gets stock Trio64V2/DX BIOS to boot. (no whatsnew)

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This commit is contained in:
mahlemiut 2014-09-07 10:18:41 +00:00
parent 2840edff6f
commit 602ff95946
3 changed files with 8 additions and 1 deletions
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2
src/emu/bus/isa/svga_s3.c
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@ -16,7 +16,7 @@ ROM_START( s3_764 )
ROM_IGNORE( 0x8000 ) ROM_IGNORE( 0x8000 )
// The following are from Trio64V2/DX based cards // The following are from Trio64V2/DX based cards
ROM_SYSTEM_BIOS( 1, "s3_9503", "PCI S3 9503-62 (S3 Trio64V2/DX)" ) ROM_SYSTEM_BIOS( 1, "trio64v2", "PCI S3 86C765 v1.03-08N (S3 Trio64V2/DX)" )
ROMX_LOAD("pci_9503-62_s3.bin", 0x00000, 0x8000, CRC(0e9d79d8) SHA1(274b5b98cc998f2783567000cdb12b14308bc290), ROM_BIOS(2) ) ROMX_LOAD("pci_9503-62_s3.bin", 0x00000, 0x8000, CRC(0e9d79d8) SHA1(274b5b98cc998f2783567000cdb12b14308bc290), ROM_BIOS(2) )
ROM_SYSTEM_BIOS( 2, "winner1k", "PCI Elsa Winner 1000/T2D 6.01.00 (S3 Trio64V2/DX)" ) ROM_SYSTEM_BIOS( 2, "winner1k", "PCI Elsa Winner 1000/T2D 6.01.00 (S3 Trio64V2/DX)" )

6
src/emu/video/pc_vga.c
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@ -2005,6 +2005,8 @@ void s3_vga_device::device_reset()
// Power-on strapping bits. Sampled at reset, but can be modified later. // Power-on strapping bits. Sampled at reset, but can be modified later.
// These are just assumed defaults. // These are just assumed defaults.
s3.strapping = 0x000f0b1e; s3.strapping = 0x000f0b1e;
s3.sr10 = 0x42;
s3.sr11 = 0x41;
} }
READ8_MEMBER(vga_device::mem_r) READ8_MEMBER(vga_device::mem_r)
@ -3241,6 +3243,10 @@ UINT8 s3_vga_device::s3_seq_reg_read(UINT8 index)
case 0x15: case 0x15:
res = s3.sr15; res = s3.sr15;
break; break;
case 0x17:
res = s3.sr17; // CLKSYN test register
s3.sr17--; // who knows what it should return, docs only say it defaults to 0, and is reserved for testing of the clock synthesiser
break;
} }
} }

1
src/emu/video/pc_vga.h
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@ -584,6 +584,7 @@ protected:
UINT8 sr12; // DCLK PLL UINT8 sr12; // DCLK PLL
UINT8 sr13; // DCLK PLL UINT8 sr13; // DCLK PLL
UINT8 sr15; // CLKSYN control 2 UINT8 sr15; // CLKSYN control 2
UINT8 sr17; // CLKSYN test
UINT8 clk_pll_r; // individual DCLK PLL values UINT8 clk_pll_r; // individual DCLK PLL values
UINT8 clk_pll_m; UINT8 clk_pll_m;
UINT8 clk_pll_n; UINT8 clk_pll_n;