mirror of
https://github.com/holub/mame
synced 2025-04-23 00:39:36 +03:00
z8002: Correct width of I/O space (16-bit, not 8-bit)
This commit is contained in:
AJR
parent
19b87b747b
commit
626194e842
@ -27,19 +27,19 @@ DEFINE_DEVICE_TYPE(Z8002, z8002_device, "z8002", "Zilog Z8002")
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z8002_device::z8002_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock)
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: z8002_device(mconfig, Z8002, tag, owner, clock, 16, 8, 1)
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: z8002_device(mconfig, Z8002, tag, owner, clock, 16, 1)
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{
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}
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z8002_device::z8002_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, uint32_t clock, int addrbits, int iobits, int vecmult)
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z8002_device::z8002_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, uint32_t clock, int addrbits, int vecmult)
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: cpu_device(mconfig, type, tag, owner, clock)
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, m_program_config("program", ENDIANNESS_BIG, 16, addrbits, 0)
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, m_data_config("data", ENDIANNESS_BIG, 16, addrbits, 0)
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, m_io_config("I/O", ENDIANNESS_BIG, iobits, 16, 0)
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, m_io_config("I/O", ENDIANNESS_BIG, 16, 16, 0)
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, m_opcodes_config("first word", ENDIANNESS_BIG, 16, addrbits, 0)
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, m_stack_config("stack", ENDIANNESS_BIG, 16, addrbits, 0)
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, m_sio_config("special I/O", ENDIANNESS_BIG, iobits, 16, 0)
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, m_sio_config("special I/O", ENDIANNESS_BIG, 16, 16, 0)
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, m_iack_in(*this)
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, m_mo_out(*this)
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, m_ppc(0), m_pc(0), m_psapseg(0), m_psapoff(0), m_fcw(0), m_refresh(0), m_nspseg(0), m_nspoff(0), m_irq_req(0), m_irq_vec(0), m_op_valid(0), m_nmi_state(0), m_mi(0), m_halt(false), m_program(nullptr), m_data(nullptr), m_cache(nullptr), m_io(nullptr), m_icount(0)
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@ -49,7 +49,7 @@ z8002_device::z8002_device(const machine_config &mconfig, device_type type, cons
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z8001_device::z8001_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock)
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: z8002_device(mconfig, Z8001, tag, owner, clock, 20, 16, 2)
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: z8002_device(mconfig, Z8001, tag, owner, clock, 20, 2)
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{
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}
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@ -258,21 +258,6 @@ uint8_t z8002_device::RDPORT_B(int mode, uint16_t addr)
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}
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uint16_t z8002_device::RDPORT_W(int mode, uint16_t addr)
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{
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if(mode == 0)
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{
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// FIXME: this should perform a 16-bit big-endian word read
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return m_io->read_byte((uint16_t)(addr)) +
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(m_io->read_byte((uint16_t)(addr+1)) << 8);
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}
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else
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{
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/* how to handle MMU reads? */
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return m_sio->read_word_unaligned((uint16_t)addr);
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}
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}
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uint16_t z8001_device::RDPORT_W(int mode, uint16_t addr)
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{
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if(mode == 0)
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{
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@ -299,21 +284,6 @@ void z8002_device::WRPORT_B(int mode, uint16_t addr, uint8_t value)
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}
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void z8002_device::WRPORT_W(int mode, uint16_t addr, uint16_t value)
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{
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if(mode == 0)
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{
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// FIXME: this should perform a 16-bit big-endian word write
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m_io->write_byte((uint16_t)(addr),value & 0xff);
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m_io->write_byte((uint16_t)(addr+1),(value >> 8) & 0xff);
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}
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else
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{
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/* how to handle MMU writes? */
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m_sio->write_word_unaligned((uint16_t)addr, value);
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}
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}
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void z8001_device::WRPORT_W(int mode, uint16_t addr, uint16_t value)
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{
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if(mode == 0)
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{
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@ -58,7 +58,7 @@ public:
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DECLARE_WRITE_LINE_MEMBER(mi_w) { m_mi = state; } // XXX: this has to apply in the middle of an insn for now
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protected:
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z8002_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, uint32_t clock, int addrbits, int iobits, int vecmult);
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z8002_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, uint32_t clock, int addrbits, int vecmult);
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// device-level overrides
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virtual void device_start() override;
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@ -145,9 +145,9 @@ protected:
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inline void WRMEM_W(address_space &space, uint32_t addr, uint16_t value);
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inline void WRMEM_L(address_space &space, uint32_t addr, uint32_t value);
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inline uint8_t RDPORT_B(int mode, uint16_t addr);
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virtual uint16_t RDPORT_W(int mode, uint16_t addr);
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inline uint16_t RDPORT_W(int mode, uint16_t addr);
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inline void WRPORT_B(int mode, uint16_t addr, uint8_t value);
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virtual void WRPORT_W(int mode, uint16_t addr, uint16_t value);
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inline void WRPORT_W(int mode, uint16_t addr, uint16_t value);
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inline void cycles(int cycles);
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virtual void PUSH_PC();
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virtual void CHANGE_FCW(uint16_t fcw);
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@ -683,8 +683,6 @@ protected:
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// z8002_device overrides
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virtual bool get_segmented_mode() const override;
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virtual uint32_t adjust_addr_for_nonseg_mode(uint32_t addr) override;
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virtual uint16_t RDPORT_W(int mode, uint16_t addr) override;
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virtual void WRPORT_W(int mode, uint16_t addr, uint16_t value) override;
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virtual void PUSH_PC() override;
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virtual void CHANGE_FCW(uint16_t fcw) override;
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virtual uint32_t GET_PC(uint32_t VEC) override;
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@ -98,16 +98,16 @@ void onyx_state::z8002_m1_w(uint8_t data)
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void onyx_state::c8002_io(address_map &map)
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{
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map(0xff00, 0xff07).lrw8(NAME([this] (offs_t offset) { return m_sio[0]->cd_ba_r(offset >> 1); }), NAME([this] (offs_t offset, u8 data) { m_sio[0]->cd_ba_w(offset >> 1, data); }));
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map(0xff08, 0xff0f).lrw8(NAME([this] (offs_t offset) { return m_sio[1]->cd_ba_r(offset >> 1); }), NAME([this] (offs_t offset, u8 data) { m_sio[1]->cd_ba_w(offset >> 1, data); }));
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map(0xff10, 0xff17).lrw8(NAME([this] (offs_t offset) { return m_sio[2]->cd_ba_r(offset >> 1); }), NAME([this] (offs_t offset, u8 data) { m_sio[2]->cd_ba_w(offset >> 1, data); }));
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map(0xff18, 0xff1f).lrw8(NAME([this] (offs_t offset) { return m_sio[3]->cd_ba_r(offset >> 1); }), NAME([this] (offs_t offset, u8 data) { m_sio[3]->cd_ba_w(offset >> 1, data); }));
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map(0xff20, 0xff27).lrw8(NAME([this] (offs_t offset) { return m_sio[4]->cd_ba_r(offset >> 1); }), NAME([this] (offs_t offset, u8 data) { m_sio[4]->cd_ba_w(offset >> 1, data); }));
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map(0xff30, 0xff37).lrw8(NAME([this] (offs_t offset) { return m_ctc[0]->read(offset >> 1); }), NAME([this] (offs_t offset, u8 data) { m_ctc[0]->write(offset >> 1, data); }));
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map(0xff38, 0xff3f).lrw8(NAME([this] (offs_t offset) { return m_ctc[1]->read(offset >> 1); }), NAME([this] (offs_t offset, u8 data) { m_ctc[1]->write(offset >> 1, data); }));
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map(0xff40, 0xff47).lrw8(NAME([this] (offs_t offset) { return m_ctc[2]->read(offset >> 1); }), NAME([this] (offs_t offset, u8 data) { m_ctc[2]->write(offset >> 1, data); }));
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map(0xff50, 0xff57).lrw8(NAME([this] (offs_t offset) { return m_pio[0]->read(offset >> 1); }), NAME([this] (offs_t offset, u8 data) { m_pio[0]->write(offset >> 1, data); }));
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map(0xff58, 0xff5f).lrw8(NAME([this] (offs_t offset) { return m_pio[1]->read(offset >> 1); }), NAME([this] (offs_t offset, u8 data) { m_pio[1]->write(offset >> 1, data); }));
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map(0xff00, 0xff07).rw(m_sio[0], FUNC(z80sio_device::cd_ba_r), FUNC(z80sio_device::cd_ba_w)).umask16(0x00ff);
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map(0xff08, 0xff0f).rw(m_sio[1], FUNC(z80sio_device::cd_ba_r), FUNC(z80sio_device::cd_ba_w)).umask16(0x00ff);
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map(0xff10, 0xff17).rw(m_sio[2], FUNC(z80sio_device::cd_ba_r), FUNC(z80sio_device::cd_ba_w)).umask16(0x00ff);
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map(0xff18, 0xff1f).rw(m_sio[3], FUNC(z80sio_device::cd_ba_r), FUNC(z80sio_device::cd_ba_w)).umask16(0x00ff);
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map(0xff20, 0xff27).rw(m_sio[4], FUNC(z80sio_device::cd_ba_r), FUNC(z80sio_device::cd_ba_w)).umask16(0x00ff);
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map(0xff30, 0xff37).rw(m_ctc[0], FUNC(z80ctc_device::read), FUNC(z80ctc_device::write)).umask16(0x00ff);
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map(0xff38, 0xff3f).rw(m_ctc[1], FUNC(z80ctc_device::read), FUNC(z80ctc_device::write)).umask16(0x00ff);
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map(0xff40, 0xff47).rw(m_ctc[2], FUNC(z80ctc_device::read), FUNC(z80ctc_device::write)).umask16(0x00ff);
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map(0xff50, 0xff57).rw(m_pio[0], FUNC(z80pio_device::read), FUNC(z80pio_device::write)).umask16(0x00ff);
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map(0xff58, 0xff5f).rw(m_pio[1], FUNC(z80pio_device::read), FUNC(z80pio_device::write)).umask16(0x00ff);
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map(0xffb9, 0xffb9).w(FUNC(onyx_state::z8002_m1_w));
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}
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@ -43,7 +43,6 @@ class wicat_state : public driver_device
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public:
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wicat_state(const machine_config &mconfig, device_type type, const char *tag) :
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driver_device(mconfig, type, tag),
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m_vram(*this, "vram"),
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m_maincpu(*this, "maincpu"),
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m_rtc(*this, "rtc"),
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m_via(*this, "via"),
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@ -74,16 +73,6 @@ private:
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DECLARE_WRITE_LINE_MEMBER(bdir_w);
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DECLARE_WRITE8_MEMBER(via_a_w);
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DECLARE_WRITE8_MEMBER(via_b_w);
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DECLARE_READ8_MEMBER(video_r);
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DECLARE_WRITE8_MEMBER(video_w);
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DECLARE_READ8_MEMBER(video_dma_r);
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DECLARE_WRITE8_MEMBER(video_dma_w);
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DECLARE_READ8_MEMBER(video_uart0_r);
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DECLARE_WRITE8_MEMBER(video_uart0_w);
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DECLARE_READ8_MEMBER(video_uart1_r);
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DECLARE_WRITE8_MEMBER(video_uart1_w);
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DECLARE_READ8_MEMBER(videosram_r);
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DECLARE_WRITE8_MEMBER(videosram_w);
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DECLARE_WRITE8_MEMBER(videosram_store_w);
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DECLARE_WRITE8_MEMBER(videosram_recall_w);
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DECLARE_READ8_MEMBER(video_timer_r);
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@ -102,7 +91,6 @@ private:
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DECLARE_WRITE16_MEMBER(via_w);
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I8275_DRAW_CHARACTER_MEMBER(wicat_display_pixels);
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required_shared_ptr<uint8_t> m_vram;
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required_device<m68000_device> m_maincpu;
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required_device<mm58274c_device> m_rtc;
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required_device<via6522_device> m_via;
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@ -185,20 +173,20 @@ void wicat_state::video_mem(address_map &map)
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void wicat_state::video_io(address_map &map)
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{
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// these are largely wild guesses...
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map(0x0000, 0x0003).rw(FUNC(wicat_state::video_timer_r), FUNC(wicat_state::video_timer_w)); // some sort of timer?
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map(0x0100, 0x0107).rw(FUNC(wicat_state::video_uart0_r), FUNC(wicat_state::video_uart0_w)); // INS2651 UART #1
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map(0x0200, 0x0207).rw(FUNC(wicat_state::video_uart1_r), FUNC(wicat_state::video_uart1_w)); // INS2651 UART #2
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map(0x0000, 0x0003).rw(FUNC(wicat_state::video_timer_r), FUNC(wicat_state::video_timer_w)).umask16(0xff00); // some sort of timer?
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map(0x0100, 0x0107).rw(m_videouart0, FUNC(scn2651_device::read), FUNC(scn2651_device::write)).umask16(0xff00); // INS2651 UART #1
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map(0x0200, 0x0207).rw(m_videouart1, FUNC(scn2651_device::read), FUNC(scn2651_device::write)).umask16(0xff00); // INS2651 UART #2
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map(0x0304, 0x0304).r(FUNC(wicat_state::video_status_r));
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map(0x0400, 0x047f).rw(FUNC(wicat_state::videosram_r), FUNC(wicat_state::videosram_w)); // XD2210 4-bit NOVRAM
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map(0x0400, 0x047f).rw(m_videosram, FUNC(x2210_device::read), FUNC(x2210_device::write)).umask16(0xff00); // XD2210 4-bit NOVRAM
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map(0x0500, 0x0500).w(FUNC(wicat_state::videosram_recall_w));
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map(0x0600, 0x0600).w(FUNC(wicat_state::videosram_store_w));
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map(0x0800, 0x0807).w("videoctrl", FUNC(ls259_device::write_d0)).umask16(0xffff);
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map(0x0a00, 0x0a1f).rw(FUNC(wicat_state::video_dma_r), FUNC(wicat_state::video_dma_w)); // AM9517A DMA
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map(0x0b00, 0x0b03).rw(FUNC(wicat_state::video_r), FUNC(wicat_state::video_w)); // i8275 CRTC
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map(0x0a00, 0x0a1f).rw(m_videodma, FUNC(am9517a_device::read), FUNC(am9517a_device::write)).umask16(0xff00); // AM9517A DMA
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map(0x0b00, 0x0b03).rw(m_crtc, FUNC(i8275_device::read), FUNC(i8275_device::write)).umask16(0xff00); // i8275 CRTC
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map(0x0e00, 0x0eff).ram();
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map(0x4000, 0x5fff).ram().share("vram"); // video RAM?
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map(0x8000, 0x8fff).rom().region("g2char", 0x0000);
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map(0x9000, 0x9fff).rom().region("g2char", 0x0000);
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map(0x4000, 0x5fff).ram(); // video RAM?
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map(0x8000, 0x8fff).lr8(NAME([this] (offs_t offset) { return m_chargen->as_u8(offset); }));
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map(0x9000, 0x9fff).lr8(NAME([this] (offs_t offset) { return m_chargen->as_u8(offset); }));
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}
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void wicat_state::wd1000_mem(address_map &map)
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@ -547,32 +535,6 @@ WRITE16_MEMBER(wicat_state::via_w)
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m_via->write(offset,data>>8);
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}
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READ8_MEMBER(wicat_state::video_r)
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{
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switch(offset)
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{
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case 0x00:
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return m_crtc->read(0);
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case 0x02:
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return m_crtc->read(1);
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default:
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return 0xff;
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}
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}
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WRITE8_MEMBER(wicat_state::video_w)
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{
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switch(offset)
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{
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case 0x00:
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m_crtc->write(0,data);
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break;
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case 0x02:
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m_crtc->write(1,data);
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break;
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}
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}
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READ8_MEMBER( wicat_state::vram_r )
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{
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return m_videocpu->space(AS_IO).read_byte(offset*2);
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@ -583,56 +545,6 @@ WRITE8_MEMBER( wicat_state::vram_w )
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m_videocpu->space(AS_IO).write_byte(offset*2,data);
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}
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READ8_MEMBER(wicat_state::video_dma_r)
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{
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return m_videodma->read(offset/2);
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}
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WRITE8_MEMBER(wicat_state::video_dma_w)
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{
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if(!(offset & 0x01))
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m_videodma->write(offset/2,data);
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}
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READ8_MEMBER(wicat_state::video_uart0_r)
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{
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uint16_t noff = offset >> 1;
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return m_videouart0->read(noff);
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}
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WRITE8_MEMBER(wicat_state::video_uart0_w)
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{
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uint16_t noff = offset >> 1;
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m_videouart0->write(noff,data);
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}
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READ8_MEMBER(wicat_state::video_uart1_r)
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{
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uint16_t noff = offset >> 1;
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return m_videouart1->read(noff);
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}
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WRITE8_MEMBER(wicat_state::video_uart1_w)
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{
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uint16_t noff = offset >> 1;
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m_videouart1->write(noff,data);
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}
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// XD2210 64 x 4bit NOVRAM
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READ8_MEMBER(wicat_state::videosram_r)
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{
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if(offset & 0x01)
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return 0xff;
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else
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return m_videosram->read(space,offset/2);
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}
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WRITE8_MEMBER(wicat_state::videosram_w)
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{
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if(!(offset & 0x01))
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m_videosram->write(offset/2,data);
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}
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WRITE8_MEMBER(wicat_state::videosram_store_w)
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{
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if(data & 0x01) // unsure of the actual bit checked, the terminal code just writes 0xff
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@ -659,7 +571,7 @@ READ8_MEMBER(wicat_state::video_timer_r)
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if(offset == 0x00)
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return (m_videouart->dr_r() << 4) | (m_videouart->tbre_r() && m_videoctrl->q6_r() ? 0x08 : 0x00);
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if(offset == 0x02)
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if(offset == 0x01)
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{
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if (!machine().side_effects_disabled())
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{
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@ -674,7 +586,7 @@ READ8_MEMBER(wicat_state::video_timer_r)
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WRITE8_MEMBER(wicat_state::video_timer_w)
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{
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logerror("I/O port 0x%04x write %02x\n",offset,data);
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if(offset == 0x02)
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if(offset == 0x01)
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m_videouart->write(data);
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}
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||||
|
||||
|
||||
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Reference in New Issue
Block a user