mirror of
https://github.com/holub/mame
synced 2025-10-04 16:34:53 +03:00
Cleanups and version bump
This commit is contained in:
Miodrag Milanovic
parent
e5caefbfbd
commit
64e16ca8cf
@ -7,7 +7,7 @@
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<description>Acer CPR</description>
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<year>1995</year>
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<publisher>Acer America Corporation</publisher>
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<info name="version" value="1.2a" /> <!-- floppy version 1.2a, CD version 1.2 -->
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<info name="version" value="1.2a" /> <!-- floppy version 1.2a, CD version 1.2 -->
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<part name="flop1" interface="floppy_3_5">
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<feature name="disk_label" value="Hard Drive Recovery Start-Up Diskette" />
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@ -1878,7 +1878,7 @@ The following floppies came with the machines.
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<software name="3dwater">
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<description>3D Water Driver (Jpn)</description>
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<year>19??</year>
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<publisher><tape2disk hack></publisher> <!-- or maybe cart2disk -->
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<publisher><tape2disk hack></publisher> <!-- or maybe cart2disk -->
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<part name="flop1" interface="floppy_3_5">
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<dataarea name="flop" size="737280">
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@ -376,7 +376,7 @@ The following floppies came with the machines.
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</dataarea>
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</part>
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<!-- This is the sound cartridge that came with the game Snatcher. This sound cartridge
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can also be used with the MSX Game Collections from Konami. -->
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can also be used with the MSX Game Collections from Konami. -->
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<part name="cart" interface="msx_cart">
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<feature name="slot" value="sound_snatcher" />
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<dataarea name="ram" size="65536">
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@ -404,7 +404,7 @@ The following floppies came with the machines.
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</dataarea>
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</part>
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<!-- This is the sound cartridge that came with the game Snatcher. This sound cartridge
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can also be used with the MSX Game Collections from Konami. -->
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can also be used with the MSX Game Collections from Konami. -->
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<part name="cart" interface="msx_cart">
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<feature name="slot" value="sound_snatcher" />
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<dataarea name="ram" size="65536">
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@ -432,7 +432,7 @@ The following floppies came with the machines.
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</dataarea>
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</part>
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<!-- This is the sound cartridge that came with the game SD Snatcher. This sound cartridge
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can _not_ be used with the MSX Game Collections from Konami. -->
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can _not_ be used with the MSX Game Collections from Konami. -->
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<part name="cart" interface="msx_cart">
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<feature name="slot" value="sound_sdsnatch" />
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<dataarea name="ram" size="65536">
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@ -460,7 +460,7 @@ The following floppies came with the machines.
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</dataarea>
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</part>
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<!-- This is the sound cartridge that came with the game SD Snatcher. This sound cartridge
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can _not_ be used with the MSX Game Collections from Konami. -->
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can _not_ be used with the MSX Game Collections from Konami. -->
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<part name="cart" interface="msx_cart">
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<feature name="slot" value="sound_sdsnatch" />
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<dataarea name="ram" size="65536">
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@ -37,8 +37,8 @@
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// ======================> c1541_base_t
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class c1541_base_t : public device_t,
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public device_cbm_iec_interface,
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public device_c64_floppy_parallel_interface
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public device_cbm_iec_interface,
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public device_c64_floppy_parallel_interface
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{
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public:
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// construction/destruction
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@ -39,8 +39,8 @@
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// ======================> c1571_t
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class c1571_t : public device_t,
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public device_cbm_iec_interface,
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public device_c64_floppy_parallel_interface
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public device_cbm_iec_interface,
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public device_c64_floppy_parallel_interface
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{
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public:
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// construction/destruction
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@ -35,7 +35,7 @@
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// ======================> c1581_t
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class c1581_t : public device_t,
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public device_cbm_iec_interface
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public device_cbm_iec_interface
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{
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public:
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// construction/destruction
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@ -45,7 +45,7 @@
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// ======================> interpod_device
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class interpod_device : public device_t,
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public device_cbm_iec_interface
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public device_cbm_iec_interface
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{
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public:
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// construction/destruction
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@ -6,31 +6,31 @@
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50-pin slot
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1 GND 26 /MREQ
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2 A8 27 /WR
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3 A7 28 /C4
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4 A6 29 (not used)
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5 A9 30 /C1
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6 A5 31 BD3
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7 A4 32 /C3
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8 A3 33 (not used)
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9 A10 34 /C2
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10 A2 35 DB6
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11 A11 36 /RD
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12 A1 37 BD4
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13 A0 38 (not used)
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14 A12 39 BD7
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15 A14 40 (not used)
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16 A13 41 BD5
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17 /RFSH 42 (not useD)
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18 A15 43 BD0
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19 /INT 44 (not used)
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20 /BUSRQ 45 BD2
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21 /NMI 46 /RESET
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22 /WAIT 47 /M1
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23 /HALT 48 /IORQ
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24 /BUSAK 49 BD1
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25 /ROMDIS 50 +5V
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1 GND 26 /MREQ
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2 A8 27 /WR
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3 A7 28 /C4
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4 A6 29 (not used)
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5 A9 30 /C1
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6 A5 31 BD3
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7 A4 32 /C3
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8 A3 33 (not used)
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9 A10 34 /C2
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10 A2 35 DB6
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11 A11 36 /RD
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12 A1 37 BD4
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13 A0 38 (not used)
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14 A12 39 BD7
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15 A14 40 (not used)
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16 A13 41 BD5
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17 /RFSH 42 (not useD)
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18 A15 43 BD0
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19 /INT 44 (not used)
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20 /BUSRQ 45 BD2
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21 /NMI 46 /RESET
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22 /WAIT 47 /M1
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23 /HALT 48 /IORQ
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24 /BUSAK 49 BD1
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25 /ROMDIS 50 +5V
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***************************************************************************/
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@ -83,7 +83,7 @@ static MACHINE_CONFIG_FRAGMENT( cgenie_fdc )
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MCFG_FLOPPY_DRIVE_ADD("fd1793:2", cgenie_floppies, NULL, cgenie_fdc_device::floppy_formats)
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MCFG_FLOPPY_DRIVE_ADD("fd1793:3", cgenie_floppies, NULL, cgenie_fdc_device::floppy_formats)
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// MCFG_SOFTWARE_LIST_ADD("floppy_list", "cgenie_flop")
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// MCFG_SOFTWARE_LIST_ADD("floppy_list", "cgenie_flop")
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MCFG_GENERIC_SOCKET_ADD("socket", generic_plain_slot, "cgenie_socket")
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MCFG_GENERIC_EXTENSIONS("bin,rom")
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@ -6,16 +6,16 @@
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20-pin slot
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1 GND 11 IOB2
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2 +12V 12 IOB1
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3 IOA3 13 IOB0
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4 IOA4 14 IOB3
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5 IOA0 15 IOB4
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6 IOA5 16 IOB5
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7 IOA1 17 IOB7
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8 IOA2 18 IOB6
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9 IOA7 19 +5V
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10 IOA6 20 -12V
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1 GND 11 IOB2
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2 +12V 12 IOB1
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3 IOA3 13 IOB0
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4 IOA4 14 IOB3
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5 IOA0 15 IOB4
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6 IOA5 16 IOB5
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7 IOA1 17 IOB7
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8 IOA2 18 IOB6
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9 IOA7 19 +5V
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10 IOA6 20 -12V
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***************************************************************************/
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@ -2,13 +2,13 @@
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// copyright-holders:Barry Rodewald
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/*
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Brunword MK4 - Word processor ROM / expansion
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Brunword MK4 - Word processor ROM / expansion
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Software is provided as an expansion device, which uses it own ROM mapping
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Software is provided as an expansion device, which uses it own ROM mapping
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The ROM select port will be handled by this device, calling back to the standard driver when necessary.
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Not enabled for the CPC Plus, as ROM selection wraps after 63, making it impossible to see cartridge
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banks in the upper ROM area (0x80-0xff)
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The ROM select port will be handled by this device, calling back to the standard driver when necessary.
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Not enabled for the CPC Plus, as ROM selection wraps after 63, making it impossible to see cartridge
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banks in the upper ROM area (0x80-0xff)
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*/
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#include "brunword4.h"
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@ -108,4 +108,3 @@ void cpc_brunword4_device::set_mapping()
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membank(":bank4")->set_base(ROM+((bank*0x4000) + 0x2000));
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}
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}
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@ -2,7 +2,7 @@
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// copyright-holders:Barry Rodewald
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/*
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Brunword MK4 - Word processor ROM / expansion
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Brunword MK4 - Word processor ROM / expansion
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*/
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@ -36,4 +36,3 @@ private:
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// device type definition
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extern const device_type CPC_BRUNWORD_MK4;
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@ -748,7 +748,6 @@ WRITE8_MEMBER(gb_rom_mmm01_device::write_bank)
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READ8_MEMBER(gb_rom_sachen_mmc1_device::read_rom)
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{
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UINT16 off_edit = offset;
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/* Wait for 0x31 transitions of A15 (hi -> lo), i.e. ROM accesses; A15 = HI while in bootstrap */
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@ -780,7 +779,6 @@ READ8_MEMBER(gb_rom_sachen_mmc1_device::read_rom)
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WRITE8_MEMBER(gb_rom_sachen_mmc1_device::write_bank)
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{
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/* Only A15..A6, A4, A1..A0 are connected */
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/* We only decode upper three bits */
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switch ((offset & 0xFFD3) & 0xE000)
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@ -822,7 +820,6 @@ WRITE8_MEMBER(gb_rom_sachen_mmc1_device::write_bank)
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READ8_MEMBER(gb_rom_sachen_mmc2_device::read_rom)
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{
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UINT16 off_edit = offset;
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/* Wait for 0x30 transitions of A15 (lo -> hi), i.e. ROM accesses; A15 = HI while in bootstrap */
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@ -861,7 +858,6 @@ READ8_MEMBER(gb_rom_sachen_mmc2_device::read_rom)
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READ8_MEMBER(gb_rom_sachen_mmc2_device::read_ram)
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{
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if (m_mode == MODE_LOCKED_DMG) {
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m_unlock_cnt = 0x00;
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m_mode = MODE_LOCKED_CGB;
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@ -872,7 +868,6 @@ READ8_MEMBER(gb_rom_sachen_mmc2_device::read_ram)
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WRITE8_MEMBER(gb_rom_sachen_mmc2_device::write_ram)
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{
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if (m_mode == MODE_LOCKED_DMG) {
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m_unlock_cnt = 0x00;
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m_mode = MODE_LOCKED_CGB;
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@ -28,7 +28,7 @@
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// ======================> c2040_t
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class c2040_t : public device_t,
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public device_ieee488_interface
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public device_ieee488_interface
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{
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public:
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// construction/destruction
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@ -28,7 +28,7 @@
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// ======================> c8050_t
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class c8050_t : public device_t,
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public device_ieee488_interface
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public device_ieee488_interface
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{
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public:
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// construction/destruction
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@ -27,7 +27,7 @@
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// ======================> c8280_t
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class c8280_t : public device_t,
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public device_ieee488_interface
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public device_ieee488_interface
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{
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public:
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// construction/destruction
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@ -28,7 +28,7 @@
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// ======================> d9060_base_t
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class d9060_base_t : public device_t,
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public device_ieee488_interface
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public device_ieee488_interface
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{
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public:
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enum
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@ -2,7 +2,7 @@
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// copyright-holders:Fabio Priuli
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/**********************************************************************
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Megadrive carts
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Megadrive carts
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**********************************************************************/
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@ -131,8 +131,8 @@ class nasbus_slot_device : public device_t, public device_slot_interface
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{
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public:
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// construction/destruction
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nasbus_slot_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
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nasbus_slot_device(const machine_config &mconfig, device_type type, const char *name,
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nasbus_slot_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
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nasbus_slot_device(const machine_config &mconfig, device_type type, const char *name,
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const char *tag, device_t *owner, UINT32 clock, const char *shortname, const char *source);
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// device-level overrides
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@ -155,7 +155,7 @@ class nasbus_device : public device_t
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{
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public:
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// construction/destruction
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nasbus_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
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nasbus_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
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virtual ~nasbus_device();
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template<class _Object> static devcb_base &set_ram_disable_handler(device_t &device, _Object object)
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@ -273,7 +273,7 @@ WRITE32_MEMBER( nubus_image_device::file_cmd_w )
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char fullpath[1024];
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UINT64 filesize;
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// data = ((data & 0xff) << 24) | ((data & 0xff00) << 8) | ((data & 0xff0000) >> 8) | ((data & 0xff000000) >> 24);
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// data = ((data & 0xff) << 24) | ((data & 0xff00) << 8) | ((data & 0xff0000) >> 8) | ((data & 0xff000000) >> 24);
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filectx.curcmd = data;
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switch(data) {
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case kFileCmdGetDir:
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@ -27,7 +27,7 @@
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// ======================> c1551_t
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class c1551_t : public device_t,
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public device_plus4_expansion_card_interface
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public device_plus4_expansion_card_interface
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{
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public:
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// construction/destruction
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@ -1882,7 +1882,7 @@ int media_identifier::find_by_hash(const hash_collection &hashes, int length)
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{
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int found = 0;
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slname_map listnames;
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slname_map shortnames;
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slname_map shortnames;
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// iterate over drivers
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m_drivlist.reset();
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@ -1891,26 +1891,26 @@ int media_identifier::find_by_hash(const hash_collection &hashes, int length)
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// iterate over devices, regions and files within the region */
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device_iterator deviter(m_drivlist.config().root_device());
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for (device_t *device = deviter.first(); device != NULL; device = deviter.next())
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{
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if (shortnames.add(device->shortname(), 0, FALSE) != TMERR_DUPLICATE)
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{
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for (const rom_entry *region = rom_first_region(*device); region != NULL; region = rom_next_region(region))
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for (const rom_entry *rom = rom_first_file(region); rom != NULL; rom = rom_next_file(rom))
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{
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hash_collection romhashes(ROM_GETHASHDATA(rom));
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if (!romhashes.flag(hash_collection::FLAG_NO_DUMP) && hashes == romhashes)
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{
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bool baddump = romhashes.flag(hash_collection::FLAG_BAD_DUMP);
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{
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if (shortnames.add(device->shortname(), 0, FALSE) != TMERR_DUPLICATE)
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{
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for (const rom_entry *region = rom_first_region(*device); region != NULL; region = rom_next_region(region))
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for (const rom_entry *rom = rom_first_file(region); rom != NULL; rom = rom_next_file(rom))
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{
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hash_collection romhashes(ROM_GETHASHDATA(rom));
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if (!romhashes.flag(hash_collection::FLAG_NO_DUMP) && hashes == romhashes)
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{
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bool baddump = romhashes.flag(hash_collection::FLAG_BAD_DUMP);
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// output information about the match
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if (found)
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osd_printf_info(" ");
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osd_printf_info("= %s%-20s %-10s %s\n", baddump ? "(BAD) " : "", ROM_GETNAME(rom), m_drivlist.driver().name, m_drivlist.driver().description);
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found++;
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}
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}
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}
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}
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// output information about the match
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if (found)
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osd_printf_info(" ");
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osd_printf_info("= %s%-20s %-10s %s\n", baddump ? "(BAD) " : "", ROM_GETNAME(rom), m_drivlist.driver().name, m_drivlist.driver().description);
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found++;
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}
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}
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}
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}
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// next iterate over softlists
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software_list_device_iterator iter(m_drivlist.config().root_device());
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@ -1906,9 +1906,9 @@ void avr8_device::timer5_tick()
|
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case WGM5_FAST_PWM_ICR:
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case WGM5_FAST_PWM_OCR:
|
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#if LOG_TIMER_5
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printf("Unimplemented timer#5 waveform generation mode: AVR8_WGM5 = 0x%02X\n", AVR8_WGM5);
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printf("Unimplemented timer#5 waveform generation mode: AVR8_WGM5 = 0x%02X\n", AVR8_WGM5);
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#endif
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break;
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break;
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case WGM5_CTC_OCR:
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//TODO: verify this! Can be very wrong!!!
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|
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@ -296,7 +296,6 @@ void e0c6200_cpu_device::execute_one()
|
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default:
|
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switch (m_op)
|
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{
|
||||
|
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// LD r,q: load register with register
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case 0xec0: /* m_a = m_a; */ break;
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case 0xec1: m_a = m_b; break;
|
||||
@ -698,7 +697,6 @@ void e0c6200_cpu_device::execute_one()
|
||||
default:
|
||||
switch (m_op & 0xff0)
|
||||
{
|
||||
|
||||
// LD r,i: load register with 4-bit immediate data
|
||||
case 0xe00: m_a = m_op & 0xf; break;
|
||||
case 0xe10: m_b = m_op & 0xf; break;
|
||||
|
||||
@ -180,7 +180,6 @@ CPU_DISASSEMBLE(e0c6200)
|
||||
default:
|
||||
switch (op)
|
||||
{
|
||||
|
||||
// RLC r
|
||||
case 0xaf0: case 0xaf5: case 0xafa: case 0xaff:
|
||||
m = em_RLC; p1 = ep_R0;
|
||||
@ -475,7 +474,6 @@ CPU_DISASSEMBLE(e0c6200)
|
||||
default:
|
||||
switch (op & 0xff0)
|
||||
{
|
||||
|
||||
// ADC XH,i
|
||||
case 0xa00:
|
||||
m = em_ADC; p1 = ep_XH; p2 = ep_I;
|
||||
|
||||
@ -166,7 +166,7 @@ void mips3_device::clear_fastram(UINT32 select_start)
|
||||
m_fastram[i].readonly = false;
|
||||
m_fastram[i].base = NULL;
|
||||
}
|
||||
m_fastram_select=select_start;
|
||||
m_fastram_select=select_start;
|
||||
}
|
||||
|
||||
/*-------------------------------------------------
|
||||
|
||||
@ -6,9 +6,9 @@
|
||||
|
||||
emulation by Luca Elia, based on the Z80 core by Juergen Buchmueller
|
||||
|
||||
ChangeLog:
|
||||
ChangeLog:
|
||||
|
||||
20150517 Fixed TRUN bit masking (timers start/stop handling) [Rainer Keuchel]
|
||||
20150517 Fixed TRUN bit masking (timers start/stop handling) [Rainer Keuchel]
|
||||
|
||||
*************************************************************************************************************/
|
||||
|
||||
|
||||
@ -5,21 +5,21 @@
|
||||
ds1315.c
|
||||
|
||||
Dallas Semiconductor's Phantom Time Chip DS1315.
|
||||
NOTE: writes are decoded, but the host's time will always be returned when asked.
|
||||
NOTE: writes are decoded, but the host's time will always be returned when asked.
|
||||
|
||||
April 2015: chip enable / chip reset / phantom writes by Karl-Ludwig Deisenhofer
|
||||
April 2015: chip enable / chip reset / phantom writes by Karl-Ludwig Deisenhofer
|
||||
|
||||
November 2001: implementation by Tim Lindner
|
||||
November 2001: implementation by Tim Lindner
|
||||
|
||||
HOW DOES IT WORK?
|
||||
HOW DOES IT WORK?
|
||||
|
||||
READS: pattern recognition (64 bits in correct order). When RTC finally enables
|
||||
64 bits of data can be read. Chance of accidential pattern recognition is minimal.
|
||||
READS: pattern recognition (64 bits in correct order). When RTC finally enables
|
||||
64 bits of data can be read. Chance of accidential pattern recognition is minimal.
|
||||
|
||||
WRITES: two different locations (bits 0 and 1) are used to transfer data to the
|
||||
DS1315. 64 bit with time/date info are transmitted directly after recognition
|
||||
of the magic 64 bit pattern (see read above).
|
||||
**************************************************************************************/
|
||||
WRITES: two different locations (bits 0 and 1) are used to transfer data to the
|
||||
DS1315. 64 bit with time/date info are transmitted directly after recognition
|
||||
of the magic 64 bit pattern (see read above).
|
||||
**************************************************************************************/
|
||||
|
||||
#include "ds1315.h"
|
||||
#include "coreutil.h"
|
||||
@ -242,7 +242,7 @@ void ds1315_device::input_raw_data()
|
||||
flag = 1;
|
||||
|
||||
if (m_raw_data[i] & 1)
|
||||
raw[j] |= flag;
|
||||
raw[j] |= flag;
|
||||
flag <<= 1;
|
||||
}
|
||||
raw[0] = bcd_2_dec(raw[0]); // hundreds of seconds
|
||||
@ -256,8 +256,8 @@ void ds1315_device::input_raw_data()
|
||||
raw[7] = bcd_2_dec(raw[7]); // year (two digits)
|
||||
|
||||
printf("\nDS1315 RTC INPUT (WILL BE IGNORED) mm/dd/yy hh:mm:ss - %02d/%02d/%02d %02d/%02d/%02d",
|
||||
raw[6], raw[5], raw[7], raw[3], raw[2], raw[1]
|
||||
);
|
||||
raw[6], raw[5], raw[7], raw[3], raw[2], raw[1]
|
||||
);
|
||||
}
|
||||
|
||||
/*-------------------------------------------------
|
||||
|
||||
@ -40,7 +40,7 @@ Implements WD2010 / WD1010 controller basics.
|
||||
// DEC RD51 chip; different STEP / CYLINDER LIMIT (**):
|
||||
|
||||
// WD 1010 CONFIGURATION (1024 cylinder limit)
|
||||
// #define STEP_LIMIT 1024
|
||||
// #define STEP_LIMIT 1024
|
||||
// #define CYLINDER_HIGH_MASK 0x03
|
||||
|
||||
// --------------------------------------------------------
|
||||
@ -245,7 +245,6 @@ READ8_MEMBER(wd2010_device::read)
|
||||
|
||||
if (offset == TASK_FILE_SDH_REGISTER)
|
||||
{
|
||||
|
||||
logerror("(READ) %s WD2010 '%s' SDH: %u\n", machine().describe_context(), tag(), data);
|
||||
logerror("(READ) %s WD2010 '%s' Head: %u\n", machine().describe_context(), tag(), HEAD);
|
||||
logerror("(READ) %s WD2010 '%s' Drive: %u\n", machine().describe_context(), tag(), DRIVE);
|
||||
@ -490,7 +489,7 @@ void wd2010_device::seek(UINT8 data)
|
||||
}
|
||||
else
|
||||
{
|
||||
while (step_pulses > 0) // issue STEP PULSES
|
||||
while (step_pulses > 0) // issue STEP PULSES
|
||||
{
|
||||
if (direction == 0)
|
||||
{
|
||||
@ -528,7 +527,7 @@ void wd2010_device::seek(UINT8 data)
|
||||
|
||||
logerror("SEEK (END) - m_present_cylinder = %u\n", m_present_cylinder);
|
||||
|
||||
cmd_timer->adjust(attotime::from_msec(35), newstatus); // 35 msecs makes "SEEK_TIMING" test happy.
|
||||
cmd_timer->adjust(attotime::from_msec(35), newstatus); // 35 msecs makes "SEEK_TIMING" test happy.
|
||||
}
|
||||
|
||||
//-------------------------------------------------
|
||||
@ -728,7 +727,7 @@ void wd2010_device::complete_write_sector(UINT8 data)
|
||||
// ******************************************************
|
||||
// AUTO SCAN-ID (whenever DRIVE # changes):
|
||||
|
||||
// * does nothing right now *
|
||||
// * does nothing right now *
|
||||
// ******************************************************
|
||||
void wd2010_device::auto_scan_id(UINT8 data)
|
||||
{
|
||||
@ -860,16 +859,16 @@ void wd2010_device::format(UINT8 data)
|
||||
return;
|
||||
}
|
||||
|
||||
// UINT8 format_sector_count = m_task_file[TASK_FILE_SECTOR_COUNT];
|
||||
// do
|
||||
// {
|
||||
// < WRITE GAP 1 or GAP 3 >
|
||||
// UINT8 format_sector_count = m_task_file[TASK_FILE_SECTOR_COUNT];
|
||||
// do
|
||||
// {
|
||||
// < WRITE GAP 1 or GAP 3 >
|
||||
|
||||
// < Wait for SEEK_COMPLETE=1 (extend GAP if SEEK_COMPLETE = 0) >
|
||||
// < Assume SEEK COMPLETE >
|
||||
// < Wait for SEEK_COMPLETE=1 (extend GAP if SEEK_COMPLETE = 0) >
|
||||
// < Assume SEEK COMPLETE >
|
||||
|
||||
// format_sector_count--;
|
||||
// if (format_sector_count != 0)
|
||||
// format_sector_count--;
|
||||
// if (format_sector_count != 0)
|
||||
{
|
||||
// The Rainbow 100 driver does ignore multiple sector
|
||||
// transfers so WRITE FORMAT does not actually write -
|
||||
@ -878,10 +877,10 @@ void wd2010_device::format(UINT8 data)
|
||||
|
||||
// NOTE: decrementing TASK_FILE_SECTOR_COUNT does * NOT WORK *
|
||||
}
|
||||
// else
|
||||
// { // < Write 4Es until INDEX (*** UNIMPLEMENTED ****) >
|
||||
// }
|
||||
// } while (format_sector_count > 0);
|
||||
// else
|
||||
// { // < Write 4Es until INDEX (*** UNIMPLEMENTED ****) >
|
||||
// }
|
||||
// } while (format_sector_count > 0);
|
||||
|
||||
// ** DELAY INTRQ UNTIL WRITE IS COMPLETE :
|
||||
complete_write_when_buffer_ready_high->adjust(attotime::from_usec(1), newstatus | STATUS_DRQ); // 1 USECs
|
||||
@ -962,7 +961,7 @@ void wd2010_device::complete_immediate(UINT8 status)
|
||||
status &= ~(STATUS_RDY | STATUS_WF | STATUS_SC); // RDY 0x40 / WF 0x20 / SC 0x10
|
||||
status |= (m_in_drdy_cb() ? 0x40 : 0) | (m_in_wf_cb() ? 0x20 : 0) | (m_in_sc_cb() ? 0x10 : 0);
|
||||
|
||||
if (status & STATUS_DRQ) // if DRQ was set, reset
|
||||
if (status & STATUS_DRQ) // if DRQ was set, reset
|
||||
{
|
||||
status &= ~(STATUS_DRQ);
|
||||
m_out_bdrq_cb(0);
|
||||
@ -988,4 +987,3 @@ void wd2010_device::complete_cmd(UINT8 status)
|
||||
{
|
||||
cmd_timer->adjust(attotime::from_msec(1), status);
|
||||
}
|
||||
|
||||
|
||||
@ -1788,13 +1788,13 @@ horizon // (c) 1985
|
||||
youjyudn // (c) 1986 (Japan)
|
||||
|
||||
vigilant // (c) 1988 (World Rev E)
|
||||
vigilanta // (c) 1988 (World Rev A)
|
||||
vigilanta // (c) 1988 (World Rev A)
|
||||
vigilantb // (c) 1988 (US Rev B)
|
||||
vigilantc // (c) 1988 (World Rev C)
|
||||
vigilantc // (c) 1988 (World Rev C)
|
||||
vigilantd // (c) 1988 (Japan Rev D)
|
||||
vigilantg // (c) 1988 (US Rev G)
|
||||
vigilano // (c) 1988 (US)
|
||||
vigilanbl // bootleg
|
||||
vigilantg // (c) 1988 (US Rev G)
|
||||
vigilano // (c) 1988 (US)
|
||||
vigilanbl // bootleg
|
||||
kikcubic // (c) 1988 (Japan)
|
||||
kikcubicb // bootleg
|
||||
buccanrs // (c) 1989 Duintronic
|
||||
@ -6348,7 +6348,7 @@ ddribble // GX690 (c) 1986
|
||||
ddribblep // GX690 (c) 1986
|
||||
contra // GX633 (c) 1987
|
||||
contra1 // GX633 (c) 1987
|
||||
contrae // GX633 (c) 1987
|
||||
contrae // GX633 (c) 1987
|
||||
contraj // GX633 (c) 1987 (Japan)
|
||||
contraj1 // GX633 (c) 1987 (Japan)
|
||||
gryzor // GX633 (c) 1987
|
||||
@ -10901,7 +10901,7 @@ wheelfir // (c) 199? TCH
|
||||
littlerb // (c) 1993 TCH
|
||||
tattack // (c) 198? Shonan
|
||||
mosaicf2 // (c) 1999 F2 System
|
||||
royalpk2 //
|
||||
royalpk2 //
|
||||
finalgdr // (c) 2001 Semicom
|
||||
mrkicker // (c) 2001 Semicom
|
||||
wivernwg // (c) 2001 Semicom
|
||||
|
||||
@ -24,7 +24,7 @@ public:
|
||||
m_gfxdecode(*this, "gfxdecode"),
|
||||
m_screen(*this, "screen"),
|
||||
m_palette(*this, "palette"),
|
||||
m_video_ram(*this, "video_ram") { }
|
||||
m_video_ram(*this, "video_ram") { }
|
||||
|
||||
/* devices */
|
||||
required_device<cpu_device> m_maincpu;
|
||||
|
||||
@ -1059,7 +1059,7 @@ static const struct {
|
||||
UINT8 write_byte;
|
||||
} modify[16];
|
||||
} hacks[2] = { { "chihiro", { { 0x6a79f, 0x01 }, { 0x6a7a0, 0x00 }, { 0x6b575, 0x00 }, { 0x6b576, 0x00 }, { 0x6b5af, 0x75 }, { 0x6b78a, 0x75 }, { 0x6b7ca, 0x00 }, { 0x6b7b8, 0x00 }, { 0x8f5b2, 0x75 }, { 0x79a9e, 0x74 }, { 0x79b80, 0x74 }, { 0x79b97, 0x74 }, { 0, 0 } } },
|
||||
{ "outr2", { { 0x12e4cf, 0x01 }, { 0x12e4d0, 0x00 }, { 0x4793e, 0x01 }, { 0x4793f, 0x00 }, { 0x47aa3, 0x01 }, { 0x47aa4, 0x00 }, { 0x14f2b6, 0x84 }, { 0x14f2d1, 0x75 }, { 0x8732f, 0x7d }, { 0x87384, 0x7d }, { 0x87388, 0xeb }, { 0, 0 } } } };
|
||||
{ "outr2", { { 0x12e4cf, 0x01 }, { 0x12e4d0, 0x00 }, { 0x4793e, 0x01 }, { 0x4793f, 0x00 }, { 0x47aa3, 0x01 }, { 0x47aa4, 0x00 }, { 0x14f2b6, 0x84 }, { 0x14f2d1, 0x75 }, { 0x8732f, 0x7d }, { 0x87384, 0x7d }, { 0x87388, 0xeb }, { 0, 0 } } } };
|
||||
|
||||
READ32_MEMBER(chihiro_state::usbctrl_r)
|
||||
{
|
||||
|
||||
@ -4,7 +4,7 @@
|
||||
|
||||
Double Dragon 3 Technos Japan Corp 1990
|
||||
The Combatribes Technos Japan Corp 1990
|
||||
WWF WrestleFest Technos Japan Corp 1991
|
||||
WWF WrestleFest Technos Japan Corp 1991
|
||||
|
||||
Notes:
|
||||
|
||||
|
||||
@ -255,9 +255,9 @@ static MACHINE_CONFIG_START( royalpk2, mosaicf2_state )
|
||||
/* sound hardware */
|
||||
MCFG_SPEAKER_STANDARD_STEREO("lspeaker", "rspeaker")
|
||||
|
||||
// MCFG_YM2151_ADD("ymsnd", XTAL_14_31818MHz/4) /* 3.579545 MHz */
|
||||
// MCFG_SOUND_ROUTE(0, "lspeaker", 1.0)
|
||||
// MCFG_SOUND_ROUTE(1, "rspeaker", 1.0)
|
||||
// MCFG_YM2151_ADD("ymsnd", XTAL_14_31818MHz/4) /* 3.579545 MHz */
|
||||
// MCFG_SOUND_ROUTE(0, "lspeaker", 1.0)
|
||||
// MCFG_SOUND_ROUTE(1, "rspeaker", 1.0)
|
||||
|
||||
MCFG_OKIM6295_ADD("oki", XTAL_14_31818MHz/8, OKIM6295_PIN7_HIGH) /* 1.7897725 MHz */
|
||||
MCFG_SOUND_ROUTE(ALL_OUTPUTS, "lspeaker", 1.0)
|
||||
|
||||
@ -64,14 +64,14 @@ public:
|
||||
m_upd7759(*this, "7759") { }
|
||||
|
||||
required_device<cpu_device> m_maincpu;
|
||||
optional_device<upd7759_device> m_upd7759;
|
||||
int m_comms_state;
|
||||
optional_device<upd7759_device> m_upd7759;
|
||||
int m_comms_state;
|
||||
int m_comms_ind;
|
||||
UINT8 m_comms_data[1002];
|
||||
int m_comms_cmd;
|
||||
int m_comms_expect;
|
||||
int m_comms_blocks;
|
||||
bool m_comms_ack;
|
||||
int m_comms_cmd;
|
||||
int m_comms_expect;
|
||||
int m_comms_blocks;
|
||||
bool m_comms_ack;
|
||||
|
||||
virtual void machine_start();
|
||||
DECLARE_READ16_MEMBER(comms_r);
|
||||
@ -97,233 +97,233 @@ static const UINT8 password[] = {5, 2, 0, 3, 0, 0, 2, 4, 5, 6, 0x16};
|
||||
|
||||
READ16_MEMBER(gambl186_state::comms_r)
|
||||
{
|
||||
UINT16 retval = 0;
|
||||
UINT16 retval = 0;
|
||||
|
||||
if ((offset == 0) && ACCESSING_BITS_0_7) //port 680 == data
|
||||
{
|
||||
if (m_comms_state == 0x16) //read mode, just in case
|
||||
{
|
||||
if (!m_comms_ind && (m_comms_cmd == 0xff))
|
||||
{
|
||||
m_comms_cmd = m_comms_data[1];
|
||||
if ((offset == 0) && ACCESSING_BITS_0_7) //port 680 == data
|
||||
{
|
||||
if (m_comms_state == 0x16) //read mode, just in case
|
||||
{
|
||||
if (!m_comms_ind && (m_comms_cmd == 0xff))
|
||||
{
|
||||
m_comms_cmd = m_comms_data[1];
|
||||
|
||||
switch (m_comms_cmd)
|
||||
{
|
||||
case 0:
|
||||
{
|
||||
m_comms_expect = 4;
|
||||
break;
|
||||
}
|
||||
switch (m_comms_cmd)
|
||||
{
|
||||
case 0:
|
||||
{
|
||||
m_comms_expect = 4;
|
||||
break;
|
||||
}
|
||||
|
||||
case 1:
|
||||
{
|
||||
m_comms_expect = 12;
|
||||
m_comms_blocks = 2;
|
||||
break;
|
||||
}
|
||||
case 1:
|
||||
{
|
||||
m_comms_expect = 12;
|
||||
m_comms_blocks = 2;
|
||||
break;
|
||||
}
|
||||
|
||||
case 2:
|
||||
{
|
||||
m_comms_expect = 408;
|
||||
m_comms_blocks = 4;
|
||||
break;
|
||||
}
|
||||
case 2:
|
||||
{
|
||||
m_comms_expect = 408;
|
||||
m_comms_blocks = 4;
|
||||
break;
|
||||
}
|
||||
|
||||
case 3:
|
||||
{
|
||||
m_comms_expect = 7;
|
||||
m_comms_blocks = 3;
|
||||
break;
|
||||
}
|
||||
case 3:
|
||||
{
|
||||
m_comms_expect = 7;
|
||||
m_comms_blocks = 3;
|
||||
break;
|
||||
}
|
||||
|
||||
case 4:
|
||||
{
|
||||
m_comms_expect = 2;
|
||||
m_comms_blocks = 2;
|
||||
break;
|
||||
}
|
||||
case 4:
|
||||
{
|
||||
m_comms_expect = 2;
|
||||
m_comms_blocks = 2;
|
||||
break;
|
||||
}
|
||||
|
||||
case 5:
|
||||
{
|
||||
m_comms_expect = 13;
|
||||
m_comms_blocks = 4;
|
||||
break;
|
||||
}
|
||||
case 5:
|
||||
{
|
||||
m_comms_expect = 13;
|
||||
m_comms_blocks = 4;
|
||||
break;
|
||||
}
|
||||
|
||||
case 6:
|
||||
{
|
||||
m_comms_expect = 1003;
|
||||
break;
|
||||
}
|
||||
case 6:
|
||||
{
|
||||
m_comms_expect = 1003;
|
||||
break;
|
||||
}
|
||||
|
||||
default: //unknown
|
||||
{
|
||||
m_comms_expect = 1;
|
||||
}
|
||||
}
|
||||
}
|
||||
default: //unknown
|
||||
{
|
||||
m_comms_expect = 1;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
if (m_comms_ind < sizeof(m_comms_data))
|
||||
{
|
||||
if (m_comms_expect && !--m_comms_expect)
|
||||
{
|
||||
m_comms_ack = true;
|
||||
if (m_comms_ind < sizeof(m_comms_data))
|
||||
{
|
||||
if (m_comms_expect && !--m_comms_expect)
|
||||
{
|
||||
m_comms_ack = true;
|
||||
|
||||
if (m_comms_ind)
|
||||
{
|
||||
int i, sum;
|
||||
if (m_comms_ind)
|
||||
{
|
||||
int i, sum;
|
||||
|
||||
for (i = 1, sum = 0; i < m_comms_ind; sum += m_comms_data[i++]);
|
||||
m_comms_data[m_comms_ind] = (unsigned char) sum;
|
||||
for (i = 1, sum = 0; i < m_comms_ind; sum += m_comms_data[i++]);
|
||||
m_comms_data[m_comms_ind] = (unsigned char) sum;
|
||||
|
||||
switch (m_comms_cmd)
|
||||
{
|
||||
case 1:
|
||||
{
|
||||
if (m_comms_blocks == 2)
|
||||
{
|
||||
m_comms_expect = 5;
|
||||
}
|
||||
else
|
||||
{
|
||||
m_comms_data[m_comms_ind] += 5; //compensate for ack
|
||||
}
|
||||
switch (m_comms_cmd)
|
||||
{
|
||||
case 1:
|
||||
{
|
||||
if (m_comms_blocks == 2)
|
||||
{
|
||||
m_comms_expect = 5;
|
||||
}
|
||||
else
|
||||
{
|
||||
m_comms_data[m_comms_ind] += 5; //compensate for ack
|
||||
}
|
||||
|
||||
break;
|
||||
}
|
||||
break;
|
||||
}
|
||||
|
||||
case 2:
|
||||
{
|
||||
if (m_comms_blocks == 4)
|
||||
{
|
||||
m_comms_expect = 5;
|
||||
}
|
||||
else
|
||||
{
|
||||
m_comms_data[m_comms_ind] += 5; //compensate for ack
|
||||
m_comms_expect = 3;
|
||||
}
|
||||
case 2:
|
||||
{
|
||||
if (m_comms_blocks == 4)
|
||||
{
|
||||
m_comms_expect = 5;
|
||||
}
|
||||
else
|
||||
{
|
||||
m_comms_data[m_comms_ind] += 5; //compensate for ack
|
||||
m_comms_expect = 3;
|
||||
}
|
||||
|
||||
break;
|
||||
}
|
||||
break;
|
||||
}
|
||||
|
||||
case 3:
|
||||
{
|
||||
if (m_comms_blocks == 3)
|
||||
{
|
||||
m_comms_expect = 3;
|
||||
}
|
||||
else
|
||||
{
|
||||
m_comms_data[m_comms_ind] += 5; //compensate for ack
|
||||
m_comms_expect = 5;
|
||||
}
|
||||
case 3:
|
||||
{
|
||||
if (m_comms_blocks == 3)
|
||||
{
|
||||
m_comms_expect = 3;
|
||||
}
|
||||
else
|
||||
{
|
||||
m_comms_data[m_comms_ind] += 5; //compensate for ack
|
||||
m_comms_expect = 5;
|
||||
}
|
||||
|
||||
break;
|
||||
}
|
||||
break;
|
||||
}
|
||||
|
||||
case 5:
|
||||
{
|
||||
m_comms_expect = 3;
|
||||
case 5:
|
||||
{
|
||||
m_comms_expect = 3;
|
||||
|
||||
if (m_comms_blocks < 4)
|
||||
{
|
||||
m_comms_data[m_comms_ind] += 5; //compensate for ack
|
||||
if (m_comms_blocks < 4)
|
||||
{
|
||||
m_comms_data[m_comms_ind] += 5; //compensate for ack
|
||||
|
||||
if (m_comms_blocks == 2)
|
||||
{
|
||||
m_comms_expect = 2;
|
||||
}
|
||||
}
|
||||
if (m_comms_blocks == 2)
|
||||
{
|
||||
m_comms_expect = 2;
|
||||
}
|
||||
}
|
||||
|
||||
break;
|
||||
}
|
||||
break;
|
||||
}
|
||||
|
||||
default:
|
||||
{
|
||||
}
|
||||
}
|
||||
}
|
||||
else if (m_comms_cmd == 4)
|
||||
{
|
||||
if (!memcmp(m_comms_data, password, sizeof(password)))
|
||||
{
|
||||
m_comms_data[1] = 0x55;
|
||||
m_comms_data[2] = 0x55;
|
||||
}
|
||||
default:
|
||||
{
|
||||
}
|
||||
}
|
||||
}
|
||||
else if (m_comms_cmd == 4)
|
||||
{
|
||||
if (!memcmp(m_comms_data, password, sizeof(password)))
|
||||
{
|
||||
m_comms_data[1] = 0x55;
|
||||
m_comms_data[2] = 0x55;
|
||||
}
|
||||
|
||||
m_comms_expect = 2;
|
||||
m_comms_ack = false;
|
||||
}
|
||||
m_comms_expect = 2;
|
||||
m_comms_ack = false;
|
||||
}
|
||||
|
||||
if (!m_comms_blocks || !--m_comms_blocks)
|
||||
{
|
||||
m_comms_cmd = 0xff;
|
||||
}
|
||||
}
|
||||
if (!m_comms_blocks || !--m_comms_blocks)
|
||||
{
|
||||
m_comms_cmd = 0xff;
|
||||
}
|
||||
}
|
||||
|
||||
retval = m_comms_data[m_comms_ind++];
|
||||
}
|
||||
}
|
||||
}
|
||||
else if (offset == 1) //port 681 == status
|
||||
{
|
||||
if (m_comms_state == 0x16) //read mode
|
||||
{
|
||||
retval = 2; //read ready
|
||||
}
|
||||
else if (m_comms_state == 0x31) //write mode
|
||||
{
|
||||
retval = 4; //write ready
|
||||
}
|
||||
}
|
||||
retval = m_comms_data[m_comms_ind++];
|
||||
}
|
||||
}
|
||||
}
|
||||
else if (offset == 1) //port 681 == status
|
||||
{
|
||||
if (m_comms_state == 0x16) //read mode
|
||||
{
|
||||
retval = 2; //read ready
|
||||
}
|
||||
else if (m_comms_state == 0x31) //write mode
|
||||
{
|
||||
retval = 4; //write ready
|
||||
}
|
||||
}
|
||||
|
||||
return retval;
|
||||
return retval;
|
||||
}
|
||||
|
||||
WRITE16_MEMBER(gambl186_state::comms_w)
|
||||
{
|
||||
if (offset == 0)
|
||||
{
|
||||
if ((m_comms_state == 0x31) && (m_comms_ind < 1000))
|
||||
{
|
||||
if (!m_comms_ack || (data == 0x15)) //validation failure
|
||||
{
|
||||
if (m_comms_cmd == 6) //1000 bytes transfer
|
||||
{
|
||||
data = ~data;
|
||||
}
|
||||
else if (m_comms_ack)
|
||||
{
|
||||
m_comms_cmd = 0xfe;
|
||||
m_comms_expect = 2;
|
||||
data = 5;
|
||||
}
|
||||
if (offset == 0)
|
||||
{
|
||||
if ((m_comms_state == 0x31) && (m_comms_ind < 1000))
|
||||
{
|
||||
if (!m_comms_ack || (data == 0x15)) //validation failure
|
||||
{
|
||||
if (m_comms_cmd == 6) //1000 bytes transfer
|
||||
{
|
||||
data = ~data;
|
||||
}
|
||||
else if (m_comms_ack)
|
||||
{
|
||||
m_comms_cmd = 0xfe;
|
||||
m_comms_expect = 2;
|
||||
data = 5;
|
||||
}
|
||||
|
||||
m_comms_data[++m_comms_ind] = (UINT8) data;
|
||||
}
|
||||
m_comms_data[++m_comms_ind] = (UINT8) data;
|
||||
}
|
||||
|
||||
m_comms_ack = false;
|
||||
}
|
||||
}
|
||||
else if (offset == 1)
|
||||
{
|
||||
if (m_comms_state != data) //detect transition
|
||||
{
|
||||
m_comms_ind = 0;
|
||||
m_comms_ack = false;
|
||||
}
|
||||
}
|
||||
else if (offset == 1)
|
||||
{
|
||||
if (m_comms_state != data) //detect transition
|
||||
{
|
||||
m_comms_ind = 0;
|
||||
|
||||
if (data == 0x4e) //reset
|
||||
{
|
||||
m_comms_data[0] = 5; //operation complete
|
||||
m_comms_cmd = 0xff; //none
|
||||
m_comms_expect = 0;
|
||||
m_comms_blocks = 0;
|
||||
m_comms_ack = false;
|
||||
}
|
||||
}
|
||||
if (data == 0x4e) //reset
|
||||
{
|
||||
m_comms_data[0] = 5; //operation complete
|
||||
m_comms_cmd = 0xff; //none
|
||||
m_comms_expect = 0;
|
||||
m_comms_blocks = 0;
|
||||
m_comms_ack = false;
|
||||
}
|
||||
}
|
||||
|
||||
m_comms_state = data;
|
||||
}
|
||||
m_comms_state = data;
|
||||
}
|
||||
}
|
||||
|
||||
WRITE16_MEMBER( gambl186_state::data_bank_w)
|
||||
@ -352,16 +352,16 @@ WRITE16_MEMBER( gambl186_state::data_bank_w)
|
||||
WRITE16_MEMBER(gambl186_state::upd_w)
|
||||
{
|
||||
//// FIXME
|
||||
// m_upd7759->reset_w(0);
|
||||
// m_upd7759->reset_w(1);
|
||||
// m_upd7759->reset_w(0);
|
||||
// m_upd7759->reset_w(1);
|
||||
|
||||
// if (mem_mask&0x00ff) m_upd7759->port_w(space, 0, data & 0xff);
|
||||
// if (mem_mask&0xff00) m_upd7759->port_w(space, 0, (data >> 8) & 0xff);
|
||||
// if (mem_mask&0x00ff) m_upd7759->port_w(space, 0, data & 0xff);
|
||||
// if (mem_mask&0xff00) m_upd7759->port_w(space, 0, (data >> 8) & 0xff);
|
||||
data = (data >> 8);
|
||||
popmessage("sample index: %02x", data);
|
||||
popmessage("sample index: %02x", data);
|
||||
|
||||
// m_upd7759->start_w(0);
|
||||
// m_upd7759->start_w(1);
|
||||
// m_upd7759->start_w(0);
|
||||
// m_upd7759->start_w(1);
|
||||
}
|
||||
|
||||
|
||||
@ -378,7 +378,7 @@ static ADDRESS_MAP_START( gambl186_io, AS_IO, 16, gambl186_state )
|
||||
AM_RANGE(0x0580, 0x0581) AM_READ_PORT("DSW1")
|
||||
AM_RANGE(0x0582, 0x0583) AM_READ_PORT("JOY")
|
||||
AM_RANGE(0x0584, 0x0585) AM_READ_PORT("DSW0") AM_WRITENOP // Watchdog: bit 8
|
||||
// AM_RANGE(0x0600, 0x0603) AM_WRITENOP // lamps
|
||||
// AM_RANGE(0x0600, 0x0603) AM_WRITENOP // lamps
|
||||
AM_RANGE(0x0680, 0x0683) AM_READWRITE(comms_r, comms_w)
|
||||
AM_RANGE(0x0700, 0x0701) AM_WRITE(data_bank_w)
|
||||
ADDRESS_MAP_END
|
||||
@ -493,7 +493,7 @@ ROM_START( gambl186 )
|
||||
ROM_LOAD16_BYTE( "se403p.u9", 0x00000, 0x20000, CRC(1021cc20) SHA1(d9bb67676b05458ff813d608431ff06946ab7721) )
|
||||
ROM_LOAD16_BYTE( "so403p.u10", 0x00001, 0x20000, CRC(af9746c9) SHA1(3f1ab8110cc5eadec661181779799693ad695e21) )
|
||||
|
||||
ROM_REGION( 0x20000, "upd", 0 ) // upd7759 sound samples
|
||||
ROM_REGION( 0x20000, "upd", 0 ) // upd7759 sound samples
|
||||
ROM_LOAD( "347.u302", 0x00000, 0x20000, CRC(7ce8f490) SHA1(2f856e31d189e9d46ba6b322133d99133e0b52ac) )
|
||||
ROM_END
|
||||
|
||||
@ -506,7 +506,7 @@ ROM_START( gambl186a )
|
||||
ROM_LOAD16_BYTE( "se403p.u9", 0x00000, 0x20000, CRC(1021cc20) SHA1(d9bb67676b05458ff813d608431ff06946ab7721) )
|
||||
ROM_LOAD16_BYTE( "so403p.u10", 0x00001, 0x20000, CRC(af9746c9) SHA1(3f1ab8110cc5eadec661181779799693ad695e21) )
|
||||
|
||||
ROM_REGION( 0x20000, "upd", 0 ) // upd7759 sound samples
|
||||
ROM_REGION( 0x20000, "upd", 0 ) // upd7759 sound samples
|
||||
ROM_LOAD( "347.u302", 0x00000, 0x20000, CRC(7ce8f490) SHA1(2f856e31d189e9d46ba6b322133d99133e0b52ac) )
|
||||
ROM_END
|
||||
|
||||
|
||||
@ -142,13 +142,13 @@ void iteagle_state::machine_reset()
|
||||
{
|
||||
}
|
||||
|
||||
#define PCI_ID_IDE ":pci:06.0"
|
||||
// Primary IDE Control ":pci:06.1"
|
||||
// Seconday IDE Control ":pci:06.2"
|
||||
#define PCI_ID_SOUND ":pci:07.0"
|
||||
#define PCI_ID_FPGA ":pci:08.0"
|
||||
#define PCI_ID_VIDEO ":pci:09.0"
|
||||
#define PCI_ID_EEPROM ":pci:0a.0"
|
||||
#define PCI_ID_IDE ":pci:06.0"
|
||||
// Primary IDE Control ":pci:06.1"
|
||||
// Seconday IDE Control ":pci:06.2"
|
||||
#define PCI_ID_SOUND ":pci:07.0"
|
||||
#define PCI_ID_FPGA ":pci:08.0"
|
||||
#define PCI_ID_VIDEO ":pci:09.0"
|
||||
#define PCI_ID_EEPROM ":pci:0a.0"
|
||||
|
||||
static MACHINE_CONFIG_START( iteagle, iteagle_state )
|
||||
|
||||
|
||||
@ -64,23 +64,23 @@ TI TVP3409
|
||||
V53C16258HK40 x24
|
||||
V53C511816500K60 x4
|
||||
|
||||
U38 and U97 on main board 3DFX
|
||||
500-0004-02
|
||||
BF2733.1 TMU
|
||||
9748 20001
|
||||
TAIWAN 1001
|
||||
U38 and U97 on main board 3DFX
|
||||
500-0004-02
|
||||
BF2733.1 TMU
|
||||
9748 20001
|
||||
TAIWAN 1001
|
||||
|
||||
U4 on daughter board Zoran ZR36050PQC
|
||||
-29.5
|
||||
85 GF7B9726E
|
||||
U4 on daughter board Zoran ZR36050PQC
|
||||
-29.5
|
||||
85 GF7B9726E
|
||||
|
||||
U11 on main board Removed heatsink, Couldn't see anything...
|
||||
U11 on main board Removed heatsink, Couldn't see anything...
|
||||
|
||||
|
||||
U71 on main board Galileo
|
||||
GT-64010A-B-0
|
||||
BB8018.1
|
||||
TAIWAN
|
||||
U71 on main board Galileo
|
||||
GT-64010A-B-0
|
||||
BB8018.1
|
||||
TAIWAN
|
||||
14.31818 Oscillator by the TI part
|
||||
50.0000 Oscillator by EPROMS
|
||||
33.0000 Oscillator by the V53C511816500K60
|
||||
|
||||
@ -309,10 +309,10 @@ WRITE8_MEMBER(miniboy7_state::ay_pa_w)
|
||||
// output_set_lamp_value(3, (data >> 3) & 1); // [-x---]
|
||||
// output_set_lamp_value(4, (data >> 4) & 1); // [x----]
|
||||
|
||||
coin_counter_w(machine(), 0, data & 0x40); // counter
|
||||
coin_counter_w(machine(), 0, data & 0x40); // counter
|
||||
|
||||
// popmessage("Out Lamps: %02x", data);
|
||||
// logerror("Out Lamps: %02x\n", data);
|
||||
// logerror("Out Lamps: %02x\n", data);
|
||||
|
||||
}
|
||||
|
||||
|
||||
@ -89,17 +89,17 @@ static Mono9602Desc a8_desc(K_OHM(27.0), U_FARAD(1.0), K_OHM(27.0), U_FARAD(1.0)
|
||||
CIRCUIT_LAYOUT( breakout )
|
||||
|
||||
#if (SLOW_BUT_ACCURATE)
|
||||
SOLVER(Solver, 48000)
|
||||
PARAM(Solver.ACCURACY, 1e-8) // less accuracy and diode will not work
|
||||
PARAM(Solver.GS_THRESHOLD, 6)
|
||||
SOLVER(Solver, 48000)
|
||||
PARAM(Solver.ACCURACY, 1e-8) // less accuracy and diode will not work
|
||||
PARAM(Solver.GS_THRESHOLD, 6)
|
||||
#else
|
||||
SOLVER(Solver, 48000)
|
||||
PARAM(Solver.ACCURACY, 1e-6)
|
||||
PARAM(Solver.GS_THRESHOLD, 6)
|
||||
// FIXME: PARALLEL Doesn't work in breakout.
|
||||
PARAM(Solver.PARALLEL, 0)
|
||||
SOLVER(Solver, 48000)
|
||||
PARAM(Solver.ACCURACY, 1e-6)
|
||||
PARAM(Solver.GS_THRESHOLD, 6)
|
||||
// FIXME: PARALLEL Doesn't work in breakout.
|
||||
PARAM(Solver.PARALLEL, 0)
|
||||
#endif
|
||||
PARAM(NETLIST.USE_DEACTIVATE, 1)
|
||||
PARAM(NETLIST.USE_DEACTIVATE, 1)
|
||||
|
||||
// DIPSWITCH - Free game
|
||||
SWITCH(S1_1)
|
||||
@ -129,7 +129,7 @@ CIRCUIT_LAYOUT( breakout )
|
||||
// Clock circuit
|
||||
//----------------------------------------------------------------
|
||||
#if 0 || (SLOW_BUT_ACCURATE)
|
||||
MAINCLOCK(Y1, 14318000.0)
|
||||
MAINCLOCK(Y1, 14318000.0)
|
||||
CHIP("F1", 9316)
|
||||
NET_C(Y1.Q, F1.2)
|
||||
|
||||
@ -149,24 +149,24 @@ CIRCUIT_LAYOUT( breakout )
|
||||
#define DICECLOCK "H1", 11
|
||||
#else
|
||||
/*
|
||||
* 9316 2 3 4 5 6 7 8 9 10 11 12 13 14 15 2 3 4 5 6
|
||||
* A 0 1 0 1 0 1 0 1 0 1 0 1 0 1
|
||||
* B 1 1 0 0 1 1 0 0 1 1 0 0 1 1
|
||||
* CKBH 1 1 0 0 1 1 0 0 1 1 0 0 1 1 1 1
|
||||
* 9316 2 3 4 5 6 7 8 9 10 11 12 13 14 15 2 3 4 5 6
|
||||
* A 0 1 0 1 0 1 0 1 0 1 0 1 0 1
|
||||
* B 1 1 0 0 1 1 0 0 1 1 0 0 1 1
|
||||
* CKBH 1 1 0 0 1 1 0 0 1 1 0 0 1 1 1 1
|
||||
* ^--- Pattern Start
|
||||
* CLOCK 1 0 1 1 1 0 1 1 1 0 1 1 1 0 1 0 1 1 1
|
||||
* CLOCK 1 0 1 1 1 0 1 1 1 0 1 1 1 0 1 0 1 1 1
|
||||
* ^--- Pattern Start
|
||||
* <--------> 3 Clocks Offset
|
||||
*/
|
||||
EXTCLOCK(Y1, 14318000.0, "4,4,4,4,4,8")
|
||||
EXTCLOCK(Y2, 14318000.0, "2,6,2,6,2,2,2,6")
|
||||
PARAM(Y2.OFFSET, 3.0 / 14318000.0 + 20.0e-9 )
|
||||
EXTCLOCK(Y1, 14318000.0, "4,4,4,4,4,8")
|
||||
EXTCLOCK(Y2, 14318000.0, "2,6,2,6,2,2,2,6")
|
||||
PARAM(Y2.OFFSET, 3.0 / 14318000.0 + 20.0e-9 )
|
||||
#define CKBH "Y1", Q
|
||||
#define DICECLOCK "Y2", Q
|
||||
|
||||
NET_C(ttlhigh, H1.13)
|
||||
NET_C(ttlhigh, H1.12)
|
||||
NET_C(ttlhigh, E1.5)
|
||||
NET_C(ttlhigh, H1.13)
|
||||
NET_C(ttlhigh, H1.12)
|
||||
NET_C(ttlhigh, E1.5)
|
||||
#endif
|
||||
|
||||
//----------------------------------------------------------------
|
||||
@ -175,38 +175,38 @@ CIRCUIT_LAYOUT( breakout )
|
||||
|
||||
TTL_INPUT(antenna, 0)
|
||||
|
||||
DIODE(CR3, "1N914")
|
||||
DIODE(CR4, "1N914")
|
||||
DIODE(CR5, "1N914")
|
||||
DIODE(CR7, "1N914")
|
||||
DIODE(CR3, "1N914")
|
||||
DIODE(CR4, "1N914")
|
||||
DIODE(CR5, "1N914")
|
||||
DIODE(CR7, "1N914")
|
||||
|
||||
QBJT_EB(Q1, "2N3644")
|
||||
QBJT_EB(Q2, "2N3643")
|
||||
QBJT_EB(Q3, "2N3643")
|
||||
CAP(C19, CAP_U(0.1))
|
||||
CAP(C16, CAP_U(0.1))
|
||||
QBJT_EB(Q1, "2N3644")
|
||||
QBJT_EB(Q2, "2N3643")
|
||||
QBJT_EB(Q3, "2N3643")
|
||||
CAP(C19, CAP_U(0.1))
|
||||
CAP(C16, CAP_U(0.1))
|
||||
|
||||
RES(R25, 100)
|
||||
RES(R26, 330)
|
||||
RES(R27, 100)
|
||||
RES(R31, 220)
|
||||
RES(R32, 100)
|
||||
RES(R25, 100)
|
||||
RES(R26, 330)
|
||||
RES(R27, 100)
|
||||
RES(R31, 220)
|
||||
RES(R32, 100)
|
||||
|
||||
NET_C(GND, CR5.A, Q2.E, C16.2, R25.2, Q3.E)
|
||||
NET_C(CR5.K, Q2.B, antenna)
|
||||
NET_C(Q2.C, C16.1, R25.1, Q3.B, R27.2)
|
||||
NET_C(R27.1, CR7.A, R31.2) //CR7.K == IN
|
||||
NET_C(R31.1, Q1.C)
|
||||
NET_C(Q3.C, R26.2, CR3.A, CR4.A, E9.5) // E9.6 = Q Q3.C=QQ CR3.K = COIN*1 CR4.K = COIN*2
|
||||
NET_C(R26.1, Q1.B, C19.2, R32.2)
|
||||
NET_C(Q1.E, C19.1, R32.1, V5)
|
||||
NET_C(GND, CR5.A, Q2.E, C16.2, R25.2, Q3.E)
|
||||
NET_C(CR5.K, Q2.B, antenna)
|
||||
NET_C(Q2.C, C16.1, R25.1, Q3.B, R27.2)
|
||||
NET_C(R27.1, CR7.A, R31.2) //CR7.K == IN
|
||||
NET_C(R31.1, Q1.C)
|
||||
NET_C(Q3.C, R26.2, CR3.A, CR4.A, E9.5) // E9.6 = Q Q3.C=QQ CR3.K = COIN*1 CR4.K = COIN*2
|
||||
NET_C(R26.1, Q1.B, C19.2, R32.2)
|
||||
NET_C(Q1.E, C19.1, R32.1, V5)
|
||||
|
||||
#define LAT_Q "E9", 6
|
||||
#define Q_n "Q3", C
|
||||
#define COIN1_n "F8", 5
|
||||
#define COIN2_n "H9", 5
|
||||
|
||||
CONNECTION("CR7", K, "D8", 11) //set
|
||||
CONNECTION("CR7", K, "D8", 11) //set
|
||||
CONNECTION("CR3", K, COIN1_n) //reset
|
||||
CONNECTION("CR4", K, COIN2_n) //reset
|
||||
|
||||
@ -440,31 +440,31 @@ CIRCUIT_LAYOUT( breakout )
|
||||
#define EGL "C37" , 2
|
||||
#define EGL_n "C5", 2
|
||||
|
||||
#define RAM_PLAYER1 "E7", 4
|
||||
#define A1 "H6", 14
|
||||
#define B1 "H6", 13
|
||||
#define C1 "H6", 12
|
||||
#define D1 "H6", 11
|
||||
#define E1 "J6", 14
|
||||
#define F1 "J6", 13
|
||||
#define G1 "J6", 12
|
||||
#define H01 "J6", 11
|
||||
#define I1 "K6", 14
|
||||
#define J1 "K6", 13
|
||||
#define K1 "K6", 12
|
||||
#define L1 "K6", 11
|
||||
#define A2 "N6", 14
|
||||
#define B2 "N6", 13
|
||||
#define C2 "N6", 12
|
||||
#define D2 "N6", 11
|
||||
#define E2s "M6", 14
|
||||
#define F2 "M6", 13
|
||||
#define G2 "M6", 12
|
||||
#define H02 "M6", 11 //TODO: better name for these signals
|
||||
#define I2 "L6", 14
|
||||
#define J2 "L6", 13
|
||||
#define K2 "L6", 12
|
||||
#define L2 "L6", 11
|
||||
#define RAM_PLAYER1 "E7", 4
|
||||
#define A1 "H6", 14
|
||||
#define B1 "H6", 13
|
||||
#define C1 "H6", 12
|
||||
#define D1 "H6", 11
|
||||
#define E1 "J6", 14
|
||||
#define F1 "J6", 13
|
||||
#define G1 "J6", 12
|
||||
#define H01 "J6", 11
|
||||
#define I1 "K6", 14
|
||||
#define J1 "K6", 13
|
||||
#define K1 "K6", 12
|
||||
#define L1 "K6", 11
|
||||
#define A2 "N6", 14
|
||||
#define B2 "N6", 13
|
||||
#define C2 "N6", 12
|
||||
#define D2 "N6", 11
|
||||
#define E2s "M6", 14
|
||||
#define F2 "M6", 13
|
||||
#define G2 "M6", 12
|
||||
#define H02 "M6", 11 //TODO: better name for these signals
|
||||
#define I2 "L6", 14
|
||||
#define J2 "L6", 13
|
||||
#define K2 "L6", 12
|
||||
#define L2 "L6", 11
|
||||
|
||||
#define CX0 "C6", 11
|
||||
#define CX1 "C6", 6
|
||||
@ -772,18 +772,18 @@ CIRCUIT_LAYOUT( breakout )
|
||||
CONNECTION(BALL_C, "C4", 10)
|
||||
CONNECTION("A4", 11, "C4", 9)
|
||||
|
||||
CONNECTION(A2, "N5", 1)
|
||||
CONNECTION(E2s, "N5", 2)
|
||||
CONNECTION(I2, "N5", 3)
|
||||
CONNECTION("C5", 6, "N5", 4)
|
||||
CONNECTION(A1, "N5", 5)
|
||||
CONNECTION(E1, "N5", 6)
|
||||
CONNECTION(I1, "N5", 7)
|
||||
CONNECTION(PLAYER_2_n, "N5", 9)
|
||||
CONNECTION(H32_n, "N5", 10)
|
||||
CONNECTION(V16, "N5", 11)
|
||||
CONNECTION(V64, "N5", 12)
|
||||
CONNECTION(V128, "N5", 13)
|
||||
CONNECTION(A2, "N5", 1)
|
||||
CONNECTION(E2s, "N5", 2)
|
||||
CONNECTION(I2, "N5", 3)
|
||||
CONNECTION("C5", 6, "N5", 4)
|
||||
CONNECTION(A1, "N5", 5)
|
||||
CONNECTION(E1, "N5", 6)
|
||||
CONNECTION(I1, "N5", 7)
|
||||
CONNECTION(PLAYER_2_n, "N5", 9)
|
||||
CONNECTION(H32_n, "N5", 10)
|
||||
CONNECTION(V16, "N5", 11)
|
||||
CONNECTION(V64, "N5", 12)
|
||||
CONNECTION(V128, "N5", 13)
|
||||
|
||||
CONNECTION(B2, "M5", 1)
|
||||
CONNECTION(F2, "M5", 2)
|
||||
@ -1561,7 +1561,7 @@ CIRCUIT_LAYOUT( breakout )
|
||||
CONNECTION(PSYNC, "B9", 1)
|
||||
CONNECTION(VSYNC_n, "B9", 2)
|
||||
|
||||
// VIDEO SUMMING
|
||||
// VIDEO SUMMING
|
||||
RES(R41, RES_K(3.9))
|
||||
RES(R42, RES_K(3.9))
|
||||
RES(R43, RES_K(3.9))
|
||||
|
||||
@ -9,14 +9,14 @@
|
||||
|
||||
#include "netlist/devices/net_lib.h"
|
||||
|
||||
#define FAST_CLOCK (1)
|
||||
#define FAST_CLOCK (1)
|
||||
|
||||
NETLIST_START(pong_fast)
|
||||
SOLVER(Solver, 48000)
|
||||
PARAM(Solver.PARALLEL, 0) // Don't do parallel solvers
|
||||
PARAM(Solver.ACCURACY, 1e-4) // works and is sufficient
|
||||
PARAM(Solver.LTE, 1e-4) // Default is not enough for paddle control if using LTE
|
||||
PARAM(NETLIST.USE_DEACTIVATE, 1)
|
||||
PARAM(NETLIST.USE_DEACTIVATE, 1)
|
||||
|
||||
ANALOG_INPUT(V5, 5)
|
||||
|
||||
|
||||
@ -2,32 +2,32 @@
|
||||
// copyright-holders:Ville Linde
|
||||
/* Konami NWK-TR System
|
||||
|
||||
Driver by Ville Linde
|
||||
Driver by Ville Linde
|
||||
|
||||
|
||||
|
||||
Hardware overview:
|
||||
Hardware overview:
|
||||
|
||||
GN676 CPU Board:
|
||||
----------------
|
||||
IBM PowerPC 403GA at 32MHz (main CPU)
|
||||
Motorola MC68EC000 at 16MHz (sound CPU)
|
||||
Konami K056800 (MIRAC), sound system interface
|
||||
Ricoh RF5c400 sound chip
|
||||
National Semiconductor ADC12138
|
||||
GN676 CPU Board:
|
||||
----------------
|
||||
IBM PowerPC 403GA at 32MHz (main CPU)
|
||||
Motorola MC68EC000 at 16MHz (sound CPU)
|
||||
Konami K056800 (MIRAC), sound system interface
|
||||
Ricoh RF5c400 sound chip
|
||||
National Semiconductor ADC12138
|
||||
|
||||
GN676 GFX Board:
|
||||
----------------
|
||||
Analog Devices ADSP-21062 SHARC DSP at 36MHz
|
||||
Konami K001604 (2D tilemaps + 2x ROZ)
|
||||
Konami 0000033906 (PCI bridge)
|
||||
3DFX 500-0003-03 (Voodoo) FBI with 2MB RAM
|
||||
2x 3DFX 500-0004-02 (Voodoo) TMU with 2MB RAM
|
||||
GN676 GFX Board:
|
||||
----------------
|
||||
Analog Devices ADSP-21062 SHARC DSP at 36MHz
|
||||
Konami K001604 (2D tilemaps + 2x ROZ)
|
||||
Konami 0000033906 (PCI bridge)
|
||||
3DFX 500-0003-03 (Voodoo) FBI with 2MB RAM
|
||||
2x 3DFX 500-0004-02 (Voodoo) TMU with 2MB RAM
|
||||
|
||||
GN676 LAN Board:
|
||||
----------------
|
||||
Xilinx XC5210 FPGA
|
||||
Xilinx XC5204 FPGA
|
||||
GN676 LAN Board:
|
||||
----------------
|
||||
Xilinx XC5210 FPGA
|
||||
Xilinx XC5204 FPGA
|
||||
|
||||
|
||||
Konami 'NWK-TR' Hardware
|
||||
@ -90,56 +90,56 @@ Konami 1997
|
||||
|M48T58Y-70PC1 CN4 DSW(8) CN6 64.000MHz|
|
||||
|--------------------------------------------------------------|
|
||||
Notes:
|
||||
DRM1M4SJ8 - Fujitsu 81C4256 256kx4 DRAM (SOJ24)
|
||||
SRAM256K - Cypress CY7C199 32kx8 SRAM (SOJ28)
|
||||
DRAM16X16 - Fujitsu 8118160A-60 16megx16 DRAM (SOJ42)
|
||||
M48T58Y-70PC1 - ST Timekeeper RAM
|
||||
RF5C400 - Ricoh RF5C400 PCM 32Ch, 44.1 kHz Stereo, 3D Effect Spatializer, clock input 16.9344MHz
|
||||
056800 - Konami Custom (QFP80)
|
||||
058232 - Konami Custom Ceramic Package (SIL14)
|
||||
ADC12138 - National Semiconductor ADC12138 A/D Converter, 12-bit + Serial I/O With MUX (SOP28)
|
||||
MACH111 - AMD MACH111 CPLD (Stamped 'N676A1', PLCC44)
|
||||
68EC000 - Motorola MC68EC000, running at 16.0MHz (64/4)
|
||||
PPC403GA - IBM PowerPC 403GA CPU, clock input 32.0MHz (64/2) (QFP160)
|
||||
SM5877AM - Nippon Precision Circuits 3rd Order 2-Channel D/A Converter (SOIC24)
|
||||
4AK16 - Hitachi 4AK16 Silicon N-Channel Power MOS FET Array (SIL10)
|
||||
NE5532AN - Philips, Dual Low-Noise High-Speed Audio OP Amp (DIP8)
|
||||
SP485CS - Sipex SP485CS Low Power Half Duplex RS485 Transceiver (DIP8)
|
||||
AN7395S - Panasonic AM7395S Spatializer Audio Processor IC for 3D surround (SOIC20)
|
||||
PAL1 - AMD PALCE16V8 (stamped 'N676A4', DIP20)
|
||||
PAL2 - AMD PALCE16V8 (stamped 'N676A2', DIP20)
|
||||
PAL3 - AMD PALCE16V8 (stamped 'N676A3', DIP20)
|
||||
PAL4 - AMD PALCE16V8 (stamped 'N676A5', DIP20)
|
||||
JP1 - 25M O O-O 32M
|
||||
JP2 - 25M O O-O 32M
|
||||
JP3 - RW O O O RO
|
||||
JP4 - PROG 32M O O-O 16M
|
||||
JP5 - DATA 32M O-O O 16M
|
||||
JP6 - BOOT 16 O-O O 32
|
||||
JP7 - SRC DOUT2 O O-O 0
|
||||
JP8 - 64M&32M O-O O 16M
|
||||
JP9 - 64M O O-O 32M&16M
|
||||
JP10 - 64M&32M O-O O 16M
|
||||
JP11 - 64M O O-O 32M&16M
|
||||
JP12 - through O-O O SP
|
||||
JP13 - through O-O O SP
|
||||
JP14 - WDT O O
|
||||
JP15 - MONO O-O O SURR
|
||||
JP16 - HIGH O O O MID (N/C LOW)
|
||||
CN1 to CN3 - D-SUB Connectors
|
||||
CN4 - Multi-pin Connector for Network PCB
|
||||
CN5 - DIN96 connector (pads only, not used)
|
||||
CN6 - DIN96 joining connector to lower PCB
|
||||
CN7 - Multi-pin connector (pads only, not used)
|
||||
CN9 to CN13 - Power Connectors
|
||||
CN14 to CN17 - RCA Stereo Audio OUT
|
||||
CN18 - RCA Mono Audio OUT
|
||||
CN19 - USB Connector
|
||||
DRM1M4SJ8 - Fujitsu 81C4256 256kx4 DRAM (SOJ24)
|
||||
SRAM256K - Cypress CY7C199 32kx8 SRAM (SOJ28)
|
||||
DRAM16X16 - Fujitsu 8118160A-60 16megx16 DRAM (SOJ42)
|
||||
M48T58Y-70PC1 - ST Timekeeper RAM
|
||||
RF5C400 - Ricoh RF5C400 PCM 32Ch, 44.1 kHz Stereo, 3D Effect Spatializer, clock input 16.9344MHz
|
||||
056800 - Konami Custom (QFP80)
|
||||
058232 - Konami Custom Ceramic Package (SIL14)
|
||||
ADC12138 - National Semiconductor ADC12138 A/D Converter, 12-bit + Serial I/O With MUX (SOP28)
|
||||
MACH111 - AMD MACH111 CPLD (Stamped 'N676A1', PLCC44)
|
||||
68EC000 - Motorola MC68EC000, running at 16.0MHz (64/4)
|
||||
PPC403GA - IBM PowerPC 403GA CPU, clock input 32.0MHz (64/2) (QFP160)
|
||||
SM5877AM - Nippon Precision Circuits 3rd Order 2-Channel D/A Converter (SOIC24)
|
||||
4AK16 - Hitachi 4AK16 Silicon N-Channel Power MOS FET Array (SIL10)
|
||||
NE5532AN - Philips, Dual Low-Noise High-Speed Audio OP Amp (DIP8)
|
||||
SP485CS - Sipex SP485CS Low Power Half Duplex RS485 Transceiver (DIP8)
|
||||
AN7395S - Panasonic AM7395S Spatializer Audio Processor IC for 3D surround (SOIC20)
|
||||
PAL1 - AMD PALCE16V8 (stamped 'N676A4', DIP20)
|
||||
PAL2 - AMD PALCE16V8 (stamped 'N676A2', DIP20)
|
||||
PAL3 - AMD PALCE16V8 (stamped 'N676A3', DIP20)
|
||||
PAL4 - AMD PALCE16V8 (stamped 'N676A5', DIP20)
|
||||
JP1 - 25M O O-O 32M
|
||||
JP2 - 25M O O-O 32M
|
||||
JP3 - RW O O O RO
|
||||
JP4 - PROG 32M O O-O 16M
|
||||
JP5 - DATA 32M O-O O 16M
|
||||
JP6 - BOOT 16 O-O O 32
|
||||
JP7 - SRC DOUT2 O O-O 0
|
||||
JP8 - 64M&32M O-O O 16M
|
||||
JP9 - 64M O O-O 32M&16M
|
||||
JP10 - 64M&32M O-O O 16M
|
||||
JP11 - 64M O O-O 32M&16M
|
||||
JP12 - through O-O O SP
|
||||
JP13 - through O-O O SP
|
||||
JP14 - WDT O O
|
||||
JP15 - MONO O-O O SURR
|
||||
JP16 - HIGH O O O MID (N/C LOW)
|
||||
CN1 to CN3 - D-SUB Connectors
|
||||
CN4 - Multi-pin Connector for Network PCB
|
||||
CN5 - DIN96 connector (pads only, not used)
|
||||
CN6 - DIN96 joining connector to lower PCB
|
||||
CN7 - Multi-pin connector (pads only, not used)
|
||||
CN9 to CN13 - Power Connectors
|
||||
CN14 to CN17 - RCA Stereo Audio OUT
|
||||
CN18 - RCA Mono Audio OUT
|
||||
CN19 - USB Connector
|
||||
|
||||
|
||||
ROM Usage
|
||||
---------
|
||||
|------------------------------- ROM Locations -------------------------------------|
|
||||
|------------------------------- ROM Locations -------------------------------------|
|
||||
Game 27P 25P 22P 16P 14P 12P 9P 16T 14T 12T 9T 7S
|
||||
--------------------------------------------------------------------------------------------------
|
||||
Racing Jam 676NC01 - - 676A09 676A10 - - 676A04 676A05 - - 676A08
|
||||
@ -163,18 +163,18 @@ sticker - GC713AC
|
||||
| CN1 |
|
||||
|------------------------|
|
||||
Notes:
|
||||
CN1 - Connector joining to CPU board CN4
|
||||
CN2/3 - RCA jacks for network cable
|
||||
2G - Small SOIC8 chip with number 0038323 at location 2G. An identical chip is present on
|
||||
*some* Hornet games on the GN715 CPU board at location 30C. It may be a PIC or EEPROM.
|
||||
On Hornet, the chip seems to refresh the data in the Timekeeper RAM when the battery
|
||||
dies and keeps the game working. It's purpose on the network board is unknown but it may
|
||||
'upgrade' the data in the NVRAM to the network version of the game for a twin cabinet set-up.
|
||||
HYC2485S - Hybrid ceramic module for RS485
|
||||
CY7C199 - 32k x8 SRAM
|
||||
XC5204 - Xilinx XC5204 FPGA
|
||||
XC5210 - Xilink XC5210 FPGA
|
||||
N676H1 - PALCE16V8Q-15 stamped 'N676H1'
|
||||
CN1 - Connector joining to CPU board CN4
|
||||
CN2/3 - RCA jacks for network cable
|
||||
2G - Small SOIC8 chip with number 0038323 at location 2G. An identical chip is present on
|
||||
*some* Hornet games on the GN715 CPU board at location 30C. It may be a PIC or EEPROM.
|
||||
On Hornet, the chip seems to refresh the data in the Timekeeper RAM when the battery
|
||||
dies and keeps the game working. It's purpose on the network board is unknown but it may
|
||||
'upgrade' the data in the NVRAM to the network version of the game for a twin cabinet set-up.
|
||||
HYC2485S - Hybrid ceramic module for RS485
|
||||
CY7C199 - 32k x8 SRAM
|
||||
XC5204 - Xilinx XC5204 FPGA
|
||||
XC5210 - Xilink XC5210 FPGA
|
||||
N676H1 - PALCE16V8Q-15 stamped 'N676H1'
|
||||
|
||||
|
||||
Bottom Board (VIDEO PCB)
|
||||
@ -211,34 +211,34 @@ GN676 PWB(B)B
|
||||
| 256KSRAM 256KSRAM JP2 CN1 PAL2 |
|
||||
|-------------------------------------------------------------------------------------------|
|
||||
Notes:
|
||||
4M_EDO - Silicon Magic SM81C256K16CJ-35 EDO DRAM 66MHz (SOJ40)
|
||||
1MSRAM - Cypress CY7C109-25VC 1Meg SRAM (SOJ32)
|
||||
256KSRAM - Winbond W24257AJ-15 256k SRAM (SOJ28)
|
||||
TEXELFX - 3DFX 500-0004-02 BD0665.1 TMU (QFP208)
|
||||
PIXELFX - 3DFX 500-0003-03 F001701.1 FBI (QFP240)
|
||||
001604 - Konami Custom (QFP208)
|
||||
MC44200FT - Motorola MC44200FT 3 Channel Video D/A Converter (QFP44)
|
||||
MACH111 - AMD MACH111 CPLD (Stamped '03161A', PLCC44)
|
||||
PLCC44_SOCKET - empty PLCC44 socket
|
||||
AV9170 - Integrated Circuit Systems Inc. Clock Multiplier (SOIC8)
|
||||
AM7201 - AMD AM7201 FIFO (PLCC32)
|
||||
PAL1 - AMD PALCE16V8 (stamped 'N676B4', DIP20)
|
||||
PAL2 - AMD PALCE16V8 (stamped 'N676B5', DIP20)
|
||||
PAL3 - AMD PALCE16V8 (stamped 'N676B2', DIP20)
|
||||
JP1 - SLV O O-O MST,TWN (sets board to MASTER TWIN or SLAVE)
|
||||
JP2 - SLV O O-O MST (sets board to MASTER or SLAVE)
|
||||
CN1 - 96 Pin joining connector to upper PCB
|
||||
CN2 - 8-Pin 24kHz RGB OUT
|
||||
CN3 - 15-Pin DSUB VGA Video MAIN OUT
|
||||
CN4 - 6-Pin Power Connector
|
||||
CN5 - 4-Pin Power Connector
|
||||
CN6 - 2-Pin Connector (Not Used)
|
||||
CN7 - 6-Pin Connector
|
||||
4M_EDO - Silicon Magic SM81C256K16CJ-35 EDO DRAM 66MHz (SOJ40)
|
||||
1MSRAM - Cypress CY7C109-25VC 1Meg SRAM (SOJ32)
|
||||
256KSRAM - Winbond W24257AJ-15 256k SRAM (SOJ28)
|
||||
TEXELFX - 3DFX 500-0004-02 BD0665.1 TMU (QFP208)
|
||||
PIXELFX - 3DFX 500-0003-03 F001701.1 FBI (QFP240)
|
||||
001604 - Konami Custom (QFP208)
|
||||
MC44200FT - Motorola MC44200FT 3 Channel Video D/A Converter (QFP44)
|
||||
MACH111 - AMD MACH111 CPLD (Stamped '03161A', PLCC44)
|
||||
PLCC44_SOCKET - empty PLCC44 socket
|
||||
AV9170 - Integrated Circuit Systems Inc. Clock Multiplier (SOIC8)
|
||||
AM7201 - AMD AM7201 FIFO (PLCC32)
|
||||
PAL1 - AMD PALCE16V8 (stamped 'N676B4', DIP20)
|
||||
PAL2 - AMD PALCE16V8 (stamped 'N676B5', DIP20)
|
||||
PAL3 - AMD PALCE16V8 (stamped 'N676B2', DIP20)
|
||||
JP1 - SLV O O-O MST,TWN (sets board to MASTER TWIN or SLAVE)
|
||||
JP2 - SLV O O-O MST (sets board to MASTER or SLAVE)
|
||||
CN1 - 96 Pin joining connector to upper PCB
|
||||
CN2 - 8-Pin 24kHz RGB OUT
|
||||
CN3 - 15-Pin DSUB VGA Video MAIN OUT
|
||||
CN4 - 6-Pin Power Connector
|
||||
CN5 - 4-Pin Power Connector
|
||||
CN6 - 2-Pin Connector (Not Used)
|
||||
CN7 - 6-Pin Connector
|
||||
|
||||
|
||||
ROM Usage
|
||||
---------
|
||||
|------ ROM Locations -------|
|
||||
|------ ROM Locations -------|
|
||||
Game 8X 8Y 16X 16Y
|
||||
-------------------------------------------
|
||||
Racing Jam 676A13 - 676A14 -
|
||||
|
||||
@ -425,47 +425,47 @@ WRITE32_MEMBER(savquest_state::bios_ec000_ram_w)
|
||||
|
||||
static const UINT8 m_hasp_cmppass[] = {0xc3, 0xd9, 0xd3, 0xfb, 0x9d, 0x89, 0xb9, 0xa1, 0xb3, 0xc1, 0xf1, 0xcd, 0xdf, 0x9d}; /* 0x9d or 0x9e */
|
||||
static const UINT8 m_hasp_prodinfo[] = {0x51, 0x4c, 0x52, 0x4d, 0x53, 0x4e, 0x53, 0x4e, 0x53, 0x49, 0x53, 0x48, 0x53, 0x4b, 0x53, 0x4a,
|
||||
0x53, 0x43, 0x53, 0x45, 0x52, 0x46, 0x53, 0x43, 0x53, 0x41, 0xac, 0x40, 0x53, 0xbc, 0x53, 0x42,
|
||||
0x53, 0x57, 0x53, 0x5d, 0x52, 0x5e, 0x53, 0x5b, 0x53, 0x59, 0xac, 0x58, 0x53, 0xa4
|
||||
};
|
||||
0x53, 0x43, 0x53, 0x45, 0x52, 0x46, 0x53, 0x43, 0x53, 0x41, 0xac, 0x40, 0x53, 0xbc, 0x53, 0x42,
|
||||
0x53, 0x57, 0x53, 0x5d, 0x52, 0x5e, 0x53, 0x5b, 0x53, 0x59, 0xac, 0x58, 0x53, 0xa4
|
||||
};
|
||||
|
||||
READ8_MEMBER(savquest_state::parallel_port_r)
|
||||
{
|
||||
if (offset == 1)
|
||||
{
|
||||
if ((m_haspstate == HASPSTATE_READ)
|
||||
&& (m_hasp_passmode == 3)
|
||||
)
|
||||
&& (m_hasp_passmode == 3)
|
||||
)
|
||||
{
|
||||
/* passmode 3 is used to retrieve the product(s) information
|
||||
it comes in two parts: header and product
|
||||
the header has this format:
|
||||
offset range purpose
|
||||
00 01 header type
|
||||
01 01-05 count of used product slots, must be 2
|
||||
02 01-05 count of unused product slots
|
||||
this is assumed to be 6-(count of used slots)
|
||||
but it is not enforced here
|
||||
however a total of 6 structures will be checked
|
||||
03 01-02 unknown
|
||||
04 01-46 country code
|
||||
05-0f 00 reserved
|
||||
the used product slots have this format:
|
||||
(the unused product slots must be entirely zeroes)
|
||||
00-01 0001-000a product ID, one must be 6, the other 0a
|
||||
02 0001-0003 unknown but must be 0001
|
||||
04 01-05 HASP plug country ID
|
||||
05 01-02 unknown but must be 01
|
||||
06 05 unknown
|
||||
07-0a any unknown, not used
|
||||
0b ff unknown
|
||||
0c ff unknown
|
||||
0d-0f 00 reserved
|
||||
offset range purpose
|
||||
00 01 header type
|
||||
01 01-05 count of used product slots, must be 2
|
||||
02 01-05 count of unused product slots
|
||||
this is assumed to be 6-(count of used slots)
|
||||
but it is not enforced here
|
||||
however a total of 6 structures will be checked
|
||||
03 01-02 unknown
|
||||
04 01-46 country code
|
||||
05-0f 00 reserved
|
||||
the used product slots have this format:
|
||||
(the unused product slots must be entirely zeroes)
|
||||
00-01 0001-000a product ID, one must be 6, the other 0a
|
||||
02 0001-0003 unknown but must be 0001
|
||||
04 01-05 HASP plug country ID
|
||||
05 01-02 unknown but must be 01
|
||||
06 05 unknown
|
||||
07-0a any unknown, not used
|
||||
0b ff unknown
|
||||
0c ff unknown
|
||||
0d-0f 00 reserved
|
||||
|
||||
the read is performed by accessing an array of 16-bit big-endian values
|
||||
and returning one bit at a time into bit 5 of the result
|
||||
the 16-bit value is then XORed with 0x534d and the register index
|
||||
*/
|
||||
the read is performed by accessing an array of 16-bit big-endian values
|
||||
and returning one bit at a time into bit 5 of the result
|
||||
the 16-bit value is then XORed with 0x534d and the register index
|
||||
*/
|
||||
|
||||
if (m_hasp_prodind <= (sizeof(m_hasp_prodinfo) * 8))
|
||||
{
|
||||
@ -567,24 +567,24 @@ WRITE8_MEMBER(savquest_state::parallel_port_w)
|
||||
*/
|
||||
|
||||
if ((data8 == 0x94)
|
||||
|| (data8 == 0x9e)
|
||||
|| (data8 == 0xa4)
|
||||
|| (data8 == 0xb2)
|
||||
|| (data8 == 0xbe)
|
||||
|| (data8 == 0xd0)
|
||||
)
|
||||
|| (data8 == 0x9e)
|
||||
|| (data8 == 0xa4)
|
||||
|| (data8 == 0xb2)
|
||||
|| (data8 == 0xbe)
|
||||
|| (data8 == 0xd0)
|
||||
)
|
||||
{
|
||||
return;
|
||||
}
|
||||
|
||||
if ((data8 == 0x8a)
|
||||
|| (data8 == 0x8e)
|
||||
|| (data8 == 0xca)
|
||||
|| (data8 == 0xd2)
|
||||
|| (data8 == 0xe2)
|
||||
|| (data8 == 0xf0)
|
||||
|| (data8 == 0xfc)
|
||||
)
|
||||
|| (data8 == 0x8e)
|
||||
|| (data8 == 0xca)
|
||||
|| (data8 == 0xd2)
|
||||
|| (data8 == 0xe2)
|
||||
|| (data8 == 0xf0)
|
||||
|| (data8 == 0xfc)
|
||||
)
|
||||
{
|
||||
/* someone with access to the actual dongle could dump the true values
|
||||
I've never seen it so I just determined the relevant bits instead
|
||||
@ -648,8 +648,8 @@ WRITE8_MEMBER(savquest_state::parallel_port_w)
|
||||
if (data8 & 1)
|
||||
{
|
||||
if ((m_hasp_passmode == 1)
|
||||
&& (data8 == 0x9d)
|
||||
)
|
||||
&& (data8 == 0x9d)
|
||||
)
|
||||
{
|
||||
m_hasp_passmode = 2;
|
||||
}
|
||||
@ -663,8 +663,8 @@ WRITE8_MEMBER(savquest_state::parallel_port_w)
|
||||
if (++m_hasp_passind == sizeof(m_hasp_tmppass))
|
||||
{
|
||||
if ((m_hasp_tmppass[0] == 0x9c)
|
||||
&& (m_hasp_tmppass[1] == 0x9e)
|
||||
)
|
||||
&& (m_hasp_tmppass[1] == 0x9e)
|
||||
)
|
||||
{
|
||||
int i;
|
||||
|
||||
@ -690,7 +690,7 @@ WRITE8_MEMBER(savquest_state::parallel_port_w)
|
||||
}
|
||||
}
|
||||
else if ((m_haspstate == HASPSTATE_PASSBEG)
|
||||
&& (data8 & 1)
|
||||
&& (data8 & 1)
|
||||
)
|
||||
{
|
||||
m_hasp_tmppass[m_hasp_passind] = data8;
|
||||
@ -725,7 +725,7 @@ WRITE8_MEMBER(savquest_state::smram_w)
|
||||
}
|
||||
|
||||
static ADDRESS_MAP_START(savquest_map, AS_PROGRAM, 32, savquest_state)
|
||||
ADDRESS_MAP_UNMAP_HIGH
|
||||
ADDRESS_MAP_UNMAP_HIGH
|
||||
AM_RANGE(0x00000000, 0x0009ffff) AM_RAM
|
||||
AM_RANGE(0x000a0000, 0x000bffff) AM_READWRITE8(smram_r,smram_w,0xffffffff) //AM_DEVREADWRITE8("vga", vga_device, mem_r, mem_w, 0xffffffff)
|
||||
AM_RANGE(0x000c0000, 0x000c7fff) AM_ROM AM_REGION("video_bios", 0)
|
||||
|
||||
@ -55,8 +55,8 @@ public:
|
||||
|
||||
PALETTE_INIT_MEMBER(sealy_state,sealy)
|
||||
{
|
||||
// for (int i = 0; i < 32768; i++)
|
||||
// palette.set_pen_color(i,pal5bit(i >> 5),pal5bit(i >> 10),pal5bit(i >> 0));
|
||||
// for (int i = 0; i < 32768; i++)
|
||||
// palette.set_pen_color(i,pal5bit(i >> 5),pal5bit(i >> 10),pal5bit(i >> 0));
|
||||
}
|
||||
|
||||
UINT32 sealy_state::screen_update_sealy(screen_device &screen, bitmap_rgb32 &bitmap, const rectangle &cliprect)
|
||||
|
||||
@ -194,12 +194,12 @@ static ADDRESS_MAP_START( segasp_map, AS_PROGRAM, 64, segasp_state )
|
||||
/* External Device */
|
||||
AM_RANGE(0x01000000, 0x0100ffff) AM_RAM // banked access to ROM/NET board address space, mainly backup SRAM and ATA
|
||||
AM_RANGE(0x01010000, 0x01010007) AM_READWRITE(sp_bank_r, sp_bank_w )
|
||||
// AM_RANGE(0x01010080, 0x01010087) IRQ pending/reset, ATA control
|
||||
// AM_RANGE(0x01010080, 0x01010087) IRQ pending/reset, ATA control
|
||||
AM_RANGE(0x01010100, 0x01010127) AM_READ(sp_io_r)
|
||||
AM_RANGE(0x01010128, 0x0101012f) AM_READWRITE(sp_eeprom_r, sp_eeprom_w )
|
||||
AM_RANGE(0x01010150, 0x01010157) AM_READ(sp_rombdflg_r)
|
||||
// AM_RANGE(0x01010180, 0x010101af) custom UART 1
|
||||
// AM_RANGE(0x010101c0, 0x010101ef) custom UART 2
|
||||
// AM_RANGE(0x01010180, 0x010101af) custom UART 1
|
||||
// AM_RANGE(0x010101c0, 0x010101ef) custom UART 2
|
||||
|
||||
/* Area 1 */
|
||||
AM_RANGE(0x04000000, 0x04ffffff) AM_MIRROR(0x02000000) AM_RAM AM_SHARE("dc_texture_ram") // texture memory 64 bit access
|
||||
@ -370,7 +370,7 @@ ROM_START( brickppl )
|
||||
ROM_LOAD( "ic64", 0x08000000, 0x4000000, CRC(383e90d9) SHA1(eeca4b1bd0cd1fed7b85f045d71e0c7258d4350b) )
|
||||
ROM_LOAD( "ic65", 0x0c000000, 0x4000000, CRC(4c29b5ac) SHA1(9e6a79ad2d2498eed5b2590c8764222e7d6c0229) )
|
||||
|
||||
ROM_REGION( 0x04, "boardid", ROMREGION_ERASEVAL(0x08)) // 8x 512Mbit FlashROMs
|
||||
ROM_REGION( 0x04, "boardid", ROMREGION_ERASEVAL(0x08)) // 8x 512Mbit FlashROMs
|
||||
|
||||
ROM_REGION( 0x800, "pic_readout", 0 )
|
||||
ROM_LOAD( "317-0558-com.ic15", 0, 0x800, BAD_DUMP CRC(7592d004) SHA1(632373d807f54953d68c95a9f874ed3e8011f085) )
|
||||
@ -392,7 +392,7 @@ ROM_START( dinoking )
|
||||
ROM_LOAD( "ic69s", 0x07000000, 0x01000000, CRC(c78e46c2) SHA1(b8224c68face23010414d13ebb4cc05a2a9dce8a) )
|
||||
|
||||
|
||||
ROM_REGION( 0x04, "boardid", ROMREGION_ERASEVAL(0x02)) // actually 8x 128Mbit FlashROMs
|
||||
ROM_REGION( 0x04, "boardid", ROMREGION_ERASEVAL(0x02)) // actually 8x 128Mbit FlashROMs
|
||||
|
||||
ROM_REGION( 0x800, "pic_readout", 0 )
|
||||
ROM_LOAD( "317-0408-com.ic15", 0, 0x800, BAD_DUMP CRC(0e94daba) SHA1(4e9722333a29afd0dbadba78b16344b77a689610) )
|
||||
@ -413,7 +413,7 @@ ROM_START( dinokior )
|
||||
ROM_LOAD( "ic68s", 0x06000000, 0x01000000, CRC(ff5ed2b8) SHA1(d8d86b3ed976c8c8fc51d225ae661e5f237b6e1d) )
|
||||
ROM_LOAD( "ic69s", 0x07000000, 0x01000000, CRC(ab8ac4eb) SHA1(e6b3ce796ae4887011e2764261f3f437dc9939f9) )
|
||||
|
||||
ROM_REGION( 0x04, "boardid", ROMREGION_ERASEVAL(0x02)) // actually 8x 128Mbit FlashROMs
|
||||
ROM_REGION( 0x04, "boardid", ROMREGION_ERASEVAL(0x02)) // actually 8x 128Mbit FlashROMs
|
||||
|
||||
ROM_REGION( 0x800, "pic_readout", 0 )
|
||||
ROM_LOAD( "317-0408-com.ic15", 0, 0x800, BAD_DUMP CRC(0e94daba) SHA1(4e9722333a29afd0dbadba78b16344b77a689610) )
|
||||
@ -429,7 +429,7 @@ ROM_START( lovebery )
|
||||
ROM_LOAD( "ic62", 0x00000000, 0x4000000, CRC(1bd80ed0) SHA1(d50307573389ebe71e381a75deb83811fa397b94) )
|
||||
ROM_LOAD( "ic63", 0x04000000, 0x4000000, CRC(d3870287) SHA1(efd3630d54068f5a8caf242a48db410bedf48e7a) )
|
||||
|
||||
ROM_REGION( 0x04, "boardid", ROMREGION_ERASEVAL(0x08)) // 8x 512Mbit FlashROMs
|
||||
ROM_REGION( 0x04, "boardid", ROMREGION_ERASEVAL(0x08)) // 8x 512Mbit FlashROMs
|
||||
|
||||
ROM_REGION( 0x800, "pic_readout", 0 )
|
||||
ROM_LOAD( "317-0446-com.ic15", 0, 0x800, BAD_DUMP CRC(60f56bf2) SHA1(35e697aca7213e3fb1ebe75bb8991b1b992af6d9) )
|
||||
@ -453,7 +453,7 @@ ROM_START( lovebero )
|
||||
ROM_LOAD( "ic62", 0x00000000, 0x4000000, CRC(0a23cea3) SHA1(1780d935b0d641769859b2022df8e4262e7bafd8) )
|
||||
ROM_LOAD( "ic63", 0x04000000, 0x4000000, CRC(d3870287) SHA1(efd3630d54068f5a8caf242a48db410bedf48e7a) )
|
||||
|
||||
ROM_REGION( 0x04, "boardid", ROMREGION_ERASEVAL(0x08)) // 8x 512Mbit FlashROMs
|
||||
ROM_REGION( 0x04, "boardid", ROMREGION_ERASEVAL(0x08)) // 8x 512Mbit FlashROMs
|
||||
|
||||
ROM_REGION( 0x800, "pic_readout", 0 )
|
||||
ROM_LOAD( "317-0446-com.ic15", 0, 0x800, BAD_DUMP CRC(60f56bf2) SHA1(35e697aca7213e3fb1ebe75bb8991b1b992af6d9) )
|
||||
@ -469,7 +469,7 @@ ROM_START( tetgiant )
|
||||
ROM_LOAD( "ic62", 0x00000000, 0x4000000, CRC(31ba1938) SHA1(9b5a05193b3df13cd7617a38913e0b0fbd61da44) )
|
||||
ROM_LOAD( "ic63", 0x04000000, 0x4000000, CRC(cb946213) SHA1(6195e33c44a1e8eb464dfc3558dc1c9b4d910ef3) )
|
||||
|
||||
ROM_REGION( 0x04, "boardid", ROMREGION_ERASEVAL(0x02)) // 2x 512Mbit FlashROMs
|
||||
ROM_REGION( 0x04, "boardid", ROMREGION_ERASEVAL(0x02)) // 2x 512Mbit FlashROMs
|
||||
|
||||
ROM_REGION( 0x800, "pic_readout", 0 )
|
||||
ROM_LOAD( "317-0604-com.ic15", 0, 0x800, BAD_DUMP CRC(e8dd2b86) SHA1(765ffd2e4a36302b1db0815e842c9656e29f2457) )
|
||||
@ -487,7 +487,7 @@ ROM_START( dinoki25 )
|
||||
DISK_REGION( "cflash" )
|
||||
DISK_IMAGE( "mda-c0047", 0, SHA1(0f97291d9c5dbe3e66a5220da05aebdfaa78b35d) )
|
||||
|
||||
ROM_REGION( 0x04, "boardid", ROMREGION_ERASEVAL(0x08)) // 8x 512Mbit FlashROMs
|
||||
ROM_REGION( 0x04, "boardid", ROMREGION_ERASEVAL(0x08)) // 8x 512Mbit FlashROMs
|
||||
|
||||
ROM_REGION( 0x800, "pic_readout", 0 )
|
||||
ROM_LOAD( "317-0408-com.ic15", 0, 0x800, BAD_DUMP CRC(0e94daba) SHA1(4e9722333a29afd0dbadba78b16344b77a689610) )
|
||||
@ -511,7 +511,7 @@ ROM_START( loveber3 )
|
||||
DISK_REGION( "cflash" )
|
||||
DISK_IMAGE( "mda-c0042", 0, SHA1(9992d90dae8ce7636e4153e02b779c27931b3be6) )
|
||||
|
||||
ROM_REGION( 0x04, "boardid", ROMREGION_ERASEVAL(0x08)) // 8x 512Mbit FlashROMs
|
||||
ROM_REGION( 0x04, "boardid", ROMREGION_ERASEVAL(0x08)) // 8x 512Mbit FlashROMs
|
||||
|
||||
ROM_REGION( 0x800, "pic_readout", 0 )
|
||||
ROM_LOAD( "317-0446-com.ic15", 0, 0x800, BAD_DUMP CRC(60f56bf2) SHA1(35e697aca7213e3fb1ebe75bb8991b1b992af6d9) )
|
||||
@ -528,7 +528,7 @@ ROM_START( tetgiano )
|
||||
DISK_REGION( "cflash" )
|
||||
DISK_IMAGE( "mda-c0076", 0, SHA1(6987c888d2a3ada2d07f6396d47fdba507ca859d) )
|
||||
|
||||
ROM_REGION( 0x04, "boardid", ROMREGION_ERASEVAL(0x02)) // 2x 512Mbit FlashROMs
|
||||
ROM_REGION( 0x04, "boardid", ROMREGION_ERASEVAL(0x02)) // 2x 512Mbit FlashROMs
|
||||
|
||||
ROM_REGION( 0x800, "pic_readout", 0 )
|
||||
ROM_LOAD( "317-0604-com.ic15", 0, 0x800, BAD_DUMP CRC(e8dd2b86) SHA1(765ffd2e4a36302b1db0815e842c9656e29f2457) )
|
||||
|
||||
@ -300,7 +300,7 @@ void sigmab98_state::video_start()
|
||||
|
||||
inline int integer_part(int x)
|
||||
{
|
||||
// return x >> 16;
|
||||
// return x >> 16;
|
||||
return (x + 0x8000) >> 16;
|
||||
}
|
||||
|
||||
@ -328,14 +328,14 @@ void sigmab98_state::draw_sprites(bitmap_ind16 &bitmap, const rectangle &cliprec
|
||||
int ny = ((s[ 0x06 ] & 0xf8) >> 3) + 1;
|
||||
int dsty = (s[ 0x06 ] & 0x03) * 256 + s[ 0x07 ];
|
||||
|
||||
int dstdx = (s[ 0x08 ] & 0xff) * 256 + s[ 0x09 ]; // 0x100 = no zoom, 0x200 = 50% zoom
|
||||
int dstdy = (s[ 0x0a ] & 0xff) * 256 + s[ 0x0b ]; // ""
|
||||
int dstdx = (s[ 0x08 ] & 0xff) * 256 + s[ 0x09 ]; // 0x100 = no zoom, 0x200 = 50% zoom
|
||||
int dstdy = (s[ 0x0a ] & 0xff) * 256 + s[ 0x0b ]; // ""
|
||||
|
||||
int srcx = (s[ 0x0c ] & 0xff) * 256 + s[ 0x0d ];
|
||||
int srcy = (s[ 0x0e ] & 0xff) * 256 + s[ 0x0f ];
|
||||
|
||||
// Sign extend the position
|
||||
dstx = (dstx & 0x01ff) - (dstx & 0x0200); // or 0x3ff/0x400?
|
||||
dstx = (dstx & 0x01ff) - (dstx & 0x0200); // or 0x3ff/0x400?
|
||||
dsty = (dsty & 0x01ff) - (dsty & 0x0200);
|
||||
|
||||
// Flipping
|
||||
@ -390,17 +390,17 @@ void sigmab98_state::draw_sprites(bitmap_ind16 &bitmap, const rectangle &cliprec
|
||||
dsty <<= 16;
|
||||
|
||||
// Source delta (equal for x and y)
|
||||
int z = int( sqrt(dstdx * dstdx + dstdy * dstdy) + 0.5 ); // dest delta vector is scaled by the source delta!?
|
||||
int z = int( sqrt(dstdx * dstdx + dstdy * dstdy) + 0.5 ); // dest delta vector is scaled by the source delta!?
|
||||
if (!z)
|
||||
z = 0x100;
|
||||
int srcdzz = z << 8;
|
||||
|
||||
// Destination x and y deltas
|
||||
int dstdxx = (dstdx << 16) / z; // dest x delta for source x increments
|
||||
int dstdyx = (dstdy << 16) / z; // dest y delta for source x increments
|
||||
int dstdxx = (dstdx << 16) / z; // dest x delta for source x increments
|
||||
int dstdyx = (dstdy << 16) / z; // dest y delta for source x increments
|
||||
|
||||
int dstdxy = -dstdyx; // dest x delta for source y increments (orthogonal to the above vector)
|
||||
int dstdyy = dstdxx; // dest y delta for source y increments
|
||||
int dstdxy = -dstdyx; // dest x delta for source y increments (orthogonal to the above vector)
|
||||
int dstdyy = dstdxx; // dest y delta for source y increments
|
||||
|
||||
// Transform the source offset in a destination offset (negate, scale and rotate it)
|
||||
srcx = (-srcx << 8) / z;
|
||||
|
||||
@ -1055,14 +1055,14 @@ ROM_START( buccanrsa )
|
||||
ROM_LOAD( "prom2.u99", 0x0300, 0x0100, CRC(e0aa8869) SHA1(ac8bdfeba69420ba56ec561bf3d0f1229d02cea2) )
|
||||
ROM_END
|
||||
|
||||
GAME( 1988, vigilant, 0, vigilant, vigilant, driver_device, 0, ROT0, "Irem", "Vigilante (World, Rev E)", GAME_NO_COCKTAIL | GAME_SUPPORTS_SAVE )
|
||||
GAME( 1988, vigilantg, vigilant, vigilant, vigilant, driver_device, 0, ROT0, "Irem (Data East license)", "Vigilante (US, Rev G)", GAME_NO_COCKTAIL | GAME_SUPPORTS_SAVE )
|
||||
GAME( 1988, vigilano, vigilant, vigilant, vigilant, driver_device, 0, ROT0, "Irem (Data East license)", "Vigilante (US)", GAME_NO_COCKTAIL | GAME_SUPPORTS_SAVE )
|
||||
GAME( 1988, vigilanta, vigilant, vigilant, vigilant, driver_device, 0, ROT0, "Irem", "Vigilante (World, Rev A)", GAME_NO_COCKTAIL | GAME_SUPPORTS_SAVE )
|
||||
GAME( 1988, vigilantb, vigilant, vigilant, vigilant, driver_device, 0, ROT0, "Irem (Data East license)", "Vigilante (US, Rev B)", GAME_NO_COCKTAIL | GAME_SUPPORTS_SAVE )
|
||||
GAME( 1988, vigilantc, vigilant, vigilant, vigilant, driver_device, 0, ROT0, "Irem", "Vigilante (World, Rev C)", GAME_NO_COCKTAIL | GAME_SUPPORTS_SAVE )
|
||||
GAME( 1988, vigilantd, vigilant, vigilant, vigilant, driver_device, 0, ROT0, "Irem", "Vigilante (Japan, Rev D)", GAME_NO_COCKTAIL | GAME_SUPPORTS_SAVE )
|
||||
GAME( 1988, vigilanbl, vigilant, vigilant, vigilant, driver_device, 0, ROT0, "bootleg", "Vigilante (bootleg)", GAME_NO_COCKTAIL | GAME_SUPPORTS_SAVE )
|
||||
GAME( 1988, vigilant, 0, vigilant, vigilant, driver_device, 0, ROT0, "Irem", "Vigilante (World, Rev E)", GAME_NO_COCKTAIL | GAME_SUPPORTS_SAVE )
|
||||
GAME( 1988, vigilantg, vigilant, vigilant, vigilant, driver_device, 0, ROT0, "Irem (Data East license)", "Vigilante (US, Rev G)", GAME_NO_COCKTAIL | GAME_SUPPORTS_SAVE )
|
||||
GAME( 1988, vigilano, vigilant, vigilant, vigilant, driver_device, 0, ROT0, "Irem (Data East license)", "Vigilante (US)", GAME_NO_COCKTAIL | GAME_SUPPORTS_SAVE )
|
||||
GAME( 1988, vigilanta, vigilant, vigilant, vigilant, driver_device, 0, ROT0, "Irem", "Vigilante (World, Rev A)", GAME_NO_COCKTAIL | GAME_SUPPORTS_SAVE )
|
||||
GAME( 1988, vigilantb, vigilant, vigilant, vigilant, driver_device, 0, ROT0, "Irem (Data East license)", "Vigilante (US, Rev B)", GAME_NO_COCKTAIL | GAME_SUPPORTS_SAVE )
|
||||
GAME( 1988, vigilantc, vigilant, vigilant, vigilant, driver_device, 0, ROT0, "Irem", "Vigilante (World, Rev C)", GAME_NO_COCKTAIL | GAME_SUPPORTS_SAVE )
|
||||
GAME( 1988, vigilantd, vigilant, vigilant, vigilant, driver_device, 0, ROT0, "Irem", "Vigilante (Japan, Rev D)", GAME_NO_COCKTAIL | GAME_SUPPORTS_SAVE )
|
||||
GAME( 1988, vigilanbl, vigilant, vigilant, vigilant, driver_device, 0, ROT0, "bootleg", "Vigilante (bootleg)", GAME_NO_COCKTAIL | GAME_SUPPORTS_SAVE )
|
||||
|
||||
GAME( 1988, kikcubic, 0, kikcubic, kikcubic, driver_device, 0, ROT0, "Irem", "Meikyu Jima (Japan)", GAME_NO_COCKTAIL | GAME_SUPPORTS_SAVE ) /* English title is Kickle Cubicle */
|
||||
GAME( 1988, kikcubicb, kikcubic, kikcubic, kikcubic, driver_device, 0, ROT0, "bootleg", "Kickle Cubele", GAME_NO_COCKTAIL | GAME_SUPPORTS_SAVE )
|
||||
|
||||
@ -77,7 +77,7 @@
|
||||
#define VIDEO_CLOCK XTAL_14_31818MHz // Pletronics MP49 14.31818 MHz. Crystal. Used in common VGA ISA cards.
|
||||
|
||||
#define UART_CLOCK XTAL_1_8432MHz // Seems UART clock, since allows integer division to common baud rates.
|
||||
// (16 * 115200 baud, 192 * 9600 baud, 1536 * 1200 baud, etc...)
|
||||
// (16 * 115200 baud, 192 * 9600 baud, 1536 * 1200 baud, etc...)
|
||||
|
||||
|
||||
#include "emu.h"
|
||||
|
||||
@ -195,7 +195,7 @@ yyyyyyyy fccccccc x???pppp xxxxxxxx
|
||||
sx = sprram[offs + 3] - ((sprram[offs + 2] & 0x80) << 1);
|
||||
sy = 256 - 8 - sprram[offs + 0] - 23; // center player sprite: 256 - 8 - 0x71 + dy = 256/2-32/2 -> dy = -23
|
||||
|
||||
// int flipx = sprram[offs + 2] & 0x40; // nope
|
||||
// int flipx = sprram[offs + 2] & 0x40; // nope
|
||||
int flipx = 0;
|
||||
int flipy = sprram[offs + 1] & 0x80;
|
||||
|
||||
|
||||
@ -18,7 +18,7 @@ public:
|
||||
m_bg_videoram(*this, "bg_videoram"),
|
||||
m_spriteram(*this, "spriteram"),
|
||||
m_rombank(*this, "rombank"),
|
||||
m_adpcmrom(*this, "adpcm") { }
|
||||
m_adpcmrom(*this, "adpcm") { }
|
||||
|
||||
required_device<cpu_device> m_maincpu;
|
||||
required_device<cpu_device> m_audiocpu;
|
||||
|
||||
@ -1723,17 +1723,17 @@ int n64_periphs::pif_channel_handle_command(int channel, int slength, UINT8 *sda
|
||||
// Read status
|
||||
switch ((machine().root_device().ioport("input")->read() >> (2 * channel)) & 3)
|
||||
{
|
||||
case 0: //NONE (unconnected)
|
||||
case 3: //Invalid
|
||||
case 0: //NONE (unconnected)
|
||||
case 3: //Invalid
|
||||
return 1;
|
||||
|
||||
case 1: //JOYPAD
|
||||
case 1: //JOYPAD
|
||||
rdata[0] = 0x05;
|
||||
rdata[1] = 0x00;
|
||||
rdata[2] = 0x01;
|
||||
return 0;
|
||||
|
||||
case 2: //MOUSE
|
||||
case 2: //MOUSE
|
||||
rdata[0] = 0x02;
|
||||
rdata[1] = 0x00;
|
||||
rdata[2] = 0x01;
|
||||
@ -1778,15 +1778,15 @@ int n64_periphs::pif_channel_handle_command(int channel, int slength, UINT8 *sda
|
||||
case 0: // P1 Inputs
|
||||
case 1: // P2 Inputs
|
||||
case 2: // P3 Inputs
|
||||
case 3: // P4 Inputs
|
||||
case 3: // P4 Inputs
|
||||
{
|
||||
switch ((machine().root_device().ioport("input")->read() >> (2 * channel)) & 3)
|
||||
{
|
||||
case 0: //NONE
|
||||
case 3: //Invalid
|
||||
case 0: //NONE
|
||||
case 3: //Invalid
|
||||
return 1;
|
||||
|
||||
case 1: //JOYPAD
|
||||
case 1: //JOYPAD
|
||||
buttons = machine().root_device().ioport(portnames[(channel*5) + 0])->read();
|
||||
x = machine().root_device().ioport(portnames[(channel*5) + 1])->read() - 128;
|
||||
y = machine().root_device().ioport(portnames[(channel*5) + 2])->read() - 128;
|
||||
@ -1797,7 +1797,7 @@ int n64_periphs::pif_channel_handle_command(int channel, int slength, UINT8 *sda
|
||||
rdata[3] = (UINT8)(y);
|
||||
return 0;
|
||||
|
||||
case 2: //MOUSE
|
||||
case 2: //MOUSE
|
||||
buttons = machine().root_device().ioport(portnames[(channel*5) + 0])->read();
|
||||
x = (INT16)machine().root_device().ioport(portnames[(channel*5) + 1 + 2])->read();// - 128;
|
||||
y = (INT16)machine().root_device().ioport(portnames[(channel*5) + 2 + 2])->read();// - 128;
|
||||
|
||||
@ -442,11 +442,11 @@ void n64_rdp::set_suba_input_rgb(UINT8** input_r, UINT8** input_g, UINT8** input
|
||||
case 3: *input_r = &userdata->m_prim_color.i.r; *input_g = &userdata->m_prim_color.i.g; *input_b = &userdata->m_prim_color.i.b; break;
|
||||
case 4: *input_r = &userdata->m_shade_color.i.r; *input_g = &userdata->m_shade_color.i.g; *input_b = &userdata->m_shade_color.i.b; break;
|
||||
case 5: *input_r = &userdata->m_env_color.i.r; *input_g = &userdata->m_env_color.i.g; *input_b = &userdata->m_env_color.i.b; break;
|
||||
case 6: *input_r = &m_one.i.r; *input_g = &m_one.i.g; *input_b = &m_one.i.b; break;
|
||||
case 6: *input_r = &m_one.i.r; *input_g = &m_one.i.g; *input_b = &m_one.i.b; break;
|
||||
case 7: *input_r = &userdata->m_noise_color.i.r; *input_g = &userdata->m_noise_color.i.g; *input_b = &userdata->m_noise_color.i.b; break;
|
||||
case 8: case 9: case 10: case 11: case 12: case 13: case 14: case 15:
|
||||
{
|
||||
*input_r = &m_zero.i.r; *input_g = &m_zero.i.g; *input_b = &m_zero.i.b; break;
|
||||
*input_r = &m_zero.i.r; *input_g = &m_zero.i.g; *input_b = &m_zero.i.b; break;
|
||||
}
|
||||
}
|
||||
}
|
||||
@ -462,10 +462,10 @@ void n64_rdp::set_subb_input_rgb(UINT8** input_r, UINT8** input_g, UINT8** input
|
||||
case 4: *input_r = &userdata->m_shade_color.i.r; *input_g = &userdata->m_shade_color.i.g; *input_b = &userdata->m_shade_color.i.b; break;
|
||||
case 5: *input_r = &userdata->m_env_color.i.r; *input_g = &userdata->m_env_color.i.g; *input_b = &userdata->m_env_color.i.b; break;
|
||||
case 6: fatalerror("SET_SUBB_RGB_INPUT: key_center\n");
|
||||
case 7: *input_r = (UINT8*)&m_k4; *input_g = (UINT8*)&m_k4; *input_b = (UINT8*)&m_k4; break;
|
||||
case 7: *input_r = (UINT8*)&m_k4; *input_g = (UINT8*)&m_k4; *input_b = (UINT8*)&m_k4; break;
|
||||
case 8: case 9: case 10: case 11: case 12: case 13: case 14: case 15:
|
||||
{
|
||||
*input_r = &m_zero.i.r; *input_g = &m_zero.i.g; *input_b = &m_zero.i.b; break;
|
||||
*input_r = &m_zero.i.r; *input_g = &m_zero.i.g; *input_b = &m_zero.i.b; break;
|
||||
}
|
||||
}
|
||||
}
|
||||
@ -493,7 +493,7 @@ void n64_rdp::set_mul_input_rgb(UINT8** input_r, UINT8** input_g, UINT8** input_
|
||||
case 16: case 17: case 18: case 19: case 20: case 21: case 22: case 23:
|
||||
case 24: case 25: case 26: case 27: case 28: case 29: case 30: case 31:
|
||||
{
|
||||
*input_r = &m_zero.i.r; *input_g = &m_zero.i.g; *input_b = &m_zero.i.b; break;
|
||||
*input_r = &m_zero.i.r; *input_g = &m_zero.i.g; *input_b = &m_zero.i.b; break;
|
||||
}
|
||||
}
|
||||
}
|
||||
@ -508,8 +508,8 @@ void n64_rdp::set_add_input_rgb(UINT8** input_r, UINT8** input_g, UINT8** input_
|
||||
case 3: *input_r = &userdata->m_prim_color.i.r; *input_g = &userdata->m_prim_color.i.g; *input_b = &userdata->m_prim_color.i.b; break;
|
||||
case 4: *input_r = &userdata->m_shade_color.i.r; *input_g = &userdata->m_shade_color.i.g; *input_b = &userdata->m_shade_color.i.b; break;
|
||||
case 5: *input_r = &userdata->m_env_color.i.r; *input_g = &userdata->m_env_color.i.g; *input_b = &userdata->m_env_color.i.b; break;
|
||||
case 6: *input_r = &m_one.i.r; *input_g = &m_one.i.g; *input_b = &m_one.i.b; break;
|
||||
case 7: *input_r = &m_zero.i.r; *input_g = &m_zero.i.g; *input_b = &m_zero.i.b; break;
|
||||
case 6: *input_r = &m_one.i.r; *input_g = &m_one.i.g; *input_b = &m_one.i.b; break;
|
||||
case 7: *input_r = &m_zero.i.r; *input_g = &m_zero.i.g; *input_b = &m_zero.i.b; break;
|
||||
}
|
||||
}
|
||||
|
||||
@ -2623,7 +2623,7 @@ void n64_rdp::cmd_set_other_modes(UINT32 w1, UINT32 w2)
|
||||
m_other_modes.blend_m2b_0 = (w2 >> 18) & 0x3; // 00
|
||||
m_other_modes.blend_m2b_1 = (w2 >> 16) & 0x3; // 01
|
||||
m_other_modes.force_blend = (w2 >> 14) & 1; // 0
|
||||
m_other_modes.blend_shift = m_other_modes.force_blend ? 5 : 2;
|
||||
m_other_modes.blend_shift = m_other_modes.force_blend ? 5 : 2;
|
||||
m_other_modes.alpha_cvg_select = (w2 >> 13) & 1; // 1
|
||||
m_other_modes.cvg_times_alpha = (w2 >> 12) & 1; // 0
|
||||
m_other_modes.z_mode = (w2 >> 10) & 0x3; // 00
|
||||
|
||||
@ -101,7 +101,7 @@
|
||||
|
||||
//sign-extension macros
|
||||
#define SIGN22(x) (((x & 0x00200000) * 0x7ff) | (x & 0x1fffff))
|
||||
#define SIGN17(x) (((x & 0x00010000) * 0xffff) | (x & 0xffff))
|
||||
#define SIGN17(x) (((x & 0x00010000) * 0xffff) | (x & 0xffff))
|
||||
#define SIGN16(x) (((x & 0x00008000) * 0x1ffff) | (x & 0x7fff))
|
||||
#define SIGN13(x) (((x & 0x00001000) * 0xfffff) | (x & 0xfff))
|
||||
#define SIGN11(x) (((x & 0x00000400) * 0x3fffff) | (x & 0x3ff))
|
||||
@ -222,7 +222,7 @@ struct misc_state_t
|
||||
INT32 m_fb_format; // Framebuffer pixel format index (0 - I, 1 - IA, 2 - CI, 3 - RGBA)
|
||||
INT32 m_fb_size; // Framebuffer pixel size index (0 - 4bpp, 1 - 8bpp, 2 - 16bpp, 3 - 32bpp)
|
||||
INT32 m_fb_width; // Framebuffer width, in pixels
|
||||
INT32 m_fb_height; // Framebuffer height, in pixels
|
||||
INT32 m_fb_height; // Framebuffer height, in pixels
|
||||
UINT32 m_fb_address; // Framebuffer source address offset (in bytes) from start of RDRAM
|
||||
|
||||
UINT32 m_zb_address; // Z-buffer source address offset (in bytes) from start of RDRAM
|
||||
@ -367,10 +367,10 @@ struct rdp_span_aux
|
||||
INT32 m_shift_b;
|
||||
INT32 m_precomp_s;
|
||||
INT32 m_precomp_t;
|
||||
INT32 m_blend_enable;
|
||||
INT32 m_blend_enable;
|
||||
bool m_pre_wrap;
|
||||
INT32 m_dzpix_enc;
|
||||
UINT8* m_tmem; /* pointer to texture cache for this polygon */
|
||||
UINT8* m_tmem; /* pointer to texture cache for this polygon */
|
||||
bool m_start_span;
|
||||
};
|
||||
|
||||
@ -398,11 +398,11 @@ struct cv_mask_derivative_t
|
||||
|
||||
struct rdp_poly_state
|
||||
{
|
||||
n64_rdp* m_rdp; /* pointer back to the RDP state */
|
||||
n64_rdp* m_rdp; /* pointer back to the RDP state */
|
||||
|
||||
misc_state_t m_misc_state; /* miscellaneous rasterizer bits */
|
||||
other_modes_t m_other_modes; /* miscellaneous rasterizer bits (2) */
|
||||
span_base_t m_span_base; /* span initial values for triangle rasterization */
|
||||
other_modes_t m_other_modes; /* miscellaneous rasterizer bits (2) */
|
||||
span_base_t m_span_base; /* span initial values for triangle rasterization */
|
||||
rectangle_t m_scissor; /* screen-space scissor bounds */
|
||||
UINT32 m_fill_color; /* poly fill color */
|
||||
n64_tile_t m_tiles[8]; /* texture tile state */
|
||||
@ -488,10 +488,10 @@ public:
|
||||
void set_blender_input(INT32 cycle, INT32 which, UINT8** input_r, UINT8** input_g, UINT8** input_b, UINT8** input_a, INT32 a, INT32 b, rdp_span_aux* userdata);
|
||||
|
||||
// Span rasterization
|
||||
void span_draw_1cycle(INT32 scanline, const extent_t &extent, const rdp_poly_state &object, INT32 threadid);
|
||||
void span_draw_2cycle(INT32 scanline, const extent_t &extent, const rdp_poly_state &object, INT32 threadid);
|
||||
void span_draw_copy(INT32 scanline, const extent_t &extent, const rdp_poly_state &object, INT32 threadid);
|
||||
void span_draw_fill(INT32 scanline, const extent_t &extent, const rdp_poly_state &object, INT32 threadid);
|
||||
void span_draw_1cycle(INT32 scanline, const extent_t &extent, const rdp_poly_state &object, INT32 threadid);
|
||||
void span_draw_2cycle(INT32 scanline, const extent_t &extent, const rdp_poly_state &object, INT32 threadid);
|
||||
void span_draw_copy(INT32 scanline, const extent_t &extent, const rdp_poly_state &object, INT32 threadid);
|
||||
void span_draw_fill(INT32 scanline, const extent_t &extent, const rdp_poly_state &object, INT32 threadid);
|
||||
|
||||
// Render-related (move into eventual drawing-related classes?)
|
||||
void tc_div(INT32 ss, INT32 st, INT32 sw, INT32* sss, INT32* sst);
|
||||
@ -575,7 +575,7 @@ public:
|
||||
|
||||
UINT32 m_fill_color;
|
||||
|
||||
other_modes_t m_other_modes;
|
||||
other_modes_t m_other_modes;
|
||||
|
||||
n64_blender_t m_blender;
|
||||
|
||||
@ -588,7 +588,7 @@ public:
|
||||
UINT16 m_dzpix_normalize[0x10000];
|
||||
|
||||
rectangle_t m_scissor;
|
||||
span_base_t m_span_base;
|
||||
span_base_t m_span_base;
|
||||
|
||||
rectangle m_visarea;
|
||||
|
||||
@ -602,16 +602,16 @@ public:
|
||||
|
||||
bool rdp_range_check(UINT32 addr);
|
||||
|
||||
n64_tile_t m_tiles[8];
|
||||
n64_tile_t m_tiles[8];
|
||||
|
||||
private:
|
||||
void write_pixel(UINT32 curpixel, INT32 r, INT32 g, INT32 b, rdp_span_aux* userdata, const rdp_poly_state &object);
|
||||
void read_pixel(UINT32 curpixel, rdp_span_aux* userdata, const rdp_poly_state &object);
|
||||
void copy_pixel(UINT32 curpixel, INT32 r, INT32 g, INT32 b, INT32 m_current_pix_cvg, const rdp_poly_state &object);
|
||||
void fill_pixel(UINT32 curpixel, const rdp_poly_state &object);
|
||||
void write_pixel(UINT32 curpixel, INT32 r, INT32 g, INT32 b, rdp_span_aux* userdata, const rdp_poly_state &object);
|
||||
void read_pixel(UINT32 curpixel, rdp_span_aux* userdata, const rdp_poly_state &object);
|
||||
void copy_pixel(UINT32 curpixel, INT32 r, INT32 g, INT32 b, INT32 m_current_pix_cvg, const rdp_poly_state &object);
|
||||
void fill_pixel(UINT32 curpixel, const rdp_poly_state &object);
|
||||
|
||||
void precalc_cvmask_derivatives(void);
|
||||
void z_build_com_table(void);
|
||||
void precalc_cvmask_derivatives(void);
|
||||
void z_build_com_table(void);
|
||||
|
||||
void video_update16(n64_periphs* n64, bitmap_rgb32 &bitmap);
|
||||
void video_update32(n64_periphs* n64, bitmap_rgb32 &bitmap);
|
||||
@ -624,15 +624,15 @@ private:
|
||||
|
||||
cv_mask_derivative_t cvarray[(1 << 8)];
|
||||
|
||||
UINT16 m_z_com_table[0x40000]; //precalced table of compressed z values, 18b: 512 KB array!
|
||||
UINT32 m_z_complete_dec_table[0x4000]; //the same for decompressed z values, 14b
|
||||
UINT8 m_compressed_cvmasks[0x10000]; //16bit cvmask -> to byte
|
||||
UINT16 m_z_com_table[0x40000]; //precalced table of compressed z values, 18b: 512 KB array!
|
||||
UINT32 m_z_complete_dec_table[0x4000]; //the same for decompressed z values, 14b
|
||||
UINT8 m_compressed_cvmasks[0x10000]; //16bit cvmask -> to byte
|
||||
|
||||
UINT32 m_cmd_data[0x1000];
|
||||
UINT32 m_temp_rect_data[0x1000];
|
||||
|
||||
INT32 m_cmd_ptr;
|
||||
INT32 m_cmd_cur;
|
||||
INT32 m_cmd_ptr;
|
||||
INT32 m_cmd_cur;
|
||||
|
||||
UINT32 m_start;
|
||||
UINT32 m_end;
|
||||
|
||||
@ -72,8 +72,8 @@ class n64_blender_t
|
||||
INT32 dither_alpha(INT32 alpha, INT32 dither);
|
||||
INT32 dither_color(INT32 color, INT32 dither);
|
||||
|
||||
UINT8 m_color_dither[256 * 8];
|
||||
UINT8 m_alpha_dither[256 * 8];
|
||||
UINT8 m_color_dither[256 * 8];
|
||||
UINT8 m_alpha_dither[256 * 8];
|
||||
};
|
||||
|
||||
#endif // _VIDEO_RDPBLEND_H_
|
||||
|
||||
@ -255,7 +255,7 @@ void n64_texture_pipe_t::clamp_cycle_light(INT32* S, INT32* T, const bool maxs,
|
||||
|
||||
void n64_texture_pipe_t::cycle_nearest(color_t* TEX, color_t* prev, INT32 SSS, INT32 SST, UINT32 tilenum, UINT32 cycle, rdp_span_aux* userdata, const rdp_poly_state& object)
|
||||
{
|
||||
// const n64_tile_t* tiles = object.m_tiles;
|
||||
// const n64_tile_t* tiles = object.m_tiles;
|
||||
const n64_tile_t& tile = object.m_tiles[tilenum];
|
||||
const UINT32 tformat = tile.format;
|
||||
const UINT32 tsize = tile.size;
|
||||
|
||||
@ -158,15 +158,15 @@ class n64_texture_pipe_t
|
||||
UINT32 fetch_i8_tlut1(INT32 s, INT32 t, INT32 tbase, INT32 tpal, rdp_span_aux* userdata);
|
||||
UINT32 fetch_i8_raw(INT32 s, INT32 t, INT32 tbase, INT32 tpal, rdp_span_aux* userdata);
|
||||
|
||||
texel_fetcher_t m_texel_fetch[16*5];
|
||||
texel_fetcher_t m_texel_fetch[16*5];
|
||||
|
||||
n64_rdp* m_rdp;
|
||||
|
||||
INT32 m_maskbits_table[16];
|
||||
UINT32 m_expand_16to32_table[0x10000];
|
||||
UINT16 m_lod_lookup[0x80000];
|
||||
INT32 m_clamp_s_diff[8];
|
||||
INT32 m_clamp_t_diff[8];
|
||||
UINT16 m_lod_lookup[0x80000];
|
||||
INT32 m_clamp_s_diff[8];
|
||||
INT32 m_clamp_t_diff[8];
|
||||
};
|
||||
|
||||
#endif // _VIDEO_RDPTEXPIPE_H_
|
||||
|
||||
@ -139,11 +139,11 @@ Notes:
|
||||
|
||||
/*
|
||||
|
||||
TODO:
|
||||
TODO:
|
||||
|
||||
- cassette
|
||||
- abc806 RTC
|
||||
- abc806 disks except ufd631 won't boot
|
||||
- cassette
|
||||
- abc806 RTC
|
||||
- abc806 disks except ufd631 won't boot
|
||||
|
||||
*/
|
||||
|
||||
|
||||
@ -393,7 +393,7 @@ WRITE8_MEMBER( camplynx_state::port84_w )
|
||||
// Square wave output
|
||||
m_cass->output(BIT(data, 5) ? -1.0 : +1.0);
|
||||
}
|
||||
else // speaker output
|
||||
else // speaker output
|
||||
m_dac->write_unsigned8(space, 0, data);
|
||||
}
|
||||
|
||||
@ -432,7 +432,7 @@ WRITE8_MEMBER( camplynx_state::lynx128k_port84_w )
|
||||
// Square wave output
|
||||
m_cass->output(BIT(data, 5) ? -1.0 : +1.0);
|
||||
}
|
||||
else // speaker output
|
||||
else // speaker output
|
||||
m_dac->write_unsigned8(space, 0, data);
|
||||
}
|
||||
|
||||
|
||||
@ -261,7 +261,7 @@ static MACHINE_CONFIG_START( ctstein, ctstein_state )
|
||||
MCFG_COP400_CONFIG(COP400_CKI_DIVISOR_16, COP400_CKO_OSCILLATOR_OUTPUT, COP400_MICROBUS_DISABLED) // guessed
|
||||
|
||||
MCFG_TIMER_DRIVER_ADD_PERIODIC("display_decay", hh_cop400_state, display_decay_tick, attotime::from_msec(1))
|
||||
// MCFG_DEFAULT_LAYOUT(layout_ctstein)
|
||||
// MCFG_DEFAULT_LAYOUT(layout_ctstein)
|
||||
|
||||
/* no video! */
|
||||
|
||||
@ -633,7 +633,7 @@ static MACHINE_CONFIG_START( plus1, plus1_state )
|
||||
MCFG_COP400_CONFIG(COP400_CKI_DIVISOR_16, COP400_CKO_OSCILLATOR_OUTPUT, COP400_MICROBUS_ENABLED) // guessed
|
||||
|
||||
MCFG_TIMER_DRIVER_ADD_PERIODIC("display_decay", hh_cop400_state, display_decay_tick, attotime::from_msec(1))
|
||||
// MCFG_DEFAULT_LAYOUT(layout_plus1)
|
||||
// MCFG_DEFAULT_LAYOUT(layout_plus1)
|
||||
|
||||
/* no video! */
|
||||
|
||||
|
||||
@ -1722,7 +1722,7 @@ static MACHINE_CONFIG_START( efootb4, efootb4_state )
|
||||
MCFG_TMS1XXX_WRITE_O_CB(WRITE16(efootb4_state, write_o))
|
||||
|
||||
MCFG_TIMER_DRIVER_ADD_PERIODIC("display_decay", hh_tms1k_state, display_decay_tick, attotime::from_msec(1))
|
||||
// MCFG_DEFAULT_LAYOUT(layout_efootb4)
|
||||
// MCFG_DEFAULT_LAYOUT(layout_efootb4)
|
||||
MCFG_DEFAULT_LAYOUT(layout_hh_tms1k_test)
|
||||
|
||||
/* no video! */
|
||||
@ -1836,7 +1836,7 @@ static MACHINE_CONFIG_START( ebaskb2, ebaskb2_state )
|
||||
MCFG_TMS1XXX_WRITE_O_CB(WRITE16(ebaskb2_state, write_o))
|
||||
|
||||
MCFG_TIMER_DRIVER_ADD_PERIODIC("display_decay", hh_tms1k_state, display_decay_tick, attotime::from_msec(1))
|
||||
// MCFG_DEFAULT_LAYOUT(layout_ebaskb2)
|
||||
// MCFG_DEFAULT_LAYOUT(layout_ebaskb2)
|
||||
MCFG_DEFAULT_LAYOUT(layout_hh_tms1k_test)
|
||||
|
||||
/* no video! */
|
||||
@ -4081,7 +4081,7 @@ static MACHINE_CONFIG_START( tbreakup, tbreakup_state )
|
||||
MCFG_TMS1XXX_WRITE_O_CB(WRITE16(tbreakup_state, write_o))
|
||||
|
||||
MCFG_TIMER_DRIVER_ADD_PERIODIC("display_decay", hh_tms1k_state, display_decay_tick, attotime::from_msec(1))
|
||||
// MCFG_DEFAULT_LAYOUT(layout_tbreakup)
|
||||
// MCFG_DEFAULT_LAYOUT(layout_tbreakup)
|
||||
MCFG_DEFAULT_LAYOUT(layout_hh_tms1k_test)
|
||||
|
||||
/* no video! */
|
||||
|
||||
@ -35,54 +35,54 @@ public:
|
||||
monty_state(const machine_config &mconfig, device_type type, const char *tag)
|
||||
: driver_device(mconfig, type, tag)
|
||||
, m_maincpu(*this, "maincpu")
|
||||
, m_sed0(*this, "sed1520_0")
|
||||
, m_writeUpper(false)
|
||||
, m_sed0(*this, "sed1520_0")
|
||||
, m_writeUpper(false)
|
||||
{
|
||||
for (int i = 0; i < 42*32; i++)
|
||||
m_pixels[i] = 0xff000000;
|
||||
for (int i = 0; i < 42*32; i++)
|
||||
m_pixels[i] = 0xff000000;
|
||||
}
|
||||
|
||||
DECLARE_READ8_MEMBER(ioInputRead);
|
||||
DECLARE_READ8_MEMBER(ioInputRead);
|
||||
|
||||
DECLARE_WRITE8_MEMBER(ioDisplayWrite);
|
||||
DECLARE_WRITE8_MEMBER(ioCommandWrite0);
|
||||
DECLARE_WRITE8_MEMBER(ioCommandWrite1);
|
||||
DECLARE_WRITE8_MEMBER(ioDisplayWrite);
|
||||
DECLARE_WRITE8_MEMBER(ioCommandWrite0);
|
||||
DECLARE_WRITE8_MEMBER(ioCommandWrite1);
|
||||
|
||||
// screen updates
|
||||
// screen updates
|
||||
UINT32 lcd_update(screen_device& screen, bitmap_rgb32& bitmap, const rectangle& cliprect);
|
||||
|
||||
private:
|
||||
required_device<cpu_device> m_maincpu;
|
||||
required_device<sed1520_device> m_sed0; // TODO: This isn't actually a SED1520, it's a SED1503F
|
||||
//required_device<sed1520_device> m_sed1; // TODO: Also, there are 2 SED1503Fs on the board - one is flipped upside down
|
||||
required_device<sed1520_device> m_sed0; // TODO: This isn't actually a SED1520, it's a SED1503F
|
||||
//required_device<sed1520_device> m_sed1; // TODO: Also, there are 2 SED1503Fs on the board - one is flipped upside down
|
||||
|
||||
// Test
|
||||
UINT8 m_writeUpper;
|
||||
UINT32 m_pixels[42*32];
|
||||
// Test
|
||||
UINT8 m_writeUpper;
|
||||
UINT32 m_pixels[42*32];
|
||||
};
|
||||
|
||||
|
||||
static ADDRESS_MAP_START(monty_mem, AS_PROGRAM, 8, monty_state)
|
||||
AM_RANGE(0x0000, 0x3fff) AM_ROM
|
||||
//AM_RANGE(0x4000, 0x4000) // The main rom checks to see if another program is here on startup
|
||||
AM_RANGE(0xf800, 0xffff) AM_RAM
|
||||
//AM_RANGE(0x4000, 0x4000) // The main rom checks to see if another program is here on startup
|
||||
AM_RANGE(0xf800, 0xffff) AM_RAM
|
||||
ADDRESS_MAP_END
|
||||
|
||||
|
||||
static ADDRESS_MAP_START(monty_io, AS_IO, 8, monty_state)
|
||||
ADDRESS_MAP_GLOBAL_MASK(0xff)
|
||||
AM_RANGE(0x00, 0x00) AM_WRITE(ioCommandWrite0)
|
||||
AM_RANGE(0x02, 0x02) AM_WRITE(ioCommandWrite1)
|
||||
AM_RANGE(0x80, 0xff) AM_WRITE(ioDisplayWrite)
|
||||
AM_RANGE(0x00, 0x00) AM_WRITE(ioCommandWrite0)
|
||||
AM_RANGE(0x02, 0x02) AM_WRITE(ioCommandWrite1)
|
||||
AM_RANGE(0x80, 0xff) AM_WRITE(ioDisplayWrite)
|
||||
|
||||
// 7 reads from a bit shifted IO port
|
||||
AM_RANGE(0x01, 0x01) AM_READ(ioInputRead)
|
||||
AM_RANGE(0x02, 0x02) AM_READ(ioInputRead)
|
||||
AM_RANGE(0x04, 0x04) AM_READ(ioInputRead)
|
||||
AM_RANGE(0x08, 0x08) AM_READ(ioInputRead)
|
||||
AM_RANGE(0x10, 0x10) AM_READ(ioInputRead)
|
||||
AM_RANGE(0x20, 0x20) AM_READ(ioInputRead)
|
||||
AM_RANGE(0x40, 0x40) AM_READ(ioInputRead)
|
||||
// 7 reads from a bit shifted IO port
|
||||
AM_RANGE(0x01, 0x01) AM_READ(ioInputRead)
|
||||
AM_RANGE(0x02, 0x02) AM_READ(ioInputRead)
|
||||
AM_RANGE(0x04, 0x04) AM_READ(ioInputRead)
|
||||
AM_RANGE(0x08, 0x08) AM_READ(ioInputRead)
|
||||
AM_RANGE(0x10, 0x10) AM_READ(ioInputRead)
|
||||
AM_RANGE(0x20, 0x20) AM_READ(ioInputRead)
|
||||
AM_RANGE(0x40, 0x40) AM_READ(ioInputRead)
|
||||
ADDRESS_MAP_END
|
||||
|
||||
|
||||
@ -93,79 +93,79 @@ INPUT_PORTS_END
|
||||
|
||||
READ8_MEMBER( monty_state::ioInputRead )
|
||||
{
|
||||
//UINT8 foo; // = machine().rand() & 0xff;
|
||||
//if (m_maincpu->pc() == 0x135f)
|
||||
// foo = 0x14;
|
||||
//if (m_maincpu->pc() == 0x1371)
|
||||
// foo = 0x1f;
|
||||
//UINT8 foo; // = machine().rand() & 0xff;
|
||||
//if (m_maincpu->pc() == 0x135f)
|
||||
// foo = 0x14;
|
||||
//if (m_maincpu->pc() == 0x1371)
|
||||
// foo = 0x1f;
|
||||
|
||||
UINT8 foo = (machine().rand() & 0xff) | 0x14;
|
||||
UINT8 foo = (machine().rand() & 0xff) | 0x14;
|
||||
|
||||
//printf("(%04x) %02x %02x\n", m_maincpu->pc(), foo, (foo & 0x14));
|
||||
return foo;
|
||||
//printf("(%04x) %02x %02x\n", m_maincpu->pc(), foo, (foo & 0x14));
|
||||
return foo;
|
||||
}
|
||||
|
||||
|
||||
WRITE8_MEMBER( monty_state::ioCommandWrite0 )
|
||||
{
|
||||
//printf("(%04x) Command Port 0 write : %02x\n", m_maincpu->pc(), data);
|
||||
m_writeUpper = false;
|
||||
//printf("(%04x) Command Port 0 write : %02x\n", m_maincpu->pc(), data);
|
||||
m_writeUpper = false;
|
||||
}
|
||||
|
||||
|
||||
WRITE8_MEMBER( monty_state::ioCommandWrite1 )
|
||||
{
|
||||
//if (data == 0xfe)
|
||||
// printf("---\n");
|
||||
//if (data == 0xfe)
|
||||
// printf("---\n");
|
||||
|
||||
//printf("(%04x) Command Port 1 write : %02x\n", m_maincpu->pc(), data);
|
||||
m_writeUpper = true;
|
||||
//printf("(%04x) Command Port 1 write : %02x\n", m_maincpu->pc(), data);
|
||||
m_writeUpper = true;
|
||||
}
|
||||
|
||||
|
||||
WRITE8_MEMBER( monty_state::ioDisplayWrite )
|
||||
{
|
||||
// Offset directly corresponds to sed1503, DD RAM address (offset 0x7f may be special?)
|
||||
//printf("(%04x) %02x %02x\n", m_maincpu->pc(), offset, data);
|
||||
// Offset directly corresponds to sed1503, DD RAM address (offset 0x7f may be special?)
|
||||
//printf("(%04x) %02x %02x\n", m_maincpu->pc(), offset, data);
|
||||
|
||||
const UINT8 localUpper = (offset & 0x40) >> 6;
|
||||
const UINT8 seg = offset & 0x3f;
|
||||
const UINT8 com = data;
|
||||
const UINT8 localUpper = (offset & 0x40) >> 6;
|
||||
const UINT8 seg = offset & 0x3f;
|
||||
const UINT8 com = data;
|
||||
|
||||
// Skip the controller and write straight to the LCD (pc=134f)
|
||||
for (int i = 0; i < 8; i++)
|
||||
{
|
||||
// Pixel location
|
||||
const int upperSedOffset = m_writeUpper ? 8*2 : 0;
|
||||
// Skip the controller and write straight to the LCD (pc=134f)
|
||||
for (int i = 0; i < 8; i++)
|
||||
{
|
||||
// Pixel location
|
||||
const int upperSedOffset = m_writeUpper ? 8*2 : 0;
|
||||
|
||||
const size_t x = seg;
|
||||
const size_t y = i + (localUpper*8) + upperSedOffset;
|
||||
const size_t x = seg;
|
||||
const size_t y = i + (localUpper*8) + upperSedOffset;
|
||||
|
||||
// Pixel color
|
||||
const bool on = (com >> i) & 0x01;
|
||||
m_pixels[(y*42) + x] = on ? 0xffffffff : 0xff000000;
|
||||
}
|
||||
// Pixel color
|
||||
const bool on = (com >> i) & 0x01;
|
||||
m_pixels[(y*42) + x] = on ? 0xffffffff : 0xff000000;
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
UINT32 monty_state::lcd_update(screen_device& screen, bitmap_rgb32& bitmap, const rectangle& cliprect)
|
||||
{
|
||||
for (int y = 0; y < 32; y++)
|
||||
{
|
||||
for (int x = 0; x < 42; x++)
|
||||
{
|
||||
bitmap.pix32(y, x) = m_pixels[(y*42) + x];
|
||||
}
|
||||
}
|
||||
for (int y = 0; y < 32; y++)
|
||||
{
|
||||
for (int x = 0; x < 42; x++)
|
||||
{
|
||||
bitmap.pix32(y, x) = m_pixels[(y*42) + x];
|
||||
}
|
||||
}
|
||||
|
||||
return 0x00;
|
||||
return 0x00;
|
||||
}
|
||||
|
||||
|
||||
SED1520_UPDATE_CB(monty_screen_update)
|
||||
{
|
||||
// TODO: Not really a SED1520 - there are two SED1503s
|
||||
return 0x00;
|
||||
// TODO: Not really a SED1520 - there are two SED1503s
|
||||
return 0x00;
|
||||
}
|
||||
|
||||
|
||||
@ -177,15 +177,15 @@ static MACHINE_CONFIG_START( monty, monty_state )
|
||||
MCFG_CPU_IO_MAP(monty_io)
|
||||
|
||||
// Video hardware
|
||||
MCFG_SCREEN_ADD("screen", LCD)
|
||||
MCFG_SCREEN_REFRESH_RATE(50)
|
||||
MCFG_SCREEN_VBLANK_TIME(ATTOSECONDS_IN_USEC(2500)) // Not accurate
|
||||
MCFG_SCREEN_SIZE(42, 32) // Two SED1503s (42x16 pixels) control the top and bottom halves
|
||||
MCFG_SCREEN_VISIBLE_AREA(0, 42-1, 0, 32-1)
|
||||
MCFG_SCREEN_UPDATE_DRIVER(monty_state, lcd_update)
|
||||
MCFG_SCREEN_ADD("screen", LCD)
|
||||
MCFG_SCREEN_REFRESH_RATE(50)
|
||||
MCFG_SCREEN_VBLANK_TIME(ATTOSECONDS_IN_USEC(2500)) // Not accurate
|
||||
MCFG_SCREEN_SIZE(42, 32) // Two SED1503s (42x16 pixels) control the top and bottom halves
|
||||
MCFG_SCREEN_VISIBLE_AREA(0, 42-1, 0, 32-1)
|
||||
MCFG_SCREEN_UPDATE_DRIVER(monty_state, lcd_update)
|
||||
|
||||
// LCD controller interfaces
|
||||
MCFG_SED1520_ADD("sed1520_0", monty_screen_update)
|
||||
// LCD controller interfaces
|
||||
MCFG_SED1520_ADD("sed1520_0", monty_screen_update)
|
||||
MACHINE_CONFIG_END
|
||||
|
||||
|
||||
@ -193,15 +193,15 @@ MACHINE_CONFIG_END
|
||||
ROM_START( monty )
|
||||
ROM_REGION(0xc000, "maincpu", 0)
|
||||
ROM_LOAD( "monty_main.bin", 0x0000, 0x4000, CRC(720b4f55) SHA1(0106eb88d3fbbf25a745b9b6ee785ba13689d095) ) // 27128
|
||||
ROM_LOAD( "monty_module1.bin", 0x4000, 0x4000, CRC(2725d8c3) SHA1(8273b9779c0915f9c7c43ea4fb460f43ce036358) ) // 27128
|
||||
ROM_LOAD( "monty_module2.bin", 0x8000, 0x4000, CRC(db672e47) SHA1(bb14fe86df06cfa4b19625ba417d1a5bc8eae155) ) // 27128
|
||||
ROM_LOAD( "monty_module1.bin", 0x4000, 0x4000, CRC(2725d8c3) SHA1(8273b9779c0915f9c7c43ea4fb460f43ce036358) ) // 27128
|
||||
ROM_LOAD( "monty_module2.bin", 0x8000, 0x4000, CRC(db672e47) SHA1(bb14fe86df06cfa4b19625ba417d1a5bc8eae155) ) // 27128
|
||||
ROM_END
|
||||
|
||||
ROM_START( mmonty )
|
||||
ROM_REGION(0x10000, "maincpu", 0)
|
||||
ROM_LOAD( "master_monty_main.bin", 0x0000, 0x8000, CRC(bb5ef4d4) SHA1(ba2c759e429f8740df419f9abb60832eddfba8ab) ) // 27C256
|
||||
ROM_LOAD( "monty_module1.bin", 0x8000, 0x4000, CRC(2725d8c3) SHA1(8273b9779c0915f9c7c43ea4fb460f43ce036358) ) // 27128
|
||||
ROM_LOAD( "monty_module2.bin", 0xc000, 0x4000, CRC(db672e47) SHA1(bb14fe86df06cfa4b19625ba417d1a5bc8eae155) ) // 27128
|
||||
ROM_LOAD( "monty_module1.bin", 0x8000, 0x4000, CRC(2725d8c3) SHA1(8273b9779c0915f9c7c43ea4fb460f43ce036358) ) // 27128
|
||||
ROM_LOAD( "monty_module2.bin", 0xc000, 0x4000, CRC(db672e47) SHA1(bb14fe86df06cfa4b19625ba417d1a5bc8eae155) ) // 27128
|
||||
ROM_END
|
||||
|
||||
|
||||
|
||||
@ -175,12 +175,12 @@ DIAGNOSTIC-LEDs |J3 | |J2 | |J1 |
|
||||
|-------------PCB# 5416206 / 5016205-01C1-------------|
|
||||
|
||||
CONNECTORS ("J"):
|
||||
...J5... ...J4... both: RD51 controller (hard disk)
|
||||
...J5... ...J4... both: EXTENDED COMM. controller
|
||||
...J5... ...J4... both: RD51 controller (hard disk)
|
||||
...J5... ...J4... both: EXTENDED COMM. controller
|
||||
|
||||
...J6... is the MEMORY OPTION connector (52 pin)
|
||||
...J7... is the GRAPHICS OPTION connector (40 pin)
|
||||
...J9... RX50 FLOPPY CONTROLLER (40 pin; REQUIRED)
|
||||
...J6... is the MEMORY OPTION connector (52 pin)
|
||||
...J7... is the GRAPHICS OPTION connector (40 pin)
|
||||
...J9... RX50 FLOPPY CONTROLLER (40 pin; REQUIRED)
|
||||
|
||||
JUMPERS (labeled "W"):
|
||||
W5 + W6 are out when 16K x 8 EPROMS are used
|
||||
@ -212,7 +212,7 @@ W17 pulls J1 serial port pin 1 to GND when set (chassis to logical GND).
|
||||
|
||||
// (2) KEYBOARD_WORKAROUND : also requires FORCE...LOGO (and preliminary headers)
|
||||
//#define KEYBOARD_WORKAROUND
|
||||
//#define KBD_DELAY 8 // (debounce delay)
|
||||
//#define KBD_DELAY 8 // (debounce delay)
|
||||
// ---------------------------------------------------------------------------
|
||||
|
||||
|
||||
@ -386,10 +386,10 @@ private:
|
||||
IRQ_8088_MAILBOX = 0, // 27/A7 9C/29C - [built-in] Interrupt from Z80A
|
||||
IRQ_8088_KBD, // 26/A6 98/298 - [built-in] KEYBOARD Interrupt - 8251A
|
||||
IRQ_BDL_INTR_L, // 25/A5 94/294 - [ext. BUNDLE OPTION] Hard disk or Extended communication IRQ (no DMA)
|
||||
// IRQ_COMM_PTR_INTR_L, // 24/A4 90/290 - [built-in 7201] Communication/Printer interrupt
|
||||
// IRQ_DMAC_INTR_L, // 23/A3 8C/28C - [ext. COMM.BOARD only] - external DMA Controller (8237) interrupt
|
||||
// IRQ_GRF_INTR_L, // 22/A2 88/288 - [ext. COLOR GRAPHICS]
|
||||
// IRQ_BDL_INTR_1L, // 21/A1 84/284 - [ext. COMM.BOARD only]
|
||||
// IRQ_COMM_PTR_INTR_L, // 24/A4 90/290 - [built-in 7201] Communication/Printer interrupt
|
||||
// IRQ_DMAC_INTR_L, // 23/A3 8C/28C - [ext. COMM.BOARD only] - external DMA Controller (8237) interrupt
|
||||
// IRQ_GRF_INTR_L, // 22/A2 88/288 - [ext. COLOR GRAPHICS]
|
||||
// IRQ_BDL_INTR_1L, // 21/A1 84/284 - [ext. COMM.BOARD only]
|
||||
IRQ_8088_VBL, // 20/A0 80/280 - [built-in DC012] - VERT INTR L (= schematics)
|
||||
IRQ_8088_NMI // 02/02 08/08 - [external MEMORY EXTENSION] - PARITY ERROR L
|
||||
}; // HIGHEST PRIORITY
|
||||
@ -808,22 +808,22 @@ void rainbow_state::machine_reset()
|
||||
// BIOS can't handle soft resets (would trigger ERROR 16).
|
||||
// As a fallback, execute a hard reboot!
|
||||
if (COLD_BOOT == 2)
|
||||
{ // FIXME: ask for confirmation (via UI ?)
|
||||
{ // FIXME: ask for confirmation (via UI ?)
|
||||
device().machine().schedule_hard_reset();
|
||||
}
|
||||
|
||||
/* *****************************************************************************************************************
|
||||
Suitable Solutions ClikClok (one of the more compatible battery backed real time clocks)
|
||||
|
||||
DESCRIPTION: plugs into NVRAM chip socket on a 100-A and into one of the (EP)ROM sockets on the 100-B
|
||||
............ (there is a socket on the ClikClok for the NVRAM / EPROM chip).
|
||||
DESCRIPTION: plugs into NVRAM chip socket on a 100-A and into one of the (EP)ROM sockets on the 100-B
|
||||
............ (there is a socket on the ClikClok for the NVRAM / EPROM chip).
|
||||
|
||||
DS1315 phantom clock. No address space needed (-> IRQs must be disabled to block ROM accesses during reads).
|
||||
DS1315 phantom clock. No address space needed (-> IRQs must be disabled to block ROM accesses during reads).
|
||||
|
||||
DRIVERS: 'rbclik.zip' DOS and CP/M binaries plus source from DEC employee; Reads & displays times. Y2K READY.
|
||||
+ 'newclk.arc' (Suitable Solutions; sets time and date; uses FE000 and up). 2 digit year here.
|
||||
DRIVERS: 'rbclik.zip' DOS and CP/M binaries plus source from DEC employee; Reads & displays times. Y2K READY.
|
||||
+ 'newclk.arc' (Suitable Solutions; sets time and date; uses FE000 and up). 2 digit year here.
|
||||
|
||||
TODO: obtain hardware / check address decoders. Access logic here is derived from Vincent Esser's source.
|
||||
TODO: obtain hardware / check address decoders. Access logic here is derived from Vincent Esser's source.
|
||||
*****************************************************************************************************************/
|
||||
|
||||
// * Reset RTC to a defined state *
|
||||
@ -933,12 +933,12 @@ void rainbow_state::machine_reset()
|
||||
UINT32 rainbow_state::screen_update_rainbow(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect)
|
||||
{
|
||||
/*
|
||||
// Suppress display when accessing floppy (switch to 'smooth scroll' when working with DOS, please)!
|
||||
if (MOTOR_DISABLE_counter) // IF motor running...
|
||||
{
|
||||
if (m_p_vol_ram[0x84] == 0x00) // IF jump scroll
|
||||
return 0;
|
||||
}
|
||||
// Suppress display when accessing floppy (switch to 'smooth scroll' when working with DOS, please)!
|
||||
if (MOTOR_DISABLE_counter) // IF motor running...
|
||||
{
|
||||
if (m_p_vol_ram[0x84] == 0x00) // IF jump scroll
|
||||
return 0;
|
||||
}
|
||||
*/
|
||||
m_crtc->palette_select(m_inp9->read());
|
||||
|
||||
@ -1045,22 +1045,22 @@ WRITE8_MEMBER(rainbow_state::share_z80_w)
|
||||
|
||||
// ------------------------ClikClok (for model B; DS1315) ---------------------------------
|
||||
#define RTC_RESET_MACRO m_rtc->chip_reset(); \
|
||||
UINT8 *rom = memregion("maincpu")->base();
|
||||
UINT8 *rom = memregion("maincpu")->base();
|
||||
|
||||
#define RTC_ENABLE_MACRO \
|
||||
if (m_inp11->read() == 0x01) \
|
||||
{ \
|
||||
if (offset & 1) \
|
||||
if (m_inp11->read() == 0x01) \
|
||||
{ \
|
||||
if (offset & 1) \
|
||||
m_rtc->read_1(space, 0); \
|
||||
else \
|
||||
m_rtc->read_0(space, 0); \
|
||||
} \
|
||||
UINT8 *rom = memregion("maincpu")->base();
|
||||
m_rtc->read_0(space, 0); \
|
||||
} \
|
||||
UINT8 *rom = memregion("maincpu")->base();
|
||||
|
||||
#define RTC_READ_MACRO \
|
||||
if (m_rtc->chip_enable() && (m_inp11->read() == 0x01)) \
|
||||
return (m_rtc->read_data(space, 0) & 0x01); \
|
||||
UINT8 *rom = memregion("maincpu")->base();
|
||||
if (m_rtc->chip_enable() && (m_inp11->read() == 0x01)) \
|
||||
return (m_rtc->read_data(space, 0) & 0x01); \
|
||||
UINT8 *rom = memregion("maincpu")->base();
|
||||
|
||||
// *********** RTC RESET **************
|
||||
READ8_MEMBER(rainbow_state::rtc_reset)
|
||||
@ -1078,7 +1078,7 @@ READ8_MEMBER(rainbow_state::rtc_reset2)
|
||||
// *********** RTC ENABLE **************
|
||||
READ8_MEMBER(rainbow_state::rtc_enable)
|
||||
{
|
||||
RTC_ENABLE_MACRO
|
||||
RTC_ENABLE_MACRO
|
||||
return rom[RTC_PATTERN_0 + offset];
|
||||
}
|
||||
|
||||
@ -1242,7 +1242,7 @@ WRITE_LINE_MEMBER(rainbow_state::hdc_read_sector)
|
||||
// Pointer to info + C + H + S
|
||||
UINT32 lbasector = get_and_print_lbasector(info, cylinder, SDH & 0x07, sector_number);
|
||||
|
||||
if ((cylinder <= info->cylinders) && // filter invalid ranges
|
||||
if ((cylinder <= info->cylinders) && // filter invalid ranges
|
||||
(SECTOR_SIZES[(SDH >> 5) & 0x03] == info->sectorbytes) // may not vary in image!
|
||||
)
|
||||
{
|
||||
@ -1261,8 +1261,8 @@ WRITE_LINE_MEMBER(rainbow_state::hdc_read_sector)
|
||||
if (read_status != 0)
|
||||
{
|
||||
logerror("...** READ FAILED WITH STATUS %u ** (CYLINDER %u - HEAD %u - SECTOR # %u - SECTOR_SIZE %u ) ***\n",
|
||||
read_status, cylinder, SDH & 0x07, sector_number, SECTOR_SIZES[(SDH >> 5) & 0x03]
|
||||
) ;
|
||||
read_status, cylinder, SDH & 0x07, sector_number, SECTOR_SIZES[(SDH >> 5) & 0x03]
|
||||
) ;
|
||||
}
|
||||
|
||||
} // (on BCS 1 -> 0)
|
||||
@ -1352,7 +1352,7 @@ int rainbow_state::do_write_sector()
|
||||
int sector_number = m_hdc->read(space(AS_PROGRAM), 0x03);
|
||||
int sector_count = m_hdc->read(space(AS_PROGRAM), 0x02); // (1 = single sector)
|
||||
|
||||
if (!((cylinder <= info->cylinders) && // filter invalid cylinders
|
||||
if (!((cylinder <= info->cylinders) && // filter invalid cylinders
|
||||
(SECTOR_SIZES[(SDH >> 5) & 0x03] == info->sectorbytes) // 512, may not vary
|
||||
))
|
||||
{
|
||||
@ -1426,7 +1426,7 @@ WRITE8_MEMBER(rainbow_state::hd_status_60_w)
|
||||
// - disk drive(latched status signals)
|
||||
READ8_MEMBER(rainbow_state::hd_status_68_r)
|
||||
{
|
||||
// (*) Bits 5-7 : HARD WIRED IDENTIFICATION BITS, bits 5+7 = 1 and bit 6 = 0 (= 101 für RD51 module)
|
||||
// (*) Bits 5-7 : HARD WIRED IDENTIFICATION BITS, bits 5+7 = 1 and bit 6 = 0 (= 101 f?r RD51 module)
|
||||
int data = 0xe0; // 111 gives DRIVE NOT READY (when W is pressed on boot screen)
|
||||
if ((m_inp5->read() == 0x01) && (rainbow_hdc_file(0) != NULL))
|
||||
data = 0xa0; // A0 : OK, DRIVE IS READY (!)
|
||||
@ -1439,23 +1439,23 @@ READ8_MEMBER(rainbow_state::hd_status_68_r)
|
||||
// Bit 4 : SEEK COMPLETE: This status bit indicates that the disk drive positioned the R/W heads over the desired track on the disk surface.
|
||||
|
||||
// (ALT.TEXT): "Seek Complete - When this signal from the disk drive goes low(0), it indicates that the R /W heads settled on the correct track.
|
||||
// Writing is inhibited until this signal goes low(0). Seek complete is high(1) during normal seek operation.
|
||||
// Writing is inhibited until this signal goes low(0). Seek complete is high(1) during normal seek operation.
|
||||
if (stat & 16) // SEEK COMPLETE (bit 4)?
|
||||
data |= 16;
|
||||
|
||||
// Bit 3 : DIRECTION : This bit indicates the direction the read/write heads in the disk
|
||||
// drive will move when the WD1010 chip issues step pulse(s). When high(1), the R / W heads will move toward the spindle.
|
||||
// When low (0), the heads will move away from the spindle, towards track O.
|
||||
// drive will move when the WD1010 chip issues step pulse(s). When high(1), the R / W heads will move toward the spindle.
|
||||
// When low (0), the heads will move away from the spindle, towards track O.
|
||||
if (m_hdc_direction)
|
||||
data |= 8;
|
||||
|
||||
// Bit 2 : LATCHED STEP PULSE: This status bit from the step pulse latch indicates if the WD1010
|
||||
// chip issued a step pulse since the last time the 8088 processor cleared the step pulse latch.
|
||||
// chip issued a step pulse since the last time the 8088 processor cleared the step pulse latch.
|
||||
if (m_hdc_step_latch)
|
||||
data |= 4;
|
||||
|
||||
// Bit 1 : LATCHED INDEX : This status bit from the index latch indicates if the disk drive
|
||||
// encountered an index mark since the last time the 8088 processor cleared the index latch.
|
||||
// encountered an index mark since the last time the 8088 processor cleared the index latch.
|
||||
if (m_hdc_index_latch)
|
||||
data |= 2;
|
||||
|
||||
@ -1468,7 +1468,7 @@ READ8_MEMBER(rainbow_state::hd_status_68_r)
|
||||
}
|
||||
|
||||
|
||||
// 68 (WRITE): Secondary Command Registers (68H) - - ERKLÄRUNG: "write-only register for commands"
|
||||
// 68 (WRITE): Secondary Command Registers (68H) - - ERKL?RUNG: "write-only register for commands"
|
||||
// - see TABLE 4.8 (4-24)
|
||||
WRITE8_MEMBER(rainbow_state::hd_status_68_w)
|
||||
{
|
||||
@ -1693,7 +1693,7 @@ READ8_MEMBER(rainbow_state::system_parameter_r)
|
||||
((m_inp6->read() == 1) ? 0 : 2) |
|
||||
((m_inp7->read() == 1) ? 0 : 4) |
|
||||
((m_inp8->read() > BOARD_RAM) ? 0 : 8)
|
||||
// 16 | 32 | 64 | 128 // to be verified.
|
||||
// 16 | 32 | 64 | 128 // to be verified.
|
||||
);
|
||||
}
|
||||
|
||||
@ -1709,7 +1709,7 @@ READ8_MEMBER(rainbow_state::comm_control_r)
|
||||
*/
|
||||
int data = 0;
|
||||
if (COLD_BOOT == 2)
|
||||
data = 0; // During boot phase 2, never enable MHFU (prevents errors).
|
||||
data = 0; // During boot phase 2, never enable MHFU (prevents errors).
|
||||
else
|
||||
{
|
||||
data = m_crtc->MHFU(1);
|
||||
@ -1831,8 +1831,8 @@ READ8_MEMBER(rainbow_state::z80_generalstat_r)
|
||||
|
||||
int track = 0;
|
||||
int fdc_step = 0;
|
||||
int fdc_ready = 0;
|
||||
int tk00 = 0;
|
||||
int fdc_ready = 0;
|
||||
int tk00 = 0;
|
||||
int fdc_write_gate = 0;
|
||||
int last_dir = 0;
|
||||
|
||||
@ -2131,13 +2131,13 @@ WRITE8_MEMBER(rainbow_state::diagnostic_w) // 8088 (port 0A WRITTEN). Fig.4-28 +
|
||||
allows the floppy data separator and the serial video output to be tested
|
||||
through the use of the printer port. The following table shows how signals are routed.
|
||||
|
||||
DIAGNOSTIC LOOPBACK = 0 DIAGNOSTIC LOOPBACK = 1 SIGNAL INPUT
|
||||
SIGNAL SOURCE SIGNAL SOURCE TO
|
||||
FROM FROM
|
||||
PRT RDATA(J2) VIDEO OUT PRT RXD(7201)
|
||||
PRT RXTXC 500 KHZ PRT RXTXC(7201)
|
||||
MASTER CLK 250 KHZ VIDEO CLK(DCO11)
|
||||
FLOPPY RAW DATA PRT TXD(7201) FLOPPY DATA SEPARATOR
|
||||
DIAGNOSTIC LOOPBACK = 0 DIAGNOSTIC LOOPBACK = 1 SIGNAL INPUT
|
||||
SIGNAL SOURCE SIGNAL SOURCE TO
|
||||
FROM FROM
|
||||
PRT RDATA(J2) VIDEO OUT PRT RXD(7201)
|
||||
PRT RXTXC 500 KHZ PRT RXTXC(7201)
|
||||
MASTER CLK 250 KHZ VIDEO CLK(DCO11)
|
||||
FLOPPY RAW DATA PRT TXD(7201) FLOPPY DATA SEPARATOR
|
||||
|
||||
During Diagnostic Loopback, the - TEST input of the 8088 is connected to the
|
||||
interrupt output of the MPSC.Thus, using the 8088's WAIT instruction in a
|
||||
@ -2420,8 +2420,8 @@ ROM_RELOAD(0xfc000, 0x4000)
|
||||
ROM_REGION(0x1000, "chargen", 0)
|
||||
ROM_LOAD("chargen.bin", 0x0000, 0x1000, CRC(1685e452) SHA1(bc299ff1cb74afcededf1a7beb9001188fdcf02f))
|
||||
|
||||
// ROM_REGION(0x800, BUFFER, 0) // HDC RAM buffer 2 K -- NEW HDC
|
||||
// // ROM_FILL(0x000, 0x800, 0x00)
|
||||
// ROM_REGION(0x800, BUFFER, 0) // HDC RAM buffer 2 K -- NEW HDC
|
||||
// // ROM_FILL(0x000, 0x800, 0x00)
|
||||
ROM_END
|
||||
|
||||
// 'Rainbow 190 B' (announced March 1985) is identical to 100-B, with alternate ROM v5.05.
|
||||
|
||||
@ -667,84 +667,84 @@ static MACHINE_CONFIG_START( replicator, replicator_state )
|
||||
MACHINE_CONFIG_END
|
||||
|
||||
ROM_START( replica1 )
|
||||
ROM_REGION( 0x20000, "maincpu", 0 )
|
||||
ROM_DEFAULT_BIOS("v750")
|
||||
ROM_REGION( 0x20000, "maincpu", 0 )
|
||||
ROM_DEFAULT_BIOS("v750")
|
||||
|
||||
/* Version 5.1 release:
|
||||
- Initial firmware release
|
||||
*/
|
||||
ROM_SYSTEM_BIOS( 0, "v51", "V 5.1" )
|
||||
ROMX_LOAD("mighty-mb40-v5.1.bin", 0x0000, 0x10b90, CRC(20d65cd1) SHA1(da18c3eb5a29a6bc1eecd92eaae6063fe29d0305), ROM_BIOS(1))
|
||||
/* Version 5.1 release:
|
||||
- Initial firmware release
|
||||
*/
|
||||
ROM_SYSTEM_BIOS( 0, "v51", "V 5.1" )
|
||||
ROMX_LOAD("mighty-mb40-v5.1.bin", 0x0000, 0x10b90, CRC(20d65cd1) SHA1(da18c3eb5a29a6bc1eecd92eaae6063fe29d0305), ROM_BIOS(1))
|
||||
|
||||
/* Version 5.2 release:
|
||||
- Nozzle Tolerance added to EEPROM
|
||||
- Updated onboard menus
|
||||
- X,Y calibration tool added
|
||||
*/
|
||||
ROM_SYSTEM_BIOS( 1, "v52", "V 5.2" )
|
||||
ROMX_LOAD("mighty-mb40-v5.2.bin", 0x0000, 0x126c4, CRC(555e47cf) SHA1(9d24a3dbeddce16669bb4d29c3366220ddf15d2a), ROM_BIOS(2))
|
||||
/* Version 5.2 release:
|
||||
- Nozzle Tolerance added to EEPROM
|
||||
- Updated onboard menus
|
||||
- X,Y calibration tool added
|
||||
*/
|
||||
ROM_SYSTEM_BIOS( 1, "v52", "V 5.2" )
|
||||
ROMX_LOAD("mighty-mb40-v5.2.bin", 0x0000, 0x126c4, CRC(555e47cf) SHA1(9d24a3dbeddce16669bb4d29c3366220ddf15d2a), ROM_BIOS(2))
|
||||
|
||||
/* Version 5.5 release:
|
||||
- Acceleration added to motor motion
|
||||
- Digipot updates
|
||||
*/
|
||||
ROM_SYSTEM_BIOS( 2, "v55", "V 5.5" )
|
||||
ROMX_LOAD("mighty-mb40-v5.5.bin", 0x0000, 0x1a420, CRC(9327d7e4) SHA1(d734ba2bda12f50ec3ac0035ab11591909d9edde), ROM_BIOS(3))
|
||||
/* Version 5.5 release:
|
||||
- Acceleration added to motor motion
|
||||
- Digipot updates
|
||||
*/
|
||||
ROM_SYSTEM_BIOS( 2, "v55", "V 5.5" )
|
||||
ROMX_LOAD("mighty-mb40-v5.5.bin", 0x0000, 0x1a420, CRC(9327d7e4) SHA1(d734ba2bda12f50ec3ac0035ab11591909d9edde), ROM_BIOS(3))
|
||||
|
||||
/* Version 6.2.0 release:
|
||||
- Bug fix release to firmware 6.0
|
||||
- Addresses wavy print issue above 1cm
|
||||
- Left extruder prints with makerware.
|
||||
*/
|
||||
ROM_SYSTEM_BIOS( 3, "v620", "V 6.2.0" )
|
||||
ROMX_LOAD("mighty_one_v6.2.0.bin", 0x0000, 0x1cf54, CRC(00df6f48) SHA1(db05afc2e1ebc104fb04753634a911187e396556), ROM_BIOS(4))
|
||||
/* Version 6.2.0 release:
|
||||
- Bug fix release to firmware 6.0
|
||||
- Addresses wavy print issue above 1cm
|
||||
- Left extruder prints with makerware.
|
||||
*/
|
||||
ROM_SYSTEM_BIOS( 3, "v620", "V 6.2.0" )
|
||||
ROMX_LOAD("mighty_one_v6.2.0.bin", 0x0000, 0x1cf54, CRC(00df6f48) SHA1(db05afc2e1ebc104fb04753634a911187e396556), ROM_BIOS(4))
|
||||
|
||||
/* Version 7.0.0 release:
|
||||
- Major upgrade to Stepper Motor Smoothness (via Sailfish team)
|
||||
- X3G format introduced
|
||||
- Heaters default to leaving 'preheat' on more of the time
|
||||
*/
|
||||
ROM_SYSTEM_BIOS( 4, "v700", "V 7.0.0" )
|
||||
ROMX_LOAD("mighty_one_v7.0.0.bin", 0x0000, 0x1cb52, CRC(aa2a5fcf) SHA1(934e642b0b2d007689249680bad03c9255ae016a), ROM_BIOS(5))
|
||||
/* Version 7.0.0 release:
|
||||
- Major upgrade to Stepper Motor Smoothness (via Sailfish team)
|
||||
- X3G format introduced
|
||||
- Heaters default to leaving 'preheat' on more of the time
|
||||
*/
|
||||
ROM_SYSTEM_BIOS( 4, "v700", "V 7.0.0" )
|
||||
ROMX_LOAD("mighty_one_v7.0.0.bin", 0x0000, 0x1cb52, CRC(aa2a5fcf) SHA1(934e642b0b2d007689249680bad03c9255ae016a), ROM_BIOS(5))
|
||||
|
||||
/* Version 7.2.0 release:
|
||||
- Removes support for S3G files
|
||||
- X3G is the recognized format
|
||||
- Minor bug fixes
|
||||
*/
|
||||
ROM_SYSTEM_BIOS( 5, "v720", "V 7.2.0" )
|
||||
ROMX_LOAD("mighty_one_v7.2.0.bin", 0x0000, 0x1cb80, CRC(5e546706) SHA1(ed4aaf7522d5a5beea7eb69bf2c85d7a89f8f188), ROM_BIOS(6))
|
||||
/* Version 7.2.0 release:
|
||||
- Removes support for S3G files
|
||||
- X3G is the recognized format
|
||||
- Minor bug fixes
|
||||
*/
|
||||
ROM_SYSTEM_BIOS( 5, "v720", "V 7.2.0" )
|
||||
ROMX_LOAD("mighty_one_v7.2.0.bin", 0x0000, 0x1cb80, CRC(5e546706) SHA1(ed4aaf7522d5a5beea7eb69bf2c85d7a89f8f188), ROM_BIOS(6))
|
||||
|
||||
/* Version 7.3.0 release:
|
||||
- Pause at Z Height
|
||||
- Elapsed time displays during prints
|
||||
- Minor bug fixes
|
||||
*/
|
||||
ROM_SYSTEM_BIOS( 6, "v730", "V 7.3.0" )
|
||||
ROMX_LOAD("mighty_one_v7.3.0.bin", 0x0000, 0x1d738, CRC(71811ff5) SHA1(6728ea600ab3ff4b589adca90b0d700d9b70bd18), ROM_BIOS(7))
|
||||
/* Version 7.3.0 release:
|
||||
- Pause at Z Height
|
||||
- Elapsed time displays during prints
|
||||
- Minor bug fixes
|
||||
*/
|
||||
ROM_SYSTEM_BIOS( 6, "v730", "V 7.3.0" )
|
||||
ROMX_LOAD("mighty_one_v7.3.0.bin", 0x0000, 0x1d738, CRC(71811ff5) SHA1(6728ea600ab3ff4b589adca90b0d700d9b70bd18), ROM_BIOS(7))
|
||||
|
||||
/* Version 7.4.0 (bugfix) release:
|
||||
- Fixes issues with Z Pause and elapsed print time
|
||||
*/
|
||||
ROM_SYSTEM_BIOS( 7, "v740", "V 7.4.0" )
|
||||
ROMX_LOAD("mighty_one_v7.4.0.bin", 0x0000, 0x1b9e2, CRC(97b05a27) SHA1(76ca2c9c1db2e006e501c3177a8a1aa693dda0f9), ROM_BIOS(8))
|
||||
/* Version 7.4.0 (bugfix) release:
|
||||
- Fixes issues with Z Pause and elapsed print time
|
||||
*/
|
||||
ROM_SYSTEM_BIOS( 7, "v740", "V 7.4.0" )
|
||||
ROMX_LOAD("mighty_one_v7.4.0.bin", 0x0000, 0x1b9e2, CRC(97b05a27) SHA1(76ca2c9c1db2e006e501c3177a8a1aa693dda0f9), ROM_BIOS(8))
|
||||
|
||||
/* Version 7.5.0 (bugfix) release:
|
||||
- Fixes issue with Heat Hold
|
||||
*/
|
||||
ROM_SYSTEM_BIOS( 8, "v750", "V 7.5.0" )
|
||||
ROMX_LOAD("mighty_one_v7.5.0.bin", 0x0000, 0x1b9c4, CRC(169d6709) SHA1(62b5aacd1bc46969042aea7a50531ec467a4ff1f), ROM_BIOS(9))
|
||||
/* Version 7.5.0 (bugfix) release:
|
||||
- Fixes issue with Heat Hold
|
||||
*/
|
||||
ROM_SYSTEM_BIOS( 8, "v750", "V 7.5.0" )
|
||||
ROMX_LOAD("mighty_one_v7.5.0.bin", 0x0000, 0x1b9c4, CRC(169d6709) SHA1(62b5aacd1bc46969042aea7a50531ec467a4ff1f), ROM_BIOS(9))
|
||||
|
||||
/* Sailfish firmware image - Metamáquina experimental build v7.5.0 */
|
||||
ROM_SYSTEM_BIOS( 9, "v750mm", "V 7.5.0 - Metamáquina" )
|
||||
ROMX_LOAD("mighty_one_v7.5.0.mm.bin", 0x0000, 0x1ef9a, CRC(0d36d9e7) SHA1(a53899775b4c4eea87b6903758ebb75f06710a69), ROM_BIOS(10))
|
||||
/* Sailfish firmware image - Metam??quina experimental build v7.5.0 */
|
||||
ROM_SYSTEM_BIOS( 9, "v750mm", "V 7.5.0 - Metam??quina" )
|
||||
ROMX_LOAD("mighty_one_v7.5.0.mm.bin", 0x0000, 0x1ef9a, CRC(0d36d9e7) SHA1(a53899775b4c4eea87b6903758ebb75f06710a69), ROM_BIOS(10))
|
||||
|
||||
|
||||
/*Arduino MEGA bootloader */
|
||||
ROM_LOAD( "atmegaboot_168_atmega1280.bin", 0x1f000, 0x0f16, CRC(c041f8db) SHA1(d995ebf360a264cccacec65f6dc0c2257a3a9224) )
|
||||
/*Arduino MEGA bootloader */
|
||||
ROM_LOAD( "atmegaboot_168_atmega1280.bin", 0x1f000, 0x0f16, CRC(c041f8db) SHA1(d995ebf360a264cccacec65f6dc0c2257a3a9224) )
|
||||
|
||||
/* on-die 4kbyte eeprom */
|
||||
ROM_REGION( 0x1000, "eeprom", ROMREGION_ERASEFF )
|
||||
/* on-die 4kbyte eeprom */
|
||||
ROM_REGION( 0x1000, "eeprom", ROMREGION_ERASEFF )
|
||||
ROM_END
|
||||
|
||||
/* YEAR NAME PARENT COMPAT MACHINE INPUT INIT COMPANY FULLNAME */
|
||||
|
||||
@ -222,7 +222,7 @@ static ADDRESS_MAP_START (spectrum_128_io, AS_IO, 8, spectrum_state )
|
||||
AM_RANGE(0x001f, 0x001f) AM_READ(spectrum_port_1f_r) AM_MIRROR(0xff00)
|
||||
AM_RANGE(0x007f, 0x007f) AM_READ(spectrum_port_7f_r) AM_MIRROR(0xff00)
|
||||
AM_RANGE(0x00df, 0x00df) AM_READ(spectrum_port_df_r) AM_MIRROR(0xff00)
|
||||
AM_RANGE(0x0000, 0x0000) AM_WRITE(spectrum_128_port_7ffd_w) AM_MIRROR(0x7ffd) // (A15 | A1) == 0, note: reading from this port does write to it by value from data bus
|
||||
AM_RANGE(0x0000, 0x0000) AM_WRITE(spectrum_128_port_7ffd_w) AM_MIRROR(0x7ffd) // (A15 | A1) == 0, note: reading from this port does write to it by value from data bus
|
||||
AM_RANGE(0x8000, 0x8000) AM_DEVWRITE("ay8912", ay8910_device, data_w) AM_MIRROR(0x3ffd)
|
||||
AM_RANGE(0xc000, 0xc000) AM_DEVREADWRITE("ay8912", ay8910_device, data_r, address_w) AM_MIRROR(0x3ffd)
|
||||
AM_RANGE(0x0001, 0x0001) AM_READ(spectrum_128_ula_r) AM_MIRROR(0xfffe)
|
||||
|
||||
@ -17,7 +17,7 @@
|
||||
0x0071: RAM fill to 0x00
|
||||
0x1c8f: UPD7220
|
||||
|
||||
// vt240: x2212 nvram at E56
|
||||
// vt240: x2212 nvram at E56
|
||||
****************************************************************************/
|
||||
|
||||
#include "emu.h"
|
||||
|
||||
@ -1,3 +1,2 @@
|
||||
// license:LGPL-2.1+
|
||||
// copyright-holders: Angelo Salese
|
||||
|
||||
|
||||
@ -95,64 +95,64 @@ public:
|
||||
required_device<mc6845_device> m_crtc;
|
||||
required_device<z80ctc_device> m_ctc;
|
||||
|
||||
UINT8 *m_tvram; /**< Pointer for Text Video RAM */
|
||||
UINT8 *m_avram; /**< Pointer for Attribute Video RAM */
|
||||
UINT8 *m_kvram; /**< Pointer for Extended Kanji Video RAM (X1 Turbo) */
|
||||
UINT8 *m_ipl_rom; /**< Pointer for IPL ROM */
|
||||
UINT8 *m_work_ram; /**< Pointer for base work RAM */
|
||||
UINT8 *m_emm_ram; /**< Pointer for EMM RAM */
|
||||
UINT8 *m_pcg_ram; /**< Pointer for PCG GFX RAM */
|
||||
UINT8 *m_cg_rom; /**< Pointer for GFX ROM */
|
||||
UINT8 *m_kanji_rom; /**< Pointer for Kanji ROMs */
|
||||
int m_xstart, /**< Start X offset for screen drawing. */
|
||||
m_ystart; /**< Start Y offset for screen drawing. */
|
||||
UINT8 m_hres_320; /**< Pixel clock divider setting: (1) 48 (0) 24 */
|
||||
UINT8 m_io_switch; /**< Enable access for special bitmap RMW phase in isolated i/o. */
|
||||
UINT8 m_io_sys; /**< Read-back for PPI port C */
|
||||
UINT8 m_vsync; /**< Screen V-Sync bit, active low */
|
||||
UINT8 m_vdisp; /**< Screen V-Disp bit, active high */
|
||||
UINT8 m_io_bank_mode; /**< Helper for special bitmap RMW phase. */
|
||||
UINT8 *m_gfx_bitmap_ram; /**< Pointer for bitmap layer RAM. */
|
||||
UINT8 m_pcg_reset; /**< @todo Unused variable. */
|
||||
UINT8 m_sub_obf; /**< MCU side: OBF flag active low, indicates that there are parameters in comm buffer. */
|
||||
UINT8 m_ctc_irq_flag; /**< @todo Unused variable. */
|
||||
scrn_reg_t m_scrn_reg; /**< Base Video Registers. */
|
||||
turbo_reg_t m_turbo_reg; /**< Turbo Z Video Registers. */
|
||||
x1_rtc_t m_rtc; /**< Struct for RTC related variables */
|
||||
emu_timer *m_rtc_timer; /**< Pointer for RTC timer. */
|
||||
UINT8 m_pcg_write_addr; /**< @todo Unused variable. */
|
||||
UINT8 m_sub_cmd; /**< MCU side: current command issued from Main to Sub. */
|
||||
UINT8 m_sub_cmd_length; /**< MCU side: number of parameters, in bytes. */
|
||||
UINT8 m_sub_val[8]; /**< MCU side: parameters buffer. */
|
||||
int m_sub_val_ptr; /**< MCU side: index for parameter read-back */
|
||||
int m_key_i; /**< MCU side: index for keyboard read-back during OBF phase. */
|
||||
UINT8 m_irq_vector; /**< @todo Unused variable. */
|
||||
UINT8 m_cmt_current_cmd; /**< MCU side: CMT command issued. */
|
||||
UINT8 m_cmt_test; /**< MCU side: Tape BREAK status bit. */
|
||||
UINT8 m_rom_index[3]; /**< Current ROM address. */
|
||||
UINT32 m_kanji_offset; /**< @todo Unused variable. */
|
||||
UINT8 m_bios_offset; /**< @todo Unused variable. */
|
||||
UINT8 m_x_b; /**< Palette Register for Blue Gun */
|
||||
UINT8 m_x_g; /**< Palette Register for Green Gun */
|
||||
UINT8 m_x_r; /**< Palette Register for Red Gun */
|
||||
UINT16 m_kanji_addr_latch; /**< Internal Kanji ROM address. */
|
||||
UINT32 m_kanji_addr; /**< Latched Kanji ROM address. */
|
||||
UINT8 m_kanji_eksel; /**< Kanji ROM register bit for latch phase. */
|
||||
UINT8 m_pcg_reset_occurred; /**< @todo Unused variable. */
|
||||
UINT32 m_old_key1; /**< Keyboard read buffer for i/o port "key1" */
|
||||
UINT32 m_old_key2; /**< Keyboard read buffer for i/o port "key2" */
|
||||
UINT32 m_old_key3; /**< Keyboard read buffer for i/o port "key3" */
|
||||
UINT32 m_old_key4; /**< Keyboard read buffer for i/o port "tenkey" */
|
||||
UINT32 m_old_fkey; /**< Keyboard read buffer for i/o port "f_keys" */
|
||||
UINT8 m_key_irq_flag; /**< Keyboard IRQ pending. */
|
||||
UINT8 m_key_irq_vector; /**< Keyboard IRQ vector. */
|
||||
UINT32 m_emm_addr; /**< EMM RAM current address */
|
||||
UINT8 *m_pal_4096; /**< X1 Turbo Z: pointer for 4096 palette entries */
|
||||
UINT8 m_crtc_vreg[0x100], /**< CRTC register buffer. */
|
||||
m_crtc_index; /**< CRTC register index. */
|
||||
UINT8 m_is_turbo; /**< Machine type: (0) X1 Vanilla, (1) X1 Turbo */
|
||||
UINT8 m_ex_bank; /**< X1 Turbo Z: RAM bank register */
|
||||
UINT8 m_ram_bank; /**< Regular RAM bank for 0x0000-0x7fff memory window: (0) ROM/IPL (1) RAM */
|
||||
UINT8 *m_tvram; /**< Pointer for Text Video RAM */
|
||||
UINT8 *m_avram; /**< Pointer for Attribute Video RAM */
|
||||
UINT8 *m_kvram; /**< Pointer for Extended Kanji Video RAM (X1 Turbo) */
|
||||
UINT8 *m_ipl_rom; /**< Pointer for IPL ROM */
|
||||
UINT8 *m_work_ram; /**< Pointer for base work RAM */
|
||||
UINT8 *m_emm_ram; /**< Pointer for EMM RAM */
|
||||
UINT8 *m_pcg_ram; /**< Pointer for PCG GFX RAM */
|
||||
UINT8 *m_cg_rom; /**< Pointer for GFX ROM */
|
||||
UINT8 *m_kanji_rom; /**< Pointer for Kanji ROMs */
|
||||
int m_xstart, /**< Start X offset for screen drawing. */
|
||||
m_ystart; /**< Start Y offset for screen drawing. */
|
||||
UINT8 m_hres_320; /**< Pixel clock divider setting: (1) 48 (0) 24 */
|
||||
UINT8 m_io_switch; /**< Enable access for special bitmap RMW phase in isolated i/o. */
|
||||
UINT8 m_io_sys; /**< Read-back for PPI port C */
|
||||
UINT8 m_vsync; /**< Screen V-Sync bit, active low */
|
||||
UINT8 m_vdisp; /**< Screen V-Disp bit, active high */
|
||||
UINT8 m_io_bank_mode; /**< Helper for special bitmap RMW phase. */
|
||||
UINT8 *m_gfx_bitmap_ram; /**< Pointer for bitmap layer RAM. */
|
||||
UINT8 m_pcg_reset; /**< @todo Unused variable. */
|
||||
UINT8 m_sub_obf; /**< MCU side: OBF flag active low, indicates that there are parameters in comm buffer. */
|
||||
UINT8 m_ctc_irq_flag; /**< @todo Unused variable. */
|
||||
scrn_reg_t m_scrn_reg; /**< Base Video Registers. */
|
||||
turbo_reg_t m_turbo_reg; /**< Turbo Z Video Registers. */
|
||||
x1_rtc_t m_rtc; /**< Struct for RTC related variables */
|
||||
emu_timer *m_rtc_timer; /**< Pointer for RTC timer. */
|
||||
UINT8 m_pcg_write_addr; /**< @todo Unused variable. */
|
||||
UINT8 m_sub_cmd; /**< MCU side: current command issued from Main to Sub. */
|
||||
UINT8 m_sub_cmd_length; /**< MCU side: number of parameters, in bytes. */
|
||||
UINT8 m_sub_val[8]; /**< MCU side: parameters buffer. */
|
||||
int m_sub_val_ptr; /**< MCU side: index for parameter read-back */
|
||||
int m_key_i; /**< MCU side: index for keyboard read-back during OBF phase. */
|
||||
UINT8 m_irq_vector; /**< @todo Unused variable. */
|
||||
UINT8 m_cmt_current_cmd; /**< MCU side: CMT command issued. */
|
||||
UINT8 m_cmt_test; /**< MCU side: Tape BREAK status bit. */
|
||||
UINT8 m_rom_index[3]; /**< Current ROM address. */
|
||||
UINT32 m_kanji_offset; /**< @todo Unused variable. */
|
||||
UINT8 m_bios_offset; /**< @todo Unused variable. */
|
||||
UINT8 m_x_b; /**< Palette Register for Blue Gun */
|
||||
UINT8 m_x_g; /**< Palette Register for Green Gun */
|
||||
UINT8 m_x_r; /**< Palette Register for Red Gun */
|
||||
UINT16 m_kanji_addr_latch; /**< Internal Kanji ROM address. */
|
||||
UINT32 m_kanji_addr; /**< Latched Kanji ROM address. */
|
||||
UINT8 m_kanji_eksel; /**< Kanji ROM register bit for latch phase. */
|
||||
UINT8 m_pcg_reset_occurred; /**< @todo Unused variable. */
|
||||
UINT32 m_old_key1; /**< Keyboard read buffer for i/o port "key1" */
|
||||
UINT32 m_old_key2; /**< Keyboard read buffer for i/o port "key2" */
|
||||
UINT32 m_old_key3; /**< Keyboard read buffer for i/o port "key3" */
|
||||
UINT32 m_old_key4; /**< Keyboard read buffer for i/o port "tenkey" */
|
||||
UINT32 m_old_fkey; /**< Keyboard read buffer for i/o port "f_keys" */
|
||||
UINT8 m_key_irq_flag; /**< Keyboard IRQ pending. */
|
||||
UINT8 m_key_irq_vector; /**< Keyboard IRQ vector. */
|
||||
UINT32 m_emm_addr; /**< EMM RAM current address */
|
||||
UINT8 *m_pal_4096; /**< X1 Turbo Z: pointer for 4096 palette entries */
|
||||
UINT8 m_crtc_vreg[0x100], /**< CRTC register buffer. */
|
||||
m_crtc_index; /**< CRTC register index. */
|
||||
UINT8 m_is_turbo; /**< Machine type: (0) X1 Vanilla, (1) X1 Turbo */
|
||||
UINT8 m_ex_bank; /**< X1 Turbo Z: RAM bank register */
|
||||
UINT8 m_ram_bank; /**< Regular RAM bank for 0x0000-0x7fff memory window: (0) ROM/IPL (1) RAM */
|
||||
/**
|
||||
@brief Refresh current bitmap palette.
|
||||
*/
|
||||
|
||||
@ -758,4 +758,3 @@ WRITE8_MEMBER( lk201_device::spi_w )
|
||||
|
||||
// printf("SPI %02x to %x (PC=%x)\n", data, offset, m_maincpu->pc());
|
||||
}
|
||||
|
||||
|
||||
@ -2,7 +2,7 @@
|
||||
// copyright-holders:Curt Coder
|
||||
/**********************************************************************
|
||||
|
||||
Wang PC keyboard emulation
|
||||
Wang PC keyboard emulation
|
||||
|
||||
*********************************************************************/
|
||||
|
||||
|
||||
@ -2,11 +2,11 @@
|
||||
// copyright-holders:R. Belmont,Ryan Holtz
|
||||
/***************************************************************************
|
||||
|
||||
gba.c
|
||||
gba.c
|
||||
|
||||
File to handle emulation of the video hardware of the Game Boy Advance
|
||||
File to handle emulation of the video hardware of the Game Boy Advance
|
||||
|
||||
By R. Belmont, MooglyGuy
|
||||
By R. Belmont, MooglyGuy
|
||||
|
||||
***************************************************************************/
|
||||
|
||||
|
||||
@ -264,7 +264,7 @@ WRITE8_MEMBER(vt100_video_device::dc012_w)
|
||||
//printf("\n PC %05x - MHFU MAGIC -2 %02x\n", PC, magic2);
|
||||
//if (VERBOSE)
|
||||
|
||||
//if(1 )
|
||||
//if(1 )
|
||||
if ((rom[PC - 2] == 0x0C) &&
|
||||
(rom[PC - 1] == 0x01)
|
||||
)
|
||||
@ -904,7 +904,7 @@ int rainbow_video_device::MHFU(int ASK)
|
||||
|
||||
return -100;
|
||||
|
||||
case -200: // -200 : RESET and DISABLE MHFU
|
||||
case -200: // -200 : RESET and DISABLE MHFU
|
||||
MHFU_counter = 0;
|
||||
|
||||
if(1) //if (VERBOSE)
|
||||
|
||||
@ -1655,7 +1655,7 @@ void shaders::bloom_pass(render_target *rt, vec2f &texsize, vec2f &delta, poly_i
|
||||
|
||||
void shaders::screen_pass(render_target *rt, vec2f &texsize, vec2f &delta, poly_info *poly, int vertnum)
|
||||
{
|
||||
UINT num_passes = 0;
|
||||
UINT num_passes = 0;
|
||||
|
||||
curr_effect = simple_effect;
|
||||
curr_effect->update_uniforms();
|
||||
|
||||
@ -102,17 +102,17 @@ class tool_options_t : public poptions
|
||||
public:
|
||||
tool_options_t() :
|
||||
poptions(),
|
||||
opt_ttr ("t", "time_to_run", 1.0, "time to run the emulation (seconds)", this),
|
||||
opt_ttr ("t", "time_to_run", 1.0, "time to run the emulation (seconds)", this),
|
||||
opt_logs("l", "logs", "", "colon separated list of terminals to log", this),
|
||||
opt_file("f", "file", "-", "file to process (default is stdin)", this),
|
||||
opt_cmd ("c", "cmd", "run", "run|convert|listdevices", this),
|
||||
opt_cmd ("c", "cmd", "run", "run|convert|listdevices", this),
|
||||
opt_verb("v", "verbose", "be verbose - this produces lots of output", this),
|
||||
opt_help("h", "help", "display help", this)
|
||||
{}
|
||||
|
||||
poption_double opt_ttr;
|
||||
poption_str opt_logs;
|
||||
poption_str opt_file;
|
||||
poption_str opt_file;
|
||||
poption_str opt_cmd;
|
||||
poption_bool opt_verb;
|
||||
poption_bool opt_help;
|
||||
@ -639,21 +639,21 @@ private:
|
||||
};
|
||||
|
||||
convert_t::sp_unit convert_t::m_sp_units[] = {
|
||||
{"T", "", 1.0e12 },
|
||||
{"G", "", 1.0e9 },
|
||||
{"MEG", "RES_M(%g)", 1.0e6 },
|
||||
{"K", "RES_K(%g)", 1.0e3 },
|
||||
{"", "%g", 1.0e0 },
|
||||
{"M", "CAP_M(%g)", 1.0e-3 },
|
||||
{"U", "CAP_U(%g)", 1.0e-6 },
|
||||
{"µ", "CAP_U(%g)", 1.0e-6 },
|
||||
{"N", "CAP_N(%g)", 1.0e-9 },
|
||||
{"T", "", 1.0e12 },
|
||||
{"G", "", 1.0e9 },
|
||||
{"MEG", "RES_M(%g)", 1.0e6 },
|
||||
{"K", "RES_K(%g)", 1.0e3 },
|
||||
{"", "%g", 1.0e0 },
|
||||
{"M", "CAP_M(%g)", 1.0e-3 },
|
||||
{"U", "CAP_U(%g)", 1.0e-6 },
|
||||
{"??", "CAP_U(%g)", 1.0e-6 },
|
||||
{"N", "CAP_N(%g)", 1.0e-9 },
|
||||
{"P", "CAP_P(%g)", 1.0e-12},
|
||||
{"F", "%ge-15", 1.0e-15},
|
||||
{"F", "%ge-15", 1.0e-15},
|
||||
|
||||
{"MIL", "%e", 25.4e-6},
|
||||
|
||||
{"-", "%g", 1.0 }
|
||||
{"-", "%g", 1.0 }
|
||||
};
|
||||
|
||||
|
||||
@ -665,7 +665,6 @@ convert_t::sp_unit convert_t::m_sp_units[] = {
|
||||
|
||||
int main(int argc, char *argv[])
|
||||
{
|
||||
|
||||
track_memory(true);
|
||||
{
|
||||
tool_options_t opts;
|
||||
|
||||
@ -8,7 +8,7 @@
|
||||
|
||||
***************************************************************************/
|
||||
|
||||
#define BARE_BUILD_VERSION "0.161"
|
||||
#define BARE_BUILD_VERSION "0.162"
|
||||
|
||||
extern const char bare_build_version[];
|
||||
extern const char build_version[];
|
||||
|
||||
Loading…
Reference in New Issue
Block a user