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drivers starting with c and d: completed read* and write* macros removal (nw)

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This commit is contained in:
Ivan Vangelista 2020-06-08 17:17:27 +02:00
parent ddc7ec4db2
commit 65d282d19e
241 changed files with 2317 additions and 2338 deletions
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8
src/devices/cpu/powerpc/ppc.h
View File

@ -501,8 +501,8 @@ protected:
uint64_t m_dec_zero_cycles;
emu_timer * m_decrementer_int_timer;
read32_delegate m_dcr_read_func;
write32_delegate m_dcr_write_func;
read32sm_delegate m_dcr_read_func;
write32sm_delegate m_dcr_write_func;
write32sm_delegate m_dcstore_cb;
@ -756,8 +756,8 @@ public:
void ppc4xx_set_dma_read_handler(int channel, read32_delegate callback, int rate);
void ppc4xx_set_dma_write_handler(int channel, write32sm_delegate callback, int rate);
void ppc4xx_set_dcr_read_handler(read32_delegate dcr_read_func);
void ppc4xx_set_dcr_write_handler(write32_delegate dcr_write_func);
void ppc4xx_set_dcr_read_handler(read32sm_delegate dcr_read_func);
void ppc4xx_set_dcr_write_handler(write32sm_delegate dcr_write_func);
uint8_t ppc4xx_spu_r(offs_t offset);
void ppc4xx_spu_w(offs_t offset, uint8_t data);

8
src/devices/cpu/powerpc/ppccom.cpp
View File

@ -1924,7 +1924,7 @@ void ppc_device::ppccom_execute_mfdcr()
else
m_core->param1 = 0;
} else {
m_core->param1 = m_dcr_read_func(*m_program,m_core->param0,0xffffffff);
m_core->param1 = m_dcr_read_func(m_core->param0);
}
}
@ -2014,7 +2014,7 @@ void ppc_device::ppccom_execute_mtdcr()
if (m_core->param0 < ARRAY_LENGTH(m_dcr))
m_dcr[m_core->param0] = m_core->param1;
} else {
m_dcr_write_func(*m_program,m_core->param0,m_core->param1,0xffffffff);
m_dcr_write_func(m_core->param0,m_core->param1);
}
}
@ -2903,7 +2903,7 @@ void ppc4xx_device::ppc4xx_set_dma_write_handler(int channel, write32sm_delegate
ppc4xx_set_dcr_read_handler
-------------------------------------------------*/
void ppc4xx_device::ppc4xx_set_dcr_read_handler(read32_delegate dcr_read_func)
void ppc4xx_device::ppc4xx_set_dcr_read_handler(read32sm_delegate dcr_read_func)
{
m_dcr_read_func = dcr_read_func;
@ -2913,7 +2913,7 @@ void ppc4xx_device::ppc4xx_set_dcr_read_handler(read32_delegate dcr_read_func)
ppc4xx_set_dcr_write_handler
-------------------------------------------------*/
void ppc4xx_device::ppc4xx_set_dcr_write_handler(write32_delegate dcr_write_func)
void ppc4xx_device::ppc4xx_set_dcr_write_handler(write32sm_delegate dcr_write_func)
{
m_dcr_write_func = dcr_write_func;
}

6
src/mame/audio/canyon.cpp
View File

@ -2,7 +2,7 @@
// copyright-holders:Mike Balfour
/*************************************************************************
audio\canyon.c
audio\canyon.cpp
*************************************************************************/
#include "emu.h"
@ -16,13 +16,13 @@
*
*************************************/
WRITE8_MEMBER(canyon_state::canyon_motor_w)
void canyon_state::canyon_motor_w(offs_t offset, uint8_t data)
{
m_discrete->write(NODE_RELATIVE(CANYON_MOTOR1_DATA, (offset & 0x01)), data & 0x0f);
}
WRITE8_MEMBER(canyon_state::canyon_explode_w)
void canyon_state::canyon_explode_w(uint8_t data)
{
m_discrete->write(CANYON_EXPLODE_DATA, data >> 4);
}

4
src/mame/audio/carnival.cpp
View File

@ -61,7 +61,7 @@ enum
};
WRITE8_MEMBER( carnival_state::carnival_audio_1_w )
void carnival_state::carnival_audio_1_w(uint8_t data)
{
int bitsChanged;
int bitsGoneHigh;
@ -126,7 +126,7 @@ WRITE8_MEMBER( carnival_state::carnival_audio_1_w )
}
}
WRITE8_MEMBER( carnival_state::carnival_audio_2_w )
void carnival_state::carnival_audio_2_w(uint8_t data)
{
int bitsChanged;
//int bitsGoneHigh;

12
src/mame/audio/cchasm.cpp
View File

@ -13,7 +13,7 @@
#include "sound/ay8910.h"
WRITE8_MEMBER(cchasm_state::reset_coin_flag_w)
void cchasm_state::reset_coin_flag_w(uint8_t data)
{
if (m_coin_flag)
{
@ -31,27 +31,27 @@ INPUT_CHANGED_MEMBER(cchasm_state::set_coin_flag )
}
}
READ8_MEMBER(cchasm_state::coin_sound_r)
uint8_t cchasm_state::coin_sound_r()
{
uint8_t coin = (ioport("IN3")->read() >> 4) & 0x7;
return m_sound_flags | (m_coin_flag << 3) | coin;
}
READ8_MEMBER(cchasm_state::soundlatch2_r)
uint8_t cchasm_state::soundlatch2_r()
{
m_sound_flags &= ~0x80;
m_ctc->trg2(0);
return m_soundlatch2->read();
}
WRITE8_MEMBER(cchasm_state::soundlatch4_w)
void cchasm_state::soundlatch4_w(uint8_t data)
{
m_sound_flags |= 0x40;
m_soundlatch4->write(data);
m_maincpu->set_input_line(1, HOLD_LINE);
}
WRITE16_MEMBER(cchasm_state::io_w)
void cchasm_state::io_w(offs_t offset, uint16_t data, uint16_t mem_mask)
{
//static int led;
@ -76,7 +76,7 @@ WRITE16_MEMBER(cchasm_state::io_w)
}
}
READ16_MEMBER(cchasm_state::io_r)
uint16_t cchasm_state::io_r(offs_t offset)
{
switch (offset & 0xf)
{

2
src/mame/audio/cinemat.cpp
View File

@ -1442,7 +1442,7 @@ void demon_state::demon_sound(machine_config &config)
*
*************************************/
WRITE8_MEMBER(qb3_state::qb3_sound_fifo_w)
void qb3_state::qb3_sound_fifo_w(uint8_t data)
{
uint16_t rega = m_maincpu->state_int(ccpu_cpu_device::CCPU_A);
machine().scheduler().synchronize(timer_expired_delegate(FUNC(qb3_state::synced_sound_w), this), rega & 0x0f);

6
src/mame/audio/crbaloon.cpp
View File

@ -31,13 +31,13 @@
WRITE8_MEMBER(crbaloon_state::crbaloon_audio_set_music_freq)
void crbaloon_state::crbaloon_audio_set_music_freq(uint8_t data)
{
m_discrete->write(CRBALOON_MUSIC_DATA, data);
}
WRITE8_MEMBER(crbaloon_state::crbaloon_audio_set_music_enable)
void crbaloon_state::crbaloon_audio_set_music_enable(uint8_t data)
{
m_discrete->write(CRBALOON_MUSIC_EN, data);
}
@ -65,7 +65,7 @@ void crbaloon_state::crbaloon_audio_set_appear_enable(int enabled)
}
WRITE8_MEMBER(crbaloon_state::crbaloon_audio_set_laugh_enable)
void crbaloon_state::crbaloon_audio_set_laugh_enable(uint8_t data)
{
m_discrete->write(CRBALOON_LAUGH_EN, data);
}

73
src/mame/audio/dcs.cpp
View File

@ -910,13 +910,16 @@ void dcs_audio_device::install_speedup(void)
{
if (m_polling_offset) {
if (m_rev < REV_DSIO) {
m_cpu->space(AS_DATA).install_readwrite_handler(m_polling_offset, m_polling_offset, read16_delegate(*this, FUNC(dcs_audio_device::dcs_polling_r)), write16_delegate(*this, FUNC(dcs_audio_device::dcs_polling_w)));
m_cpu->space(AS_DATA).install_read_handler(m_polling_offset, m_polling_offset, read16mo_delegate(*this, FUNC(dcs_audio_device::dcs_polling_r)));
m_cpu->space(AS_DATA).install_write_handler(m_polling_offset, m_polling_offset, write16s_delegate(*this, FUNC(dcs_audio_device::dcs_polling_w)));
}
else {
// ADSP 2181 (DSIO and DENVER) use program memory
m_cpu->space(AS_PROGRAM).install_readwrite_handler(m_polling_offset, m_polling_offset, read32_delegate(*this, FUNC(dcs_audio_device::dcs_polling32_r)), write32_delegate(*this, FUNC(dcs_audio_device::dcs_polling32_w)));
m_cpu->space(AS_PROGRAM).install_read_handler(m_polling_offset, m_polling_offset, read32mo_delegate(*this, FUNC(dcs_audio_device::dcs_polling32_r)));
m_cpu->space(AS_PROGRAM).install_write_handler(m_polling_offset, m_polling_offset, write32s_delegate(*this, FUNC(dcs_audio_device::dcs_polling32_w)));
// DSIO and DENVER poll in two spots. This offset covers all three machines (mwskins, sf2049, roadburn).
m_cpu->space(AS_PROGRAM).install_readwrite_handler(m_polling_offset + 9, m_polling_offset + 9, read32_delegate(*this, FUNC(dcs_audio_device::dcs_polling32_r)), write32_delegate(*this, FUNC(dcs_audio_device::dcs_polling32_w)));
m_cpu->space(AS_PROGRAM).install_read_handler(m_polling_offset + 9, m_polling_offset + 9, read32mo_delegate(*this, FUNC(dcs_audio_device::dcs_polling32_r)));
m_cpu->space(AS_PROGRAM).install_write_handler(m_polling_offset + 9, m_polling_offset + 9, write32s_delegate(*this, FUNC(dcs_audio_device::dcs_polling32_w)));
}
}
}
@ -934,14 +937,14 @@ void dcs_audio_device::set_auto_ack(int state)
*
*************************************/
READ16_MEMBER( dcs_audio_device::dcs_dataram_r )
uint16_t dcs_audio_device::dcs_dataram_r(offs_t offset)
{
assert(m_external_program_ram != nullptr);
return m_external_program_ram[offset] >> 8;
}
WRITE16_MEMBER( dcs_audio_device::dcs_dataram_w )
void dcs_audio_device::dcs_dataram_w(offs_t offset, uint16_t data, uint16_t mem_mask)
{
assert(m_external_program_ram != nullptr);
uint16_t val = m_external_program_ram[offset] >> 8;
@ -950,7 +953,7 @@ WRITE16_MEMBER( dcs_audio_device::dcs_dataram_w )
}
WRITE16_MEMBER( dcs_audio_device::dcs_data_bank_select_w )
void dcs_audio_device::dcs_data_bank_select_w(uint16_t data)
{
if (m_rev != REV_DCS1P5)
m_sounddata_bank = data & 0x7ff;
@ -966,7 +969,7 @@ WRITE16_MEMBER( dcs_audio_device::dcs_data_bank_select_w )
#endif
}
WRITE16_MEMBER( dcs_audio_device::dcs_data_bank_select2_w )
void dcs_audio_device::dcs_data_bank_select2_w(uint16_t data)
{
m_sounddata_bank = (m_sounddata_bank & 0x00ff) | ((data & 0x01) << 8) | ((data & 0xfc) << 7);
@ -1082,7 +1085,7 @@ void dcs_audio_device::sdrc_reset()
*
*************************************/
READ16_MEMBER( dcs_audio_device::sdrc_r )
uint16_t dcs_audio_device::sdrc_r(offs_t offset)
{
sdrc_state &sdrc = m_sdrc;
uint16_t result = sdrc.reg[offset];
@ -1131,7 +1134,7 @@ READ16_MEMBER( dcs_audio_device::sdrc_r )
}
WRITE16_MEMBER( dcs_audio_device::sdrc_w )
void dcs_audio_device::sdrc_w(offs_t offset, uint16_t data)
{
sdrc_state &sdrc = m_sdrc;
uint16_t diff = sdrc.reg[offset] ^ data;
@ -1214,7 +1217,7 @@ void dcs_audio_device::dsio_reset()
}
READ16_MEMBER( dcs_audio_device::dsio_r )
uint16_t dcs_audio_device::dsio_r(offs_t offset)
{
dsio_state &dsio = m_dsio;
uint16_t result = dsio.reg[offset];
@ -1230,7 +1233,7 @@ READ16_MEMBER( dcs_audio_device::dsio_r )
}
WRITE16_MEMBER( dcs_audio_device::dsio_w )
void dcs_audio_device::dsio_w(offs_t offset, uint16_t data)
{
dsio_state &dsio = m_dsio;
@ -1291,7 +1294,7 @@ void dcs_audio_device::denver_alloc_dmadac()
// recompute_sample_rate();
}
READ16_MEMBER( dcs_audio_device::denver_r )
uint16_t dcs_audio_device::denver_r(offs_t offset)
{
uint16_t result = m_dsio.reg[offset];
@ -1307,7 +1310,7 @@ READ16_MEMBER( dcs_audio_device::denver_r )
}
WRITE16_MEMBER( dcs_audio_device::denver_w )
void dcs_audio_device::denver_w(offs_t offset, uint16_t data)
{
dsio_state &dsio = m_dsio;
int channels;
@ -1365,7 +1368,7 @@ WRITE16_MEMBER( dcs_audio_device::denver_w )
*
*************************************/
WRITE32_MEMBER( dcs_audio_device::dsio_idma_addr_w )
void dcs_audio_device::dsio_idma_addr_w(uint32_t data)
{
if (LOG_DCS_TRANSFERS)
logerror("%s IDMA_addr = %04X\n", machine().describe_context(), data);
@ -1375,7 +1378,7 @@ WRITE32_MEMBER( dcs_audio_device::dsio_idma_addr_w )
}
WRITE32_MEMBER( dcs_audio_device::dsio_idma_data_w )
void dcs_audio_device::dsio_idma_data_w(offs_t offset, uint32_t data, uint32_t mem_mask)
{
dsio_state &dsio = m_dsio;
// IDMA is to internal memory only
@ -1405,7 +1408,7 @@ WRITE32_MEMBER( dcs_audio_device::dsio_idma_data_w )
}
READ32_MEMBER( dcs_audio_device::dsio_idma_data_r )
uint32_t dcs_audio_device::dsio_idma_data_r()
{
uint32_t result;
// IDMA is to internal memory only
@ -1495,7 +1498,7 @@ void dcs_audio_device::reset_w(int state)
}
READ16_MEMBER( dcs_audio_device::latch_status_r )
uint16_t dcs_audio_device::latch_status_r(address_space &space)
{
int result = 0;
if (IS_INPUT_FULL())
@ -1510,7 +1513,7 @@ READ16_MEMBER( dcs_audio_device::latch_status_r )
}
READ16_MEMBER( dcs_audio_device::fifo_input_r )
uint16_t dcs_audio_device::fifo_input_r()
{
if (!m_fifo_data_r.isnull())
return m_fifo_data_r();
@ -1566,7 +1569,7 @@ void dcs_audio_device::data_w(uint16_t data)
}
WRITE16_MEMBER( dcs_audio_device::input_latch_ack_w )
void dcs_audio_device::input_latch_ack_w(uint16_t data)
{
if (!m_last_input_empty && !m_input_empty_cb.isnull())
m_input_empty_cb(m_last_input_empty = 1);
@ -1578,20 +1581,20 @@ WRITE16_MEMBER( dcs_audio_device::input_latch_ack_w )
}
READ16_MEMBER( dcs_audio_device::input_latch_r )
uint16_t dcs_audio_device::input_latch_r()
{
if (m_auto_ack)
input_latch_ack_w(space,0,0,0xffff);
input_latch_ack_w(0);
if (LOG_DCS_IO)
logerror("%s input_latch_r(%04X)\n", machine().describe_context(), m_input_data);
return m_input_data;
}
READ32_MEMBER( dcs_audio_device::input_latch32_r )
uint32_t dcs_audio_device::input_latch32_r()
{
if (m_auto_ack)
input_latch_ack_w(space,0,0,0xffff);
input_latch_ack_w(0);
if (LOG_DCS_IO)
logerror("%s input_latch32_r(%04X)\n", machine().describe_context(), m_input_data);
return m_input_data << 8;
@ -1619,7 +1622,7 @@ void dcs_audio_device::output_latch_w(uint16_t data)
machine().scheduler().synchronize(timer_expired_delegate(FUNC(dcs_audio_device::latch_delayed_w),this), data>>8);
}
WRITE32_MEMBER( dcs_audio_device::output_latch32_w )
void dcs_audio_device::output_latch32_w(uint32_t data)
{
m_pre_output_data = data >> 8;
if (LOG_DCS_IO)
@ -1681,7 +1684,7 @@ TIMER_CALLBACK_MEMBER( dcs_audio_device::output_control_delayed_w )
}
WRITE16_MEMBER( dcs_audio_device::output_control_w )
void dcs_audio_device::output_control_w(uint16_t data)
{
if (LOG_DCS_IO)
logerror("%s output_control_w = %04X\n", machine().describe_context(), data);
@ -1689,7 +1692,7 @@ WRITE16_MEMBER( dcs_audio_device::output_control_w )
}
READ16_MEMBER( dcs_audio_device::output_control_r )
uint16_t dcs_audio_device::output_control_r()
{
if (LOG_DCS_IO)
logerror("%s output_control_r = %04X\n", machine().describe_context(), m_output_control);
@ -1857,7 +1860,7 @@ WRITE_LINE_MEMBER(dcs_audio_device::timer_enable_callback)
0x3c00-0x3fff = Memory Mapped control registers & reserved.
*/
READ16_MEMBER( dcs_audio_device::adsp_control_r )
uint16_t dcs_audio_device::adsp_control_r(offs_t offset)
{
uint16_t result = 0xffff;
@ -1891,7 +1894,7 @@ READ16_MEMBER( dcs_audio_device::adsp_control_r )
}
WRITE16_MEMBER(dcs_audio_device:: adsp_control_w )
void dcs_audio_device:: adsp_control_w(offs_t offset, uint16_t data)
{
m_control_regs[offset] = data;
@ -1972,7 +1975,7 @@ WRITE16_MEMBER(dcs_audio_device:: adsp_control_w )
case IDMA_CONTROL_REG:
if (m_rev == REV_DSIO || m_rev == REV_DENV)
dsio_idma_addr_w(space, offset, data);
dsio_idma_addr_w(data);
break;
}
if (LOG_DCS_IO)
@ -2136,7 +2139,7 @@ void dcs_audio_device::sound_tx_callback(offs_t offset, uint32_t data)
VERY BASIC & SAFE OPTIMIZATIONS
****************************************************************************/
READ16_MEMBER( dcs_audio_device::dcs_polling_r )
uint16_t dcs_audio_device::dcs_polling_r(address_space &space)
{
if (m_polling_count++ > 5)
space.device().execute().eat_cycles(2000);
@ -2144,19 +2147,19 @@ READ16_MEMBER( dcs_audio_device::dcs_polling_r )
}
WRITE16_MEMBER( dcs_audio_device::dcs_polling_w )
void dcs_audio_device::dcs_polling_w(offs_t offset, uint16_t data, uint16_t mem_mask)
{
m_polling_count = 0;
COMBINE_DATA(&m_polling_value);
}
READ32_MEMBER(dcs_audio_device::dcs_polling32_r)
uint32_t dcs_audio_device::dcs_polling32_r(address_space &space)
{
space.device().execute().eat_cycles(1000);
return m_polling32_value;
}
WRITE32_MEMBER(dcs_audio_device::dcs_polling32_w)
void dcs_audio_device::dcs_polling32_w(offs_t offset, uint32_t data, uint32_t mem_mask)
{
m_polling_count = 0;
COMBINE_DATA(&m_polling32_value);
@ -2356,8 +2359,6 @@ int dcs_audio_device::preprocess_stage_1(uint16_t data)
TIMER_CALLBACK_MEMBER( dcs_audio_device::s2_ack_callback )
{
address_space &space = m_cpu->space(AS_PROGRAM);
/* if the output is full, stall for a usec */
if (IS_OUTPUT_FULL())
{
@ -2365,7 +2366,7 @@ TIMER_CALLBACK_MEMBER( dcs_audio_device::s2_ack_callback )
return;
}
output_latch_w(param);
output_control_w(space, 0, (m_output_control & ~0xff00) | 0x0300, 0xffff);
output_control_w((m_output_control & ~0xff00) | 0x0300);
}

54
src/mame/audio/dcs.h
View File

@ -39,9 +39,9 @@ public:
void fifo_notify(int count, int max);
DECLARE_WRITE32_MEMBER( dsio_idma_addr_w );
DECLARE_WRITE32_MEMBER( dsio_idma_data_w );
DECLARE_READ32_MEMBER( dsio_idma_data_r );
void dsio_idma_addr_w(uint32_t data);
void dsio_idma_data_w(offs_t offset, uint32_t data, uint32_t mem_mask = ~0);
uint32_t dsio_idma_data_r();
void dmovlay_remap_memory();
void dmovlay_callback(uint32_t data);
void denver_postload(void);
@ -51,51 +51,51 @@ public:
void dcs_boot();
TIMER_CALLBACK_MEMBER( dcs_reset );
void dcs_register_state();
DECLARE_READ16_MEMBER( dcs_dataram_r );
DECLARE_WRITE16_MEMBER( dcs_dataram_w );
DECLARE_WRITE16_MEMBER( dcs_data_bank_select_w );
DECLARE_WRITE16_MEMBER( dcs_data_bank_select2_w );
uint16_t dcs_dataram_r(offs_t offset);
void dcs_dataram_w(offs_t offset, uint16_t data, uint16_t mem_mask = ~0);
void dcs_data_bank_select_w(uint16_t data);
void dcs_data_bank_select2_w(uint16_t data);
inline void sdrc_update_bank_pointers();
void sdrc_remap_memory();
void sdrc_reset();
DECLARE_READ16_MEMBER( sdrc_r );
DECLARE_WRITE16_MEMBER( sdrc_w );
uint16_t sdrc_r(offs_t offset);
void sdrc_w(offs_t offset, uint16_t data);
void dsio_reset();
DECLARE_READ16_MEMBER( dsio_r );
DECLARE_WRITE16_MEMBER( dsio_w );
uint16_t dsio_r(offs_t offset);
void dsio_w(offs_t offset, uint16_t data);
void denver_alloc_dmadac(void);
void denver_reset();
DECLARE_READ16_MEMBER( denver_r );
DECLARE_WRITE16_MEMBER( denver_w );
DECLARE_READ16_MEMBER( latch_status_r );
DECLARE_READ16_MEMBER( fifo_input_r );
uint16_t denver_r(offs_t offset);
void denver_w(offs_t offset, uint16_t data);
uint16_t latch_status_r(address_space &space);
uint16_t fifo_input_r();
void dcs_delayed_data_w(uint16_t data);
TIMER_CALLBACK_MEMBER( dcs_delayed_data_w_callback );
DECLARE_WRITE16_MEMBER( input_latch_ack_w );
DECLARE_READ16_MEMBER( input_latch_r );
DECLARE_READ32_MEMBER( input_latch32_r );
void input_latch_ack_w(uint16_t data);
uint16_t input_latch_r();
uint32_t input_latch32_r();
TIMER_CALLBACK_MEMBER( latch_delayed_w );
void output_latch_w(uint16_t data);
DECLARE_WRITE32_MEMBER( output_latch32_w );
void output_latch32_w(uint32_t data);
void delayed_ack_w();
TIMER_CALLBACK_MEMBER( delayed_ack_w_callback );
TIMER_CALLBACK_MEMBER( output_control_delayed_w );
DECLARE_WRITE16_MEMBER( output_control_w );
DECLARE_READ16_MEMBER( output_control_r );
void output_control_w(uint16_t data);
uint16_t output_control_r();
void update_timer_count();
TIMER_DEVICE_CALLBACK_MEMBER( internal_timer_callback );
void reset_timer();
DECLARE_WRITE_LINE_MEMBER(timer_enable_callback);
DECLARE_READ16_MEMBER( adsp_control_r );
DECLARE_WRITE16_MEMBER( adsp_control_w );
uint16_t adsp_control_r(offs_t offset);
void adsp_control_w(offs_t offset, uint16_t data);
TIMER_DEVICE_CALLBACK_MEMBER( dcs_irq );
TIMER_DEVICE_CALLBACK_MEMBER( sport0_irq );
void recompute_sample_rate();
void sound_tx_callback(offs_t offset, uint32_t data);
DECLARE_READ16_MEMBER( dcs_polling_r );
DECLARE_WRITE16_MEMBER( dcs_polling_w );
DECLARE_READ32_MEMBER(dcs_polling32_r);
DECLARE_WRITE32_MEMBER(dcs_polling32_w);
uint16_t dcs_polling_r(address_space &space);
void dcs_polling_w(offs_t offset, uint16_t data, uint16_t mem_mask = ~0);
uint32_t dcs_polling32_r(address_space &space);
void dcs_polling32_w(offs_t offset, uint32_t data, uint32_t mem_mask = ~0);
TIMER_DEVICE_CALLBACK_MEMBER( transfer_watchdog_callback );
TIMER_CALLBACK_MEMBER( s1_ack_callback2 );
TIMER_CALLBACK_MEMBER( s1_ack_callback1 );

2
src/mame/audio/depthch.cpp
View File

@ -42,7 +42,7 @@ enum
};
WRITE8_MEMBER( vicdual_state::depthch_audio_w )
void vicdual_state::depthch_audio_w(uint8_t data)
{
int bitsChanged;
int bitsGoneHigh;

2
src/mame/audio/dkong.cpp
View File

@ -1254,7 +1254,7 @@ void dkong_state::dkong_p1_w(uint8_t data)
*
****************************************************************/
WRITE8_MEMBER(dkong_state::dkong_audio_irq_w)
void dkong_state::dkong_audio_irq_w(uint8_t data)
{
if (data)
m_soundcpu->set_input_line(0, ASSERT_LINE);

14
src/mame/drivers/cabal.cpp
View File

@ -70,7 +70,7 @@ MACHINE_RESET_MEMBER(cabal_state,cabalbl)
/******************************************************************************************/
WRITE16_MEMBER(cabal_state::cabalbl_sndcmd_w)
void cabal_state::cabalbl_sndcmd_w(offs_t offset, uint16_t data)
{
switch (offset)
{
@ -95,7 +95,7 @@ void cabal_state::sound_irq_trigger_word_w(offs_t, u16 data, u16 mem_mask)
m_maincpu->spin_until_time(attotime::from_usec(50));
}
WRITE16_MEMBER(cabal_state::cabalbl_sound_irq_trigger_word_w)
void cabal_state::cabalbl_sound_irq_trigger_word_w(uint16_t data)
{
m_audiocpu->pulse_input_line(INPUT_LINE_NMI, attotime::zero);
}
@ -157,17 +157,17 @@ void cabal_state::cabalbl_main_map(address_map &map)
/*********************************************************************/
READ8_MEMBER(cabal_state::cabalbl_snd2_r)
uint8_t cabal_state::cabalbl_snd2_r()
{
return bitswap<8>(m_sound_command2, 7,2,4,5,3,6,1,0);
}
READ8_MEMBER(cabal_state::cabalbl_snd1_r)
uint8_t cabal_state::cabalbl_snd1_r()
{
return bitswap<8>(m_sound_command1, 7,2,4,5,3,6,1,0);
}
WRITE8_MEMBER(cabal_state::cabalbl_coin_w)
void cabal_state::cabalbl_coin_w(uint8_t data)
{
machine().bookkeeping().coin_counter_w(0, data & 1);
machine().bookkeeping().coin_counter_w(1, data & 2);
@ -245,7 +245,7 @@ void cabal_state::cabalbl2_predecrypted_opcodes_map(address_map &map)
/* the bootleg has 2x z80 sample players */
WRITE8_MEMBER(cabal_state::cabalbl_1_adpcm_w)
void cabal_state::cabalbl_1_adpcm_w(uint8_t data)
{
m_msm1->reset_w(BIT(data, 7));
/* ?? bit 6?? */
@ -253,7 +253,7 @@ WRITE8_MEMBER(cabal_state::cabalbl_1_adpcm_w)
m_msm1->vclk_w(1);
m_msm1->vclk_w(0);
}
WRITE8_MEMBER(cabal_state::cabalbl_2_adpcm_w)
void cabal_state::cabalbl_2_adpcm_w(uint8_t data)
{
m_msm2->reset_w(BIT(data, 7));
/* ?? bit 6?? */

6
src/mame/drivers/canyon.cpp
View File

@ -68,7 +68,7 @@ void canyon_state::canyon_palette(palette_device &palette) const
*
*************************************/
READ8_MEMBER(canyon_state::canyon_switches_r)
uint8_t canyon_state::canyon_switches_r(offs_t offset)
{
uint8_t val = 0;
@ -82,7 +82,7 @@ READ8_MEMBER(canyon_state::canyon_switches_r)
}
READ8_MEMBER(canyon_state::canyon_options_r)
uint8_t canyon_state::canyon_options_r(offs_t offset)
{
return (ioport("DSW")->read() >> (2 * (~offset & 3))) & 3;
}
@ -96,7 +96,7 @@ READ8_MEMBER(canyon_state::canyon_options_r)
*
*************************************/
WRITE8_MEMBER(canyon_state::output_latch_w)
void canyon_state::output_latch_w(offs_t offset, uint8_t data)
{
// ADR1 = D, ADR8 = A2, ADR7 = A1, ADR0 = A0
m_outlatch->write_bit((offset & 0x180) >> 6 | BIT(offset, 0), BIT(offset, 1));

10
src/mame/drivers/capbowl.cpp
View File

@ -153,7 +153,7 @@ TIMER_CALLBACK_MEMBER(capbowl_state::update)
*
*************************************/
WRITE8_MEMBER(capbowl_state::capbowl_rom_select_w)
void capbowl_state::capbowl_rom_select_w(uint8_t data)
{
// 2009-11 FP: shall we add a check to be sure that bank < 6?
membank("bank1")->set_entry(((data & 0x0c) >> 1) + (data & 0x01));
@ -167,19 +167,19 @@ WRITE8_MEMBER(capbowl_state::capbowl_rom_select_w)
*
*************************************/
READ8_MEMBER(capbowl_state::track_0_r)
uint8_t capbowl_state::track_0_r()
{
return (ioport("IN0")->read() & 0xf0) | ((ioport("TRACKY")->read() - m_last_trackball_val[0]) & 0x0f);
}
READ8_MEMBER(capbowl_state::track_1_r)
uint8_t capbowl_state::track_1_r()
{
return (ioport("IN1")->read() & 0xf0) | ((ioport("TRACKX")->read() - m_last_trackball_val[1]) & 0x0f);
}
WRITE8_MEMBER(capbowl_state::track_reset_w)
void capbowl_state::track_reset_w(uint8_t data)
{
/* reset the trackball counters */
m_last_trackball_val[0] = ioport("TRACKY")->read();
@ -196,7 +196,7 @@ WRITE8_MEMBER(capbowl_state::track_reset_w)
*
*************************************/
WRITE8_MEMBER(capbowl_state::sndcmd_w)
void capbowl_state::sndcmd_w(uint8_t data)
{
m_audiocpu->set_input_line(M6809_IRQ_LINE, HOLD_LINE);
m_soundlatch->write(data);

16
src/mame/drivers/cbasebal.cpp
View File

@ -32,7 +32,7 @@
*
*************************************/
WRITE8_MEMBER(cbasebal_state::cbasebal_bankswitch_w)
void cbasebal_state::cbasebal_bankswitch_w(uint8_t data)
{
/* bits 0-4 select ROM bank */
//logerror("%04x: bankswitch %02x\n", m_maincpu->pc(), data);
@ -46,40 +46,40 @@ WRITE8_MEMBER(cbasebal_state::cbasebal_bankswitch_w)
}
READ8_MEMBER(cbasebal_state::bankedram_r)
uint8_t cbasebal_state::bankedram_r(offs_t offset)
{
switch (m_rambank)
{
case 2:
return cbasebal_textram_r(space, offset); /* VRAM */
return cbasebal_textram_r(offset); /* VRAM */
case 1:
if (offset < 0x800)
return m_palette->basemem().read8(offset);
else
return 0;
default:
return cbasebal_scrollram_r(space, offset); /* SCROLL */
return cbasebal_scrollram_r(offset); /* SCROLL */
}
}
WRITE8_MEMBER(cbasebal_state::bankedram_w)
void cbasebal_state::bankedram_w(offs_t offset, uint8_t data)
{
switch (m_rambank)
{
case 2:
cbasebal_textram_w(space, offset, data);
cbasebal_textram_w(offset, data);
break;
case 1:
if (offset < 0x800)
m_palette->write8(offset, data);
break;
default:
cbasebal_scrollram_w(space, offset, data);
cbasebal_scrollram_w(offset, data);
break;
}
}
WRITE8_MEMBER(cbasebal_state::cbasebal_coinctrl_w)
void cbasebal_state::cbasebal_coinctrl_w(uint8_t data)
{
machine().bookkeeping().coin_lockout_w(0, ~data & 0x04);
machine().bookkeeping().coin_lockout_w(1, ~data & 0x08);

10
src/mame/drivers/ccastles.cpp
View File

@ -238,7 +238,7 @@ void ccastles_state::machine_reset()
*
*************************************/
WRITE8_MEMBER(ccastles_state::irq_ack_w)
void ccastles_state::irq_ack_w(uint8_t data)
{
if (m_irq_state)
{
@ -248,7 +248,7 @@ WRITE8_MEMBER(ccastles_state::irq_ack_w)
}
READ8_MEMBER(ccastles_state::leta_r)
uint8_t ccastles_state::leta_r(offs_t offset)
{
static const char *const letanames[] = { "LETA0", "LETA1", "LETA2", "LETA3" };
@ -263,7 +263,7 @@ READ8_MEMBER(ccastles_state::leta_r)
*
*************************************/
WRITE8_MEMBER(ccastles_state::nvram_recall_w)
void ccastles_state::nvram_recall_w(uint8_t data)
{
m_nvram_4b->recall(0);
m_nvram_4b->recall(1);
@ -281,13 +281,13 @@ WRITE_LINE_MEMBER(ccastles_state::nvram_store_w)
}
READ8_MEMBER(ccastles_state::nvram_r)
uint8_t ccastles_state::nvram_r(address_space &space, offs_t offset)
{
return (m_nvram_4b->read(space, offset) & 0x0f) | (m_nvram_4a->read(space,offset) << 4);
}
WRITE8_MEMBER(ccastles_state::nvram_w)
void ccastles_state::nvram_w(offs_t offset, uint8_t data)
{
m_nvram_4b->write(offset, data);
m_nvram_4a->write(offset, data >> 4);

4
src/mame/drivers/cdi.cpp
View File

@ -356,13 +356,13 @@ uint8_t quizard_state::mcu_rx()
* DVC cartridge *
*************************/
READ16_MEMBER( cdi_state::dvc_r )
uint16_t cdi_state::dvc_r(offs_t offset, uint16_t mem_mask)
{
LOGMASKED(LOG_DVC, "%s: dvc_r: %08x = 0000 & %04x\n", machine().describe_context(), 0xe80000 + (offset << 1), mem_mask);
return 0;
}
WRITE16_MEMBER( cdi_state::dvc_w )
void cdi_state::dvc_w(offs_t offset, uint16_t data, uint16_t mem_mask)
{
LOGMASKED(LOG_DVC, "%s: dvc_w: %08x = %04x & %04x\n", machine().describe_context(), 0xe80000 + (offset << 1), data, mem_mask);
}

32
src/mame/drivers/centiped.cpp
View File

@ -471,7 +471,7 @@ MACHINE_RESET_MEMBER(centiped_state,magworm)
}
WRITE8_MEMBER(centiped_state::irq_ack_w)
void centiped_state::irq_ack_w(uint8_t data)
{
m_maincpu->set_input_line(0, CLEAR_LINE);
}
@ -529,24 +529,24 @@ inline int centiped_state::read_trackball(int idx, int switch_port)
}
READ8_MEMBER(centiped_state::centiped_IN0_r)
uint8_t centiped_state::centiped_IN0_r()
{
return read_trackball(0, 0);
}
READ8_MEMBER(centiped_state::centiped_IN2_r)
uint8_t centiped_state::centiped_IN2_r()
{
return read_trackball(1, 2);
}
READ8_MEMBER(centiped_state::milliped_IN1_r)
uint8_t centiped_state::milliped_IN1_r()
{
return read_trackball(1, 1);
}
READ8_MEMBER(centiped_state::milliped_IN2_r)
uint8_t centiped_state::milliped_IN2_r()
{
uint8_t data = ioport("IN2")->read();
@ -580,7 +580,7 @@ WRITE_LINE_MEMBER(centiped_state::control_select_w)
}
READ8_MEMBER(centiped_state::mazeinv_input_r)
uint8_t centiped_state::mazeinv_input_r()
{
static const char *const sticknames[] = { "STICK0", "STICK1", "STICK2", "STICK3" };
@ -588,12 +588,12 @@ READ8_MEMBER(centiped_state::mazeinv_input_r)
}
WRITE8_MEMBER(centiped_state::mazeinv_input_select_w)
void centiped_state::mazeinv_input_select_w(offs_t offset, uint8_t data)
{
m_control_select = offset & 3;
}
READ8_MEMBER(centiped_state::bullsdrt_data_port_r)
uint8_t centiped_state::bullsdrt_data_port_r()
{
switch (m_maincpu->pc())
{
@ -653,12 +653,12 @@ WRITE_LINE_MEMBER(centiped_state::bullsdrt_coin_count_w)
*
*************************************/
READ8_MEMBER(centiped_state::earom_read)
uint8_t centiped_state::earom_read()
{
return m_earom->data();
}
WRITE8_MEMBER(centiped_state::earom_write)
void centiped_state::earom_write(offs_t offset, uint8_t data)
{
m_earom->set_address(offset & 0x3f);
m_earom->set_data(data);
@ -760,13 +760,13 @@ void centiped_state::caterplr_map(address_map &map)
map(0x1000, 0x100f).rw(FUNC(centiped_state::caterplr_AY8910_r), FUNC(centiped_state::caterplr_AY8910_w));
}
WRITE8_MEMBER(centiped_state::caterplr_AY8910_w)
void centiped_state::caterplr_AY8910_w(offs_t offset, uint8_t data)
{
m_aysnd->address_w(offset);
m_aysnd->data_w(data);
}
READ8_MEMBER(centiped_state::caterplr_AY8910_r)
uint8_t centiped_state::caterplr_AY8910_r(offs_t offset)
{
m_aysnd->address_w(offset);
return m_aysnd->data_r();
@ -852,12 +852,12 @@ void centiped_state::multiped_map(address_map &map)
map(0xdc00, 0xdc00).mirror(0x03ff).w(FUNC(centiped_state::multiped_gfxbank_w));
}
READ8_MEMBER(centiped_state::multiped_eeprom_r)
uint8_t centiped_state::multiped_eeprom_r()
{
return m_eeprom->do_read() ? 0x80 : 0;
}
WRITE8_MEMBER(centiped_state::multiped_eeprom_w)
void centiped_state::multiped_eeprom_w(offs_t offset, uint8_t data)
{
// a0: always high
// a3-a7: always low
@ -877,7 +877,7 @@ WRITE8_MEMBER(centiped_state::multiped_eeprom_w)
m_eeprom->cs_write((data & 0x80) ? ASSERT_LINE : CLEAR_LINE);
}
WRITE8_MEMBER(centiped_state::multiped_prgbank_w)
void centiped_state::multiped_prgbank_w(uint8_t data)
{
// d0-d6: N/C?
// d7: prg (and gfx) rom bank
@ -885,7 +885,7 @@ WRITE8_MEMBER(centiped_state::multiped_prgbank_w)
if (bank != m_prg_bank)
{
m_prg_bank = bank;
multiped_gfxbank_w(space, 0, m_gfx_bank << 6);
multiped_gfxbank_w(m_gfx_bank << 6);
// TODO: prg bankswitch and alt memory map layout for centiped
}

20
src/mame/drivers/cgc7900.cpp
View File

@ -96,7 +96,7 @@ void cgc7900_state::kbd_put(u8 data)
keyboard_r - keyboard data read
-------------------------------------------------*/
READ16_MEMBER( cgc7900_state::keyboard_r )
u16 cgc7900_state::keyboard_r()
{
u16 data;
@ -146,7 +146,7 @@ READ16_MEMBER( cgc7900_state::keyboard_r )
keyboard_w - keyboard data write
-------------------------------------------------*/
WRITE16_MEMBER( cgc7900_state::keyboard_w )
void cgc7900_state::keyboard_w(u16 data)
{
/*
@ -183,7 +183,7 @@ static const int int_vectors[16] = {
0x4b, 0x44, 0x4c, 0x43, 0x42, 0x4d, 0x45, 0x4a, 0x49, 0x46, 0x4e, 0x41, 0x40, 0x4f, 0x47, 0x48
};
WRITE16_MEMBER( cgc7900_state::interrupt_mask_w )
void cgc7900_state::interrupt_mask_w(u16 data)
{
/*
@ -255,7 +255,7 @@ void cgc7900_state::irq_encoder(int pin, int state)
disk_data_r - disk data read
-------------------------------------------------*/
READ16_MEMBER( cgc7900_state::disk_data_r )
u16 cgc7900_state::disk_data_r()
{
return 0;
}
@ -264,7 +264,7 @@ READ16_MEMBER( cgc7900_state::disk_data_r )
disk_data_w - disk data write
-------------------------------------------------*/
WRITE16_MEMBER( cgc7900_state::disk_data_w )
void cgc7900_state::disk_data_w(u16 data)
{
}
@ -272,7 +272,7 @@ WRITE16_MEMBER( cgc7900_state::disk_data_w )
disk_status_r - disk status read
-------------------------------------------------*/
READ16_MEMBER( cgc7900_state::disk_status_r )
u16 cgc7900_state::disk_status_r()
{
/*
@ -304,11 +304,11 @@ READ16_MEMBER( cgc7900_state::disk_status_r )
disk_command_w - disk command write
-------------------------------------------------*/
WRITE16_MEMBER( cgc7900_state::disk_command_w )
void cgc7900_state::disk_command_w(u16 data)
{
}
READ16_MEMBER(cgc7900_state::unmapped_r)
u16 cgc7900_state::unmapped_r()
{
return rand();
}
@ -440,9 +440,9 @@ void cgc7900_state::machine_start()
void cgc7900_state::machine_reset()
{
uint8_t *user1 = memregion(M68000_TAG)->base();
u8 *user1 = memregion(M68000_TAG)->base();
memcpy((uint8_t *)m_chrom_ram.target(), user1, 8); // not really what happens but...
memcpy((u8 *)m_chrom_ram.target(), user1, 8); // not really what happens but...
kbd_mods = 0x300; // forces cold boot -- initializes SRAM contents
kbd_data = 0;

4
src/mame/drivers/chaknpop.cpp
View File

@ -125,7 +125,7 @@ Notes:
***************************************************************************/
READ8_MEMBER(chaknpop_state::mcu_status_r)
uint8_t chaknpop_state::mcu_status_r()
{
// bit 0 = when 1, MCU is ready to receive data from main CPU
// bit 1 = when 1, MCU has sent data to the main CPU
@ -149,7 +149,7 @@ void chaknpop_state::unknown_port_3_w(uint8_t data)
//logerror("%s: write to unknown port 3: 0x%02x\n", machine().describe_context(), data);
}
WRITE8_MEMBER(chaknpop_state::coinlock_w)
void chaknpop_state::coinlock_w(uint8_t data)
{
logerror("%04x: coin lock %sable\n", m_maincpu->pc(), data ? "dis" : "en");
}

2
src/mame/drivers/champbas.cpp
View File

@ -125,7 +125,7 @@ TIMER_DEVICE_CALLBACK_MEMBER(exctsccr_state::exctsccr_sound_irq)
*************************************/
/* champbja another protection */
READ8_MEMBER(champbas_state::champbja_protection_r)
uint8_t champbas_state::champbja_protection_r(offs_t offset)
{
uint8_t data = 0;
/*

18
src/mame/drivers/changela.cpp
View File

@ -22,14 +22,14 @@ Tomasz Slanina
#include "changela.lh"
READ8_MEMBER(changela_state::mcu_r)
uint8_t changela_state::mcu_r()
{
//osd_printf_debug("Z80 MCU R = %x\n", m_mcu_out);
return m_mcu_out;
}
/* latch LS374 at U39 */
WRITE8_MEMBER(changela_state::mcu_w)
void changela_state::mcu_w(uint8_t data)
{
m_mcu_in = data;
if (!BIT(m_port_c_out, 2))
@ -62,23 +62,23 @@ void changela_state::changela_68705_port_c_w(uint8_t data)
/* U30 */
READ8_MEMBER(changela_state::changela_24_r)
uint8_t changela_state::changela_24_r()
{
return (BIT(m_port_c_out, 1) << 3) | 0x07; /* bits 2,1,0-N/C inputs */
}
READ8_MEMBER(changela_state::changela_25_r)
uint8_t changela_state::changela_25_r()
{
//collisions on bits 3,2, bits 1,0-N/C inputs
return (m_tree1_col << 3) | (m_tree0_col << 2) | 0x03;
}
READ8_MEMBER(changela_state::changela_30_r)
uint8_t changela_state::changela_30_r()
{
return ioport("WHEEL")->read() & 0x0f; //wheel control (clocked input) signal on bits 3,2,1,0
}
READ8_MEMBER(changela_state::changela_31_r)
uint8_t changela_state::changela_31_r()
{
/* If the new value is less than the old value, and it did not wrap around,
or if the new value is greater than the old value, and it did wrap around,
@ -98,7 +98,7 @@ READ8_MEMBER(changela_state::changela_31_r)
return (m_dir_31 << 3) | (m_left_bank_col << 2) | (m_right_bank_col << 1) | m_boat_shore_col;
}
READ8_MEMBER(changela_state::changela_2c_r)
uint8_t changela_state::changela_2c_r()
{
int val = ioport("IN0")->read();
@ -107,9 +107,9 @@ READ8_MEMBER(changela_state::changela_2c_r)
return val;
}
READ8_MEMBER(changela_state::changela_2d_r)
uint8_t changela_state::changela_2d_r()
{
/* the schems are unreadable - i'm not sure it is V8 (page 74, SOUND I/O BOARD SCHEMATIC 1 OF 2, FIGURE 24 - in the middle on the right side) */
/* the schems are unreadable - I'm not sure it is V8 (page 74, SOUND I/O BOARD SCHEMATIC 1 OF 2, FIGURE 24 - in the middle on the right side) */
int v8 = 0;
int gas;

16
src/mame/drivers/channelf.cpp
View File

@ -49,12 +49,12 @@ uint8_t channelf_state::port_read_with_latch(uint8_t ext, uint8_t latch_state)
return (~ext | latch_state);
}
READ8_MEMBER( channelf_state::port_0_r )
uint8_t channelf_state::port_0_r()
{
return port_read_with_latch(ioport("PANEL")->read(), m_latch[0]);
}
READ8_MEMBER( channelf_state::port_1_r )
uint8_t channelf_state::port_1_r()
{
uint8_t ext_value;
@ -66,7 +66,7 @@ READ8_MEMBER( channelf_state::port_1_r )
return port_read_with_latch(ext_value,m_latch[1]);
}
READ8_MEMBER( channelf_state::port_4_r )
uint8_t channelf_state::port_4_r()
{
uint8_t ext_value;
@ -78,12 +78,12 @@ READ8_MEMBER( channelf_state::port_4_r )
return port_read_with_latch(ext_value,m_latch[2]);
}
READ8_MEMBER( channelf_state::port_5_r )
uint8_t channelf_state::port_5_r()
{
return port_read_with_latch(0xff, m_latch[3]);
}
WRITE8_MEMBER( channelf_state::port_0_w )
void channelf_state::port_0_w(uint8_t data)
{
int offs;
@ -96,19 +96,19 @@ WRITE8_MEMBER( channelf_state::port_0_w )
}
}
WRITE8_MEMBER( channelf_state::port_1_w )
void channelf_state::port_1_w(uint8_t data)
{
m_latch[1] = data;
m_val_reg = ((data ^ 0xff) >> 6) & 0x03;
}
WRITE8_MEMBER( channelf_state::port_4_w )
void channelf_state::port_4_w(uint8_t data)
{
m_latch[2] = data;
m_col_reg = (data | 0x80) ^ 0xff;
}
WRITE8_MEMBER( channelf_state::port_5_w )
void channelf_state::port_5_w(uint8_t data)
{
m_latch[3] = data;
m_custom->sound_w((data>>6)&3);

14
src/mame/drivers/chqflag.cpp
View File

@ -35,7 +35,7 @@
/* these trampolines are less confusing than nested address_map_bank_devices */
template<int Chip>
READ8_MEMBER(chqflag_state::k051316_ramrom_r)
uint8_t chqflag_state::k051316_ramrom_r(offs_t offset)
{
if (m_k051316_readroms)
return m_k051316[Chip]->rom_r(offset);
@ -43,7 +43,7 @@ READ8_MEMBER(chqflag_state::k051316_ramrom_r)
return m_k051316[Chip]->read(offset);
}
WRITE8_MEMBER(chqflag_state::chqflag_bankswitch_w)
void chqflag_state::chqflag_bankswitch_w(uint8_t data)
{
/* bits 0-4 = ROM bank # (0x00-0x11) */
int bankaddress = data & 0x1f;
@ -56,7 +56,7 @@ WRITE8_MEMBER(chqflag_state::chqflag_bankswitch_w)
/* other bits unknown/unused */
}
WRITE8_MEMBER(chqflag_state::chqflag_vreg_w)
void chqflag_state::chqflag_vreg_w(uint8_t data)
{
/* bits 0 & 1 = coin counters */
machine().bookkeeping().coin_counter_w(1, data & 0x01);
@ -105,12 +105,12 @@ WRITE8_MEMBER(chqflag_state::chqflag_vreg_w)
/* other bits unknown. bit 5 is used. */
}
WRITE8_MEMBER(chqflag_state::select_analog_ctrl_w)
void chqflag_state::select_analog_ctrl_w(uint8_t data)
{
m_analog_ctrl = data;
}
READ8_MEMBER(chqflag_state::analog_read_r)
uint8_t chqflag_state::analog_read_r()
{
switch (m_analog_ctrl & 0x03)
{
@ -160,7 +160,7 @@ void chqflag_state::bank1000_map(address_map &map)
}
WRITE8_MEMBER(chqflag_state::k007232_bankswitch_w)
void chqflag_state::k007232_bankswitch_w(uint8_t data)
{
int bank_A, bank_B;
@ -262,7 +262,7 @@ void chqflag_state::volume_callback0(uint8_t data)
m_k007232[0]->set_volume(0, (data & 0x0f) * 0x11/2, (data >> 4) * 0x11/2);
}
WRITE8_MEMBER(chqflag_state::k007232_extvolume_w)
void chqflag_state::k007232_extvolume_w(uint8_t data)
{
// volume/pan for one of the channels on this chip
// which channel and which bits are left/right is a guess

26
src/mame/drivers/cinemat.cpp
View File

@ -84,13 +84,13 @@ void cinemat_state::machine_reset()
*
*************************************/
READ8_MEMBER(cinemat_state::inputs_r)
uint8_t cinemat_state::inputs_r(offs_t offset)
{
return (m_inputs->read() >> offset) & 1;
}
READ8_MEMBER(cinemat_state::switches_r)
uint8_t cinemat_state::switches_r(offs_t offset)
{
static const uint8_t switch_shuffle[8] = { 2,5,4,3,0,1,6,7 };
return (m_switches->read() >> switch_shuffle[offset]) & 1;
@ -112,7 +112,7 @@ INPUT_CHANGED_MEMBER(cinemat_state::coin_inserted)
}
READ8_MEMBER(cinemat_state::coin_input_r)
uint8_t cinemat_state::coin_input_r()
{
return !m_coin_detected;
}
@ -165,7 +165,7 @@ uint8_t cinemat_state::joystick_read()
*
*************************************/
READ8_MEMBER(cinemat_state::speedfrk_wheel_r)
uint8_t cinemat_state::speedfrk_wheel_r(offs_t offset)
{
static const uint8_t speedfrk_steer[] = {0xe, 0x6, 0x2, 0x0, 0x3, 0x7, 0xf};
int delta_wheel;
@ -181,7 +181,7 @@ READ8_MEMBER(cinemat_state::speedfrk_wheel_r)
}
READ8_MEMBER(cinemat_state::speedfrk_gear_r)
uint8_t cinemat_state::speedfrk_gear_r(offs_t offset)
{
int gearval = m_gear_input->read();
@ -232,7 +232,7 @@ static const struct
};
READ8_MEMBER(cinemat_16level_state::sundance_inputs_r)
uint8_t cinemat_16level_state::sundance_inputs_r(offs_t offset)
{
/* handle special keys first */
if (sundance_port_map[offset].portname)
@ -249,7 +249,7 @@ READ8_MEMBER(cinemat_16level_state::sundance_inputs_r)
*
*************************************/
READ8_MEMBER(cinemat_color_state::boxingb_dial_r)
uint8_t cinemat_color_state::boxingb_dial_r(offs_t offset)
{
int value = ioport("DIAL")->read();
if (!m_mux_select) offset += 4;
@ -264,7 +264,7 @@ READ8_MEMBER(cinemat_color_state::boxingb_dial_r)
*
*************************************/
READ8_MEMBER(qb3_state::qb3_frame_r)
uint8_t qb3_state::qb3_frame_r()
{
attotime next_update = m_screen->time_until_update();
attotime frame_period = m_screen->frame_period();
@ -275,7 +275,7 @@ READ8_MEMBER(qb3_state::qb3_frame_r)
}
WRITE8_MEMBER(qb3_state::qb3_ram_bank_w)
void qb3_state::qb3_ram_bank_w(uint8_t data)
{
membank("bank1")->set_entry(m_maincpu->state_int(ccpu_cpu_device::CCPU_P) & 3);
}
@ -1499,21 +1499,21 @@ ROM_END
void cinemat_state::init_speedfrk()
{
m_gear = 0xe;
m_maincpu->space(AS_IO).install_read_handler(0x00, 0x03, read8_delegate(*this, FUNC(cinemat_state::speedfrk_wheel_r)));
m_maincpu->space(AS_IO).install_read_handler(0x04, 0x06, read8_delegate(*this, FUNC(cinemat_state::speedfrk_gear_r)));
m_maincpu->space(AS_IO).install_read_handler(0x00, 0x03, read8sm_delegate(*this, FUNC(cinemat_state::speedfrk_wheel_r)));
m_maincpu->space(AS_IO).install_read_handler(0x04, 0x06, read8sm_delegate(*this, FUNC(cinemat_state::speedfrk_gear_r)));
save_item(NAME(m_gear));
}
void cinemat_16level_state::init_sundance()
{
m_maincpu->space(AS_IO).install_read_handler(0x00, 0x0f, read8_delegate(*this, FUNC(cinemat_16level_state::sundance_inputs_r)));
m_maincpu->space(AS_IO).install_read_handler(0x00, 0x0f, read8sm_delegate(*this, FUNC(cinemat_16level_state::sundance_inputs_r)));
}
void cinemat_color_state::init_boxingb()
{
m_maincpu->space(AS_IO).install_read_handler(0x0c, 0x0f, read8_delegate(*this, FUNC(cinemat_color_state::boxingb_dial_r)));
m_maincpu->space(AS_IO).install_read_handler(0x0c, 0x0f, read8sm_delegate(*this, FUNC(cinemat_color_state::boxingb_dial_r)));
}

10
src/mame/drivers/circusc.cpp
View File

@ -78,7 +78,7 @@ void circusc_state::machine_reset()
m_sn_latch = 0;
}
READ8_MEMBER(circusc_state::circusc_sh_timer_r)
uint8_t circusc_state::circusc_sh_timer_r()
{
/* This port reads the output of a counter clocked from the CPU clock.
* The CPU XTAL is 14.31818MHz divided by 4. It then goes through 10
@ -91,14 +91,12 @@ READ8_MEMBER(circusc_state::circusc_sh_timer_r)
* Can be shortened to:
*/
int clock;
clock = m_audiocpu->total_cycles() >> 9;
int clock = m_audiocpu->total_cycles() >> 9;
return clock & 0x1e;
}
WRITE8_MEMBER(circusc_state::circusc_sh_irqtrigger_w)
void circusc_state::circusc_sh_irqtrigger_w(uint8_t data)
{
m_audiocpu->set_input_line_and_vector(0, HOLD_LINE, 0xff); // Z80
}
@ -113,7 +111,7 @@ WRITE_LINE_MEMBER(circusc_state::coin_counter_2_w)
machine().bookkeeping().coin_counter_w(1, state);
}
WRITE8_MEMBER(circusc_state::circusc_sound_w)
void circusc_state::circusc_sound_w(offs_t offset, uint8_t data)
{
switch (offset & 7)
{

40
src/mame/drivers/cischeat.cpp
View File

@ -209,7 +209,7 @@ Cisco Heat.
Big Run
**************************************************************************/
WRITE16_MEMBER(cischeat_state::leds_out_w)
void cischeat_state::leds_out_w(offs_t offset, uint16_t data, uint16_t mem_mask)
{
// leds
if (ACCESSING_BITS_0_7)
@ -382,7 +382,7 @@ void cischeat_state::f1gpstar_map(address_map &map)
**************************************************************************/
// ad stick read select
READ16_MEMBER(cischeat_state::wildplt_xy_r)
uint16_t cischeat_state::wildplt_xy_r()
{
switch(m_ip_select)
{
@ -394,7 +394,7 @@ READ16_MEMBER(cischeat_state::wildplt_xy_r)
}
// buttons & sensors are muxed. bit 0 routes to coin chute (single according to test mode)
READ16_MEMBER(cischeat_state::wildplt_mux_r)
uint16_t cischeat_state::wildplt_mux_r()
{
uint16_t split_in = 0xffff;
switch(m_wildplt_output & 0xc)
@ -407,7 +407,7 @@ READ16_MEMBER(cischeat_state::wildplt_mux_r)
return split_in & ioport("IN1_COMMON")->read();
}
WRITE16_MEMBER(cischeat_state::wildplt_mux_w)
void cischeat_state::wildplt_mux_w(uint16_t data)
{
m_wildplt_output = data & 0xc;
}
@ -513,13 +513,13 @@ void cischeat_state::f1gpstr2_map(address_map &map)
---- ---- ---- --1- Up Limit
---- ---- ---- ---0 Down Limit */
READ16_MEMBER(cischeat_state::scudhamm_motor_status_r)
uint16_t cischeat_state::scudhamm_motor_status_r()
{
return m_scudhamm_motor_command; // Motor Status
}
READ16_MEMBER(cischeat_state::scudhamm_motor_pos_r)
uint16_t cischeat_state::scudhamm_motor_pos_r()
{
return 0x00 << 8;
}
@ -533,7 +533,7 @@ READ16_MEMBER(cischeat_state::scudhamm_motor_pos_r)
Within $20 vblanks the motor must reach the target. */
WRITE16_MEMBER(cischeat_state::scudhamm_motor_command_w)
void cischeat_state::scudhamm_motor_command_w(offs_t offset, uint16_t data, uint16_t mem_mask)
{
COMBINE_DATA( &m_scudhamm_motor_command );
}
@ -565,7 +565,7 @@ uint8_t cischeat_state::scudhamm_analog_r()
port (coins, tilt, buttons, select etc.) triggers the corresponding bit
in this word. I mapped the 3 buttons to the first 3 led.
*/
WRITE16_MEMBER(cischeat_state::scudhamm_leds_w)
void cischeat_state::scudhamm_leds_w(offs_t offset, uint16_t data, uint16_t mem_mask)
{
if (ACCESSING_BITS_8_15)
{
@ -587,12 +587,12 @@ WRITE16_MEMBER(cischeat_state::scudhamm_leds_w)
$FFFC during self test, $FFFF onwards.
It could be audio(L/R) or layers(0/2) enable.
*/
WRITE16_MEMBER(cischeat_state::scudhamm_enable_w)
void cischeat_state::scudhamm_enable_w(uint16_t data)
{
}
WRITE16_MEMBER(cischeat_state::scudhamm_oki_bank_w)
void cischeat_state::scudhamm_oki_bank_w(offs_t offset, uint16_t data, uint16_t mem_mask)
{
if (ACCESSING_BITS_0_7)
{
@ -628,12 +628,12 @@ void cischeat_state::scudhamm_map(address_map &map)
Arm Champs II
**************************************************************************/
READ16_MEMBER(armchamp2_state::motor_status_r)
uint16_t armchamp2_state::motor_status_r()
{
return 0x11;
}
WRITE16_MEMBER(armchamp2_state::motor_command_w)
void armchamp2_state::motor_command_w(offs_t offset, uint16_t data, uint16_t mem_mask)
{
// 0x00xx -> disable motor (test mode)
// 0x10ff -> automated test (test limits?)
@ -659,7 +659,7 @@ uint8_t armchamp2_state::analog_r()
---- ---- 76-- ---- Coin counters
---- ---- --54 3210
*/
WRITE16_MEMBER(armchamp2_state::output_w)
void armchamp2_state::output_w(offs_t offset, uint16_t data, uint16_t mem_mask)
{
if (ACCESSING_BITS_8_15)
{
@ -705,7 +705,7 @@ void armchamp2_state::armchmp2_map(address_map &map)
#define RIGHT 0
#define LEFT 1
WRITE16_MEMBER(captflag_state::leds_w)
void captflag_state::leds_w(offs_t offset, uint16_t data, uint16_t mem_mask)
{
COMBINE_DATA( &m_captflag_leds );
if (ACCESSING_BITS_8_15)
@ -722,7 +722,7 @@ WRITE16_MEMBER(captflag_state::leds_w)
}
}
WRITE16_MEMBER(captflag_state::oki_bank_w)
void captflag_state::oki_bank_w(offs_t offset, uint16_t data, uint16_t mem_mask)
{
if (ACCESSING_BITS_0_7)
{
@ -733,7 +733,7 @@ WRITE16_MEMBER(captflag_state::oki_bank_w)
// Motors
WRITE16_MEMBER(captflag_state::motor_command_right_w)
void captflag_state::motor_command_right_w(offs_t offset, uint16_t data, uint16_t mem_mask)
{
// Output check:
// e09a up
@ -743,7 +743,7 @@ WRITE16_MEMBER(captflag_state::motor_command_right_w)
data = COMBINE_DATA( &m_motor_command[RIGHT] );
motor_move(RIGHT, data);
}
WRITE16_MEMBER(captflag_state::motor_command_left_w)
void captflag_state::motor_command_left_w(offs_t offset, uint16_t data, uint16_t mem_mask)
{
// Output check:
// e0ba up
@ -953,7 +953,7 @@ void cischeat_state::f1gpstar_map3(address_map &map)
Big Run
**************************************************************************/
WRITE16_MEMBER(cischeat_state::bigrun_soundbank_w)
void cischeat_state::bigrun_soundbank_w(offs_t offset, uint16_t data, uint16_t mem_mask)
{
if (ACCESSING_BITS_0_7)
{
@ -978,12 +978,12 @@ void cischeat_state::bigrun_sound_map(address_map &map)
Cisco Heat
**************************************************************************/
WRITE16_MEMBER(cischeat_state::cischeat_soundbank_1_w)
void cischeat_state::cischeat_soundbank_1_w(offs_t offset, uint16_t data, uint16_t mem_mask)
{
if (ACCESSING_BITS_0_7) m_oki1->set_rom_bank(data & 1);
}
WRITE16_MEMBER(cischeat_state::cischeat_soundbank_2_w)
void cischeat_state::cischeat_soundbank_2_w(offs_t offset, uint16_t data, uint16_t mem_mask)
{
if (ACCESSING_BITS_0_7) m_oki2->set_rom_bank(data & 1);
}

4
src/mame/drivers/citycon.cpp
View File

@ -31,12 +31,12 @@ Dip locations added from dip listing at crazykong.com
#define VBEND (16)
#define VBSTART (240)
READ8_MEMBER(citycon_state::citycon_in_r)
uint8_t citycon_state::citycon_in_r()
{
return ioport(flip_screen() ? "P2" : "P1")->read();
}
READ8_MEMBER(citycon_state::citycon_irq_ack_r)
uint8_t citycon_state::citycon_irq_ack_r()
{
m_maincpu->set_input_line(0, CLEAR_LINE);

44
src/mame/drivers/clcd.cpp
View File

@ -149,7 +149,7 @@ public:
return 0;
}
READ8_MEMBER(ram_r)
uint8_t ram_r(offs_t offset)
{
if (offset < m_ram->size())
{
@ -159,7 +159,7 @@ public:
return 0xff;
}
WRITE8_MEMBER(ram_w)
void ram_w(offs_t offset, uint8_t data)
{
if (offset < m_ram->size())
{
@ -265,37 +265,37 @@ public:
}
}
WRITE8_MEMBER(mmu_mode_kern_w)
void mmu_mode_kern_w(uint8_t data)
{
update_mmu_mode(MMU_MODE_KERN);
}
WRITE8_MEMBER(mmu_mode_appl_w)
void mmu_mode_appl_w(uint8_t data)
{
update_mmu_mode(MMU_MODE_APPL);
}
WRITE8_MEMBER(mmu_mode_ram_w)
void mmu_mode_ram_w(uint8_t data)
{
update_mmu_mode(MMU_MODE_RAM);
}
WRITE8_MEMBER(mmu_mode_recall_w)
void mmu_mode_recall_w(uint8_t data)
{
update_mmu_mode(m_mmu_saved_mode);
}
WRITE8_MEMBER(mmu_mode_save_w)
void mmu_mode_save_w(uint8_t data)
{
m_mmu_saved_mode = m_mmu_mode;
}
WRITE8_MEMBER(mmu_mode_test_w)
void mmu_mode_test_w(uint8_t data)
{
update_mmu_mode(MMU_MODE_TEST);
}
WRITE8_MEMBER(mmu_offset1_w)
void mmu_offset1_w(uint8_t data)
{
if (m_mmu_offset1 != data)
{
@ -304,7 +304,7 @@ public:
}
}
WRITE8_MEMBER(mmu_offset2_w)
void mmu_offset2_w(uint8_t data)
{
if (m_mmu_offset2 != data)
{
@ -313,7 +313,7 @@ public:
}
}
WRITE8_MEMBER(mmu_offset3_w)
void mmu_offset3_w(uint8_t data)
{
if (m_mmu_offset3 != data)
{
@ -322,7 +322,7 @@ public:
}
}
WRITE8_MEMBER(mmu_offset4_w)
void mmu_offset4_w(uint8_t data)
{
if (m_mmu_offset4 != data)
{
@ -331,7 +331,7 @@ public:
}
}
WRITE8_MEMBER(mmu_offset5_w)
void mmu_offset5_w(uint8_t data)
{
if (m_mmu_offset5 != data)
{
@ -340,47 +340,47 @@ public:
}
}
READ8_MEMBER(mmu_offset1_r)
uint8_t mmu_offset1_r()
{
return m_mmu_offset1;
}
READ8_MEMBER(mmu_offset2_r)
uint8_t mmu_offset2_r()
{
return m_mmu_offset2;
}
READ8_MEMBER(mmu_offset3_r)
uint8_t mmu_offset3_r()
{
return m_mmu_offset3;
}
READ8_MEMBER(mmu_offset4_r)
uint8_t mmu_offset4_r()
{
return m_mmu_offset4;
}
READ8_MEMBER(mmu_offset5_r)
uint8_t mmu_offset5_r()
{
return m_mmu_offset5;
}
WRITE8_MEMBER(lcd_scrollx_w)
void lcd_scrollx_w(uint8_t data)
{
m_lcd_scrollx = data;
}
WRITE8_MEMBER(lcd_scrolly_w)
void lcd_scrolly_w(uint8_t data)
{
m_lcd_scrolly = data;
}
WRITE8_MEMBER(lcd_mode_w)
void lcd_mode_w(uint8_t data)
{
m_lcd_mode = data;
}
WRITE8_MEMBER(lcd_size_w)
void lcd_size_w(uint8_t data)
{
m_lcd_size = data;
}

8
src/mame/drivers/cloak.cpp
View File

@ -144,21 +144,21 @@ WRITE_LINE_MEMBER(cloak_state::coin_counter_r_w)
machine().bookkeeping().coin_counter_w(1, state);
}
WRITE8_MEMBER(cloak_state::cloak_custom_w)
void cloak_state::cloak_custom_w(uint8_t data)
{
}
WRITE8_MEMBER(cloak_state::cloak_irq_reset_0_w)
void cloak_state::cloak_irq_reset_0_w(uint8_t data)
{
m_maincpu->set_input_line(0, CLEAR_LINE);
}
WRITE8_MEMBER(cloak_state::cloak_irq_reset_1_w)
void cloak_state::cloak_irq_reset_1_w(uint8_t data)
{
m_slave->set_input_line(0, CLEAR_LINE);
}
WRITE8_MEMBER(cloak_state::cloak_nvram_enable_w)
void cloak_state::cloak_nvram_enable_w(uint8_t data)
{
m_nvram_enabled = data & 0x01;
}

8
src/mame/drivers/cloud9.cpp
View File

@ -206,7 +206,7 @@ void cloud9_state::machine_reset()
*
*************************************/
WRITE8_MEMBER(cloud9_state::irq_ack_w)
void cloud9_state::irq_ack_w(uint8_t data)
{
if (m_irq_state)
{
@ -216,7 +216,7 @@ WRITE8_MEMBER(cloud9_state::irq_ack_w)
}
READ8_MEMBER(cloud9_state::leta_r)
uint8_t cloud9_state::leta_r(offs_t offset)
{
return ioport(offset ? "TRACKX" : "TRACKY")->read();
}
@ -229,7 +229,7 @@ READ8_MEMBER(cloud9_state::leta_r)
*
*************************************/
WRITE8_MEMBER(cloud9_state::nvram_recall_w)
void cloud9_state::nvram_recall_w(uint8_t data)
{
m_nvram->recall(0);
m_nvram->recall(1);
@ -237,7 +237,7 @@ WRITE8_MEMBER(cloud9_state::nvram_recall_w)
}
WRITE8_MEMBER(cloud9_state::nvram_store_w)
void cloud9_state::nvram_store_w(uint8_t data)
{
m_nvram->store(0);
m_nvram->store(1);

2
src/mame/drivers/clshroad.cpp
View File

@ -55,7 +55,7 @@ void clshroad_state::machine_reset()
}
READ8_MEMBER(clshroad_state::input_r)
uint8_t clshroad_state::input_r(offs_t offset)
{
return ((~ioport("P1")->read() & (1 << offset)) ? 1 : 0) |
((~ioport("P2")->read() & (1 << offset)) ? 2 : 0) |

26
src/mame/drivers/cninja.cpp
View File

@ -56,14 +56,14 @@ Note about version levels using Mutant Fighter as the example:
/**********************************************************************************/
template<int Chip>
WRITE16_MEMBER(cninja_state::cninja_pf_control_w)
void cninja_state::cninja_pf_control_w(offs_t offset, uint16_t data, uint16_t mem_mask)
{
m_screen->update_partial(m_screen->vpos());
m_deco_tilegen[Chip]->pf_control_w(offset, data, mem_mask);
}
READ16_MEMBER( cninja_state::cninja_protection_region_0_104_r )
uint16_t cninja_state::cninja_protection_region_0_104_r(offs_t offset)
{
int real_address = 0 + (offset *2);
int deco146_addr = bitswap<32>(real_address, /* NC */31,30,29,28,27,26,25,24,23,22,21,20,19,18, 13,12,11,/**/ 17,16,15,14, 10,9,8, 7,6,5,4, 3,2,1,0) & 0x7fff;
@ -72,7 +72,7 @@ READ16_MEMBER( cninja_state::cninja_protection_region_0_104_r )
return data;
}
WRITE16_MEMBER( cninja_state::cninja_protection_region_0_104_w )
void cninja_state::cninja_protection_region_0_104_w(offs_t offset, uint16_t data, uint16_t mem_mask)
{
int real_address = 0 + (offset *2);
int deco146_addr = bitswap<32>(real_address, /* NC */31,30,29,28,27,26,25,24,23,22,21,20,19,18, 13,12,11,/**/ 17,16,15,14, 10,9,8, 7,6,5,4, 3,2,1,0) & 0x7fff;
@ -80,7 +80,7 @@ WRITE16_MEMBER( cninja_state::cninja_protection_region_0_104_w )
m_ioprot->write_data( deco146_addr, data, mem_mask, cs );
}
READ16_MEMBER(cninja_state::cninjabl2_sprite_dma_r)
uint16_t cninja_state::cninjabl2_sprite_dma_r()
{
m_spriteram[0]->copy();
return 0;
@ -145,7 +145,7 @@ void cninja_state::cninjabl_map(address_map &map)
map(0x1b4000, 0x1b4001).w(m_spriteram[0], FUNC(buffered_spriteram16_device::write)); /* DMA flag */
}
READ16_MEMBER( cninja_state::edrandy_protection_region_8_146_r )
uint16_t cninja_state::edrandy_protection_region_8_146_r(offs_t offset)
{
int real_address = 0x1a0000 + (offset *2);
int deco146_addr = bitswap<32>(real_address, /* NC */31,30,29,28,27,26,25,24,23,22,21,20,19,18, 13,12,11,/**/ 17,16,15,14, 10,9,8, 7,6,5,4, 3,2,1,0) & 0x7fff;
@ -154,7 +154,7 @@ READ16_MEMBER( cninja_state::edrandy_protection_region_8_146_r )
return data;
}
WRITE16_MEMBER( cninja_state::edrandy_protection_region_8_146_w )
void cninja_state::edrandy_protection_region_8_146_w(offs_t offset, uint16_t data, uint16_t mem_mask)
{
int real_address = 0x1a0000 + (offset *2);
int deco146_addr = bitswap<32>(real_address, /* NC */31,30,29,28,27,26,25,24,23,22,21,20,19,18, 13,12,11,/**/ 17,16,15,14, 10,9,8, 7,6,5,4, 3,2,1,0) & 0x7fff;
@ -162,7 +162,7 @@ WRITE16_MEMBER( cninja_state::edrandy_protection_region_8_146_w )
m_ioprot->write_data( deco146_addr, data, mem_mask, cs );
}
READ16_MEMBER( cninja_state::edrandy_protection_region_6_146_r )
uint16_t cninja_state::edrandy_protection_region_6_146_r(offs_t offset)
{
// uint16_t realdat = deco16_60_prot_r(space,offset&0x3ff,mem_mask);
@ -178,7 +178,7 @@ READ16_MEMBER( cninja_state::edrandy_protection_region_6_146_r )
return data;
}
WRITE16_MEMBER( cninja_state::edrandy_protection_region_6_146_w )
void cninja_state::edrandy_protection_region_6_146_w(offs_t offset, uint16_t data, uint16_t mem_mask)
{
// deco16_60_prot_w(space,offset&0x3ff,data,mem_mask);
@ -218,7 +218,7 @@ void cninja_state::edrandy_map(address_map &map)
map(0x1bc800, 0x1bcfff).nopw(); /* Another bug in game code? Sprite list can overrun. Doesn't seem to mirror */
}
WRITE16_MEMBER(cninja_state::robocop2_priority_w)
void cninja_state::robocop2_priority_w(offs_t offset, uint16_t data, uint16_t mem_mask)
{
COMBINE_DATA(&m_priority);
}
@ -254,7 +254,7 @@ void cninja_state::robocop2_map(address_map &map)
}
READ16_MEMBER( cninja_state::mutantf_protection_region_0_146_r )
uint16_t cninja_state::mutantf_protection_region_0_146_r(offs_t offset)
{
int real_address = 0 + (offset *2);
int deco146_addr = bitswap<32>(real_address, /* NC */31,30,29,28,27,26,25,24,23,22,21,20,19,18, 13,12,11,/**/ 17,16,15,14, 10,9,8, 7,6,5,4, 3,2,1,0) & 0x7fff;
@ -263,7 +263,7 @@ READ16_MEMBER( cninja_state::mutantf_protection_region_0_146_r )
return data;
}
WRITE16_MEMBER( cninja_state::mutantf_protection_region_0_146_w )
void cninja_state::mutantf_protection_region_0_146_w(offs_t offset, uint16_t data, uint16_t mem_mask)
{
int real_address = 0 + (offset *2);
int deco146_addr = bitswap<32>(real_address, /* NC */31,30,29,28,27,26,25,24,23,22,21,20,19,18, 13,12,11,/**/ 17,16,15,14, 10,9,8, 7,6,5,4, 3,2,1,0) & 0x7fff;
@ -271,7 +271,7 @@ WRITE16_MEMBER( cninja_state::mutantf_protection_region_0_146_w )
m_ioprot->write_data( deco146_addr, data, mem_mask, cs );
}
READ16_MEMBER( cninja_state::mutantf_71_r )
uint16_t cninja_state::mutantf_71_r()
{
return 0xffff; // todo
}
@ -2170,7 +2170,7 @@ ROM_END
void cninja_state::init_cninjabl2()
{
m_maincpu->space(AS_PROGRAM).install_ram(0x180000, 0x18ffff);
m_maincpu->space(AS_PROGRAM).install_read_handler(0x1b4000, 0x1b4001, read16_delegate(*this, FUNC(cninja_state::cninjabl2_sprite_dma_r)));
m_maincpu->space(AS_PROGRAM).install_read_handler(0x1b4000, 0x1b4001, read16smo_delegate(*this, FUNC(cninja_state::cninjabl2_sprite_dma_r)));
m_okibank->configure_entries(0, 8, memregion("oki2")->base(), 0x10000);
}

4
src/mame/drivers/coinmvga.cpp
View File

@ -301,13 +301,13 @@ uint32_t coinmvga_state::screen_update_coinmvga(screen_device &screen, bitmap_in
* Read / Write Handlers *
**************************/
//WRITE8_MEMBER(coinmvga_state::debug_w)
//void coinmvga_state::debug_w(uint8_t data)
//{
// popmessage("written : %02X", data);
//}
/*
READ16_MEMBER(coinmvga_state::test_r)
uint16_t coinmvga_state::test_r()
{
return machine().rand();
}*/

20
src/mame/drivers/coleco.cpp
View File

@ -77,27 +77,27 @@
/* Read/Write Handlers */
READ8_MEMBER( coleco_state::paddle_1_r )
uint8_t coleco_state::paddle_1_r()
{
return m_joy_d7_state[0] | coleco_paddle_read(0, m_joy_mode, m_joy_analog_state[0]);
}
READ8_MEMBER( coleco_state::paddle_2_r )
uint8_t coleco_state::paddle_2_r()
{
return m_joy_d7_state[1] | coleco_paddle_read(1, m_joy_mode, m_joy_analog_state[1]);
}
WRITE8_MEMBER( coleco_state::paddle_off_w )
void coleco_state::paddle_off_w(uint8_t data)
{
m_joy_mode = 0;
}
WRITE8_MEMBER( coleco_state::paddle_on_w )
void coleco_state::paddle_on_w(uint8_t data)
{
m_joy_mode = 1;
}
READ8_MEMBER( bit90_state::bankswitch_u4_r )
uint8_t bit90_state::bankswitch_u4_r(address_space &space)
{
if (!machine().side_effects_disabled()) {
LOG("Bankswitch to u4\n");
@ -106,7 +106,7 @@ READ8_MEMBER( bit90_state::bankswitch_u4_r )
return space.unmap();
}
READ8_MEMBER( bit90_state::bankswitch_u3_r )
uint8_t bit90_state::bankswitch_u3_r(address_space &space)
{
if (!machine().side_effects_disabled()) {
LOG("Bankswitch to u3\n");
@ -115,7 +115,7 @@ READ8_MEMBER( bit90_state::bankswitch_u3_r )
return space.unmap();
}
READ8_MEMBER( bit90_state::keyboard_r )
uint8_t bit90_state::keyboard_r(address_space &space)
{
if (m_keyselect < 8) {
return m_io_keyboard[m_keyselect]->read();
@ -123,7 +123,7 @@ READ8_MEMBER( bit90_state::keyboard_r )
return space.unmap();
}
WRITE8_MEMBER( bit90_state::u32_w )
void bit90_state::u32_w(uint8_t data)
{
// Write to a 74LS174 at u32
// Bits 4-7 are connected for keyboard scanning (actually only 4-6 are used)
@ -392,7 +392,7 @@ TIMER_DEVICE_CALLBACK_MEMBER(coleco_state::paddle_update_callback)
}
}
READ8_MEMBER( coleco_state::cart_r )
uint8_t coleco_state::cart_r(offs_t offset)
{
return m_cart->bd_r(offset & 0x7fff, 0, 0, 0, 0, 0);
}
@ -505,7 +505,7 @@ void coleco_state::machine_start()
}
if (m_cart->exists())
m_maincpu->space(AS_PROGRAM).install_read_handler(0x8000, 0xffff, read8_delegate(*this, FUNC(coleco_state::cart_r)));
m_maincpu->space(AS_PROGRAM).install_read_handler(0x8000, 0xffff, read8sm_delegate(*this, FUNC(coleco_state::cart_r)));
save_item(NAME(m_joy_mode));
save_item(NAME(m_last_nmi_state));

51
src/mame/drivers/combatsc.cpp
View File

@ -136,7 +136,7 @@ Dip location and recommended settings verified with the US manual
*
*************************************/
WRITE8_MEMBER(combatsc_state::combatsc_vreg_w)
void combatsc_state::combatsc_vreg_w(uint8_t data)
{
if (data != m_vreg)
{
@ -149,14 +149,14 @@ WRITE8_MEMBER(combatsc_state::combatsc_vreg_w)
}
}
READ8_MEMBER(combatsc_state::combatscb_io_r)
uint8_t combatsc_state::combatscb_io_r(offs_t offset)
{
static const char *const portnames[] = { "IN0", "IN1", "DSW1", "DSW2" };
return ioport(portnames[offset])->read();
}
WRITE8_MEMBER(combatsc_state::combatscb_priority_w)
void combatsc_state::combatscb_priority_w(uint8_t data)
{
if (data & 0x40)
{
@ -174,7 +174,7 @@ WRITE8_MEMBER(combatsc_state::combatscb_priority_w)
m_priority = data & 0x20;
}
WRITE8_MEMBER(combatsc_state::combatsc_bankselect_w)
void combatsc_state::combatsc_bankselect_w(uint8_t data)
{
m_priority = data & 0x20;
@ -197,18 +197,18 @@ WRITE8_MEMBER(combatsc_state::combatsc_bankselect_w)
membank("bank1")->set_entry(8 + (data & 1));
}
WRITE8_MEMBER(combatsc_state::combatscb_io_w)
void combatsc_state::combatscb_io_w(offs_t offset, uint8_t data)
{
switch (offset)
{
case 0x400: combatscb_priority_w(space, 0, data); break;
case 0x400: combatscb_priority_w(data); break;
case 0x800: m_soundlatch->write(data); break;
case 0xc00: combatsc_vreg_w(space, 0, data); break;
case 0xc00: combatsc_vreg_w(data); break;
default: m_io_ram[offset] = data; break;
}
}
WRITE8_MEMBER(combatsc_state::combatscb_bankselect_w)
void combatsc_state::combatscb_bankselect_w(address_space &space, uint8_t data)
{
if (data & 0x40)
{
@ -235,8 +235,8 @@ WRITE8_MEMBER(combatsc_state::combatscb_bankselect_w)
if (data == 0x1f)
{
membank("bank1")->set_entry(8 + (data & 1));
space.install_write_handler(0x4000, 0x7fff, write8_delegate(*this, FUNC(combatsc_state::combatscb_io_w)));
space.install_read_handler(0x4400, 0x4403, read8_delegate(*this, FUNC(combatsc_state::combatscb_io_r))); // IO RAM & Video Registers
space.install_write_handler(0x4000, 0x7fff, write8sm_delegate(*this, FUNC(combatsc_state::combatscb_io_w)));
space.install_read_handler(0x4400, 0x4403, read8sm_delegate(*this, FUNC(combatsc_state::combatscb_io_r))); // IO RAM & Video Registers
}
else
{
@ -248,7 +248,7 @@ WRITE8_MEMBER(combatsc_state::combatscb_bankselect_w)
/****************************************************************************/
WRITE8_MEMBER(combatsc_state::combatsc_coin_counter_w)
void combatsc_state::combatsc_coin_counter_w(uint8_t data)
{
/* b7-b3: unused? */
/* b1: coin counter 2 */
@ -258,7 +258,7 @@ WRITE8_MEMBER(combatsc_state::combatsc_coin_counter_w)
machine().bookkeeping().coin_counter_w(1, data & 0x02);
}
READ8_MEMBER(combatsc_state::trackball_r)
uint8_t combatsc_state::trackball_r(offs_t offset)
{
if (offset == 0)
{
@ -293,15 +293,15 @@ READ8_MEMBER(combatsc_state::trackball_r)
/* the protection is a simple multiply */
WRITE8_MEMBER(combatsc_state::protection_w)
void combatsc_state::protection_w(offs_t offset, uint8_t data)
{
m_prot[offset] = data;
}
READ8_MEMBER(combatsc_state::protection_r)
uint8_t combatsc_state::protection_r(offs_t offset)
{
return ((m_prot[0] * m_prot[1]) >> (offset * 8)) & 0xff;
}
WRITE8_MEMBER(combatsc_state::protection_clock_w)
void combatsc_state::protection_clock_w(uint8_t data)
{
/* 0x3f is written here every time before accessing the other registers */
}
@ -309,22 +309,22 @@ WRITE8_MEMBER(combatsc_state::protection_clock_w)
/****************************************************************************/
WRITE8_MEMBER(combatsc_state::combatsc_sh_irqtrigger_w)
void combatsc_state::combatsc_sh_irqtrigger_w(uint8_t data)
{
m_audiocpu->set_input_line_and_vector(0, HOLD_LINE, 0xff); // Z80
}
READ8_MEMBER(combatsc_state::combatsc_busy_r)
uint8_t combatsc_state::combatsc_busy_r()
{
return m_upd7759->busy_r() ? 1 : 0;
}
WRITE8_MEMBER(combatsc_state::combatsc_play_w)
void combatsc_state::combatsc_play_w(uint8_t data)
{
m_upd7759->start_w(data & 2);
}
WRITE8_MEMBER(combatsc_state::combatsc_voice_reset_w)
void combatsc_state::combatsc_voice_reset_w(uint8_t data)
{
m_upd7759->reset_w(data & 1);
}
@ -335,7 +335,7 @@ void combatsc_state::combatsc_portA_w(uint8_t data)
}
// causes scores to disappear during fire ranges, either sprite busy flag or screen frame number related
READ8_MEMBER(combatsc_state::unk_r)
uint8_t combatsc_state::unk_r()
{
return 0; //m_screen->frame_number() & 1;
}
@ -400,7 +400,7 @@ void combatsc_state::combatsc_sound_map(address_map &map)
map(0xe000, 0xe001).rw("ymsnd", FUNC(ym2203_device::read), FUNC(ym2203_device::write)); /* YM 2203 intercepted */
}
WRITE8_MEMBER(combatsc_state::combatscb_msm_w)
void combatsc_state::combatscb_msm_w(uint8_t data)
{
membank("bl_abank")->set_entry(BIT(data, 7));
@ -408,7 +408,7 @@ WRITE8_MEMBER(combatsc_state::combatscb_msm_w)
m_msm->data_w(data & 0x0f);
}
WRITE8_MEMBER(combatsc_state::combatscb_sound_irq_ack)
void combatsc_state::combatscb_sound_irq_ack(uint8_t data)
{
m_audiocpu->set_input_line(0, CLEAR_LINE);
}
@ -677,9 +677,6 @@ MACHINE_START_MEMBER(combatsc_state,combatscb)
void combatsc_state::machine_reset()
{
address_space &space = m_maincpu->space(AS_PROGRAM);
int i;
memset(m_io_ram, 0x00, 0x4000);
memset(m_page[0], 0x00, 0x2000);
memset(m_page[1], 0x00, 0x2000);
@ -690,13 +687,13 @@ void combatsc_state::machine_reset()
m_prot[0] = 0;
m_prot[1] = 0;
for (i = 0; i < 4; i++)
for (int i = 0; i < 4; i++)
{
m_pos[i] = 0;
m_sign[i] = 0;
}
combatsc_bankselect_w(space, 0, 0);
combatsc_bankselect_w(0);
}
/* combat school (original) */

4
src/mame/drivers/comquest.cpp
View File

@ -50,14 +50,14 @@ icq3250a-d
#ifdef UNUSED_FUNCTION
READ8_MEMBER(comquest_state::comquest_read)
uint8_t comquest_state::comquest_read(offs_t offset)
{
uint8_t data=0;
logerror("comquest read %.4x %.2x\n",offset,data);
return data;
}
WRITE8_MEMBER(comquest_state::comquest_write)
void comquest_state::comquest_write(offs_t offset, uint8_t data)
{
logerror("comquest read %.4x %.2x\n",offset,data);
}

10
src/mame/drivers/comx35.cpp
View File

@ -210,7 +210,7 @@ QUICKLOAD_LOAD_MEMBER(comx35_state::quickload_cb)
// mem_r - memory read
//-------------------------------------------------
READ8_MEMBER( comx35_state::mem_r )
uint8_t comx35_state::mem_r(offs_t offset)
{
int extrom = 1;
@ -237,7 +237,7 @@ READ8_MEMBER( comx35_state::mem_r )
// mem_w - memory write
//-------------------------------------------------
WRITE8_MEMBER( comx35_state::mem_w )
void comx35_state::mem_w(offs_t offset, uint8_t data)
{
m_exp->mwr_w(offset, data);
@ -260,7 +260,7 @@ WRITE8_MEMBER( comx35_state::mem_w )
// io_r - I/O read
//-------------------------------------------------
READ8_MEMBER( comx35_state::io_r )
uint8_t comx35_state::io_r(offs_t offset)
{
uint8_t data = m_exp->io_r(offset);
@ -277,13 +277,13 @@ READ8_MEMBER( comx35_state::io_r )
// io_w - I/O write
//-------------------------------------------------
WRITE8_MEMBER( comx35_state::io_w )
void comx35_state::io_w(offs_t offset, uint8_t data)
{
m_exp->io_w(offset, data);
if (offset >= 3)
{
cdp1869_w(space, offset, data);
cdp1869_w(offset, data);
}
}

8
src/mame/drivers/contra.cpp
View File

@ -35,22 +35,22 @@ INTERRUPT_GEN_MEMBER(contra_state::contra_interrupt)
device.execute().set_input_line(HD6309_IRQ_LINE, HOLD_LINE);
}
WRITE8_MEMBER(contra_state::contra_bankswitch_w)
void contra_state::contra_bankswitch_w(uint8_t data)
{
membank("bank1")->set_entry(data & 0x0f);
}
WRITE8_MEMBER(contra_state::contra_sh_irqtrigger_w)
void contra_state::contra_sh_irqtrigger_w(uint8_t data)
{
m_audiocpu->set_input_line(M6809_IRQ_LINE, ASSERT_LINE);
}
WRITE8_MEMBER(contra_state::sirq_clear_w)
void contra_state::sirq_clear_w(uint8_t data)
{
m_audiocpu->set_input_line(M6809_IRQ_LINE, CLEAR_LINE);
}
WRITE8_MEMBER(contra_state::contra_coin_counter_w)
void contra_state::contra_coin_counter_w(uint8_t data)
{
if (data & 0x01)
machine().bookkeeping().coin_counter_w(0, data & 0x01);

22
src/mame/drivers/coolpool.cpp
View File

@ -156,7 +156,7 @@ TIMER_DEVICE_CALLBACK_MEMBER(coolpool_state::nvram_write_timeout)
}
WRITE16_MEMBER(coolpool_state::nvram_thrash_w)
void coolpool_state::nvram_thrash_w(offs_t offset, uint16_t data)
{
/* keep track of the last few writes */
memmove(&m_nvram_write_seq[0], &m_nvram_write_seq[1], (NVRAM_UNLOCK_SEQ_LEN - 1) * sizeof(m_nvram_write_seq[0]));
@ -171,7 +171,7 @@ WRITE16_MEMBER(coolpool_state::nvram_thrash_w)
}
WRITE16_MEMBER(coolpool_state::nvram_data_w)
void coolpool_state::nvram_data_w(offs_t offset, uint16_t data, uint16_t mem_mask)
{
/* only the low 8 bits matter */
if (ACCESSING_BITS_0_7)
@ -184,10 +184,10 @@ WRITE16_MEMBER(coolpool_state::nvram_data_w)
}
WRITE16_MEMBER(coolpool_state::nvram_thrash_data_w)
void coolpool_state::nvram_thrash_data_w(offs_t offset, uint16_t data, uint16_t mem_mask)
{
nvram_data_w(space, offset, data, mem_mask);
nvram_thrash_w(space, offset, data, mem_mask);
nvram_data_w(offset, data, mem_mask);
nvram_thrash_w(offset, data);
}
@ -205,7 +205,7 @@ TIMER_DEVICE_CALLBACK_MEMBER(coolpool_state::amerdart_audio_int_gen)
}
WRITE16_MEMBER(coolpool_state::amerdart_misc_w)
void coolpool_state::amerdart_misc_w(uint16_t data)
{
logerror("%08x:IOP_system_w %04x\n",m_maincpu->pc(),data);
@ -317,7 +317,7 @@ int coolpool_state::amerdart_trackball_direction(int num, int data)
}
READ16_MEMBER(coolpool_state::amerdart_trackball_r)
uint16_t coolpool_state::amerdart_trackball_r(offs_t offset)
{
/*
Trackballs seem to be handled as though they're rotated 45 degrees anti-clockwise.
@ -389,7 +389,7 @@ READ16_MEMBER(coolpool_state::amerdart_trackball_r)
*
*************************************/
WRITE16_MEMBER(coolpool_state::coolpool_misc_w)
void coolpool_state::coolpool_misc_w(uint16_t data)
{
logerror("%08x:IOP_system_w %04x\n",m_maincpu->pc(),data);
@ -426,13 +426,13 @@ uint16_t coolpool_state::dsp_hold_line_r()
*
*************************************/
READ16_MEMBER(coolpool_state::dsp_rom_r)
uint16_t coolpool_state::dsp_rom_r()
{
return m_dsp_rom[m_iop_romaddr & (m_dsp_rom.mask())];
}
WRITE16_MEMBER(coolpool_state::dsp_romaddr_w)
void coolpool_state::dsp_romaddr_w(offs_t offset, uint16_t data)
{
switch (offset)
{
@ -454,7 +454,7 @@ WRITE16_MEMBER(coolpool_state::dsp_romaddr_w)
*
*************************************/
READ16_MEMBER(coolpool_state::coolpool_input_r)
uint16_t coolpool_state::coolpool_input_r(offs_t offset)
{
m_result = (ioport("IN1")->read() & 0x00ff) | (m_lastresult & 0xff00);
m_newx[1] = ioport("XAXIS")->read();

8
src/mame/drivers/cop01.cpp
View File

@ -78,13 +78,13 @@ Mighty Guy board layout:
*
*************************************/
WRITE8_MEMBER(cop01_state::cop01_sound_command_w)
void cop01_state::cop01_sound_command_w(uint8_t data)
{
m_soundlatch->write(data);
m_audiocpu->set_input_line(0, ASSERT_LINE);
}
READ8_MEMBER(cop01_state::cop01_sound_command_r)
uint8_t cop01_state::cop01_sound_command_r()
{
int res = (m_soundlatch->read() & 0x7f) << 1;
@ -109,12 +109,12 @@ READ_LINE_MEMBER(cop01_state::mightguy_area_r)
return (ioport("FAKE")->read() & Mask) ? 1 : 0;
}
WRITE8_MEMBER(cop01_state::cop01_irq_ack_w)
void cop01_state::cop01_irq_ack_w(uint8_t data)
{
m_maincpu->set_input_line(0, CLEAR_LINE );
}
READ8_MEMBER(cop01_state::cop01_sound_irq_ack_w)
uint8_t cop01_state::cop01_sound_irq_ack_w()
{
m_audiocpu->set_input_line(0, CLEAR_LINE );
return 0;

4
src/mame/drivers/copsnrob.cpp
View File

@ -70,12 +70,12 @@ Added Dip locations according to manual.
*
*************************************/
READ8_MEMBER(copsnrob_state::copsnrob_misc_r)
uint8_t copsnrob_state::copsnrob_misc_r()
{
return m_screen->vblank() ? 0x00 : 0x80;
}
WRITE8_MEMBER(copsnrob_state::copsnrob_misc2_w)
void copsnrob_state::copsnrob_misc2_w(uint8_t data)
{
m_misc = data & 0x7f;
/* Multi Player Start */

30
src/mame/drivers/cosmic.cpp
View File

@ -46,7 +46,7 @@ cosmicg - board can operate in b&w mode if there is no PROM, in this case
/* Schematics show 12 triggers for discrete sound circuits */
WRITE8_MEMBER(cosmic_state::panic_sound_output_w)
void cosmic_state::panic_sound_output_w(offs_t offset, uint8_t data)
{
/* Sound Enable / Disable */
if (offset == 11)
@ -112,7 +112,7 @@ WRITE8_MEMBER(cosmic_state::panic_sound_output_w)
#endif
}
WRITE8_MEMBER(cosmic_state::panic_sound_output2_w)
void cosmic_state::panic_sound_output2_w(offs_t offset, uint8_t data)
{
if (m_sound_enabled)
{
@ -128,7 +128,7 @@ WRITE8_MEMBER(cosmic_state::panic_sound_output2_w)
#endif
}
WRITE8_MEMBER(cosmic_state::cosmicg_output_w)
void cosmic_state::cosmicg_output_w(offs_t offset, uint8_t data)
{
/* Sound Enable / Disable */
if (offset == 12)
@ -190,7 +190,7 @@ WRITE8_MEMBER(cosmic_state::cosmicg_output_w)
}
WRITE8_MEMBER(cosmic_state::cosmica_sound_output_w)
void cosmic_state::cosmica_sound_output_w(offs_t offset, uint8_t data)
{
/* Sound Enable / Disable */
if (offset == 11)
@ -327,17 +327,17 @@ WRITE8_MEMBER(cosmic_state::cosmica_sound_output_w)
#endif
}
WRITE8_MEMBER(cosmic_state::dac_w)
void cosmic_state::dac_w(uint8_t data)
{
m_dac->write(BIT(data, 7));
}
READ8_MEMBER(cosmic_state::cosmica_pixel_clock_r)
uint8_t cosmic_state::cosmica_pixel_clock_r()
{
return (m_screen->vpos() >> 2) & 0x3f;
}
READ8_MEMBER(cosmic_state::cosmicg_port_0_r)
uint8_t cosmic_state::cosmicg_port_0_r(offs_t offset)
{
/* The top four address lines from the CRTC are bits 0-3 */
if (offset >= 4)
@ -346,12 +346,12 @@ READ8_MEMBER(cosmic_state::cosmicg_port_0_r)
return BIT(m_screen->vpos(), offset + 4);
}
READ8_MEMBER(cosmic_state::cosmicg_port_1_r)
uint8_t cosmic_state::cosmicg_port_1_r(offs_t offset)
{
return BIT(m_in_ports[1]->read(), offset);
}
READ8_MEMBER(cosmic_state::magspot_coinage_dip_r)
uint8_t cosmic_state::magspot_coinage_dip_r(offs_t offset)
{
return (m_dsw.read_safe(0) & (1 << (7 - offset))) ? 0 : 1;
}
@ -359,7 +359,7 @@ READ8_MEMBER(cosmic_state::magspot_coinage_dip_r)
/* Has 8 way joystick, remap combinations to missing directions */
READ8_MEMBER(cosmic_state::nomnlnd_port_0_1_r)
uint8_t cosmic_state::nomnlnd_port_0_1_r(offs_t offset)
{
int control = m_in_ports[offset]->read();
int fire = m_in_ports[3]->read();
@ -378,7 +378,7 @@ READ8_MEMBER(cosmic_state::nomnlnd_port_0_1_r)
WRITE8_MEMBER(cosmic_state::flip_screen_w)
void cosmic_state::flip_screen_w(uint8_t data)
{
flip_screen_set(data & 0x80);
}
@ -1597,16 +1597,16 @@ void cosmic_state::init_cosmica()
void cosmic_state::init_devzone()
{
m_maincpu->space(AS_PROGRAM).install_write_handler(0x4807, 0x4807, write8_delegate(*this, FUNC(cosmic_state::cosmic_background_enable_w)));
m_maincpu->space(AS_PROGRAM).install_write_handler(0x4807, 0x4807, write8smo_delegate(*this, FUNC(cosmic_state::cosmic_background_enable_w)));
}
void cosmic_state::init_nomnlnd()
{
m_maincpu->space(AS_PROGRAM).install_read_handler(0x5000, 0x5001, read8_delegate(*this, FUNC(cosmic_state::nomnlnd_port_0_1_r)));
m_maincpu->space(AS_PROGRAM).install_read_handler(0x5000, 0x5001, read8sm_delegate(*this, FUNC(cosmic_state::nomnlnd_port_0_1_r)));
m_maincpu->space(AS_PROGRAM).nop_write(0x4800, 0x4800);
m_maincpu->space(AS_PROGRAM).install_write_handler(0x4807, 0x4807, write8_delegate(*this, FUNC(cosmic_state::cosmic_background_enable_w)));
m_maincpu->space(AS_PROGRAM).install_write_handler(0x480a, 0x480a, write8_delegate(*this, FUNC(cosmic_state::dac_w)));
m_maincpu->space(AS_PROGRAM).install_write_handler(0x4807, 0x4807, write8smo_delegate(*this, FUNC(cosmic_state::cosmic_background_enable_w)));
m_maincpu->space(AS_PROGRAM).install_write_handler(0x480a, 0x480a, write8smo_delegate(*this, FUNC(cosmic_state::dac_w)));
}
void cosmic_state::init_panic()

25
src/mame/drivers/cosmicos.cpp
View File

@ -56,7 +56,7 @@ enum
/* Read/Write Handlers */
READ8_MEMBER( cosmicos_state::read )
uint8_t cosmicos_state::read(offs_t offset)
{
if (m_boot) offset |= 0xc000;
@ -78,7 +78,7 @@ READ8_MEMBER( cosmicos_state::read )
return data;
}
WRITE8_MEMBER( cosmicos_state::write )
void cosmicos_state::write(offs_t offset, uint8_t data)
{
if (m_boot) offset |= 0xc000;
@ -92,7 +92,7 @@ WRITE8_MEMBER( cosmicos_state::write )
}
}
READ8_MEMBER( cosmicos_state::video_off_r )
uint8_t cosmicos_state::video_off_r()
{
uint8_t data = 0;
@ -104,7 +104,7 @@ READ8_MEMBER( cosmicos_state::video_off_r )
return data;
}
READ8_MEMBER( cosmicos_state::video_on_r )
uint8_t cosmicos_state::video_on_r()
{
uint8_t data = 0;
@ -116,7 +116,7 @@ READ8_MEMBER( cosmicos_state::video_on_r )
return data;
}
WRITE8_MEMBER( cosmicos_state::audio_latch_w )
void cosmicos_state::audio_latch_w(uint8_t data)
{
if (m_q)
{
@ -124,12 +124,11 @@ WRITE8_MEMBER( cosmicos_state::audio_latch_w )
}
}
READ8_MEMBER( cosmicos_state::hex_keyboard_r )
uint8_t cosmicos_state::hex_keyboard_r()
{
uint8_t data = 0;
int i;
for (i = 0; i < 4; i++)
for (int i = 0; i < 4; i++)
{
if (BIT(m_keylatch, i))
{
@ -145,19 +144,19 @@ READ8_MEMBER( cosmicos_state::hex_keyboard_r )
return data;
}
WRITE8_MEMBER( cosmicos_state::hex_keylatch_w )
void cosmicos_state::hex_keylatch_w(uint8_t data)
{
m_keylatch = data & 0x0f;
}
READ8_MEMBER( cosmicos_state::reset_counter_r )
uint8_t cosmicos_state::reset_counter_r()
{
m_counter = 0;
return 0;
}
WRITE8_MEMBER( cosmicos_state::segment_w )
void cosmicos_state::segment_w(uint8_t data)
{
m_counter++;
@ -172,12 +171,12 @@ WRITE8_MEMBER( cosmicos_state::segment_w )
}
}
READ8_MEMBER( cosmicos_state::data_r )
uint8_t cosmicos_state::data_r()
{
return m_data;
}
WRITE8_MEMBER( cosmicos_state::display_w )
void cosmicos_state::display_w(uint8_t data)
{
m_segment = data;
}

78
src/mame/drivers/cps1.cpp
View File

@ -255,50 +255,50 @@ Stephh's log (2006.09.20) :
READ16_MEMBER(cps_state::cps1_dsw_r)
uint16_t cps_state::cps1_dsw_r(offs_t offset)
{
static const char *const dswname[] = { "IN0", "DSWA", "DSWB", "DSWC" };
int in = ioport(dswname[offset])->read();
return (in << 8) | 0xff;
}
READ16_MEMBER(cps_state::cps1_hack_dsw_r)
uint16_t cps_state::cps1_hack_dsw_r(offs_t offset)
{
static const char *const dswname[] = { "IN0", "DSWA", "DSWB", "DSWC" };
int in = ioport(dswname[offset])->read();
return (in << 8) | in;
}
READ16_MEMBER(cps_state::cps1_in1_r)
uint16_t cps_state::cps1_in1_r()
{
int in = ioport("IN1")->read();
return (in << 8) | in;
}
READ16_MEMBER(cps_state::cps1_in2_r)
uint16_t cps_state::cps1_in2_r()
{
int in = ioport("IN2")->read();
return (in << 8) | in;
}
READ16_MEMBER(cps_state::cps1_in3_r)
uint16_t cps_state::cps1_in3_r()
{
int in = ioport("IN3")->read();
return (in << 8) | in;
}
WRITE8_MEMBER(cps_state::cps1_snd_bankswitch_w)
void cps_state::cps1_snd_bankswitch_w(uint8_t data)
{
membank("bank1")->set_entry(data & 0x01);
}
WRITE8_MEMBER(cps_state::cps1_oki_pin7_w)
void cps_state::cps1_oki_pin7_w(uint8_t data)
{
m_oki->set_pin7(data & 1);
}
WRITE16_MEMBER(cps_state::cps1_soundlatch_w)
void cps_state::cps1_soundlatch_w(offs_t offset, uint16_t data, uint16_t mem_mask)
{
if (ACCESSING_BITS_0_7)
m_soundlatch->write(data & 0xff);
@ -306,13 +306,13 @@ WRITE16_MEMBER(cps_state::cps1_soundlatch_w)
m_soundlatch->write(data >> 8);
}
WRITE16_MEMBER(cps_state::cps1_soundlatch2_w)
void cps_state::cps1_soundlatch2_w(offs_t offset, uint16_t data, uint16_t mem_mask)
{
if (ACCESSING_BITS_0_7)
m_soundlatch2->write(data & 0xff);
}
WRITE16_MEMBER(cps_state::cps1_coinctrl_w)
void cps_state::cps1_coinctrl_w(offs_t offset, uint16_t data, uint16_t mem_mask)
{
if (ACCESSING_BITS_8_15)
{
@ -325,7 +325,7 @@ WRITE16_MEMBER(cps_state::cps1_coinctrl_w)
}
}
WRITE16_MEMBER(cps_state::cpsq_coinctrl2_w)
void cps_state::cpsq_coinctrl2_w(offs_t offset, uint16_t data, uint16_t mem_mask)
{
if (ACCESSING_BITS_0_7)
{
@ -382,7 +382,7 @@ void cps_state::cpu_space_map(address_map &map)
*
********************************************************************/
READ16_MEMBER(cps_state::qsound_rom_r)
uint16_t cps_state::qsound_rom_r(offs_t offset)
{
if (memregion("user1") != nullptr)
{
@ -396,29 +396,29 @@ READ16_MEMBER(cps_state::qsound_rom_r)
}
}
READ16_MEMBER(cps_state::qsound_sharedram1_r)
uint16_t cps_state::qsound_sharedram1_r(offs_t offset)
{
return m_qsound_sharedram1[offset] | 0xff00;
}
WRITE16_MEMBER(cps_state::qsound_sharedram1_w)
void cps_state::qsound_sharedram1_w(offs_t offset, uint16_t data, uint16_t mem_mask)
{
if (ACCESSING_BITS_0_7)
m_qsound_sharedram1[offset] = data;
}
READ16_MEMBER(cps_state::qsound_sharedram2_r)
uint16_t cps_state::qsound_sharedram2_r(offs_t offset)
{
return m_qsound_sharedram2[offset] | 0xff00;
}
WRITE16_MEMBER(cps_state::qsound_sharedram2_w)
void cps_state::qsound_sharedram2_w(offs_t offset, uint16_t data, uint16_t mem_mask)
{
if (ACCESSING_BITS_0_7)
m_qsound_sharedram2[offset] = data;
}
WRITE8_MEMBER(cps_state::qsound_banksw_w)
void cps_state::qsound_banksw_w(uint8_t data)
{
/* Z80 bank register for music note data. It's odd that it isn't encrypted though. */
int bank = data & 0x0f;
@ -13503,7 +13503,7 @@ ROM_START( sfzbch )
ROM_END
READ16_MEMBER(cps_state::sf2rb_prot_r)
uint16_t cps_state::sf2rb_prot_r(offs_t offset)
{
switch (offset)
{
@ -13519,12 +13519,12 @@ READ16_MEMBER(cps_state::sf2rb_prot_r)
void cps_state::init_sf2rb()
{
m_maincpu->space(AS_PROGRAM).install_read_handler(0x200000, 0x2fffff, read16_delegate(*this, FUNC(cps_state::sf2rb_prot_r)));
m_maincpu->space(AS_PROGRAM).install_read_handler(0x200000, 0x2fffff, read16sm_delegate(*this, FUNC(cps_state::sf2rb_prot_r)));
init_cps1();
}
READ16_MEMBER(cps_state::sf2rb2_prot_r)
uint16_t cps_state::sf2rb2_prot_r(offs_t offset)
{
switch (offset)
{
@ -13540,7 +13540,7 @@ READ16_MEMBER(cps_state::sf2rb2_prot_r)
void cps_state::init_sf2rb2()
{
m_maincpu->space(AS_PROGRAM).install_read_handler(0x200000, 0x2fffff, read16_delegate(*this, FUNC(cps_state::sf2rb2_prot_r)));
m_maincpu->space(AS_PROGRAM).install_read_handler(0x200000, 0x2fffff, read16sm_delegate(*this, FUNC(cps_state::sf2rb2_prot_r)));
init_cps1();
}
@ -13550,7 +13550,8 @@ void cps_state::init_sf2ee()
/* This specific revision of SF2 has the CPS-B custom mapped at a different address. */
/* The mapping is handled by the PAL IOB2 on the B-board */
m_maincpu->space(AS_PROGRAM).unmap_readwrite(0x800140, 0x80017f);
m_maincpu->space(AS_PROGRAM).install_readwrite_handler(0x8001c0, 0x8001ff, read16_delegate(*this, FUNC(cps_state::cps1_cps_b_r)), write16_delegate(*this, FUNC(cps_state::cps1_cps_b_w)));
m_maincpu->space(AS_PROGRAM).install_read_handler(0x8001c0, 0x8001ff, read16sm_delegate(*this, FUNC(cps_state::cps1_cps_b_r)));
m_maincpu->space(AS_PROGRAM).install_write_handler(0x8001c0, 0x8001ff, write16s_delegate(*this, FUNC(cps_state::cps1_cps_b_w)));
init_cps1();
}
@ -13558,7 +13559,8 @@ void cps_state::init_sf2ee()
void cps_state::init_sf2thndr()
{
/* This particular hack uses a modified B-board PAL which mirrors the CPS-B registers at an alternate address */
m_maincpu->space(AS_PROGRAM).install_readwrite_handler(0x8001c0, 0x8001ff, read16_delegate(*this, FUNC(cps_state::cps1_cps_b_r)), write16_delegate(*this, FUNC(cps_state::cps1_cps_b_w)));
m_maincpu->space(AS_PROGRAM).install_read_handler(0x8001c0, 0x8001ff, read16sm_delegate(*this, FUNC(cps_state::cps1_cps_b_r)));
m_maincpu->space(AS_PROGRAM).install_write_handler(0x8001c0, 0x8001ff, write16s_delegate(*this, FUNC(cps_state::cps1_cps_b_w)));
init_cps1();
}
@ -13566,7 +13568,7 @@ void cps_state::init_sf2thndr()
void cps_state::init_sf2hack()
{
/* some SF2 hacks have some inputs wired to the LSB instead of MSB */
m_maincpu->space(AS_PROGRAM).install_read_handler(0x800018, 0x80001f, read16_delegate(*this, FUNC(cps_state::cps1_hack_dsw_r)));
m_maincpu->space(AS_PROGRAM).install_read_handler(0x800018, 0x80001f, read16sm_delegate(*this, FUNC(cps_state::cps1_hack_dsw_r)));
init_cps1();
}
@ -13593,7 +13595,7 @@ void cps_state::init_sf2rk()
}
}
READ16_MEMBER(cps_state::sf2dongb_prot_r)
uint16_t cps_state::sf2dongb_prot_r(offs_t offset)
{
switch (offset)
{
@ -13608,12 +13610,12 @@ READ16_MEMBER(cps_state::sf2dongb_prot_r)
void cps_state::init_sf2dongb()
{
// There is a hacked up Altera EP910PC-30 DIP in the 5f socket instead of a 4th EPROM
m_maincpu->space(AS_PROGRAM).install_read_handler(0x180000, 0x1fffff, read16_delegate(*this, FUNC(cps_state::sf2dongb_prot_r)));
m_maincpu->space(AS_PROGRAM).install_read_handler(0x180000, 0x1fffff, read16sm_delegate(*this, FUNC(cps_state::sf2dongb_prot_r)));
init_cps1();
}
READ16_MEMBER(cps_state::sf2ceblp_prot_r)
uint16_t cps_state::sf2ceblp_prot_r()
{
if (sf2ceblp_prot == 0x0)
return 0x1992;
@ -13622,7 +13624,7 @@ READ16_MEMBER(cps_state::sf2ceblp_prot_r)
return 0xffff;
}
WRITE16_MEMBER(cps_state::sf2ceblp_prot_w)
void cps_state::sf2ceblp_prot_w(uint16_t data)
{
sf2ceblp_prot = data;
}
@ -13630,8 +13632,8 @@ WRITE16_MEMBER(cps_state::sf2ceblp_prot_w)
void cps_state::init_sf2ceblp()
{
m_maincpu->space(AS_PROGRAM).install_write_handler(0x5762b0, 0x5762b1, write16_delegate(*this, FUNC(cps_state::sf2ceblp_prot_w)));
m_maincpu->space(AS_PROGRAM).install_read_handler(0x57A2b0, 0x57A2b1, read16_delegate(*this, FUNC(cps_state::sf2ceblp_prot_r)));
m_maincpu->space(AS_PROGRAM).install_write_handler(0x5762b0, 0x5762b1, write16smo_delegate(*this, FUNC(cps_state::sf2ceblp_prot_w)));
m_maincpu->space(AS_PROGRAM).install_read_handler(0x57A2b0, 0x57A2b1, read16smo_delegate(*this, FUNC(cps_state::sf2ceblp_prot_r)));
init_cps1();
}
@ -13730,7 +13732,7 @@ void cps_state::init_pang3()
init_pang3b();
}
READ16_MEMBER(cps_state::ganbare_ram_r)
uint16_t cps_state::ganbare_ram_r(offs_t offset, uint16_t mem_mask)
{
uint16_t result = 0xffff;
@ -13742,7 +13744,7 @@ READ16_MEMBER(cps_state::ganbare_ram_r)
return result;
}
WRITE16_MEMBER(cps_state::ganbare_ram_w)
void cps_state::ganbare_ram_w(offs_t offset, uint16_t data, uint16_t mem_mask)
{
COMBINE_DATA(&m_mainram[offset]);
@ -13755,10 +13757,10 @@ void cps_state::init_ganbare()
init_cps1();
/* ram is shared between the CPS work ram and the timekeeper ram */
m_maincpu->space(AS_PROGRAM).install_readwrite_handler(0xff0000, 0xffffff, read16_delegate(*this, FUNC(cps_state::ganbare_ram_r)), write16_delegate(*this, FUNC(cps_state::ganbare_ram_w)));
m_maincpu->space(AS_PROGRAM).install_readwrite_handler(0xff0000, 0xffffff, read16s_delegate(*this, FUNC(cps_state::ganbare_ram_r)), write16s_delegate(*this, FUNC(cps_state::ganbare_ram_w)));
}
READ16_MEMBER(cps_state::dinohunt_sound_r)
uint16_t cps_state::dinohunt_sound_r()
{
/*TODO: understand what's really going on here. According to MT05805;
"I think that the values written are only qsound leftovers (after a lot of 0xFF values,
@ -13769,19 +13771,19 @@ READ16_MEMBER(cps_state::dinohunt_sound_r)
void cps_state::init_dinohunt()
{
// is this shared with the new sound hw?
m_maincpu->space(AS_PROGRAM).install_read_handler(0xf18000, 0xf19fff, read16_delegate(*this, FUNC(cps_state::dinohunt_sound_r)));
m_maincpu->space(AS_PROGRAM).install_read_handler(0xf18000, 0xf19fff, read16smo_delegate(*this, FUNC(cps_state::dinohunt_sound_r)));
m_maincpu->space(AS_PROGRAM).install_read_port(0xfc0000, 0xfc0001, "IN2"); ;
// the ym2151 doesn't seem to be used. Is it actually on the PCB?
init_cps1();
}
WRITE16_MEMBER( cps_state::sf2m3_layer_w )
void cps_state::sf2m3_layer_w(offs_t offset, uint16_t data)
{
cps1_cps_b_w(space,0x0a,data);
cps1_cps_b_w(0x0a,data);
}
WRITE16_MEMBER(cps_state::varthb2_cps_a_w)
void cps_state::varthb2_cps_a_w(offs_t offset, uint16_t data)
{
// cps-a regs are updated as normal by original code,
// but bootleg code ignores them and uses these regions instead:

20
src/mame/drivers/cps2.cpp
View File

@ -706,7 +706,7 @@ TIMER_DEVICE_CALLBACK_MEMBER(cps2_state::cps2_interrupt)
*
*************************************/
WRITE16_MEMBER( cps2_state::cps2_eeprom_port_w )
void cps2_state::cps2_eeprom_port_w(offs_t offset, uint16_t data, uint16_t mem_mask)
{
if (ACCESSING_BITS_8_15)
{
@ -797,7 +797,7 @@ TIMER_CALLBACK_MEMBER(cps2_state::cps2_update_digital_volume)
m_qsound->set_output_gain(1, m_cps2digitalvolumelevel / 39.0);
}
READ16_MEMBER(cps2_state::cps2_qsound_volume_r)
uint16_t cps2_state::cps2_qsound_volume_r()
{
static const uint16_t cps2_vol_states[40] =
{
@ -831,12 +831,12 @@ READ16_MEMBER(cps2_state::cps2_qsound_volume_r)
*
*************************************/
READ16_MEMBER(cps2_state::kludge_r)
uint16_t cps2_state::kludge_r()
{
return 0xffff;
}
READ16_MEMBER(cps2_state::joy_or_paddle_r)
uint16_t cps2_state::joy_or_paddle_r()
{
if (m_readpaddle != 0)
{
@ -848,7 +848,7 @@ READ16_MEMBER(cps2_state::joy_or_paddle_r)
}
}
READ16_MEMBER(cps2_state::joy_or_paddle_ecofghtr_r)
uint16_t cps2_state::joy_or_paddle_ecofghtr_r()
{
if (m_readpaddle == 0 || (m_io_in1->read() & 0x10) == 0x10) // ignore bit if spinner not enabled
{
@ -10011,7 +10011,7 @@ void cps2_state::init_pzloop2()
save_item(NAME(m_readpaddle));
m_maincpu->space(AS_PROGRAM).install_read_handler(0x804000, 0x804001, read16_delegate(*this, FUNC(cps2_state::joy_or_paddle_r)));
m_maincpu->space(AS_PROGRAM).install_read_handler(0x804000, 0x804001, read16smo_delegate(*this, FUNC(cps2_state::joy_or_paddle_r)));
}
void cps2_state::init_singbrd()
@ -10023,12 +10023,12 @@ void cps2_state::init_singbrd()
m_digital_volume_timer->adjust(attotime::never, 0, attotime::never);
}
READ16_MEMBER( cps2_state::gigaman2_dummyqsound_r )
uint16_t cps2_state::gigaman2_dummyqsound_r(offs_t offset)
{
return m_gigaman2_dummyqsound_ram[offset];
}
WRITE16_MEMBER( cps2_state::gigaman2_dummyqsound_w )
void cps2_state::gigaman2_dummyqsound_w(offs_t offset, uint16_t data)
{
m_gigaman2_dummyqsound_ram[offset] = data;
}
@ -10059,7 +10059,7 @@ void cps2_state::init_gigaman2()
m_gigaman2_dummyqsound_ram = std::make_unique<uint16_t[]>(0x20000 / 2);
save_pointer(NAME(m_gigaman2_dummyqsound_ram), 0x20000 / 2);
space.install_readwrite_handler(0x618000, 0x619fff, read16_delegate(*this, FUNC(cps2_state::gigaman2_dummyqsound_r)), write16_delegate(*this, FUNC(cps2_state::gigaman2_dummyqsound_w))); // no qsound..
space.install_readwrite_handler(0x618000, 0x619fff, read16sm_delegate(*this, FUNC(cps2_state::gigaman2_dummyqsound_r)), write16sm_delegate(*this, FUNC(cps2_state::gigaman2_dummyqsound_w))); // no qsound..
memcpy(m_decrypted_opcodes, memregion("maincpu")->base()+0x200000, 0x200000);
@ -10076,7 +10076,7 @@ void cps2_state::init_ecofghtr()
save_item(NAME(m_readpaddle));
m_maincpu->space(AS_PROGRAM).install_read_handler(0x804000, 0x804001, read16_delegate(*this, FUNC(cps2_state::joy_or_paddle_ecofghtr_r)));
m_maincpu->space(AS_PROGRAM).install_read_handler(0x804000, 0x804001, read16smo_delegate(*this, FUNC(cps2_state::joy_or_paddle_ecofghtr_r)));
}

48
src/mame/drivers/cps3.cpp
View File

@ -1326,12 +1326,12 @@ u32 cps3_state::screen_update(screen_device &screen, bitmap_rgb32 &bitmap, const
0x8000 - 0xffff tile character definitions
*/
READ8_MEMBER(cps3_state::ssram_r)
u8 cps3_state::ssram_r(offs_t offset)
{
return m_ss_ram[offset];
}
WRITE8_MEMBER(cps3_state::ssram_w)
void cps3_state::ssram_w(offs_t offset, u8 data)
{
if (offset >= 0x4000)
m_gfxdecode->gfx(0)->mark_dirty((offset - 0x4000)/32);
@ -1339,14 +1339,14 @@ WRITE8_MEMBER(cps3_state::ssram_w)
m_ss_ram[offset] = data;
}
WRITE32_MEMBER(cps3_state::sh2cache_ram_w)
void cps3_state::sh2cache_ram_w(offs_t offset, u32 data, u32 mem_mask)
{
COMBINE_DATA( &m_sh2cache_ram[offset] );
// store a decrypted copy
m_sh2cache_ram_decrypted[offset] = m_sh2cache_ram[offset]^cps3_mask(offset*4+0xc0000000, m_key1, m_key2);
}
WRITE32_MEMBER(cps3_state::cram_bank_w)
void cps3_state::cram_bank_w(offs_t offset, u32 data, u32 mem_mask)
{
if (ACCESSING_BITS_0_7)
{
@ -1375,14 +1375,14 @@ WRITE32_MEMBER(cps3_state::cram_bank_w)
}
}
READ32_MEMBER(cps3_state::cram_data_r)
u32 cps3_state::cram_data_r(offs_t offset)
{
u32 fulloffset = (((m_cram_bank & 0x7)*0x100000)/4) + offset;
return little_endianize_int32(m_char_ram[fulloffset]);
}
WRITE32_MEMBER(cps3_state::cram_data_w)
void cps3_state::cram_data_w(offs_t offset, u32 data, u32 mem_mask)
{
u32 fulloffset = (((m_cram_bank & 0x7)*0x100000)/4) + offset;
mem_mask = little_endianize_int32(mem_mask);
@ -1391,7 +1391,7 @@ WRITE32_MEMBER(cps3_state::cram_data_w)
m_gfxdecode->gfx(1)->mark_dirty(fulloffset/0x40);
}
WRITE16_MEMBER(cps3_state::spritedma_w)
void cps3_state::spritedma_w(offs_t offset, u16 data, u16 mem_mask)
{
u16 prev = m_spritelist_dma;
COMBINE_DATA(&m_spritelist_dma);
@ -1418,7 +1418,7 @@ WRITE16_MEMBER(cps3_state::spritedma_w)
/* FLASH ROM ACCESS */
READ32_MEMBER(cps3_state::gfxflash_r)
u32 cps3_state::gfxflash_r(offs_t offset, u32 mem_mask)
{
u32 result = 0;
if (m_cram_gfxflash_bank&1) offset += 0x200000/4;
@ -1456,7 +1456,7 @@ READ32_MEMBER(cps3_state::gfxflash_r)
return result;
}
WRITE32_MEMBER(cps3_state::gfxflash_w)
void cps3_state::gfxflash_w(offs_t offset, u32 data, u32 mem_mask)
{
int command;
if (m_cram_gfxflash_bank&1) offset += 0x200000/4;
@ -1547,7 +1547,7 @@ u32 cps3_state::flashmain_r(int which, u32 offset, u32 mem_mask)
READ32_MEMBER(cps3_state::flash1_r)
u32 cps3_state::flash1_r(offs_t offset, u32 mem_mask)
{
u32 retvalue = flashmain_r(0, offset, mem_mask);
@ -1557,7 +1557,7 @@ READ32_MEMBER(cps3_state::flash1_r)
return retvalue;
}
READ32_MEMBER(cps3_state::flash2_r)
u32 cps3_state::flash2_r(offs_t offset, u32 mem_mask)
{
u32 retvalue = flashmain_r(1, offset, mem_mask);
@ -1625,17 +1625,17 @@ void cps3_state::flashmain_w(int which, u32 offset, u32 data, u32 mem_mask)
}
}
WRITE32_MEMBER(cps3_state::flash1_w)
void cps3_state::flash1_w(offs_t offset, u32 data, u32 mem_mask)
{
flashmain_w(0,offset,data,mem_mask);
}
WRITE32_MEMBER(cps3_state::flash2_w)
void cps3_state::flash2_w(offs_t offset, u32 data, u32 mem_mask)
{
flashmain_w(1,offset,data,mem_mask);
}
WRITE32_MEMBER(cps3_state::cram_gfxflash_bank_w)
void cps3_state::cram_gfxflash_bank_w(offs_t offset, u32 data, u32 mem_mask)
{
if (ACCESSING_BITS_24_31)
{
@ -1691,12 +1691,12 @@ WRITE32_MEMBER(cps3_state::cram_gfxflash_bank_w)
}
}
READ16_MEMBER(cps3_state::dma_status_r)
u16 cps3_state::dma_status_r()
{
return m_dma_status;
}
READ16_MEMBER(cps3_state::dev_dipsw_r)
u16 cps3_state::dev_dipsw_r()
{
// presumably these data came from serial interface populated on early boards
// inverted words from 5000a00-5000a0f area ANDed with inverted words from 5000a10-5000a1f. perhaps one return DIPSW in 8 high bits, while other in 8 low bits.
@ -1707,7 +1707,7 @@ READ16_MEMBER(cps3_state::dev_dipsw_r)
/* EEPROM access is a little odd, I think it accesses eeprom through some kind of
additional interface, as these writes aren't normal for the type of eeprom we have */
READ32_MEMBER(cps3_state::eeprom_r)
u32 cps3_state::eeprom_r(offs_t offset, u32 mem_mask)
{
int addr = offset*4;
@ -1735,7 +1735,7 @@ READ32_MEMBER(cps3_state::eeprom_r)
}
}
WRITE32_MEMBER(cps3_state::eeprom_w)
void cps3_state::eeprom_w(offs_t offset, u32 data, u32 mem_mask)
{
int addr = offset*4;
@ -1757,7 +1757,7 @@ WRITE32_MEMBER(cps3_state::eeprom_w)
}
WRITE16_MEMBER(cps3_state::outport_w)
void cps3_state::outport_w(offs_t offset, u16 data, u16 mem_mask)
{
if (ACCESSING_BITS_0_7)
{
@ -1769,7 +1769,7 @@ WRITE16_MEMBER(cps3_state::outport_w)
// bits 14 and 15 some LEDs ?
}
WRITE8_MEMBER(cps3_state::ssregs_w)
void cps3_state::ssregs_w(offs_t offset, u8 data)
{
switch (offset)
{
@ -1800,7 +1800,7 @@ WRITE8_MEMBER(cps3_state::ssregs_w)
//<ElSemi> (a word each)
WRITE32_MEMBER(cps3_state::palettedma_w)
void cps3_state::palettedma_w(offs_t offset, u32 data, u32 mem_mask)
{
if (offset==0)
{
@ -2071,7 +2071,7 @@ void cps3_state::process_character_dma(u32 address)
m_dma_timer->adjust(attotime::from_usec(100)); // delay time is a hack, what is actual DMA speed?
}
WRITE32_MEMBER(cps3_state::characterdma_w)
void cps3_state::characterdma_w(offs_t offset, u32 data, u32 mem_mask)
{
if (DEBUG_PRINTF) logerror("chardma_w %08x %08x %08x\n", offset, data, mem_mask);
@ -2116,12 +2116,12 @@ WRITE32_MEMBER(cps3_state::characterdma_w)
}
}
READ16_MEMBER(cps3_state::colourram_r)
u16 cps3_state::colourram_r(offs_t offset)
{
return m_colourram[offset];
}
WRITE16_MEMBER(cps3_state::colourram_w)
void cps3_state::colourram_w(offs_t offset, u16 data, u16 mem_mask)
{
COMBINE_DATA(&m_colourram[offset]);

16
src/mame/drivers/crbaloon.cpp
View File

@ -58,7 +58,7 @@ void crbaloon_state::pc3092_update()
}
WRITE8_MEMBER(crbaloon_state::pc3092_w)
void crbaloon_state::pc3092_w(offs_t offset, uint8_t data)
{
m_pc3092_data[offset] = data & 0x0f;
@ -114,7 +114,7 @@ void crbaloon_state::pc3259_update(void)
}
READ8_MEMBER(crbaloon_state::pc3259_r)
uint8_t crbaloon_state::pc3259_r(offs_t offset)
{
uint8_t ret = 0;
uint8_t reg = offset >> 2;
@ -155,7 +155,7 @@ READ8_MEMBER(crbaloon_state::pc3259_r)
*
*************************************/
WRITE8_MEMBER(crbaloon_state::port_sound_w)
void crbaloon_state::port_sound_w(uint8_t data)
{
/* D0 - interrupt enable - also goes to PC3259 as /HTCTRL */
m_irq_mask = data & 0x01;
@ -165,7 +165,7 @@ WRITE8_MEMBER(crbaloon_state::port_sound_w)
machine().sound().system_enable((data & 0x02) ? true : false);
/* D2 - unlabeled - music enable */
crbaloon_audio_set_music_enable(space, 0, (data & 0x04) ? true : false);
crbaloon_audio_set_music_enable((data & 0x04) ? true : false);
/* D3 - EXPLOSION */
crbaloon_audio_set_explosion_enable((data & 0x08) ? true : false);
@ -177,7 +177,7 @@ WRITE8_MEMBER(crbaloon_state::port_sound_w)
crbaloon_audio_set_appear_enable((data & 0x20) ? true : false);
/* D6 - unlabeled - laugh enable */
crbaloon_audio_set_laugh_enable(space, 0, (data & 0x40) ? true : false);
crbaloon_audio_set_laugh_enable((data & 0x40) ? true : false);
/* D7 - unlabeled - goes to PC3259 pin 16 */
@ -339,11 +339,9 @@ GFXDECODE_END
void crbaloon_state::machine_reset()
{
address_space &space = m_maincpu->space(AS_IO);
pc3092_reset();
port_sound_w(space, 0, 0);
crbaloon_audio_set_music_freq(space, 0, 0);
port_sound_w(0);
crbaloon_audio_set_music_freq(0);
}

22
src/mame/drivers/crgolf.cpp
View File

@ -107,7 +107,7 @@ protected or a snippet should do the aforementioned string copy.
*
*************************************/
WRITE8_MEMBER(crgolf_state::rom_bank_select_w)
void crgolf_state::rom_bank_select_w(uint8_t data)
{
membank("bank1")->set_entry(data & 15);
}
@ -149,7 +149,7 @@ void crgolf_state::machine_reset()
*
*************************************/
READ8_MEMBER(crgolf_state::switch_input_r)
uint8_t crgolf_state::switch_input_r()
{
static const char *const portnames[] = { "IN0", "IN1", "P1", "P2", "DSW", "UNUSED0", "UNUSED1" };
@ -157,13 +157,13 @@ READ8_MEMBER(crgolf_state::switch_input_r)
}
READ8_MEMBER(crgolf_state::analog_input_r)
uint8_t crgolf_state::analog_input_r()
{
return ((ioport("STICK0")->read() >> 4) | (ioport("STICK1")->read() & 0xf0)) ^ 0x88;
}
WRITE8_MEMBER(crgolf_state::switch_input_select_w)
void crgolf_state::switch_input_select_w(uint8_t data)
{
if (!(data & 0x40)) m_port_select = 6;
if (!(data & 0x20)) m_port_select = 5;
@ -175,7 +175,7 @@ WRITE8_MEMBER(crgolf_state::switch_input_select_w)
}
WRITE8_MEMBER(crgolf_state::unknown_w)
void crgolf_state::unknown_w(uint8_t data)
{
logerror("%04X:unknown_w = %02X\n", m_audiocpu->pc(), data);
}
@ -212,7 +212,7 @@ WRITE_LINE_MEMBER(crgolf_state::vck_callback)
}
WRITE8_MEMBER(crgolf_state::crgolfhi_sample_w)
void crgolf_state::crgolfhi_sample_w(offs_t offset, uint8_t data)
{
switch (offset)
{
@ -348,22 +348,22 @@ void crgolf_state::mastrglf_submap(address_map &map)
}
READ8_MEMBER(crgolf_state::unk_sub_02_r)
uint8_t crgolf_state::unk_sub_02_r()
{
return 0x00;
}
READ8_MEMBER(crgolf_state::unk_sub_05_r)
uint8_t crgolf_state::unk_sub_05_r()
{
return 0x00;
}
READ8_MEMBER(crgolf_state::unk_sub_07_r)
uint8_t crgolf_state::unk_sub_07_r()
{
return 0x00;
}
WRITE8_MEMBER(crgolf_state::unk_sub_0c_w)
void crgolf_state::unk_sub_0c_w(uint8_t data)
{
}
@ -778,7 +778,7 @@ ROM_END
void crgolf_state::init_crgolfhi()
{
m_audiocpu->space(AS_PROGRAM).install_write_handler(0xa000, 0xa003, write8_delegate(*this, FUNC(crgolf_state::crgolfhi_sample_w)));
m_audiocpu->space(AS_PROGRAM).install_write_handler(0xa000, 0xa003, write8sm_delegate(*this, FUNC(crgolf_state::crgolfhi_sample_w)));
}

8
src/mame/drivers/crimfght.cpp
View File

@ -23,13 +23,13 @@
#include "speaker.h"
WRITE8_MEMBER(crimfght_state::crimfght_coin_w)
void crimfght_state::crimfght_coin_w(uint8_t data)
{
machine().bookkeeping().coin_counter_w(0, data & 1);
machine().bookkeeping().coin_counter_w(1, data & 2);
}
READ8_MEMBER(crimfght_state::k052109_051960_r)
uint8_t crimfght_state::k052109_051960_r(offs_t offset)
{
if (m_k052109->get_rmrd_line() == CLEAR_LINE)
{
@ -44,7 +44,7 @@ READ8_MEMBER(crimfght_state::k052109_051960_r)
return m_k052109->read(offset);
}
WRITE8_MEMBER(crimfght_state::k052109_051960_w)
void crimfght_state::k052109_051960_w(offs_t offset, uint8_t data)
{
if (offset >= 0x3800 && offset < 0x3808)
m_k051960->k051937_w(offset - 0x3800, data);
@ -54,7 +54,7 @@ WRITE8_MEMBER(crimfght_state::k052109_051960_w)
m_k051960->k051960_w(offset - 0x3c00, data);
}
WRITE8_MEMBER(crimfght_state::sound_w)
void crimfght_state::sound_w(uint8_t data)
{
// writing the latch asserts the irq line
m_soundlatch->write(data);

2
src/mame/drivers/crshrace.cpp
View File

@ -140,7 +140,7 @@ Dip locations verified with Service Mode.
#define CRSHRACE_3P_HACK 0
WRITE8_MEMBER(crshrace_state::crshrace_sh_bankswitch_w)
void crshrace_state::crshrace_sh_bankswitch_w(uint8_t data)
{
m_z80bank->set_entry(data & 0x03);
}

50
src/mame/drivers/cvs.cpp
View File

@ -120,7 +120,7 @@ WRITE_LINE_MEMBER(cvs_state::write_s2650_flag)
m_s2650_flag = state;
}
READ8_MEMBER(cvs_state::cvs_video_or_color_ram_r)
uint8_t cvs_state::cvs_video_or_color_ram_r(offs_t offset)
{
if (m_s2650_flag)
return m_video_ram[offset];
@ -128,7 +128,7 @@ READ8_MEMBER(cvs_state::cvs_video_or_color_ram_r)
return m_color_ram[offset];
}
WRITE8_MEMBER(cvs_state::cvs_video_or_color_ram_w)
void cvs_state::cvs_video_or_color_ram_w(offs_t offset, uint8_t data)
{
if (m_s2650_flag)
m_video_ram[offset] = data;
@ -137,7 +137,7 @@ WRITE8_MEMBER(cvs_state::cvs_video_or_color_ram_w)
}
READ8_MEMBER(cvs_state::cvs_bullet_ram_or_palette_r)
uint8_t cvs_state::cvs_bullet_ram_or_palette_r(offs_t offset)
{
if (m_s2650_flag)
return m_palette_ram[offset & 0x0f];
@ -145,7 +145,7 @@ READ8_MEMBER(cvs_state::cvs_bullet_ram_or_palette_r)
return m_bullet_ram[offset];
}
WRITE8_MEMBER(cvs_state::cvs_bullet_ram_or_palette_w)
void cvs_state::cvs_bullet_ram_or_palette_w(offs_t offset, uint8_t data)
{
if (m_s2650_flag)
m_palette_ram[offset & 0x0f] = data;
@ -154,7 +154,7 @@ WRITE8_MEMBER(cvs_state::cvs_bullet_ram_or_palette_w)
}
READ8_MEMBER(cvs_state::cvs_s2636_0_or_character_ram_r)
uint8_t cvs_state::cvs_s2636_0_or_character_ram_r(offs_t offset)
{
if (m_s2650_flag)
return m_character_ram[(0 * 0x800) | 0x400 | m_character_ram_page_start | offset];
@ -162,7 +162,7 @@ READ8_MEMBER(cvs_state::cvs_s2636_0_or_character_ram_r)
return m_s2636[0]->read_data(offset);
}
WRITE8_MEMBER(cvs_state::cvs_s2636_0_or_character_ram_w)
void cvs_state::cvs_s2636_0_or_character_ram_w(offs_t offset, uint8_t data)
{
if (m_s2650_flag)
{
@ -175,7 +175,7 @@ WRITE8_MEMBER(cvs_state::cvs_s2636_0_or_character_ram_w)
}
READ8_MEMBER(cvs_state::cvs_s2636_1_or_character_ram_r)
uint8_t cvs_state::cvs_s2636_1_or_character_ram_r(offs_t offset)
{
if (m_s2650_flag)
return m_character_ram[(1 * 0x800) | 0x400 | m_character_ram_page_start | offset];
@ -183,7 +183,7 @@ READ8_MEMBER(cvs_state::cvs_s2636_1_or_character_ram_r)
return m_s2636[1]->read_data(offset);
}
WRITE8_MEMBER(cvs_state::cvs_s2636_1_or_character_ram_w)
void cvs_state::cvs_s2636_1_or_character_ram_w(offs_t offset, uint8_t data)
{
if (m_s2650_flag)
{
@ -196,7 +196,7 @@ WRITE8_MEMBER(cvs_state::cvs_s2636_1_or_character_ram_w)
}
READ8_MEMBER(cvs_state::cvs_s2636_2_or_character_ram_r)
uint8_t cvs_state::cvs_s2636_2_or_character_ram_r(offs_t offset)
{
if (m_s2650_flag)
return m_character_ram[(2 * 0x800) | 0x400 | m_character_ram_page_start | offset];
@ -204,7 +204,7 @@ READ8_MEMBER(cvs_state::cvs_s2636_2_or_character_ram_r)
return m_s2636[2]->read_data(offset);
}
WRITE8_MEMBER(cvs_state::cvs_s2636_2_or_character_ram_w)
void cvs_state::cvs_s2636_2_or_character_ram_w(offs_t offset, uint8_t data)
{
if (m_s2650_flag)
{
@ -245,7 +245,7 @@ WRITE_LINE_MEMBER(cvs_state::cvs_slave_cpu_interrupt)
*
*************************************/
READ8_MEMBER(cvs_state::cvs_input_r)
uint8_t cvs_state::cvs_input_r(offs_t offset)
{
uint8_t ret = 0;
@ -309,7 +309,7 @@ void cvs_state::start_393hz_timer()
*
*************************************/
WRITE8_MEMBER(cvs_state::cvs_4_bit_dac_data_w)
void cvs_state::cvs_4_bit_dac_data_w(offs_t offset, uint8_t data)
{
uint8_t dac_value;
static int old_data[4] = {0,0,0,0};
@ -331,7 +331,7 @@ WRITE8_MEMBER(cvs_state::cvs_4_bit_dac_data_w)
m_dac2->write(dac_value);
}
WRITE8_MEMBER(cvs_state::cvs_unknown_w)
void cvs_state::cvs_unknown_w(offs_t offset, uint8_t data)
{
/* offset 2 is used in 8ball
* offset 0 is used in spacefrt
@ -356,21 +356,21 @@ WRITE8_MEMBER(cvs_state::cvs_unknown_w)
*************************************/
WRITE8_MEMBER(cvs_state::cvs_speech_rom_address_lo_w)
void cvs_state::cvs_speech_rom_address_lo_w(uint8_t data)
{
/* assuming that d0-d2 are cleared here */
m_speech_rom_bit_address = (m_speech_rom_bit_address & 0xf800) | (data << 3);
LOG(("%04x : CVS: Speech Lo %02x Address = %04x\n", m_speechcpu->pc(), data, m_speech_rom_bit_address >> 3));
}
WRITE8_MEMBER(cvs_state::cvs_speech_rom_address_hi_w)
void cvs_state::cvs_speech_rom_address_hi_w(uint8_t data)
{
m_speech_rom_bit_address = (m_speech_rom_bit_address & 0x07ff) | (data << 11);
LOG(("%04x : CVS: Speech Hi %02x Address = %04x\n", m_speechcpu->pc(), data, m_speech_rom_bit_address >> 3));
}
READ8_MEMBER(cvs_state::cvs_speech_command_r)
uint8_t cvs_state::cvs_speech_command_r()
{
/* FIXME: this was by observation on board ???
* -bit 7 is TMS status (active LO) */
@ -378,7 +378,7 @@ READ8_MEMBER(cvs_state::cvs_speech_command_r)
}
WRITE8_MEMBER(cvs_state::cvs_tms5110_ctl_w)
void cvs_state::cvs_tms5110_ctl_w(offs_t offset, uint8_t data)
{
uint8_t ctl;
/*
@ -396,7 +396,7 @@ WRITE8_MEMBER(cvs_state::cvs_tms5110_ctl_w)
}
WRITE8_MEMBER(cvs_state::cvs_tms5110_pdc_w)
void cvs_state::cvs_tms5110_pdc_w(offs_t offset, uint8_t data)
{
uint8_t out = ((~data) >> 7) & 1;
LOG(("CVS: Speech PDC = %02x %02x\n", offset, out));
@ -426,7 +426,7 @@ READ_LINE_MEMBER(cvs_state::speech_rom_read_bit)
*
*************************************/
WRITE8_MEMBER(cvs_state::audio_command_w)
void cvs_state::audio_command_w(uint8_t data)
{
LOG(("data %02x\n", data));
/* cause interrupt on audio CPU if bit 7 set */
@ -1547,7 +1547,7 @@ ROM_END
*
*************************************/
READ8_MEMBER(cvs_state::huncholy_prot_r)
uint8_t cvs_state::huncholy_prot_r(offs_t offset)
{
if (offset == 1)
{
@ -1561,7 +1561,7 @@ READ8_MEMBER(cvs_state::huncholy_prot_r)
void cvs_state::init_huncholy()
{
m_maincpu->space(AS_PROGRAM).install_read_handler(0x6ff1, 0x6ff2, read8_delegate(*this, FUNC(cvs_state::huncholy_prot_r)));
m_maincpu->space(AS_PROGRAM).install_read_handler(0x6ff1, 0x6ff2, read8sm_delegate(*this, FUNC(cvs_state::huncholy_prot_r)));
save_item(NAME(m_protection_counter));
}
@ -1576,7 +1576,7 @@ void cvs_state::init_hunchbaka()
}
READ8_MEMBER(cvs_state::superbik_prot_r)
uint8_t cvs_state::superbik_prot_r()
{
m_protection_counter++;
if ((m_protection_counter & 0x0f) == 0x02) return 0;
@ -1586,13 +1586,13 @@ READ8_MEMBER(cvs_state::superbik_prot_r)
void cvs_state::init_superbik()
{
m_protection_counter = 0;
m_maincpu->space(AS_PROGRAM).install_read_handler(0x73f1, 0x73f2, read8_delegate(*this, FUNC(cvs_state::superbik_prot_r)));
m_maincpu->space(AS_PROGRAM).install_read_handler(0x73f1, 0x73f2, read8smo_delegate(*this, FUNC(cvs_state::superbik_prot_r)));
save_item(NAME(m_protection_counter));
}
READ8_MEMBER(cvs_state::hero_prot_r)
uint8_t cvs_state::hero_prot_r(offs_t offset)
{
u8 *ROM = memregion("maincpu")->base() + 0x73f0;
@ -1619,7 +1619,7 @@ READ8_MEMBER(cvs_state::hero_prot_r)
void cvs_state::init_hero()
{
m_maincpu->space(AS_PROGRAM).install_read_handler(0x73f0, 0x73ff, read8_delegate(*this, FUNC(cvs_state::hero_prot_r)));
m_maincpu->space(AS_PROGRAM).install_read_handler(0x73f0, 0x73ff, read8sm_delegate(*this, FUNC(cvs_state::hero_prot_r)));
}

112
src/mame/drivers/cxhumax.cpp
View File

@ -34,7 +34,7 @@ static inline void ATTR_PRINTF(3,4) verboselog( device_t &device, int n_level, c
}
}
READ32_MEMBER ( cxhumax_state::cx_gxa_r )
uint32_t cxhumax_state::cx_gxa_r(offs_t offset)
{
uint32_t res = m_gxa_cmd_regs[offset];
verboselog(*this, 9, "(GXA) %08X -> %08X\n", 0xE0600000 + (offset << 2), res);
@ -58,7 +58,7 @@ READ32_MEMBER ( cxhumax_state::cx_gxa_r )
return res;
}
WRITE32_MEMBER( cxhumax_state::cx_gxa_w )
void cxhumax_state::cx_gxa_w(offs_t offset, uint32_t data, uint32_t mem_mask)
{
verboselog(*this, 9, "(GXA) %08X <- %08X\n", 0xE0600000 + (offset << 2), data);
uint8_t gxa_command_number = (offset >> 9) & 0x7F;
@ -116,7 +116,7 @@ WRITE32_MEMBER( cxhumax_state::cx_gxa_w )
}
}
WRITE32_MEMBER ( cxhumax_state::flash_w )
void cxhumax_state::flash_w(offs_t offset, uint32_t data, uint32_t mem_mask)
{
offset *= 2;
if(ACCESSING_BITS_0_15)
@ -126,7 +126,7 @@ WRITE32_MEMBER ( cxhumax_state::flash_w )
verboselog(*this, 9, "(FLASH) %08X <- %08X\n", 0xF0000000 + (offset << 2), data);
}
READ32_MEMBER ( cxhumax_state::flash_r )
uint32_t cxhumax_state::flash_r(offs_t offset, uint32_t mem_mask)
{
uint32_t res = 0;
offset *= 2;
@ -138,12 +138,12 @@ READ32_MEMBER ( cxhumax_state::flash_r )
return res;
}
READ32_MEMBER ( cxhumax_state::dummy_flash_r )
uint32_t cxhumax_state::dummy_flash_r()
{
return 0xFFFFFFFF;
}
WRITE32_MEMBER ( cxhumax_state::cx_remap_w )
void cxhumax_state::cx_remap_w(offs_t offset, uint32_t data)
{
if(!(data&1)) {
verboselog(*this, 9, "(REMAP) %08X -> %08X\n", 0xE0400014 + (offset << 2), data);
@ -151,7 +151,7 @@ WRITE32_MEMBER ( cxhumax_state::cx_remap_w )
}
}
READ32_MEMBER( cxhumax_state::cx_scratch_r )
uint32_t cxhumax_state::cx_scratch_r(offs_t offset)
{
uint32_t data = m_scratch_reg;
verboselog(*this, 9, "(SCRATCH) %08X -> %08X\n", 0xE0400024 + (offset << 2), data);
@ -175,102 +175,102 @@ READ32_MEMBER( cxhumax_state::cx_scratch_r )
return data;
}
WRITE32_MEMBER( cxhumax_state::cx_scratch_w )
void cxhumax_state::cx_scratch_w(offs_t offset, uint32_t data, uint32_t mem_mask)
{
verboselog(*this, 9, "(SCRATCH) %08X <- %08X\n", 0xE0400024 + (offset << 2), data);
COMBINE_DATA(&m_scratch_reg);
}
READ32_MEMBER( cxhumax_state::cx_hsx_r )
uint32_t cxhumax_state::cx_hsx_r(offs_t offset)
{
uint32_t data = 0; // dummy
verboselog(*this, 9, "(HSX) %08X -> %08X\n", 0xE0000000 + (offset << 2), data);
return data;
}
WRITE32_MEMBER( cxhumax_state::cx_hsx_w )
void cxhumax_state::cx_hsx_w(offs_t offset, uint32_t data)
{
verboselog(*this, 9, "(HSX) %08X <- %08X\n", 0xE0000000 + (offset << 2), data);
}
READ32_MEMBER( cxhumax_state::cx_romdescr_r )
uint32_t cxhumax_state::cx_romdescr_r(offs_t offset)
{
uint32_t data = m_romdescr_reg;
verboselog(*this, 9, "(ROMDESC0) %08X -> %08X\n", 0xE0010000 + (offset << 2), data);
return data;
}
WRITE32_MEMBER( cxhumax_state::cx_romdescr_w )
void cxhumax_state::cx_romdescr_w(offs_t offset, uint32_t data, uint32_t mem_mask)
{
verboselog(*this, 9, "(ROMDESC0) %08X <- %08X\n", 0xE0010000 + (offset << 2), data);
COMBINE_DATA(&m_romdescr_reg);
}
READ32_MEMBER( cxhumax_state::cx_isaromdescr_r )
uint32_t cxhumax_state::cx_isaromdescr_r(offs_t offset)
{
uint32_t data = m_isaromdescr_regs[offset];
verboselog(*this, 9, "(ISAROMDESC%d) %08X -> %08X\n", offset+1, 0xE0010004 + (offset << 2), data);
return data;
}
WRITE32_MEMBER( cxhumax_state::cx_isaromdescr_w )
void cxhumax_state::cx_isaromdescr_w(offs_t offset, uint32_t data, uint32_t mem_mask)
{
verboselog(*this, 9, "(ISAROMDESC%d) %08X <- %08X\n", offset+1, 0xE0010004 + (offset << 2), data);
COMBINE_DATA(&m_isaromdescr_regs[offset]);
}
READ32_MEMBER( cxhumax_state::cx_isadescr_r )
uint32_t cxhumax_state::cx_isadescr_r(offs_t offset)
{
uint32_t data = m_isaromdescr_regs[offset];
verboselog(*this, 9, "(ISA_DESC%d) %08X -> %08X\n", offset+4, 0xE0010010 + (offset << 2), data);
return data;
}
WRITE32_MEMBER( cxhumax_state::cx_isadescr_w )
void cxhumax_state::cx_isadescr_w(offs_t offset, uint32_t data, uint32_t mem_mask)
{
verboselog(*this, 9, "(ISA_DESC%d) %08X <- %08X\n", offset+4, 0xE0010010 + (offset << 2), data);
COMBINE_DATA(&m_isaromdescr_regs[offset]);
}
READ32_MEMBER( cxhumax_state::cx_rommap_r )
uint32_t cxhumax_state::cx_rommap_r(offs_t offset)
{
uint32_t data = 0;
verboselog(*this, 9, "(ROM%d_MAP) %08X -> %08X\n", offset, 0xE0010020 + (offset << 2), data);
return data;
}
WRITE32_MEMBER( cxhumax_state::cx_rommap_w )
void cxhumax_state::cx_rommap_w(offs_t offset, uint32_t data)
{
verboselog(*this, 9, "(ROM%d_MAP) %08X <- %08X\n", offset, 0xE0010020 + (offset << 2), data);
}
READ32_MEMBER( cxhumax_state::cx_rommode_r )
uint32_t cxhumax_state::cx_rommode_r(offs_t offset)
{
uint32_t data = m_rommode_reg;
verboselog(*this, 9, "(ROMMODE) %08X -> %08X\n", 0xE0010034 + (offset << 2), data);
return data;
}
WRITE32_MEMBER( cxhumax_state::cx_rommode_w )
void cxhumax_state::cx_rommode_w(offs_t offset, uint32_t data, uint32_t mem_mask)
{
verboselog(*this, 9, "(ROMMODE) %08X <- %08X\n", 0xE0010034 + (offset << 2), data);
COMBINE_DATA(&m_rommode_reg);
}
READ32_MEMBER( cxhumax_state::cx_xoemask_r )
uint32_t cxhumax_state::cx_xoemask_r(offs_t offset)
{
uint32_t data = m_xoemask_reg;
verboselog(*this, 9, "(XOEMASK) %08X -> %08X\n", 0xE0010034 + (offset << 2), data);
return data;
}
WRITE32_MEMBER( cxhumax_state::cx_xoemask_w )
void cxhumax_state::cx_xoemask_w(offs_t offset, uint32_t data, uint32_t mem_mask)
{
verboselog(*this, 9, "(XOEMASK) %08X <- %08X\n", 0xE0010034 + (offset << 2), data);
COMBINE_DATA(&m_xoemask_reg);
}
READ32_MEMBER( cxhumax_state::cx_pci_r )
uint32_t cxhumax_state::cx_pci_r(offs_t offset)
{
uint32_t data = 0;
switch (offset) {
@ -288,20 +288,20 @@ READ32_MEMBER( cxhumax_state::cx_pci_r )
return data;
}
WRITE32_MEMBER( cxhumax_state::cx_pci_w )
void cxhumax_state::cx_pci_w(offs_t offset, uint32_t data, uint32_t mem_mask)
{
verboselog(*this, 9, "(PCI) %08X <- %08X\n", 0xE0010040 + (offset << 2), data);
COMBINE_DATA(&m_pci_regs[offset]);
}
READ32_MEMBER( cxhumax_state::cx_extdesc_r )
uint32_t cxhumax_state::cx_extdesc_r(offs_t offset)
{
uint32_t data = m_extdesc_regs[offset];
verboselog(*this, 9, "(EXTDESC) %08X -> %08X\n", 0xE0010080 + (offset << 2), data);
return data;
}
WRITE32_MEMBER( cxhumax_state::cx_extdesc_w )
void cxhumax_state::cx_extdesc_w(offs_t offset, uint32_t data, uint32_t mem_mask)
{
verboselog(*this, 9, "(EXTDESC) %08X <- %08X\n", 0xE0010080 + (offset << 2), data);
COMBINE_DATA(&m_extdesc_regs[offset]);
@ -334,7 +334,7 @@ TIMER_CALLBACK_MEMBER(cxhumax_state::timer_tick)
m_timer_regs.timer[param].timer->adjust(period,param);
}
READ32_MEMBER( cxhumax_state::cx_timers_r )
uint32_t cxhumax_state::cx_timers_r(offs_t offset)
{
uint32_t data = 0;
uint8_t index = offset>>2;
@ -359,7 +359,7 @@ READ32_MEMBER( cxhumax_state::cx_timers_r )
return data;
}
WRITE32_MEMBER( cxhumax_state::cx_timers_w )
void cxhumax_state::cx_timers_w(offs_t offset, uint32_t data, uint32_t mem_mask)
{
uint8_t index = offset>>2;
if(index==16) {
@ -391,7 +391,7 @@ WRITE32_MEMBER( cxhumax_state::cx_timers_w )
}
}
READ32_MEMBER( cxhumax_state::cx_uart2_r )
uint32_t cxhumax_state::cx_uart2_r(offs_t offset)
{
uint32_t data;
switch (offset) {
@ -405,7 +405,7 @@ READ32_MEMBER( cxhumax_state::cx_uart2_r )
return data;
}
WRITE32_MEMBER( cxhumax_state::cx_uart2_w )
void cxhumax_state::cx_uart2_w(offs_t offset, uint32_t data, uint32_t mem_mask)
{
verboselog(*this, 9, "(UART2) %08X <- %08X\n", 0xE0411000 + (offset << 2), data);
switch (offset) {
@ -432,66 +432,66 @@ WRITE32_MEMBER( cxhumax_state::cx_uart2_w )
}
}
READ32_MEMBER( cxhumax_state::cx_pll_r )
uint32_t cxhumax_state::cx_pll_r(offs_t offset)
{
uint32_t data = m_pll_regs[offset];
verboselog(*this, 9, "(PLL) %08X -> %08X\n", 0xE0440000 + (offset << 2), data);
return data;
}
WRITE32_MEMBER( cxhumax_state::cx_pll_w )
void cxhumax_state::cx_pll_w(offs_t offset, uint32_t data, uint32_t mem_mask)
{
verboselog(*this, 9, "(PLL) %08X <- %08X\n", 0xE0440000 + (offset << 2), data);
COMBINE_DATA(&m_pll_regs[offset]);
}
READ32_MEMBER( cxhumax_state::cx_pllprescale_r )
uint32_t cxhumax_state::cx_pllprescale_r(offs_t offset)
{
uint32_t data = m_pllprescale_reg;
verboselog(*this, 9, "(PLLPRESCALE) %08X -> %08X\n", 0xE0440094 + (offset << 2), data);
return data;
}
WRITE32_MEMBER( cxhumax_state::cx_pllprescale_w )
void cxhumax_state::cx_pllprescale_w(offs_t offset, uint32_t data, uint32_t mem_mask)
{
verboselog(*this, 9, "(PLLPRESCALE) %08X <- %08X\n", 0xE0440094 + (offset << 2), data);
COMBINE_DATA(&m_pllprescale_reg);
}
READ32_MEMBER( cxhumax_state::cx_clkdiv_r )
uint32_t cxhumax_state::cx_clkdiv_r(offs_t offset)
{
uint32_t data = m_clkdiv_regs[offset];
verboselog(*this, 9, "(CLKDIV) %08X -> %08X\n", 0xE0440020 + (offset << 2), data);
return data;
}
WRITE32_MEMBER( cxhumax_state::cx_clkdiv_w )
void cxhumax_state::cx_clkdiv_w(offs_t offset, uint32_t data, uint32_t mem_mask)
{
verboselog(*this, 9, "(CLKDIV) %08X <- %08X\n", 0xE0440020 + (offset << 2), data);
COMBINE_DATA(&m_clkdiv_regs[offset]);
}
READ32_MEMBER( cxhumax_state::cx_chipcontrol_r )
uint32_t cxhumax_state::cx_chipcontrol_r(offs_t offset)
{
uint32_t data = m_chipcontrol_regs[offset];
verboselog(*this, 9, "(CHIPCONTROL) %08X -> %08X\n", 0xE0440100 + (offset << 2), data);
return data;
}
WRITE32_MEMBER( cxhumax_state::cx_chipcontrol_w )
void cxhumax_state::cx_chipcontrol_w(offs_t offset, uint32_t data, uint32_t mem_mask)
{
verboselog(*this, 9, "(CHIPCONTROL) %08X <- %08X\n", 0xE0440100 + (offset << 2), data);
COMBINE_DATA(&m_chipcontrol_regs[offset]);
}
READ32_MEMBER( cxhumax_state::cx_intctrl_r )
uint32_t cxhumax_state::cx_intctrl_r(offs_t offset)
{
uint32_t data = m_intctrl_regs[offset];
verboselog(*this, 9, "(INTCTRL) %08X -> %08X\n", 0xE0450000 + (offset << 2), data);
return data;
}
WRITE32_MEMBER( cxhumax_state::cx_intctrl_w )
void cxhumax_state::cx_intctrl_w(offs_t offset, uint32_t data, uint32_t mem_mask)
{
verboselog(*this, 9, "(INTCTRL) %08X <- %08X\n", 0xE0450000 + (offset << 2), data);
switch (offset >> 3) { // Decode the group
@ -559,7 +559,7 @@ WRITE32_MEMBER( cxhumax_state::cx_intctrl_w )
}
READ32_MEMBER( cxhumax_state::cx_ss_r )
uint32_t cxhumax_state::cx_ss_r(offs_t offset)
{
uint32_t data = 0;
switch(offset) {
@ -574,7 +574,7 @@ READ32_MEMBER( cxhumax_state::cx_ss_r )
return data;
}
WRITE32_MEMBER( cxhumax_state::cx_ss_w )
void cxhumax_state::cx_ss_w(offs_t offset, uint32_t data, uint32_t mem_mask)
{
verboselog(*this, 9, "(SS) %08X <- %08X\n", 0xE0490000 + (offset << 2), data);
switch(offset) {
@ -617,14 +617,14 @@ WRITE32_MEMBER( cxhumax_state::cx_ss_w )
};
}
READ32_MEMBER( cxhumax_state::cx_i2c0_r )
uint32_t cxhumax_state::cx_i2c0_r(offs_t offset)
{
uint32_t data = m_i2c0_regs[offset];
verboselog(*this, 9, "(I2C0) %08X -> %08X\n", 0xE04E0000 + (offset << 2), data);
return data;
}
WRITE32_MEMBER( cxhumax_state::cx_i2c0_w )
void cxhumax_state::cx_i2c0_w(offs_t offset, uint32_t data, uint32_t mem_mask)
{
verboselog(*this, 9, "(I2C0) %08X <- %08X\n", 0xE04E0000 + (offset << 2), data);
COMBINE_DATA(&m_i2c0_regs[offset]);
@ -678,7 +678,7 @@ void cxhumax_state::i2cmem_stop()
m_i2cmem->write_scl(0);
}
READ32_MEMBER( cxhumax_state::cx_i2c1_r )
uint32_t cxhumax_state::cx_i2c1_r(offs_t offset)
{
uint32_t data=0;
switch(offset) {
@ -692,7 +692,7 @@ READ32_MEMBER( cxhumax_state::cx_i2c1_r )
return data;
}
WRITE32_MEMBER( cxhumax_state::cx_i2c1_w )
void cxhumax_state::cx_i2c1_w(offs_t offset, uint32_t data, uint32_t mem_mask)
{
verboselog(*this, 9, "(I2C1) %08X <- %08X\n", 0xE04E1000 + (offset << 2), data);
switch(offset) {
@ -751,33 +751,33 @@ WRITE32_MEMBER( cxhumax_state::cx_i2c1_w )
}
}
READ32_MEMBER( cxhumax_state::cx_i2c2_r )
uint32_t cxhumax_state::cx_i2c2_r(offs_t offset)
{
uint32_t data = m_i2c2_regs[offset];
verboselog(*this, 9, "(I2C2) %08X -> %08X\n", 0xE04E2000 + (offset << 2), data);
return data;
}
WRITE32_MEMBER( cxhumax_state::cx_i2c2_w )
void cxhumax_state::cx_i2c2_w(offs_t offset, uint32_t data, uint32_t mem_mask)
{
verboselog(*this, 9, "(I2C2) %08X <- %08X\n", 0xE04E2000 + (offset << 2), data);
COMBINE_DATA(&m_i2c2_regs[offset]);
}
READ32_MEMBER( cxhumax_state::cx_mc_cfg_r )
uint32_t cxhumax_state::cx_mc_cfg_r(offs_t offset)
{
uint32_t data = m_mccfg_regs[offset];
verboselog(*this, 9, "(MC_CFG) %08X -> %08X\n", 0xE0500300 + (offset << 2), data);
return data;
}
WRITE32_MEMBER( cxhumax_state::cx_mc_cfg_w )
void cxhumax_state::cx_mc_cfg_w(offs_t offset, uint32_t data, uint32_t mem_mask)
{
verboselog(*this, 9, "(MC_CFG) %08X <- %08X\n", 0xE0500300 + (offset << 2), data);
COMBINE_DATA(&m_mccfg_regs[offset]);
}
READ32_MEMBER( cxhumax_state::cx_drm0_r )
uint32_t cxhumax_state::cx_drm0_r(offs_t offset)
{
uint32_t data = m_drm0_regs[offset];
verboselog(*this, 9, "(DRM0) %08X -> %08X\n", 0xE0560000 + (offset << 2), data);
@ -789,33 +789,33 @@ READ32_MEMBER( cxhumax_state::cx_drm0_r )
return data;
}
WRITE32_MEMBER( cxhumax_state::cx_drm0_w )
void cxhumax_state::cx_drm0_w(offs_t offset, uint32_t data, uint32_t mem_mask)
{
verboselog(*this, 9, "(DRM0) %08X <- %08X\n", 0xE0560000 + (offset << 2), data);
COMBINE_DATA(&m_drm0_regs[offset]);
}
READ32_MEMBER( cxhumax_state::cx_drm1_r )
uint32_t cxhumax_state::cx_drm1_r(offs_t offset)
{
uint32_t data = m_drm1_regs[offset];
verboselog(*this, 9, "(DRM1) %08X -> %08X\n", 0xE0570000 + (offset << 2), data);
return data;
}
WRITE32_MEMBER( cxhumax_state::cx_drm1_w )
void cxhumax_state::cx_drm1_w(offs_t offset, uint32_t data, uint32_t mem_mask)
{
verboselog(*this, 9, "(DRM1) %08X <- %08X\n", 0xE0570000 + (offset << 2), data);
COMBINE_DATA(&m_drm1_regs[offset]);
}
READ32_MEMBER( cxhumax_state::cx_hdmi_r )
uint32_t cxhumax_state::cx_hdmi_r(offs_t offset)
{
uint32_t data = m_hdmi_regs[offset];
verboselog(*this, 9, "(HDMI) %08X -> %08X\n", 0xE05D0800 + (offset << 2), data);
return data;
}
WRITE32_MEMBER( cxhumax_state::cx_hdmi_w )
void cxhumax_state::cx_hdmi_w(offs_t offset, uint32_t data, uint32_t mem_mask)
{
verboselog(*this, 9, "(HDMI) %08X <- %08X\n", 0xE05D0800 + (offset << 2), data);
switch(offset) {

4
src/mame/drivers/cyberbal.cpp
View File

@ -90,7 +90,7 @@ void cyberbal2p_state::machine_reset()
*
*************************************/
READ16_MEMBER(cyberbal2p_state::sound_state_r)
uint16_t cyberbal2p_state::sound_state_r()
{
int temp = 0xffff;
if (m_jsa->main_to_sound_ready()) temp ^= 0xffff;
@ -105,7 +105,7 @@ READ16_MEMBER(cyberbal2p_state::sound_state_r)
*
*************************************/
WRITE16_MEMBER(cyberbal_state::p2_reset_w)
void cyberbal_state::p2_reset_w(uint16_t data)
{
m_extracpu->set_input_line(INPUT_LINE_RESET, CLEAR_LINE);
}

18
src/mame/drivers/cybiko.cpp
View File

@ -118,12 +118,12 @@ void cybiko_state::cybikoxt_mem(address_map &map)
map(0xe00000, 0xefffff).r(FUNC(cybiko_state::cybikoxt_key_r));
}
WRITE16_MEMBER(cybiko_state::serflash_w)
void cybiko_state::serflash_w(uint16_t data)
{
m_flash1->cs_w ((data & 0x10) ? 0 : 1);
}
READ16_MEMBER(cybiko_state::clock_r)
uint16_t cybiko_state::clock_r()
{
if (m_rtc->sda_r())
{
@ -133,13 +133,13 @@ READ16_MEMBER(cybiko_state::clock_r)
return 0x04;
}
WRITE16_MEMBER(cybiko_state::clock_w)
void cybiko_state::clock_w(uint16_t data)
{
m_rtc->scl_w((data & 0x02) ? 1 : 0);
m_rtc->sda_w((data & 0x01) ? 0 : 1);
}
READ16_MEMBER(cybiko_state::xtclock_r)
uint16_t cybiko_state::xtclock_r()
{
if (m_rtc->sda_r())
{
@ -149,30 +149,30 @@ READ16_MEMBER(cybiko_state::xtclock_r)
return 0;
}
WRITE16_MEMBER(cybiko_state::xtclock_w)
void cybiko_state::xtclock_w(uint16_t data)
{
m_rtc->scl_w((data & 0x02) ? 1 : 0);
m_rtc->sda_w((data & 0x40) ? 0 : 1);
}
READ16_MEMBER(cybiko_state::xtpower_r)
uint16_t cybiko_state::xtpower_r()
{
// bit 7 = on/off button
// bit 6 = battery charged if "1"
return 0xc0;
}
READ16_MEMBER(cybiko_state::adc1_r)
uint16_t cybiko_state::adc1_r()
{
return 0x01;
}
READ16_MEMBER(cybiko_state::adc2_r)
uint16_t cybiko_state::adc2_r()
{
return 0x00;
}
READ16_MEMBER(cybiko_state::port0_r)
uint16_t cybiko_state::port0_r()
{
// bit 3 = on/off button
return 0x08;

4
src/mame/drivers/cybstorm.cpp
View File

@ -44,13 +44,13 @@ void cybstorm_state::machine_start()
*
*************************************/
READ32_MEMBER(cybstorm_state::special_port1_r)
uint32_t cybstorm_state::special_port1_r()
{
return ioport("9F0010")->read();
}
WRITE32_MEMBER(cybstorm_state::latch_w)
void cybstorm_state::latch_w(offs_t offset, uint32_t data, uint32_t mem_mask)
{
uint32_t oldword = m_latch_data;
COMBINE_DATA(&m_latch_data);

2
src/mame/drivers/darkmist.cpp
View File

@ -38,7 +38,7 @@ void darkmist_state::machine_start()
membank("bank1")->configure_entries(0, 2, memregion("maincpu")->base() + 0x10000, 0x4000);
}
WRITE8_MEMBER(darkmist_state::hw_w)
void darkmist_state::hw_w(uint8_t data)
{
m_hw=data;
membank("bank1")->set_entry((data&0x80)?1:0);

2
src/mame/drivers/darkseal.cpp
View File

@ -31,7 +31,7 @@
/******************************************************************************/
WRITE16_MEMBER(darkseal_state::irq_ack_w)
void darkseal_state::irq_ack_w(uint16_t data)
{
m_maincpu->set_input_line(M68K_IRQ_6, CLEAR_LINE);
}

12
src/mame/drivers/dassault.cpp
View File

@ -222,22 +222,22 @@ TODO:
/**********************************************************************************/
WRITE16_MEMBER(dassault_state::priority_w)
void dassault_state::priority_w(offs_t offset, uint16_t data, uint16_t mem_mask)
{
COMBINE_DATA(&m_priority);
}
WRITE16_MEMBER(dassault_state::main_irq_ack_w)
void dassault_state::main_irq_ack_w(uint16_t data)
{
m_maincpu->set_input_line(M68K_IRQ_4, CLEAR_LINE);
}
WRITE16_MEMBER(dassault_state::sub_irq_ack_w)
void dassault_state::sub_irq_ack_w(uint16_t data)
{
m_subcpu->set_input_line(M68K_IRQ_5, CLEAR_LINE);
}
READ16_MEMBER(dassault_state::dassault_control_r)
uint16_t dassault_state::dassault_control_r(offs_t offset)
{
switch (offset << 1)
{
@ -260,14 +260,14 @@ READ16_MEMBER(dassault_state::dassault_control_r)
return 0xffff;
}
WRITE16_MEMBER(dassault_state::dassault_control_w)
void dassault_state::dassault_control_w(uint16_t data)
{
machine().bookkeeping().coin_counter_w(0, data & 1);
if (data & 0xfffe)
logerror("Coin cointrol %04x\n", data);
}
READ16_MEMBER(dassault_state::dassault_sub_control_r)
uint16_t dassault_state::dassault_sub_control_r()
{
return ioport("VBLANK1")->read();
}

8
src/mame/drivers/dbz.cpp
View File

@ -74,13 +74,13 @@ TIMER_DEVICE_CALLBACK_MEMBER(dbz_state::dbz_scanline)
}
#if 0
READ16_MEMBER(dbz_state::dbzcontrol_r)
uint16_t dbz_state::dbzcontrol_r()
{
return m_control;
}
#endif
WRITE16_MEMBER(dbz_state::dbzcontrol_w)
void dbz_state::dbzcontrol_w(offs_t offset, uint16_t data, uint16_t mem_mask)
{
/* bit 10 = enable '246 readback */
@ -95,12 +95,12 @@ WRITE16_MEMBER(dbz_state::dbzcontrol_w)
machine().bookkeeping().coin_counter_w(1, data & 2);
}
WRITE16_MEMBER(dbz_state::dbz_sound_command_w)
void dbz_state::dbz_sound_command_w(uint16_t data)
{
m_soundlatch->write(data >> 8);
}
WRITE16_MEMBER(dbz_state::dbz_sound_cause_nmi)
void dbz_state::dbz_sound_cause_nmi(uint16_t data)
{
m_audiocpu->pulse_input_line(INPUT_LINE_NMI, attotime::zero);
}

16
src/mame/drivers/dccons.cpp
View File

@ -278,7 +278,7 @@
#define CPU_CLOCK (200000000)
READ64_MEMBER(dc_cons_state::dcus_idle_skip_r )
uint64_t dc_cons_state::dcus_idle_skip_r()
{
//if (m_maincpu->pc()==0xc0ba52a)
// m_maincpu->spin_until_time(attotime::from_usec(2500));
@ -287,7 +287,7 @@ READ64_MEMBER(dc_cons_state::dcus_idle_skip_r )
return dc_ram[0x2303b0/8];
}
READ64_MEMBER(dc_cons_state::dcjp_idle_skip_r )
uint64_t dc_cons_state::dcjp_idle_skip_r()
{
//if (m_maincpu->pc()==0xc0bac62)
// m_maincpu->spin_until_time(attotime::from_usec(2500));
@ -306,14 +306,14 @@ void dc_cons_state::init_dc()
void dc_cons_state::init_dcus()
{
m_maincpu->space(AS_PROGRAM).install_read_handler(0xc2303b0, 0xc2303b7, read64_delegate(*this, FUNC(dc_cons_state::dcus_idle_skip_r)));
m_maincpu->space(AS_PROGRAM).install_read_handler(0xc2303b0, 0xc2303b7, read64smo_delegate(*this, FUNC(dc_cons_state::dcus_idle_skip_r)));
init_dc();
}
void dc_cons_state::init_dcjp()
{
m_maincpu->space(AS_PROGRAM).install_read_handler(0xc2302f8, 0xc2302ff, read64_delegate(*this, FUNC(dc_cons_state::dcjp_idle_skip_r)));
m_maincpu->space(AS_PROGRAM).install_read_handler(0xc2302f8, 0xc2302ff, read64smo_delegate(*this, FUNC(dc_cons_state::dcjp_idle_skip_r)));
init_dc();
}
@ -330,7 +330,7 @@ void dc_cons_state::init_tream()
init_dcus();
}
READ64_MEMBER(dc_cons_state::dc_pdtra_r )
uint64_t dc_cons_state::dc_pdtra_r()
{
uint64_t out = PCTRA<<32;
@ -360,18 +360,18 @@ READ64_MEMBER(dc_cons_state::dc_pdtra_r )
return out;
}
WRITE64_MEMBER(dc_cons_state::dc_pdtra_w )
void dc_cons_state::dc_pdtra_w(uint64_t data)
{
PCTRA = (data>>16) & 0xffff;
PDTRA = (data & 0xffff);
}
READ8_MEMBER(dc_cons_state::dc_flash_r)
uint8_t dc_cons_state::dc_flash_r(offs_t offset)
{
return m_dcflash->read(offset+0x20000);
}
WRITE8_MEMBER(dc_cons_state::dc_flash_w)
void dc_cons_state::dc_flash_w(offs_t offset, uint8_t data)
{
m_dcflash->write(offset+0x20000,data);
}

10
src/mame/drivers/dcheese.cpp
View File

@ -58,7 +58,7 @@ void dcheese_state::update_irq_state()
}
uint8_t dcheese_state::iack_r(offs_t offset)
u8 dcheese_state::iack_r(offs_t offset)
{
if (!machine().side_effects_disabled())
{
@ -111,7 +111,7 @@ void dcheese_state::machine_start()
*
*************************************/
WRITE16_MEMBER(dcheese_state::eeprom_control_w)
void dcheese_state::eeprom_control_w(offs_t offset, u16 data, u16 mem_mask)
{
/* toggles bit $0100 very frequently while waiting for things */
/* bits $0080-$0010 are probably lamps */
@ -129,14 +129,14 @@ WRITE16_MEMBER(dcheese_state::eeprom_control_w)
*
*************************************/
READ8_MEMBER(dcheese_state::sound_status_r)
u8 dcheese_state::sound_status_r()
{
/* seems to be ready signal on BSMT or latching hardware */
return m_bsmt->read_status() << 7;
}
WRITE8_MEMBER(dcheese_state::sound_control_w)
void dcheese_state::sound_control_w(u8 data)
{
u8 const diff = data ^ m_sound_control;
m_sound_control = data;
@ -150,7 +150,7 @@ WRITE8_MEMBER(dcheese_state::sound_control_w)
}
WRITE8_MEMBER(dcheese_state::bsmt_data_w)
void dcheese_state::bsmt_data_w(offs_t offset, u8 data)
{
/* writes come in pairs; even bytes latch, odd bytes write */
if ((offset & 1) == 0)

26
src/mame/drivers/ddragon.cpp
View File

@ -165,7 +165,7 @@ MACHINE_RESET_MEMBER(ddragon_state,ddragon)
*
*************************************/
WRITE8_MEMBER(ddragon_state::ddragon_bankswitch_w)
void ddragon_state::ddragon_bankswitch_w(uint8_t data)
{
/*
76543210
@ -186,7 +186,7 @@ WRITE8_MEMBER(ddragon_state::ddragon_bankswitch_w)
}
WRITE8_MEMBER(toffy_state::toffy_bankswitch_w)
void toffy_state::toffy_bankswitch_w(uint8_t data)
{
m_scrollx_hi = data & 0x01;
m_scrolly_hi = (data & 0x02) >> 1;
@ -198,7 +198,7 @@ WRITE8_MEMBER(toffy_state::toffy_bankswitch_w)
}
READ8_MEMBER(darktowr_state::darktowr_mcu_bank_r)
uint8_t darktowr_state::darktowr_mcu_bank_r(offs_t offset)
{
// logerror("BankRead %05x %08x\n",m_maincpu->pc(),offset);
@ -226,7 +226,7 @@ READ8_MEMBER(darktowr_state::darktowr_mcu_bank_r)
}
WRITE8_MEMBER(darktowr_state::darktowr_mcu_bank_w)
void darktowr_state::darktowr_mcu_bank_w(offs_t offset, uint8_t data)
{
logerror("BankWrite %05x %08x %08x\n", m_maincpu->pc(), offset, data);
@ -239,7 +239,7 @@ WRITE8_MEMBER(darktowr_state::darktowr_mcu_bank_w)
}
WRITE8_MEMBER(darktowr_state::darktowr_bankswitch_w)
void darktowr_state::darktowr_bankswitch_w(uint8_t data)
{
m_scrollx_hi = (data & 0x01);
m_scrolly_hi = ((data & 0x02) >> 1);
@ -288,26 +288,26 @@ void ddragon_state::ddragon_interrupt_ack(offs_t offset, uint8_t data)
}
READ8_MEMBER(ddragon_state::ddragon_interrupt_r)
uint8_t ddragon_state::ddragon_interrupt_r(offs_t offset)
{
ddragon_interrupt_ack(offset, 0xff);
return 0xff;
}
WRITE8_MEMBER(ddragon_state::ddragon_interrupt_w)
void ddragon_state::ddragon_interrupt_w(offs_t offset, uint8_t data)
{
ddragon_interrupt_ack(offset, data);
}
WRITE8_MEMBER(ddragon_state::ddragon2_sub_irq_ack_w)
void ddragon_state::ddragon2_sub_irq_ack_w(uint8_t data)
{
m_subcpu->set_input_line(m_sprite_irq, CLEAR_LINE);
}
WRITE8_MEMBER(ddragon_state::ddragon2_sub_irq_w)
void ddragon_state::ddragon2_sub_irq_w(uint8_t data)
{
m_maincpu->set_input_line(M6809_IRQ_LINE, ASSERT_LINE);
}
@ -369,7 +369,7 @@ void ddragon_state::sub_port6_w(uint8_t data)
*
*************************************/
READ8_MEMBER(ddragon_state::ddragon_comram_r)
uint8_t ddragon_state::ddragon_comram_r(offs_t offset)
{
// Access to shared RAM is prevented when the sub CPU is active
if (!m_subcpu->suspended(SUSPEND_REASON_RESET | SUSPEND_REASON_HALT))
@ -379,7 +379,7 @@ READ8_MEMBER(ddragon_state::ddragon_comram_r)
}
WRITE8_MEMBER(ddragon_state::ddragon_comram_w)
void ddragon_state::ddragon_comram_w(offs_t offset, uint8_t data)
{
if (!m_subcpu->suspended(SUSPEND_REASON_RESET | SUSPEND_REASON_HALT))
return;
@ -395,7 +395,7 @@ WRITE8_MEMBER(ddragon_state::ddragon_comram_w)
*
*************************************/
WRITE8_MEMBER(ddragon_state::dd_adpcm_w)
void ddragon_state::dd_adpcm_w(offs_t offset, uint8_t data)
{
int chip = offset & 1;
@ -451,7 +451,7 @@ WRITE_LINE_MEMBER(ddragon_state::dd_adpcm_int_2)
}
READ8_MEMBER(ddragon_state::dd_adpcm_status_r)
uint8_t ddragon_state::dd_adpcm_status_r()
{
return (m_adpcm_idle[0] ? 1 : 0) | (m_adpcm_idle[1] ? 2 : 0);
}

20
src/mame/drivers/ddragon3.cpp
View File

@ -198,39 +198,39 @@ ROMs (All ROMs are 27C010 EPROM. - means not populated)
*
*************************************/
WRITE8_MEMBER(ddragon3_state::oki_bankswitch_w)
void ddragon3_state::oki_bankswitch_w(uint8_t data)
{
m_oki->set_rom_bank(data & 1);
}
WRITE16_MEMBER(wwfwfest_state::wwfwfest_soundwrite)
void wwfwfest_state::wwfwfest_soundwrite(uint16_t data)
{
// upper byte is always set to 0x31 for some reason
m_soundlatch->write(data & 0xff);
}
WRITE16_MEMBER(ddragon3_state::ddragon3_vreg_w)
void ddragon3_state::ddragon3_vreg_w(offs_t offset, uint16_t data, uint16_t mem_mask)
{
COMBINE_DATA(&m_vreg);
}
WRITE16_MEMBER(ddragon3_state::irq6_ack_w)
void ddragon3_state::irq6_ack_w(uint16_t data)
{
// this gets written to on startup and at the end of IRQ6
m_maincpu->set_input_line(6, CLEAR_LINE);
}
WRITE16_MEMBER(ddragon3_state::irq5_ack_w)
void ddragon3_state::irq5_ack_w(uint16_t data)
{
// this gets written to on startup and at the end of IRQ5 (input port read)
m_maincpu->set_input_line(5, CLEAR_LINE);
}
WRITE16_MEMBER(wwfwfest_state::wwfwfest_irq_ack_w)
void wwfwfest_state::wwfwfest_irq_ack_w(offs_t offset, uint16_t data)
{
if (offset == 0)
m_maincpu->set_input_line(3, CLEAR_LINE);
@ -239,20 +239,20 @@ WRITE16_MEMBER(wwfwfest_state::wwfwfest_irq_ack_w)
m_maincpu->set_input_line(2, CLEAR_LINE);
}
WRITE16_MEMBER(wwfwfest_state::wwfwfest_flipscreen_w)
void wwfwfest_state::wwfwfest_flipscreen_w(uint16_t data)
{
flip_screen_set(data&1);
}
/*- Palette Reads/Writes - A5 and A6 are not connected */
READ16_MEMBER(wwfwfest_state::wwfwfest_paletteram_r)
uint16_t wwfwfest_state::wwfwfest_paletteram_r(offs_t offset)
{
offset = (offset & 0x000f) | (offset & 0x7fc0) >> 2;
return m_paletteram[offset];
}
WRITE16_MEMBER(wwfwfest_state::wwfwfest_paletteram_w)
void wwfwfest_state::wwfwfest_paletteram_w(offs_t offset, uint16_t data, uint16_t mem_mask)
{
offset = (offset & 0x000f) | (offset & 0x7fc0) >> 2;
m_palette->write16(offset, data, mem_mask);
@ -261,7 +261,7 @@ WRITE16_MEMBER(wwfwfest_state::wwfwfest_paletteram_w)
/*- Priority Control -*/
WRITE8_MEMBER(wwfwfest_state::wwfwfest_priority_w)
void wwfwfest_state::wwfwfest_priority_w(uint8_t data)
{
m_pri = data;
}

12
src/mame/drivers/ddribble.cpp
View File

@ -32,33 +32,33 @@ WRITE_LINE_MEMBER(ddribble_state::vblank_irq)
}
WRITE8_MEMBER(ddribble_state::ddribble_bankswitch_w)
void ddribble_state::ddribble_bankswitch_w(uint8_t data)
{
membank("bank1")->set_entry(data & 0x07);
}
READ8_MEMBER(ddribble_state::ddribble_sharedram_r)
uint8_t ddribble_state::ddribble_sharedram_r(offs_t offset)
{
return m_sharedram[offset];
}
WRITE8_MEMBER(ddribble_state::ddribble_sharedram_w)
void ddribble_state::ddribble_sharedram_w(offs_t offset, uint8_t data)
{
m_sharedram[offset] = data;
}
READ8_MEMBER(ddribble_state::ddribble_snd_sharedram_r)
uint8_t ddribble_state::ddribble_snd_sharedram_r(offs_t offset)
{
return m_snd_sharedram[offset];
}
WRITE8_MEMBER(ddribble_state::ddribble_snd_sharedram_w)
void ddribble_state::ddribble_snd_sharedram_w(offs_t offset, uint8_t data)
{
m_snd_sharedram[offset] = data;
}
WRITE8_MEMBER(ddribble_state::ddribble_coin_counter_w)
void ddribble_state::ddribble_coin_counter_w(uint8_t data)
{
/* b4-b7: unused */
/* b2-b3: unknown */

8
src/mame/drivers/deadang.cpp
View File

@ -56,11 +56,11 @@ Dip locations and factory settings verified with US manual
/* Read/Write Handlers */
READ16_MEMBER(deadang_state::ghunter_trackball_low_r)
uint16_t deadang_state::ghunter_trackball_low_r()
{
return (ioport("TRACKX")->read() & 0xff) | ((ioport("TRACKY")->read() & 0xff) << 8);
}
READ16_MEMBER(deadang_state::ghunter_trackball_high_r)
uint16_t deadang_state::ghunter_trackball_high_r()
{
return ((ioport("TRACKX")->read() & 0x0f00) >> 4) | (ioport("TRACKY")->read() & 0x0f00);
}
@ -733,8 +733,8 @@ void deadang_state::init_ghunter()
m_adpcm1->decrypt();
m_adpcm2->decrypt();
m_maincpu->space(AS_PROGRAM).install_read_handler(0x80000, 0x80001, read16_delegate(*this, FUNC(deadang_state::ghunter_trackball_low_r)));
m_maincpu->space(AS_PROGRAM).install_read_handler(0xb0000, 0xb0001, read16_delegate(*this, FUNC(deadang_state::ghunter_trackball_high_r)));
m_maincpu->space(AS_PROGRAM).install_read_handler(0x80000, 0x80001, read16smo_delegate(*this, FUNC(deadang_state::ghunter_trackball_low_r)));
m_maincpu->space(AS_PROGRAM).install_read_handler(0xb0000, 0xb0001, read16smo_delegate(*this, FUNC(deadang_state::ghunter_trackball_high_r)));
}
/* Game Drivers */

30
src/mame/drivers/dec0.cpp
View File

@ -337,12 +337,12 @@ Notes:
/******************************************************************************/
WRITE16_MEMBER(dec0_state::dec0_control_w)
void dec0_state::dec0_control_w(offs_t offset, uint16_t data, uint16_t mem_mask)
{
switch (offset << 1)
{
case 0: /* Playfield & Sprite priority */
priority_w(space, 0, data, mem_mask);
priority_w(0, data, mem_mask);
break;
case 2: /* DMA flag */
@ -380,7 +380,7 @@ WRITE16_MEMBER(dec0_state::dec0_control_w)
}
}
WRITE16_MEMBER(dec0_automat_state::automat_control_w)
void dec0_automat_state::automat_control_w(offs_t offset, uint16_t data, uint16_t mem_mask)
{
switch (offset << 1)
{
@ -410,7 +410,7 @@ WRITE16_MEMBER(dec0_automat_state::automat_control_w)
}
}
WRITE16_MEMBER(dec0_state::midres_sound_w)
void dec0_state::midres_sound_w(offs_t offset, uint16_t data, uint16_t mem_mask)
{
if (ACCESSING_BITS_0_7)
m_soundlatch->write(data & 0xff);
@ -499,7 +499,7 @@ void dec0_state::hippodrm_sub_map(address_map &map)
}
READ16_MEMBER(dec0_state::slyspy_controls_r)
uint16_t dec0_state::slyspy_controls_r(offs_t offset)
{
switch (offset<<1)
{
@ -518,7 +518,7 @@ READ16_MEMBER(dec0_state::slyspy_controls_r)
}
// TODO: this can be a timer access, maybe video counter returns (and used as RNG in both games)
READ16_MEMBER(dec0_state::slyspy_protection_r)
uint16_t dec0_state::slyspy_protection_r(offs_t offset)
{
switch (offset<<1)
{
@ -571,13 +571,13 @@ READ16_MEMBER(dec0_state::slyspy_protection_r)
*/
WRITE16_MEMBER(dec0_state::slyspy_state_w)
void dec0_state::slyspy_state_w(uint16_t data)
{
m_slyspy_state = 0;
m_pfprotect->set_bank(m_slyspy_state);
}
READ16_MEMBER(dec0_state::slyspy_state_r)
uint16_t dec0_state::slyspy_state_r()
{
m_slyspy_state = (m_slyspy_state + 1) % 4;
m_pfprotect->set_bank(m_slyspy_state);
@ -703,7 +703,7 @@ void dec0_state::slyspy_s_map(address_map &map)
// Sly Spy sound state protection machine emulation
// similar to the video state machine
// current bank is at 0x1f0045, incremented by 1 then here is read
READ8_MEMBER(dec0_state::slyspy_sound_state_r)
uint8_t dec0_state::slyspy_sound_state_r()
{
m_slyspy_sound_state ++;
m_slyspy_sound_state &= 3;
@ -713,7 +713,7 @@ READ8_MEMBER(dec0_state::slyspy_sound_state_r)
return 0xff;
}
READ8_MEMBER(dec0_state::slyspy_sound_state_reset_r)
uint8_t dec0_state::slyspy_sound_state_reset_r()
{
m_slyspy_sound_state = 0;
m_sndprotect->set_bank(m_slyspy_sound_state);
@ -774,13 +774,13 @@ void dec0_automat_state::machine_start()
/* swizzle the palette writes around so we can use the same gfx plane ordering as the originals */
READ16_MEMBER( dec0_automat_state::automat_palette_r )
uint16_t dec0_automat_state::automat_palette_r(offs_t offset)
{
offset ^=0xf;
return m_paletteram[offset];
}
WRITE16_MEMBER( dec0_automat_state::automat_palette_w )
void dec0_automat_state::automat_palette_w(offs_t offset, uint16_t data, uint16_t mem_mask)
{
offset ^=0xf;
m_palette->write16(offset, data, mem_mask);
@ -1821,7 +1821,7 @@ void dec0_state::dec1(machine_config &config)
}
WRITE8_MEMBER(dec0_automat_state::sound_bankswitch_w)
void dec0_automat_state::sound_bankswitch_w(uint8_t data)
{
m_msm[0]->reset_w(BIT(data, 3));
m_msm[1]->reset_w(BIT(data, 4));
@ -4068,7 +4068,7 @@ void dec0_state::init_midresb()
// m_maincpu->space(AS_PROGRAM).install_write_handler(0x00180014, 0x00180015, write16_delegate(*this, FUNC(dec0_state::midres_sound_w)));
}
READ16_MEMBER(dec0_state::ffantasybl_242024_r)
uint16_t dec0_state::ffantasybl_242024_r()
{
/*
000152: 41F9 0024 2020 lea $242020.l, A0
@ -4085,7 +4085,7 @@ void dec0_state::init_ffantasybl()
{
m_maincpu->space(AS_PROGRAM).install_ram(0x24c880, 0x24cbff); // what is this? layer 3-related??
m_maincpu->space(AS_PROGRAM).install_read_handler(0x00242024, 0x00242025, read16_delegate(*this, FUNC(dec0_state::ffantasybl_242024_r)));
m_maincpu->space(AS_PROGRAM).install_read_handler(0x00242024, 0x00242025, read16smo_delegate(*this, FUNC(dec0_state::ffantasybl_242024_r)));
m_maincpu->space(AS_PROGRAM).install_read_port(0x00ff87ee, 0x00ff87ef, "VBLANK");
}

45
src/mame/drivers/dec8.cpp
View File

@ -59,7 +59,7 @@ To do:
/******************************************************************************/
WRITE8_MEMBER(dec8_state::dec8_mxc06_karn_buffer_spriteram_w)
void dec8_state::dec8_mxc06_karn_buffer_spriteram_w(uint8_t data)
{
uint8_t* spriteram = m_spriteram->live();
// copy to a 16-bit region for the sprite chip
@ -75,22 +75,21 @@ WRITE_LINE_MEMBER(dec8_state::screen_vblank_dec8)
// rising edge
if (state)
{
address_space &space = m_maincpu->space(AS_PROGRAM);
dec8_mxc06_karn_buffer_spriteram_w(space, 0, 0);
dec8_mxc06_karn_buffer_spriteram_w(0);
}
}
READ8_MEMBER(dec8_state::i8751_h_r)
uint8_t dec8_state::i8751_h_r()
{
return m_i8751_return >> 8; /* MSB */
}
READ8_MEMBER(dec8_state::i8751_l_r)
uint8_t dec8_state::i8751_l_r()
{
return m_i8751_return & 0xff; /* LSB */
}
WRITE8_MEMBER(dec8_state::i8751_reset_w)
void dec8_state::i8751_reset_w(uint8_t data)
{
// ? reset the actual MCU?
//m_i8751_return = 0;
@ -98,7 +97,7 @@ WRITE8_MEMBER(dec8_state::i8751_reset_w)
/******************************************************************************/
READ8_MEMBER(dec8_state::gondo_player_1_r)
uint8_t dec8_state::gondo_player_1_r(offs_t offset)
{
int val = 1 << ioport("AN0")->read();
@ -112,7 +111,7 @@ READ8_MEMBER(dec8_state::gondo_player_1_r)
return 0xff;
}
READ8_MEMBER(dec8_state::gondo_player_2_r)
uint8_t dec8_state::gondo_player_2_r(offs_t offset)
{
int val = 1 << ioport("AN1")->read();
@ -153,7 +152,7 @@ void dec8_state::device_timer(emu_timer &timer, device_timer_id id, int param, v
}
}
WRITE8_MEMBER(dec8_state::dec8_i8751_w)
void dec8_state::dec8_i8751_w(offs_t offset, uint8_t data)
{
switch (offset)
{
@ -170,7 +169,7 @@ WRITE8_MEMBER(dec8_state::dec8_i8751_w)
/******************************************************************************/
WRITE8_MEMBER(dec8_state::dec8_bank_w)
void dec8_state::dec8_bank_w(uint8_t data)
{
m_mainbank->set_entry(data & 0x0f);
}
@ -204,7 +203,7 @@ void dec8_state::ghostb_bank_w(uint8_t data)
flip_screen_set(BIT(data, 3));
}
WRITE8_MEMBER(dec8_state::csilver_control_w)
void dec8_state::csilver_control_w(uint8_t data)
{
/*
Bit 0x0f - ROM bank switch.
@ -216,7 +215,7 @@ WRITE8_MEMBER(dec8_state::csilver_control_w)
m_mainbank->set_entry(data & 0x0f);
}
WRITE8_MEMBER(dec8_state::dec8_sound_w)
void dec8_state::dec8_sound_w(uint8_t data)
{
m_soundlatch->write(data);
m_audiocpu->set_input_line(m6502_device::NMI_LINE, ASSERT_LINE);
@ -233,57 +232,57 @@ WRITE_LINE_MEMBER(dec8_state::csilver_adpcm_int)
m_msm5205next <<= 4;
}
READ8_MEMBER(dec8_state::csilver_adpcm_reset_r)
uint8_t dec8_state::csilver_adpcm_reset_r()
{
m_msm->reset_w(0);
return 0;
}
WRITE8_MEMBER(dec8_state::csilver_adpcm_data_w)
void dec8_state::csilver_adpcm_data_w(uint8_t data)
{
m_msm5205next = data;
}
WRITE8_MEMBER(dec8_state::csilver_sound_bank_w)
void dec8_state::csilver_sound_bank_w(uint8_t data)
{
m_soundbank->set_entry((data & 0x08) >> 3);
}
/******************************************************************************/
WRITE8_MEMBER(dec8_state::main_irq_on_w)
void dec8_state::main_irq_on_w(uint8_t data)
{
m_maincpu->set_input_line(M6809_IRQ_LINE, ASSERT_LINE);
}
WRITE8_MEMBER(dec8_state::main_irq_off_w)
void dec8_state::main_irq_off_w(uint8_t data)
{
m_maincpu->set_input_line(M6809_IRQ_LINE, CLEAR_LINE);
}
WRITE8_MEMBER(dec8_state::main_firq_off_w)
void dec8_state::main_firq_off_w(uint8_t data)
{
m_maincpu->set_input_line(M6809_FIRQ_LINE, CLEAR_LINE);
}
WRITE8_MEMBER(dec8_state::sub_irq_on_w)
void dec8_state::sub_irq_on_w(uint8_t data)
{
m_subcpu->set_input_line(M6809_IRQ_LINE, ASSERT_LINE);
}
WRITE8_MEMBER(dec8_state::sub_irq_off_w)
void dec8_state::sub_irq_off_w(uint8_t data)
{
m_subcpu->set_input_line(M6809_IRQ_LINE, CLEAR_LINE);
}
WRITE8_MEMBER(dec8_state::sub_firq_off_w)
void dec8_state::sub_firq_off_w(uint8_t data)
{
m_subcpu->set_input_line(M6809_FIRQ_LINE, CLEAR_LINE);
}
/******************************************************************************/
WRITE8_MEMBER(dec8_state::flip_screen_w){ flip_screen_set(data); }
void dec8_state::flip_screen_w(uint8_t data) { flip_screen_set(data); }
/******************************************************************************/
@ -1768,7 +1767,7 @@ WRITE_LINE_MEMBER(dec8_state::oscar_coin_irq)
m_coin_state = bool(state);
}
WRITE8_MEMBER(dec8_state::oscar_coin_clear_w)
void dec8_state::oscar_coin_clear_w(uint8_t data)
{
m_maincpu->set_input_line(INPUT_LINE_NMI, CLEAR_LINE);
}

32
src/mame/drivers/deco_mlc.cpp
View File

@ -119,12 +119,12 @@
/***************************************************************************/
READ32_MEMBER(deco_mlc_state::mlc_440008_r)
u32 deco_mlc_state::mlc_440008_r()
{
return 0xffffffff;
}
READ32_MEMBER(deco_mlc_state::mlc_44001c_r)
u32 deco_mlc_state::mlc_44001c_r(offs_t offset)
{
/*
test3 7 - vbl loop on 0x10 0000 at end of IRQ
@ -137,11 +137,11 @@ READ32_MEMBER(deco_mlc_state::mlc_44001c_r)
return 0xffffffff;
}
WRITE32_MEMBER(deco_mlc_state::mlc_44001c_w)
void deco_mlc_state::mlc_44001c_w(u32 data)
{
}
READ32_MEMBER(deco_mlc_state::mlc_200070_r)
u32 deco_mlc_state::mlc_200070_r()
{
if (!machine().side_effects_disabled())
m_vbl_i ^= 0xffffffff;
@ -150,29 +150,29 @@ READ32_MEMBER(deco_mlc_state::mlc_200070_r)
return m_vbl_i;
}
READ32_MEMBER(deco_mlc_state::mlc_200000_r)
u32 deco_mlc_state::mlc_200000_r()
{
return 0xffffffff;
}
READ32_MEMBER(deco_mlc_state::mlc_200004_r)
u32 deco_mlc_state::mlc_200004_r()
{
return 0xffffffff;
}
READ32_MEMBER(deco_mlc_state::mlc_20007c_r)
u32 deco_mlc_state::mlc_20007c_r()
{
return 0xffffffff;
}
READ32_MEMBER(deco_mlc_state::mlc_scanline_r)
u32 deco_mlc_state::mlc_scanline_r()
{
// logerror("read scanline counter (%d)\n", m_screen->vpos());
return m_screen->vpos();
}
WRITE32_MEMBER(deco_mlc_state::eeprom_w)
void deco_mlc_state::eeprom_w(offs_t offset, u32 data, u32 mem_mask)
{
if (ACCESSING_BITS_8_15)
{
@ -200,7 +200,7 @@ TIMER_DEVICE_CALLBACK_MEMBER(deco_mlc_state::interrupt_gen)
m_maincpu->set_input_line(m_irqLevel, HOLD_LINE);
}
WRITE32_MEMBER(deco_mlc_state::irq_ram_w)
void deco_mlc_state::irq_ram_w(offs_t offset, u32 data, u32 mem_mask)
{
// int scanline=m_screen->vpos();
COMBINE_DATA(&m_irq_ram[offset]);
@ -249,7 +249,7 @@ WRITE32_MEMBER(deco_mlc_state::irq_ram_w)
}
READ32_MEMBER( deco_mlc_state::spriteram_r )
u32 deco_mlc_state::spriteram_r(offs_t offset, u32 mem_mask)
{
u32 retdata = 0;
@ -267,7 +267,7 @@ READ32_MEMBER( deco_mlc_state::spriteram_r )
}
WRITE32_MEMBER( deco_mlc_state::spriteram_w )
void deco_mlc_state::spriteram_w(offs_t offset, u32 data, u32 mem_mask)
{
if (ACCESSING_BITS_16_31)
{
@ -280,7 +280,7 @@ WRITE32_MEMBER( deco_mlc_state::spriteram_w )
}
}
READ16_MEMBER( deco_mlc_state::sh96_protection_region_0_146_r )
u16 deco_mlc_state::sh96_protection_region_0_146_r(offs_t offset)
{
int real_address = 0 + (offset *2);
int deco146_addr = bitswap<32>(real_address, /* NC */31,30,29,28,27,26,25,24,23,22,21,20,19,18, 13,12,11,/**/ 17,16,15,14, 10,9,8, 7,6,5,4, 3,2,1,0) & 0x7fff;
@ -289,7 +289,7 @@ READ16_MEMBER( deco_mlc_state::sh96_protection_region_0_146_r )
return data;
}
WRITE16_MEMBER( deco_mlc_state::sh96_protection_region_0_146_w )
void deco_mlc_state::sh96_protection_region_0_146_w(offs_t offset, u16 data, u16 mem_mask)
{
int real_address = 0 + (offset *2);
int deco146_addr = bitswap<32>(real_address, /* NC */31,30,29,28,27,26,25,24,23,22,21,20,19,18, 13,12,11,/**/ 17,16,15,14, 10,9,8, 7,6,5,4, 3,2,1,0) & 0x7fff;
@ -938,7 +938,7 @@ void deco_mlc_state::descramble_sound( )
std::copy(buf.begin(), buf.end(), &rom[0]);
}
READ32_MEMBER(deco_mlc_state::avengrgs_speedup_r)
u32 deco_mlc_state::avengrgs_speedup_r()
{
const u32 a = m_mainram[0x89a0 / 4];
const u32 p = m_maincpu->pc();
@ -963,7 +963,7 @@ void deco_mlc_state::init_avengrgs()
dynamic_cast<sh2_device *>(m_maincpu.target())->sh2drc_add_fastram(0x0280000, 0x029ffff, 0, &m_vram[0]);
m_irqLevel = 1;
m_maincpu->space(AS_PROGRAM).install_read_handler(0x01089a0, 0x01089a3, read32_delegate(*this, FUNC(deco_mlc_state::avengrgs_speedup_r)));
m_maincpu->space(AS_PROGRAM).install_read_handler(0x01089a0, 0x01089a3, read32smo_delegate(*this, FUNC(deco_mlc_state::avengrgs_speedup_r)));
descramble_sound();
}

26
src/mame/drivers/decocass.cpp
View File

@ -64,16 +64,16 @@
*
***************************************************************************/
WRITE8_MEMBER(decocass_state::mirrorvideoram_w) { offset = ((offset >> 5) & 0x1f) | ((offset & 0x1f) << 5); decocass_fgvideoram_w(space, offset, data, mem_mask); }
WRITE8_MEMBER(decocass_state::mirrorcolorram_w) { offset = ((offset >> 5) & 0x1f) | ((offset & 0x1f) << 5); decocass_colorram_w(space, offset, data, mem_mask); }
void decocass_state::mirrorvideoram_w(offs_t offset, uint8_t data) { offset = ((offset >> 5) & 0x1f) | ((offset & 0x1f) << 5); decocass_fgvideoram_w(offset, data); }
void decocass_state::mirrorcolorram_w(offs_t offset, uint8_t data) { offset = ((offset >> 5) & 0x1f) | ((offset & 0x1f) << 5); decocass_colorram_w(offset, data); }
READ8_MEMBER(decocass_state::mirrorvideoram_r)
uint8_t decocass_state::mirrorvideoram_r(offs_t offset)
{
offset = ((offset >> 5) & 0x1f) | ((offset & 0x1f) << 5);
return m_fgvideoram[offset];
}
READ8_MEMBER(decocass_state::mirrorcolorram_r)
uint8_t decocass_state::mirrorcolorram_r(offs_t offset)
{
offset = ((offset >> 5) & 0x1f) | ((offset & 0x1f) << 5);
return m_colorram[offset];
@ -2061,9 +2061,9 @@ ROM_END
void decocass_state::init_decocass()
{
/* Call the state save setup code in machine/decocass.c */
/* Call the state save setup code in machine/decocass.cpp */
decocass_machine_state_save_init();
/* and in video/decocass.c, too */
/* and in video/decocass.cpp, too */
decocass_video_state_save_init();
}
@ -2074,17 +2074,17 @@ void decocass_state::init_decocrom()
/* convert charram to a banked ROM */
m_maincpu->space(AS_PROGRAM).install_read_bank(0x6000, 0xafff, "bank1");
m_maincpu->space(AS_PROGRAM).install_write_handler(0x6000, 0xafff, write8_delegate(*this, FUNC(decocass_state::decocass_de0091_w)));
m_maincpu->space(AS_PROGRAM).install_write_handler(0x6000, 0xafff, write8sm_delegate(*this, FUNC(decocass_state::decocass_de0091_w)));
membank("bank1")->configure_entry(0, m_charram);
membank("bank1")->configure_entry(1, memregion("user3")->base());
membank("bank1")->configure_entry(2, memregion("user3")->base()+0x5000);
membank("bank1")->set_entry(0);
/* install the bank selector */
m_maincpu->space(AS_PROGRAM).install_write_handler(0xe900, 0xe900, write8_delegate(*this, FUNC(decocass_state::decocass_e900_w)));
m_maincpu->space(AS_PROGRAM).install_write_handler(0xe900, 0xe900, write8smo_delegate(*this, FUNC(decocass_state::decocass_e900_w)));
}
READ8_MEMBER(decocass_state::cdsteljn_input_r )
uint8_t decocass_state::cdsteljn_input_r(offs_t offset)
{
uint8_t res;
static const char *const portnames[2][4] = {
@ -2092,14 +2092,14 @@ READ8_MEMBER(decocass_state::cdsteljn_input_r )
{"P2_MP0", "P2_MP1", "P2_MP2", "P2_MP3"} };
if(offset & 6)
return decocass_input_r(space,offset);
return decocass_input_r(offset);
res = ioport(portnames[offset & 1][m_mux_data])->read();
return res;
}
WRITE8_MEMBER(decocass_state::cdsteljn_mux_w )
void decocass_state::cdsteljn_mux_w(uint8_t data)
{
m_mux_data = (data & 0xc) >> 2;
/* bit 0 and 1 are p1/p2 lamps */
@ -2114,8 +2114,8 @@ void decocass_state::init_cdsteljn()
init_decocass();
/* install custom mahjong panel */
m_maincpu->space(AS_PROGRAM).install_write_handler(0xe413, 0xe413, write8_delegate(*this, FUNC(decocass_state::cdsteljn_mux_w)));
m_maincpu->space(AS_PROGRAM).install_read_handler(0xe600, 0xe6ff, read8_delegate(*this, FUNC(decocass_state::cdsteljn_input_r)));
m_maincpu->space(AS_PROGRAM).install_write_handler(0xe413, 0xe413, write8smo_delegate(*this, FUNC(decocass_state::cdsteljn_mux_w)));
m_maincpu->space(AS_PROGRAM).install_read_handler(0xe600, 0xe6ff, read8sm_delegate(*this, FUNC(decocass_state::cdsteljn_input_r)));
}
/* -- */ GAME( 1981, decocass, 0, decocass, decocass, decocass_state, init_decocass, ROT270, "Data East Corporation", "DECO Cassette System", MACHINE_IS_BIOS_ROOT )

4
src/mame/drivers/dietgo.cpp
View File

@ -34,7 +34,7 @@ PAL16R6A 11H
#include "speaker.h"
READ16_MEMBER( dietgo_state::dietgo_protection_region_0_104_r )
uint16_t dietgo_state::dietgo_protection_region_0_104_r(offs_t offset)
{
int real_address = 0 + (offset *2);
int deco146_addr = bitswap<32>(real_address, /* NC */31,30,29,28,27,26,25,24,23,22,21,20,19,18, 13,12,11,/**/ 17,16,15,14, 10,9,8, 7,6,5,4, 3,2,1,0) & 0x7fff;
@ -43,7 +43,7 @@ READ16_MEMBER( dietgo_state::dietgo_protection_region_0_104_r )
return data;
}
WRITE16_MEMBER( dietgo_state::dietgo_protection_region_0_104_w )
void dietgo_state::dietgo_protection_region_0_104_w(offs_t offset, uint16_t data, uint16_t mem_mask)
{
int real_address = 0 + (offset *2);
int deco146_addr = bitswap<32>(real_address, /* NC */31,30,29,28,27,26,25,24,23,22,21,20,19,18, 13,12,11,/**/ 17,16,15,14, 10,9,8, 7,6,5,4, 3,2,1,0) & 0x7fff;

10
src/mame/drivers/divebomb.cpp
View File

@ -134,7 +134,7 @@ void divebomb_state::divebomb_fgcpu_iomap(address_map &map)
}
READ8_MEMBER(divebomb_state::fgcpu_comm_flags_r)
uint8_t divebomb_state::fgcpu_comm_flags_r()
{
uint8_t result = 0;
@ -170,7 +170,7 @@ void divebomb_state::divebomb_spritecpu_iomap(address_map &map)
}
WRITE8_MEMBER(divebomb_state::spritecpu_port00_w)
void divebomb_state::spritecpu_port00_w(uint8_t data)
{
// Written with 0x00 on reset
// Written with 0x34 7 times in succession on occasion (see PC:0x00E3)
@ -184,14 +184,14 @@ WRITE8_MEMBER(divebomb_state::spritecpu_port00_w)
*************************************/
template<int Chip>
WRITE8_MEMBER(divebomb_state::rozcpu_wrap_enable_w)
void divebomb_state::rozcpu_wrap_enable_w(uint8_t data)
{
m_k051316[Chip]->wraparound_enable(!(data & 1));
}
template<int Chip>
WRITE8_MEMBER(divebomb_state::rozcpu_enable_w)
void divebomb_state::rozcpu_enable_w(uint8_t data)
{
m_roz_enable[Chip] = !(data & 1);
}
@ -222,7 +222,7 @@ void divebomb_state::divebomb_rozcpu_iomap(address_map &map)
}
WRITE8_MEMBER(divebomb_state::rozcpu_bank_w)
void divebomb_state::rozcpu_bank_w(uint8_t data)
{
uint32_t bank = bitswap<8>(data, 4, 5, 6, 7, 3, 2, 1, 0) >> 4;
m_rozbank->set_entry(bank);

12
src/mame/drivers/djboy.cpp
View File

@ -150,19 +150,19 @@ Notes:
/* KANEKO BEAST state */
READ8_MEMBER(djboy_state::beast_status_r)
uint8_t djboy_state::beast_status_r()
{
return (m_slavelatch->pending_r() ? 0x0 : 0x4) | (m_beastlatch->pending_r() ? 0x8 : 0x0);
}
/******************************************************************************/
WRITE8_MEMBER(djboy_state::trigger_nmi_on_mastercpu)
void djboy_state::trigger_nmi_on_mastercpu(uint8_t data)
{
m_mastercpu->pulse_input_line(INPUT_LINE_NMI, attotime::zero);
}
WRITE8_MEMBER(djboy_state::mastercpu_bankswitch_w)
void djboy_state::mastercpu_bankswitch_w(uint8_t data)
{
data ^= m_bankxor;
m_masterbank->set_entry(data);
@ -177,7 +177,7 @@ WRITE8_MEMBER(djboy_state::mastercpu_bankswitch_w)
* ---x---- screen flip
* ----xxxx bank
*/
WRITE8_MEMBER(djboy_state::slavecpu_bankswitch_w)
void djboy_state::slavecpu_bankswitch_w(uint8_t data)
{
m_videoreg = data;
@ -185,7 +185,7 @@ WRITE8_MEMBER(djboy_state::slavecpu_bankswitch_w)
m_slavebank->set_entry((data & 0xf));
}
WRITE8_MEMBER(djboy_state::coin_count_w)
void djboy_state::coin_count_w(uint8_t data)
{
machine().bookkeeping().coin_counter_w(0, data & 1);
machine().bookkeeping().coin_counter_w(1, data & 2);
@ -193,7 +193,7 @@ WRITE8_MEMBER(djboy_state::coin_count_w)
/******************************************************************************/
WRITE8_MEMBER(djboy_state::soundcpu_bankswitch_w)
void djboy_state::soundcpu_bankswitch_w(uint8_t data)
{
m_soundbank->set_entry(data); // shall we check data<0x07?
}

34
src/mame/drivers/djmain.cpp
View File

@ -88,7 +88,7 @@ hard drive 3.5 adapter long 3.5 IDE cable 3.5 adapter PCB
*
*************************************/
WRITE32_MEMBER(djmain_state::sndram_bank_w)
void djmain_state::sndram_bank_w(offs_t offset, uint32_t data, uint32_t mem_mask)
{
if (ACCESSING_BITS_16_31)
{
@ -96,7 +96,7 @@ WRITE32_MEMBER(djmain_state::sndram_bank_w)
}
}
READ32_MEMBER(djmain_state::sndram_r)
uint32_t djmain_state::sndram_r(offs_t offset, uint32_t mem_mask)
{
uint32_t data = 0;
@ -116,7 +116,7 @@ READ32_MEMBER(djmain_state::sndram_r)
return data;
}
WRITE32_MEMBER(djmain_state::sndram_w)
void djmain_state::sndram_w(offs_t offset, uint32_t data, uint32_t mem_mask)
{
offset |= 0x20000 * m_sndram_bank;
if (ACCESSING_BITS_24_31)
@ -135,7 +135,7 @@ WRITE32_MEMBER(djmain_state::sndram_w)
//---------
READ32_MEMBER(djmain_state::obj_ctrl_r)
uint32_t djmain_state::obj_ctrl_r(offs_t offset)
{
// read m_obj_regs[0x0c/4]: unknown
// read m_obj_regs[0x24/4]: unknown
@ -143,14 +143,14 @@ READ32_MEMBER(djmain_state::obj_ctrl_r)
return m_obj_regs[offset];
}
WRITE32_MEMBER(djmain_state::obj_ctrl_w)
void djmain_state::obj_ctrl_w(offs_t offset, uint32_t data, uint32_t mem_mask)
{
// write m_obj_regs[0x28/4]: bank for rom readthrough
COMBINE_DATA(&m_obj_regs[offset]);
}
READ32_MEMBER(djmain_state::obj_rom_r)
uint32_t djmain_state::obj_rom_r(offs_t offset, uint32_t mem_mask)
{
uint8_t *mem8 = memregion("gfx1")->base();
int bank = m_obj_regs[0x28/4] >> 16;
@ -170,7 +170,7 @@ READ32_MEMBER(djmain_state::obj_rom_r)
//---------
WRITE32_MEMBER(djmain_state::v_ctrl_w)
void djmain_state::v_ctrl_w(offs_t offset, uint32_t data, uint32_t mem_mask)
{
if (ACCESSING_BITS_16_31)
{
@ -186,7 +186,7 @@ WRITE32_MEMBER(djmain_state::v_ctrl_w)
}
}
READ32_MEMBER(djmain_state::v_rom_r)
uint32_t djmain_state::v_rom_r(offs_t offset, uint32_t mem_mask)
{
uint8_t *mem8 = memregion("k056832")->base();
int bank = m_k056832->word_r(0x34/2);
@ -207,19 +207,19 @@ READ32_MEMBER(djmain_state::v_rom_r)
//---------
READ8_MEMBER(djmain_state::inp1_r)
uint8_t djmain_state::inp1_r(offs_t offset)
{
static const char *const portnames[] = { "DSW3", "BTN3", "BTN2", "BTN1" };
return ioport(portnames[ offset & 0x03 ])->read();
}
READ8_MEMBER(djmain_state::inp2_r)
uint8_t djmain_state::inp2_r(offs_t offset)
{
static const char *const portnames[] = { "DSW1", "DSW2", "UNK2", "UNK1" };
return ioport(portnames[ offset & 0x03 ])->read();
}
READ32_MEMBER(djmain_state::turntable_r)
uint32_t djmain_state::turntable_r(offs_t offset, uint32_t mem_mask)
{
uint32_t result = 0;
@ -244,7 +244,7 @@ READ32_MEMBER(djmain_state::turntable_r)
return result;
}
WRITE32_MEMBER(djmain_state::turntable_select_w)
void djmain_state::turntable_select_w(offs_t offset, uint32_t data, uint32_t mem_mask)
{
if (ACCESSING_BITS_16_23)
m_turntable_select = (data >> 19) & 1;
@ -284,7 +284,7 @@ WRITE32_MEMBER(djmain_state::turntable_select_w)
15: not used? (always low)
*/
WRITE32_MEMBER(djmain_state::light_ctrl_1_w)
void djmain_state::light_ctrl_1_w(offs_t offset, uint32_t data, uint32_t mem_mask)
{
if (ACCESSING_BITS_16_31)
{
@ -295,7 +295,7 @@ WRITE32_MEMBER(djmain_state::light_ctrl_1_w)
}
}
WRITE32_MEMBER(djmain_state::light_ctrl_2_w)
void djmain_state::light_ctrl_2_w(offs_t offset, uint32_t data, uint32_t mem_mask)
{
if (ACCESSING_BITS_16_31)
{
@ -312,17 +312,17 @@ WRITE32_MEMBER(djmain_state::light_ctrl_2_w)
// unknown ports :-(
WRITE32_MEMBER(djmain_state::unknown590000_w)
void djmain_state::unknown590000_w(offs_t offset, uint32_t data, uint32_t mem_mask)
{
//logerror("%08X: unknown 590000 write %08X: %08X & %08X\n", m_maincpu->pcbase(), offset, data, mem_mask);
}
WRITE32_MEMBER(djmain_state::unknown802000_w)
void djmain_state::unknown802000_w(offs_t offset, uint32_t data, uint32_t mem_mask)
{
//logerror("%08X: unknown 802000 write %08X: %08X & %08X\n", m_maincpu->pcbase(), offset, data, mem_mask);
}
WRITE32_MEMBER(djmain_state::unknownc02000_w)
void djmain_state::unknownc02000_w(offs_t offset, uint32_t data, uint32_t mem_mask)
{
//logerror("%08X: unknown c02000 write %08X: %08X & %08X\n", m_maincpu->pcbase(), offset, data, mem_mask);
}

48
src/mame/drivers/dkong.cpp
View File

@ -607,12 +607,12 @@ void dkong_state::p8257_ctl_w(uint8_t data)
*
*************************************/
WRITE8_MEMBER(dkong_state::dkong3_coin_counter_w)
void dkong_state::dkong3_coin_counter_w(offs_t offset, uint8_t data)
{
machine().bookkeeping().coin_counter_w(offset, data & 0x01);
}
WRITE8_MEMBER(dkong_state::p8257_drq_w)
void dkong_state::p8257_drq_w(uint8_t data)
{
m_dma8257->dreq0_w(data & 0x01);
m_dma8257->dreq1_w(data & 0x01);
@ -620,7 +620,7 @@ WRITE8_MEMBER(dkong_state::p8257_drq_w)
machine().scheduler().boost_interleave(attotime::zero, attotime::from_usec(100)); // smooth things out a bit
}
READ8_MEMBER(dkong_state::dkong_in2_r)
uint8_t dkong_state::dkong_in2_r(offs_t offset)
{
// 2 board DK and all DKjr has a watchdog
if (m_watchdog)
@ -634,7 +634,7 @@ READ8_MEMBER(dkong_state::dkong_in2_r)
}
READ8_MEMBER(dkong_state::epos_decrypt_rom)
uint8_t dkong_state::epos_decrypt_rom(offs_t offset)
{
if (offset & 0x01)
{
@ -662,7 +662,7 @@ READ8_MEMBER(dkong_state::epos_decrypt_rom)
}
WRITE8_MEMBER(dkong_state::s2650_data_w)
void dkong_state::s2650_data_w(uint8_t data)
{
#if DEBUG_PROTECTION
logerror("write : pc = %04x, loopback = %02x\n",m_maincpu->pc(), data);
@ -683,7 +683,7 @@ WRITE_LINE_MEMBER(dkong_state::s2650_fo_w)
m_hunchloopback = 0xfb;
}
READ8_MEMBER(dkong_state::s2650_port0_r)
uint8_t dkong_state::s2650_port0_r()
{
#if DEBUG_PROTECTION
logerror("port 0 : pc = %04x, loopback = %02x fo=%d\n",m_maincpu->pc(), m_hunchloopback, m_main_fo);
@ -707,7 +707,7 @@ READ8_MEMBER(dkong_state::s2650_port0_r)
}
READ8_MEMBER(dkong_state::s2650_port1_r)
uint8_t dkong_state::s2650_port1_r()
{
#if DEBUG_PROTECTION
logerror("port 1 : pc = %04x, loopback = %02x fo=%d\n",m_maincpu->pc(), m_hunchloopback, m_main_fo);
@ -728,7 +728,7 @@ READ8_MEMBER(dkong_state::s2650_port1_r)
}
WRITE8_MEMBER(dkong_state::dkong3_2a03_reset_w)
void dkong_state::dkong3_2a03_reset_w(uint8_t data)
{
if (data & 1)
{
@ -742,7 +742,7 @@ WRITE8_MEMBER(dkong_state::dkong3_2a03_reset_w)
}
}
READ8_MEMBER(dkong_state::strtheat_inputport_0_r)
uint8_t dkong_state::strtheat_inputport_0_r()
{
if(ioport("DSW0")->read() & 0x40)
{
@ -757,7 +757,7 @@ READ8_MEMBER(dkong_state::strtheat_inputport_0_r)
}
READ8_MEMBER(dkong_state::strtheat_inputport_1_r)
uint8_t dkong_state::strtheat_inputport_1_r()
{
if(ioport("DSW0")->read() & 0x40)
{
@ -771,12 +771,12 @@ READ8_MEMBER(dkong_state::strtheat_inputport_1_r)
}
}
WRITE8_MEMBER(dkong_state::dkong_z80dma_rdy_w)
void dkong_state::dkong_z80dma_rdy_w(uint8_t data)
{
m_z80dma->rdy_w(data & 0x01);
}
WRITE8_MEMBER(dkong_state::nmi_mask_w)
void dkong_state::nmi_mask_w(uint8_t data)
{
m_nmi_mask = data & 1;
if (!m_nmi_mask)
@ -1612,7 +1612,7 @@ GFXDECODE_END
*
*************************************/
READ8_MEMBER(dkong_state::braze_eeprom_r)
uint8_t dkong_state::braze_eeprom_r()
{
return m_eeprom->do_read();
}
@ -1623,12 +1623,12 @@ WRITE_LINE_MEMBER(dkong_state::dk_braze_a15)
membank("bank2")->set_entry(state & 0x01);
}
WRITE8_MEMBER(dkong_state::dk_braze_a15_w)
void dkong_state::dk_braze_a15_w(uint8_t data)
{
dk_braze_a15(data);
}
WRITE8_MEMBER(dkong_state::braze_eeprom_w)
void dkong_state::braze_eeprom_w(uint8_t data)
{
m_eeprom->di_write(data & 0x01);
m_eeprom->cs_write(data & 0x04 ? ASSERT_LINE : CLEAR_LINE);
@ -3609,8 +3609,8 @@ void dkong_state::init_strtheat()
drakton_decrypt_rom(0x88, 0x1c000, bs[3]);
/* custom handlers supporting Joystick or Steering Wheel */
m_maincpu->space(AS_PROGRAM).install_read_handler(0x7c00, 0x7c00, read8_delegate(*this, FUNC(dkong_state::strtheat_inputport_0_r)));
m_maincpu->space(AS_PROGRAM).install_read_handler(0x7c80, 0x7c80, read8_delegate(*this, FUNC(dkong_state::strtheat_inputport_1_r)));
m_maincpu->space(AS_PROGRAM).install_read_handler(0x7c00, 0x7c00, read8smo_delegate(*this, FUNC(dkong_state::strtheat_inputport_0_r)));
m_maincpu->space(AS_PROGRAM).install_read_handler(0x7c80, 0x7c80, read8smo_delegate(*this, FUNC(dkong_state::strtheat_inputport_1_r)));
}
void dkong_state::dk_braze_decrypt()
@ -3633,8 +3633,8 @@ void dkong_state::init_dkonghs()
dk_braze_decrypt();
address_space &space = m_maincpu->space(AS_PROGRAM);
space.install_read_handler(0xc000, 0xc000, read8_delegate(*this, FUNC(dkong_state::braze_eeprom_r)));
space.install_write_handler(0xc000, 0xc000, write8_delegate(*this, FUNC(dkong_state::braze_eeprom_w)));
space.install_read_handler(0xc000, 0xc000, read8smo_delegate(*this, FUNC(dkong_state::braze_eeprom_r)));
space.install_write_handler(0xc000, 0xc000, write8smo_delegate(*this, FUNC(dkong_state::braze_eeprom_w)));
}
void dkong_state::init_dkongx()
@ -3642,10 +3642,10 @@ void dkong_state::init_dkongx()
dk_braze_decrypt();
address_space &space = m_maincpu->space(AS_PROGRAM);
space.install_write_handler(0xe000, 0xe000, write8_delegate(*this, FUNC(dkong_state::dk_braze_a15_w)));
space.install_write_handler(0xe000, 0xe000, write8smo_delegate(*this, FUNC(dkong_state::dk_braze_a15_w)));
space.install_read_handler(0xc800, 0xc800, read8_delegate(*this, FUNC(dkong_state::braze_eeprom_r)));
space.install_write_handler(0xc800, 0xc800, write8_delegate(*this, FUNC(dkong_state::braze_eeprom_w)));
space.install_read_handler(0xc800, 0xc800, read8smo_delegate(*this, FUNC(dkong_state::braze_eeprom_r)));
space.install_write_handler(0xc800, 0xc800, write8smo_delegate(*this, FUNC(dkong_state::braze_eeprom_w)));
}
void dkong_state::init_dkong3hs()
@ -3658,8 +3658,8 @@ void dkong_state::init_dkong3hs()
m_maincpu->space(AS_PROGRAM).install_rom(0x8000, 0xffff, m_decrypted.get() + 0x8000);
address_space &space = m_maincpu->space(AS_PROGRAM);
space.install_read_handler(0xc000, 0xc000, read8_delegate(*this, FUNC(dkong_state::braze_eeprom_r)));
space.install_write_handler(0xc000, 0xc000, write8_delegate(*this, FUNC(dkong_state::braze_eeprom_w)));
space.install_read_handler(0xc000, 0xc000, read8smo_delegate(*this, FUNC(dkong_state::braze_eeprom_r)));
space.install_write_handler(0xc000, 0xc000, write8smo_delegate(*this, FUNC(dkong_state::braze_eeprom_w)));
}
void dkong_state::init_dkingjr()

32
src/mame/drivers/dm7000.cpp
View File

@ -57,31 +57,31 @@ static inline void ATTR_PRINTF(3,4) verboselog( device_t &device, int n_level, c
}
}
READ8_MEMBER( dm7000_state::dm7000_iic0_r )
uint8_t dm7000_state::dm7000_iic0_r(offs_t offset)
{
uint8_t data = 0; // dummy
verboselog(*this, 9, "(IIC0) %08X -> %08X\n", 0x40030000 + offset, data);
return data;
}
WRITE8_MEMBER( dm7000_state::dm7000_iic0_w )
void dm7000_state::dm7000_iic0_w(offs_t offset, uint8_t data)
{
verboselog(*this, 9, "(IIC0) %08X <- %08X\n", 0x40030000 + offset, data);
}
READ8_MEMBER( dm7000_state::dm7000_iic1_r )
uint8_t dm7000_state::dm7000_iic1_r(offs_t offset)
{
uint8_t data = 0; // dummy
verboselog(*this, 9, "(IIC1) %08X -> %08X\n", 0x400b0000 + offset, data);
return data;
}
WRITE8_MEMBER( dm7000_state::dm7000_iic1_w )
void dm7000_state::dm7000_iic1_w(offs_t offset, uint8_t data)
{
verboselog(*this, 9, "(IIC1) %08X <- %08X\n", 0x400b0000 + offset, data);
}
READ8_MEMBER( dm7000_state::dm7000_scc0_r )
uint8_t dm7000_state::dm7000_scc0_r(offs_t offset)
{
uint8_t data = 0;
switch(offset) {
@ -102,7 +102,7 @@ READ8_MEMBER( dm7000_state::dm7000_scc0_r )
return data;
}
WRITE8_MEMBER( dm7000_state::dm7000_scc0_w )
void dm7000_state::dm7000_scc0_w(offs_t offset, uint8_t data)
{
switch(offset) {
case UART_THR:
@ -118,19 +118,19 @@ WRITE8_MEMBER( dm7000_state::dm7000_scc0_w )
verboselog(*this, 9, "(SCC0) %08X <- %08X\n", 0x40040000 + offset, data);
}
READ8_MEMBER( dm7000_state::dm7000_gpio0_r )
uint8_t dm7000_state::dm7000_gpio0_r(offs_t offset)
{
uint8_t data = 0; // dummy
verboselog(*this, 9, "(GPIO0) %08X -> %08X\n", 0x40060000 + offset, data);
return data;
}
WRITE8_MEMBER( dm7000_state::dm7000_gpio0_w )
void dm7000_state::dm7000_gpio0_w(offs_t offset, uint8_t data)
{
verboselog(*this, 9, "(GPIO0) %08X <- %08X\n", 0x40060000 + offset, data);
}
READ8_MEMBER( dm7000_state::dm7000_scp0_r )
uint8_t dm7000_state::dm7000_scp0_r(offs_t offset)
{
uint8_t data = 0; // dummy
switch(offset) {
@ -142,7 +142,7 @@ READ8_MEMBER( dm7000_state::dm7000_scp0_r )
return data;
}
WRITE8_MEMBER( dm7000_state::dm7000_scp0_w )
void dm7000_state::dm7000_scp0_w(offs_t offset, uint8_t data)
{
verboselog(*this, 9, "(SCP0) %08X <- %08X\n", 0x400c0000 + offset, data);
switch(offset) {
@ -152,7 +152,7 @@ WRITE8_MEMBER( dm7000_state::dm7000_scp0_w )
}
}
READ16_MEMBER( dm7000_state::dm7000_enet_r )
uint16_t dm7000_state::dm7000_enet_r(offs_t offset)
{
uint16_t data;
switch (offset) {
@ -173,7 +173,7 @@ READ16_MEMBER( dm7000_state::dm7000_enet_r )
return data;
}
WRITE16_MEMBER( dm7000_state::dm7000_enet_w )
void dm7000_state::dm7000_enet_w(offs_t offset, uint16_t data, uint16_t mem_mask)
{
verboselog(*this, 9, "(ENET) %08X <- %08X\n", 0x72000600 + (offset), data);
COMBINE_DATA(&m_enet_regs[offset]);
@ -261,8 +261,8 @@ void dm7000_state::machine_reset()
dcr[DCRSTB045_FRAME_BUFR_BASE] = 0x0f000000;
m_scc0_lsr = UART_LSR_THRE | UART_LSR_TEMT;
m_maincpu->ppc4xx_set_dcr_read_handler(read32_delegate(*this, FUNC(dm7000_state::dcr_r)));
m_maincpu->ppc4xx_set_dcr_write_handler(write32_delegate(*this, FUNC(dm7000_state::dcr_w)));
m_maincpu->ppc4xx_set_dcr_read_handler(read32sm_delegate(*this, FUNC(dm7000_state::dcr_r)));
m_maincpu->ppc4xx_set_dcr_write_handler(write32sm_delegate(*this, FUNC(dm7000_state::dcr_w)));
}
void dm7000_state::video_start()
@ -274,7 +274,7 @@ uint32_t dm7000_state::screen_update_dm7000(screen_device &screen, bitmap_rgb32
return 0;
}
READ32_MEMBER( dm7000_state::dcr_r )
uint32_t dm7000_state::dcr_r(offs_t offset)
{
osd_printf_debug("DCR %03X read\n", offset);
if(offset>=1024) {printf("get %04X\n", offset); return 0;} else
@ -287,7 +287,7 @@ READ32_MEMBER( dm7000_state::dcr_r )
}
WRITE32_MEMBER( dm7000_state::dcr_w )
void dm7000_state::dcr_w(offs_t offset, uint32_t data)
{
osd_printf_debug("DCR %03X write = %08X\n", offset, data);
if(offset>=1024) {printf("get %04X\n", offset); } else

4
src/mame/drivers/docastle.cpp
View File

@ -199,14 +199,14 @@ WRITE_LINE_MEMBER(docastle_state::idsoccer_adpcm_int)
}
}
READ8_MEMBER(docastle_state::idsoccer_adpcm_status_r)
uint8_t docastle_state::idsoccer_adpcm_status_r()
{
// this is wrong, but the samples work anyway!!
m_adpcm_status ^= 0x80;
return m_adpcm_status;
}
WRITE8_MEMBER(docastle_state::idsoccer_adpcm_w)
void docastle_state::idsoccer_adpcm_w(uint8_t data)
{
if (data & 0x80)
{

8
src/mame/drivers/dogfgt.cpp
View File

@ -16,24 +16,24 @@ driver by Nicola Salmoria
#include "speaker.h"
WRITE8_MEMBER(dogfgt_state::subirqtrigger_w)
void dogfgt_state::subirqtrigger_w(uint8_t data)
{
/* bit 0 used but unknown */
if (data & 0x04)
m_subcpu->set_input_line(0, ASSERT_LINE);
}
WRITE8_MEMBER(dogfgt_state::sub_irqack_w)
void dogfgt_state::sub_irqack_w(uint8_t data)
{
m_subcpu->set_input_line(0, CLEAR_LINE);
}
WRITE8_MEMBER(dogfgt_state::soundlatch_w)
void dogfgt_state::soundlatch_w(uint8_t data)
{
m_soundlatch = data;
}
WRITE8_MEMBER(dogfgt_state::soundcontrol_w)
void dogfgt_state::soundcontrol_w(uint8_t data)
{
/* bit 5 goes to YM2149 #0 BDIR pin */
if ((m_last_snd_ctrl & 0x20) == 0x20 && (data & 0x20) == 0x00)

6
src/mame/drivers/dragrace.cpp
View File

@ -58,7 +58,7 @@ void dragrace_state::speed2_w(uint8_t data)
output().set_value("tachometer2", freq);
}
READ8_MEMBER(dragrace_state::dragrace_input_r)
uint8_t dragrace_state::dragrace_input_r(offs_t offset)
{
int val = ioport("IN2")->read();
static const char *const portnames[] = { "IN0", "IN1" };
@ -81,7 +81,7 @@ READ8_MEMBER(dragrace_state::dragrace_input_r)
}
READ8_MEMBER(dragrace_state::dragrace_steering_r)
uint8_t dragrace_state::dragrace_steering_r()
{
int bitA[2];
int bitB[2];
@ -101,7 +101,7 @@ READ8_MEMBER(dragrace_state::dragrace_steering_r)
}
READ8_MEMBER(dragrace_state::dragrace_scanline_r)
uint8_t dragrace_state::dragrace_scanline_r()
{
return (m_screen->vpos() ^ 0xf0) | 0x0f;
}

6
src/mame/drivers/drgnmst.cpp
View File

@ -48,20 +48,20 @@ Notes:
#include "speaker.h"
WRITE16_MEMBER(drgnmst_base_state::coin_w)
void drgnmst_base_state::coin_w(uint16_t data)
{
machine().bookkeeping().coin_counter_w(0, data & 0x100);
machine().bookkeeping().coin_lockout_w(0, ~data & 0x400);
machine().bookkeeping().coin_lockout_w(1, ~data & 0x800);
}
WRITE8_MEMBER(drgnmst_pic_state::snd_command_w)
void drgnmst_pic_state::snd_command_w(uint8_t data)
{
m_snd_command = data;
m_maincpu->yield();
}
WRITE8_MEMBER(drgnmst_pic_state::snd_flag_w)
void drgnmst_pic_state::snd_flag_w(uint8_t data)
{
/* Enables the following 68K write operation to latch through to the PIC */
m_snd_flag = 1;

4
src/mame/drivers/drmicro.cpp
View File

@ -34,7 +34,7 @@ INTERRUPT_GEN_MEMBER(drmicro_state::drmicro_interrupt)
device.execute().pulse_input_line(INPUT_LINE_NMI, attotime::zero);
}
WRITE8_MEMBER(drmicro_state::nmi_enable_w)
void drmicro_state::nmi_enable_w(uint8_t data)
{
m_nmi_enable = data & 1;
m_flipscreen = (data & 2) ? 1 : 0;
@ -64,7 +64,7 @@ WRITE_LINE_MEMBER(drmicro_state::pcm_w)
m_msm->reset_w(1);
}
WRITE8_MEMBER(drmicro_state::pcm_set_w)
void drmicro_state::pcm_set_w(uint8_t data)
{
m_pcm_adr = ((data & 0x3f) << 9);
pcm_w(1);

82
src/mame/drivers/dynax.cpp
View File

@ -114,7 +114,7 @@ WRITE_LINE_MEMBER(dynax_state::sprtmtch_blitter_irq_w)
m_mainirq->rst4_w(1);
}
WRITE8_MEMBER(dynax_state::dynax_vblank_ack_w)
void dynax_state::dynax_vblank_ack_w(uint8_t data)
{
m_mainirq->rst2_w(0);
}
@ -138,7 +138,7 @@ WRITE_LINE_MEMBER(dynax_state::sprtmtch_vblank_w)
***************************************************************************/
/* It runs in IM 0, thus needs an opcode on the data bus */
WRITE8_MEMBER(dynax_state::jantouki_vblank_ack_w)
void dynax_state::jantouki_vblank_ack_w(uint8_t data)
{
m_mainirq->rst4_w(0);
}
@ -183,7 +183,7 @@ WRITE_LINE_MEMBER(dynax_state::jantouki_vblank_w)
Jantouki - Sound CPU
***************************************************************************/
WRITE8_MEMBER(dynax_state::jantouki_sound_vblank_ack_w)
void dynax_state::jantouki_sound_vblank_ack_w(uint8_t data)
{
m_soundirq->rst4_w(0);
}
@ -211,13 +211,13 @@ WRITE_LINE_MEMBER(dynax_state::coincounter_1_w)
machine().bookkeeping().coin_counter_w(1, state);
}
READ8_MEMBER(dynax_state::ret_ff)
uint8_t dynax_state::ret_ff()
{
return 0xff;
}
READ8_MEMBER(dynax_state::hanamai_keyboard_0_r)
uint8_t dynax_state::hanamai_keyboard_0_r()
{
int res = 0x3f;
@ -231,7 +231,7 @@ READ8_MEMBER(dynax_state::hanamai_keyboard_0_r)
return res;
}
READ8_MEMBER(dynax_state::hanamai_keyboard_1_r)
uint8_t dynax_state::hanamai_keyboard_1_r()
{
int res = 0x3f;
@ -245,36 +245,36 @@ READ8_MEMBER(dynax_state::hanamai_keyboard_1_r)
return res;
}
WRITE8_MEMBER(dynax_state::hanamai_keyboard_w)
void dynax_state::hanamai_keyboard_w(uint8_t data)
{
m_keyb = data;
}
WRITE8_MEMBER(dynax_state::dynax_rombank_w)
void dynax_state::dynax_rombank_w(uint8_t data)
{
membank("bank1")->set_entry(data & 0x0f);
}
WRITE8_MEMBER(dynax_state::jantouki_sound_rombank_w)
void dynax_state::jantouki_sound_rombank_w(uint8_t data)
{
membank("bank2")->set_entry(data);
}
WRITE8_MEMBER(dynax_state::hnoridur_rombank_w)
void dynax_state::hnoridur_rombank_w(uint8_t data)
{
m_bankdev->set_bank(data & 0x1f);
}
WRITE8_MEMBER(dynax_state::hnoridur_palette_lo_w)
void dynax_state::hnoridur_palette_lo_w(offs_t offset, uint8_t data)
{
m_palette_ram[256 * m_palbank + offset + 16 * 256] = data;
hnoridur_palette_update(offset);
}
WRITE8_MEMBER(dynax_state::hnoridur_palette_hi_w)
void dynax_state::hnoridur_palette_hi_w(offs_t offset, uint8_t data)
{
m_palette_ram[256 * m_palbank + offset] = data;
hnoridur_palette_update(offset);
@ -290,13 +290,13 @@ void dynax_state::hnoridur_palette_update(offs_t offset)
m_palette->set_pen_color(256 * m_palbank + offset, pal5bit(r), pal5bit(g), pal5bit(b));
}
WRITE8_MEMBER(dynax_state::nanajign_palette_lo_w)
void dynax_state::nanajign_palette_lo_w(offs_t offset, uint8_t data)
{
m_palette_ram[256 * m_palbank + offset + 16 * 256] = data;
nanajign_palette_update(offset);
}
WRITE8_MEMBER(dynax_state::nanajign_palette_hi_w)
void dynax_state::nanajign_palette_hi_w(offs_t offset, uint8_t data)
{
m_palette_ram[256 * m_palbank + offset] = data;
nanajign_palette_update(offset);
@ -341,12 +341,12 @@ WRITE_LINE_MEMBER(dynax_state::adpcm_int_cpu1)
}
WRITE8_MEMBER(dynax_state::adpcm_data_w)
void dynax_state::adpcm_data_w(uint8_t data)
{
m_msm5205next = data;
}
WRITE8_MEMBER(dynax_state::adpcm_reset_w)
void dynax_state::adpcm_reset_w(uint8_t data)
{
m_resetkludge = data & 1;
m_msm->reset_w(~data & 1);
@ -569,14 +569,14 @@ uint8_t dynax_state::hjingi_hopper_bit()
return (m_hopper && !(m_screen->frame_number() % 10)) ? 0 : (1 << 6);
}
READ8_MEMBER(dynax_state::hjingi_keyboard_0_r)
uint8_t dynax_state::hjingi_keyboard_0_r()
{
return hanamai_keyboard_0_r(space, 0) | hjingi_hopper_bit();
return hanamai_keyboard_0_r() | hjingi_hopper_bit();
}
READ8_MEMBER(dynax_state::hjingi_keyboard_1_r)
uint8_t dynax_state::hjingi_keyboard_1_r()
{
return hanamai_keyboard_1_r(space, 0) | ioport("BET")->read();
return hanamai_keyboard_1_r() | ioport("BET")->read();
}
void dynax_state::hjingi_mem_map(address_map &map)
@ -647,7 +647,7 @@ void dynax_state::hjingi_io_map(address_map &map)
Yarunara / Quiz TV Q&Q / Mahjong Angels
***************************************************************************/
WRITE8_MEMBER(dynax_state::yarunara_input_w)
void dynax_state::yarunara_input_w(offs_t offset, uint8_t data)
{
switch (offset)
{
@ -660,7 +660,7 @@ WRITE8_MEMBER(dynax_state::yarunara_input_w)
}
READ8_MEMBER(dynax_state::yarunara_input_r)
uint8_t dynax_state::yarunara_input_r(offs_t offset)
{
static const char *const keynames0[] = { "KEY0", "KEY1", "KEY2", "KEY3", "KEY4" };
static const char *const keynames1[] = { "KEY5", "KEY6", "KEY7", "KEY8", "KEY9" };
@ -704,12 +704,12 @@ READ8_MEMBER(dynax_state::yarunara_input_r)
return 0xff;
}
WRITE8_MEMBER(dynax_state::yarunara_rombank_w)
void dynax_state::yarunara_rombank_w(uint8_t data)
{
m_bankdev->set_bank(data & 0x3f);
}
WRITE8_MEMBER(dynax_state::yarunara_blit_romregion_w)
void dynax_state::yarunara_blit_romregion_w(uint8_t data)
{
switch(data)
{
@ -870,18 +870,18 @@ void dynax_state::nanajign_io_map(address_map &map)
Jantouki - Main CPU
***************************************************************************/
READ8_MEMBER(dynax_state::jantouki_soundlatch_ack_r)
uint8_t dynax_state::jantouki_soundlatch_ack_r()
{
machine().scheduler().synchronize();
return m_soundlatch->pending_r() ? 0x80 : 0;
}
READ8_MEMBER(dynax_state::jantouki_blitter_busy_r)
uint8_t dynax_state::jantouki_blitter_busy_r()
{
return 0; // bit 0 & 1
}
WRITE8_MEMBER(dynax_state::jantouki_rombank_w)
void dynax_state::jantouki_rombank_w(uint8_t data)
{
membank("bank1")->set_entry(data & 0x0f);
m_led = BIT(data, 4); // maybe
@ -921,7 +921,7 @@ void dynax_state::jantouki_io_map(address_map &map)
Jantouki - Sound CPU
***************************************************************************/
READ8_MEMBER(dynax_state::jantouki_soundlatch_status_r)
uint8_t dynax_state::jantouki_soundlatch_status_r()
{
return m_soundlatch->pending_r() ? 0 : 0x80;
}
@ -947,12 +947,12 @@ void dynax_state::jantouki_sound_io_map(address_map &map)
Mahjong Electron Base
***************************************************************************/
READ8_MEMBER(dynax_state::mjelctrn_keyboard_1_r)
uint8_t dynax_state::mjelctrn_keyboard_1_r()
{
return (hanamai_keyboard_1_r(space, 0) & 0x3f) | (ioport("FAKE")->read() ? 0x40 : 0);
return (hanamai_keyboard_1_r() & 0x3f) | (ioport("FAKE")->read() ? 0x40 : 0);
}
READ8_MEMBER(dynax_state::mjelctrn_dsw_r)
uint8_t dynax_state::mjelctrn_dsw_r()
{
int dsw = (m_keyb & 0xc0) >> 6;
static const char *const dswnames[] = { "DSW0", "DSW1", "DSW2", "DSW3" };
@ -1026,7 +1026,7 @@ void dynax_state::mjembase_io_map(address_map &map)
Mahjong Tenkaigen
***************************************************************************/
WRITE8_MEMBER(dynax_state::tenkai_ipsel_w)
void dynax_state::tenkai_ipsel_w(offs_t offset, uint8_t data)
{
switch (offset)
{
@ -1039,7 +1039,7 @@ WRITE8_MEMBER(dynax_state::tenkai_ipsel_w)
}
WRITE8_MEMBER(dynax_state::tenkai_ip_w)
void dynax_state::tenkai_ip_w(uint8_t data)
{
switch (m_input_sel)
{
@ -1059,7 +1059,7 @@ WRITE8_MEMBER(dynax_state::tenkai_ip_w)
logerror("%04x: unmapped ip_sel=%02x written with %02x\n", m_maincpu->pc(), m_input_sel, data);
}
READ8_MEMBER(dynax_state::tenkai_ip_r)
uint8_t dynax_state::tenkai_ip_r(offs_t offset)
{
static const char *const keynames0[] = { "KEY0", "KEY1", "KEY2", "KEY3", "KEY4" };
//static const char *const keynames1[] = { "KEY5", "KEY6", "KEY7", "KEY8", "KEY9" };
@ -1125,12 +1125,12 @@ uint8_t dynax_state::tenkai_dsw_r()
return 0xff;
}
READ8_MEMBER(dynax_state::tenkai_palette_r)
uint8_t dynax_state::tenkai_palette_r(offs_t offset)
{
return m_palette_ram[512 * m_palbank + offset];
}
WRITE8_MEMBER(dynax_state::tenkai_palette_w)
void dynax_state::tenkai_palette_w(offs_t offset, uint8_t data)
{
int addr = 512 * m_palbank + offset;
m_palette_ram[addr] = data;
@ -1216,7 +1216,7 @@ WRITE_LINE_MEMBER(dynax_state::tenkai_70_w)
tenkai_show_6c();
}
WRITE8_MEMBER(dynax_state::tenkai_blit_romregion_w)
void dynax_state::tenkai_blit_romregion_w(uint8_t data)
{
switch (data)
{
@ -1261,7 +1261,7 @@ void dynax_state::tenkai_banked_map(address_map &map)
Mahjong Gekisha
***************************************************************************/
READ8_MEMBER(dynax_state::gekisha_keyboard_0_r)
uint8_t dynax_state::gekisha_keyboard_0_r()
{
int res = 0x3f;
@ -1273,7 +1273,7 @@ READ8_MEMBER(dynax_state::gekisha_keyboard_0_r)
return res;
}
READ8_MEMBER(dynax_state::gekisha_keyboard_1_r)
uint8_t dynax_state::gekisha_keyboard_1_r()
{
int res = 0x3f;
@ -1291,7 +1291,7 @@ READ8_MEMBER(dynax_state::gekisha_keyboard_1_r)
return res;
}
WRITE8_MEMBER(dynax_state::gekisha_hopper_w)
void dynax_state::gekisha_hopper_w(offs_t offset, uint8_t data)
{
m_gekisha_val[offset] = data;
// popmessage("%02x %02x", gekisha_val[0], gekisha_val[1]);
@ -1339,7 +1339,7 @@ void dynax_state::gekisha_banked_map(address_map &map)
Castle Of Dracula
***************************************************************************/
WRITE8_MEMBER(dynax_state::cdracula_sound_rombank_w)
void dynax_state::cdracula_sound_rombank_w(uint8_t data)
{
// logerror("%s: sound bank = %02x\n", machine().describe_context(), data);

6
src/mame/drivers/fcrash.cpp
View File

@ -1073,7 +1073,7 @@ void fcrash_state::init_cawingbl()
{
m_maincpu->space(AS_PROGRAM).install_read_port(0x882000, 0x882001, "IN1");
m_maincpu->space(AS_PROGRAM).install_write_handler(0x882006, 0x882007, write16_delegate(*this, FUNC(fcrash_state::cawingbl_soundlatch_w)));
m_maincpu->space(AS_PROGRAM).install_read_handler(0x882008, 0x88200f, read16_delegate(*this, FUNC(fcrash_state::cps1_dsw_r)));
m_maincpu->space(AS_PROGRAM).install_read_handler(0x882008, 0x88200f, read16sm_delegate(*this, FUNC(fcrash_state::cps1_dsw_r)));
init_cps1();
}
@ -1081,8 +1081,8 @@ void fcrash_state::init_cawingbl()
void fcrash_state::init_kodb()
{
m_maincpu->space(AS_PROGRAM).install_read_port(0x800000, 0x800007, "IN1");
m_maincpu->space(AS_PROGRAM).install_read_handler(0x800018, 0x80001f, read16_delegate(*this, FUNC(fcrash_state::cps1_dsw_r)));
m_maincpu->space(AS_PROGRAM).install_write_handler(0x800180, 0x800187, write16_delegate(*this, FUNC(fcrash_state::cps1_soundlatch_w)));
m_maincpu->space(AS_PROGRAM).install_read_handler(0x800018, 0x80001f, read16sm_delegate(*this, FUNC(fcrash_state::cps1_dsw_r)));
m_maincpu->space(AS_PROGRAM).install_write_handler(0x800180, 0x800187, write16s_delegate(*this, FUNC(fcrash_state::cps1_soundlatch_w)));
m_maincpu->space(AS_PROGRAM).install_write_handler(0x980000, 0x98002f, write16_delegate(*this, FUNC(fcrash_state::kodb_layer_w)));
/* the original game alternates between 2 sprite ram areas to achieve flashing sprites - the bootleg doesn't do the write to the register to achieve this

4
src/mame/drivers/galaga.cpp
View File

@ -809,12 +809,12 @@ TIMER_CALLBACK_MEMBER(galaga_state::cpu3_interrupt_callback)
}
READ8_MEMBER(digdug_state::earom_read)
uint8_t digdug_state::earom_read()
{
return m_earom->data();
}
WRITE8_MEMBER(digdug_state::earom_write)
void digdug_state::earom_write(offs_t offset, uint8_t data)
{
m_earom->set_address(offset & 0x3f);
m_earom->set_data(data);

2
src/mame/drivers/galaxia.cpp
View File

@ -103,7 +103,7 @@ WRITE8_MEMBER(galaxia_state::galaxia_video_w)
{
// m_screen->update_partial(m_screen->vpos());
m_bg_tilemap->mark_tile_dirty(offset);
cvs_video_or_color_ram_w(space, offset, data);
cvs_video_or_color_ram_w(offset, data);
}
WRITE8_MEMBER(galaxia_state::galaxia_scroll_w)

6
src/mame/drivers/vicdual.cpp
View File

@ -308,7 +308,7 @@ READ8_MEMBER(vicdual_state::depthch_io_r)
WRITE8_MEMBER(vicdual_state::depthch_io_w)
{
if (offset & 0x01) assert_coin_status();
if (offset & 0x04) depthch_audio_w(space, 0, data);
if (offset & 0x04) depthch_audio_w(data);
}
@ -1159,8 +1159,8 @@ WRITE8_MEMBER(vicdual_state::spacetrk_io_w)
WRITE8_MEMBER(carnival_state::carnival_io_w)
{
if (offset & 0x01) carnival_audio_1_w(space, 0, data);
if (offset & 0x02) carnival_audio_2_w(space, 0, data);
if (offset & 0x01) carnival_audio_1_w(data);
if (offset & 0x02) carnival_audio_2_w(data);
if (offset & 0x08) assert_coin_status();
if (offset & 0x40) palette_bank_w(space, 0, data);
}

20
src/mame/includes/cabal.h
View File

@ -49,21 +49,21 @@ public:
int m_sound_command2;
// common
DECLARE_WRITE16_MEMBER(flipscreen_w);
DECLARE_WRITE16_MEMBER(background_videoram_w);
DECLARE_WRITE16_MEMBER(text_videoram_w);
void flipscreen_w(offs_t offset, uint16_t data, uint16_t mem_mask = ~0);
void background_videoram_w(offs_t offset, uint16_t data, uint16_t mem_mask = ~0);
void text_videoram_w(offs_t offset, uint16_t data, uint16_t mem_mask = ~0);
// cabal specific
void sound_irq_trigger_word_w(offs_t, u16 data, u16 mem_mask);
// cabalbl specific
DECLARE_WRITE16_MEMBER(cabalbl_sndcmd_w);
DECLARE_WRITE16_MEMBER(cabalbl_sound_irq_trigger_word_w);
DECLARE_READ8_MEMBER(cabalbl_snd2_r);
DECLARE_READ8_MEMBER(cabalbl_snd1_r);
DECLARE_WRITE8_MEMBER(cabalbl_coin_w);
DECLARE_WRITE8_MEMBER(cabalbl_1_adpcm_w);
DECLARE_WRITE8_MEMBER(cabalbl_2_adpcm_w);
void cabalbl_sndcmd_w(offs_t offset, uint16_t data);
void cabalbl_sound_irq_trigger_word_w(uint16_t data);
uint8_t cabalbl_snd2_r();
uint8_t cabalbl_snd1_r();
void cabalbl_coin_w(uint8_t data);
void cabalbl_1_adpcm_w(uint8_t data);
void cabalbl_2_adpcm_w(uint8_t data);
void init_cabal();
DECLARE_MACHINE_START(cabalbl);

4
src/mame/includes/calomega.h
View File

@ -49,8 +49,8 @@ protected:
virtual void video_start() override;
private:
DECLARE_WRITE8_MEMBER(calomega_videoram_w);
DECLARE_WRITE8_MEMBER(calomega_colorram_w);
void calomega_videoram_w(offs_t offset, uint8_t data);
void calomega_colorram_w(offs_t offset, uint8_t data);
uint8_t s903_mux_port_r();
void s903_mux_w(uint8_t data);
uint8_t s905_mux_port_r();

12
src/mame/includes/canyon.h
View File

@ -44,15 +44,15 @@ public:
void canyon(machine_config &config);
protected:
DECLARE_READ8_MEMBER(canyon_switches_r);
DECLARE_READ8_MEMBER(canyon_options_r);
DECLARE_WRITE8_MEMBER(output_latch_w);
DECLARE_WRITE8_MEMBER(canyon_videoram_w);
uint8_t canyon_switches_r(offs_t offset);
uint8_t canyon_options_r(offs_t offset);
void output_latch_w(offs_t offset, uint8_t data);
void canyon_videoram_w(offs_t offset, uint8_t data);
TILE_GET_INFO_MEMBER(get_bg_tile_info);
void canyon_palette(palette_device &palette) const;
uint32_t screen_update_canyon(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect);
DECLARE_WRITE8_MEMBER(canyon_motor_w);
DECLARE_WRITE8_MEMBER(canyon_explode_w);
void canyon_motor_w(offs_t offset, uint8_t data);
void canyon_explode_w(uint8_t data);
void draw_sprites( bitmap_ind16 &bitmap, const rectangle &cliprect );
void draw_bombs( bitmap_ind16 &bitmap, const rectangle &cliprect );

18
src/mame/includes/capbowl.h
View File

@ -55,19 +55,19 @@ public:
emu_timer *m_update_timer;
// common
DECLARE_READ8_MEMBER(track_0_r);
DECLARE_READ8_MEMBER(track_1_r);
DECLARE_WRITE8_MEMBER(track_reset_w);
DECLARE_WRITE8_MEMBER(sndcmd_w);
DECLARE_WRITE8_MEMBER(tms34061_w);
DECLARE_READ8_MEMBER(tms34061_r);
uint8_t track_0_r();
uint8_t track_1_r();
void track_reset_w(uint8_t data);
void sndcmd_w(uint8_t data);
void tms34061_w(offs_t offset, uint8_t data);
uint8_t tms34061_r(offs_t offset);
// capbowl specific
DECLARE_WRITE8_MEMBER(capbowl_rom_select_w);
void capbowl_rom_select_w(uint8_t data);
// bowlrama specific
DECLARE_WRITE8_MEMBER(bowlrama_blitter_w);
DECLARE_READ8_MEMBER(bowlrama_blitter_r);
void bowlrama_blitter_w(offs_t offset, uint8_t data);
uint8_t bowlrama_blitter_r(offs_t offset);
void init_capbowl();
virtual void machine_start() override;

28
src/mame/includes/carpolo.h
View File

@ -99,20 +99,20 @@ private:
std::unique_ptr<bitmap_ind16> m_sprite_goal_collision_bitmap2;
std::unique_ptr<bitmap_ind16> m_sprite_border_collision_bitmap;
DECLARE_READ8_MEMBER(ball_screen_collision_cause_r);
DECLARE_READ8_MEMBER(car_ball_collision_x_r);
DECLARE_READ8_MEMBER(car_ball_collision_y_r);
DECLARE_READ8_MEMBER(car_car_collision_cause_r);
DECLARE_READ8_MEMBER(car_goal_collision_cause_r);
DECLARE_READ8_MEMBER(car_ball_collision_cause_r);
DECLARE_READ8_MEMBER(car_border_collision_cause_r);
DECLARE_READ8_MEMBER(interrupt_cause_r);
DECLARE_WRITE8_MEMBER(ball_screen_interrupt_clear_w);
DECLARE_WRITE8_MEMBER(car_car_interrupt_clear_w);
DECLARE_WRITE8_MEMBER(car_goal_interrupt_clear_w);
DECLARE_WRITE8_MEMBER(car_ball_interrupt_clear_w);
DECLARE_WRITE8_MEMBER(car_border_interrupt_clear_w);
DECLARE_WRITE8_MEMBER(timer_interrupt_clear_w);
uint8_t ball_screen_collision_cause_r();
uint8_t car_ball_collision_x_r();
uint8_t car_ball_collision_y_r();
uint8_t car_car_collision_cause_r();
uint8_t car_goal_collision_cause_r();
uint8_t car_ball_collision_cause_r();
uint8_t car_border_collision_cause_r();
uint8_t interrupt_cause_r();
void ball_screen_interrupt_clear_w(uint8_t data);
void car_car_interrupt_clear_w(uint8_t data);
void car_goal_interrupt_clear_w(uint8_t data);
void car_ball_interrupt_clear_w(uint8_t data);
void car_border_interrupt_clear_w(uint8_t data);
void timer_interrupt_clear_w(uint8_t data);
void carpolo_palette(palette_device &palette) const;
uint32_t screen_update(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect);
DECLARE_WRITE_LINE_MEMBER(screen_vblank);

22
src/mame/includes/cbasebal.h
View File

@ -39,17 +39,17 @@ public:
/* misc */
uint8_t m_rambank;
DECLARE_WRITE8_MEMBER(cbasebal_bankswitch_w);
DECLARE_READ8_MEMBER(bankedram_r);
DECLARE_WRITE8_MEMBER(bankedram_w);
DECLARE_WRITE8_MEMBER(cbasebal_coinctrl_w);
DECLARE_WRITE8_MEMBER(cbasebal_textram_w);
DECLARE_READ8_MEMBER(cbasebal_textram_r);
DECLARE_WRITE8_MEMBER(cbasebal_scrollram_w);
DECLARE_READ8_MEMBER(cbasebal_scrollram_r);
DECLARE_WRITE8_MEMBER(cbasebal_gfxctrl_w);
DECLARE_WRITE8_MEMBER(cbasebal_scrollx_w);
DECLARE_WRITE8_MEMBER(cbasebal_scrolly_w);
void cbasebal_bankswitch_w(uint8_t data);
uint8_t bankedram_r(offs_t offset);
void bankedram_w(offs_t offset, uint8_t data);
void cbasebal_coinctrl_w(uint8_t data);
void cbasebal_textram_w(offs_t offset, uint8_t data);
uint8_t cbasebal_textram_r(offs_t offset);
void cbasebal_scrollram_w(offs_t offset, uint8_t data);
uint8_t cbasebal_scrollram_r(offs_t offset);
void cbasebal_gfxctrl_w(uint8_t data);
void cbasebal_scrollx_w(offs_t offset, uint8_t data);
void cbasebal_scrolly_w(offs_t offset, uint8_t data);
void init_cbasebal();
TILE_GET_INFO_MEMBER(get_bg_tile_info);
TILE_GET_INFO_MEMBER(get_fg_tile_info);

26
src/mame/includes/ccastles.h
View File

@ -36,20 +36,20 @@ public:
void ccastles(machine_config &config);
protected:
DECLARE_WRITE8_MEMBER(irq_ack_w);
DECLARE_READ8_MEMBER(leta_r);
DECLARE_WRITE8_MEMBER(nvram_recall_w);
void irq_ack_w(uint8_t data);
uint8_t leta_r(offs_t offset);
void nvram_recall_w(uint8_t data);
DECLARE_WRITE_LINE_MEMBER(nvram_store_w);
DECLARE_READ8_MEMBER(nvram_r);
DECLARE_WRITE8_MEMBER(nvram_w);
DECLARE_WRITE8_MEMBER(ccastles_hscroll_w);
DECLARE_WRITE8_MEMBER(ccastles_vscroll_w);
DECLARE_WRITE8_MEMBER(ccastles_video_control_w);
DECLARE_WRITE8_MEMBER(ccastles_paletteram_w);
DECLARE_WRITE8_MEMBER(ccastles_videoram_w);
DECLARE_READ8_MEMBER(ccastles_bitmode_r);
DECLARE_WRITE8_MEMBER(ccastles_bitmode_w);
DECLARE_WRITE8_MEMBER(ccastles_bitmode_addr_w);
uint8_t nvram_r(address_space &space, offs_t offset);
void nvram_w(offs_t offset, uint8_t data);
void ccastles_hscroll_w(uint8_t data);
void ccastles_vscroll_w(uint8_t data);
void ccastles_video_control_w(offs_t offset, uint8_t data);
void ccastles_paletteram_w(offs_t offset, uint8_t data);
void ccastles_videoram_w(offs_t offset, uint8_t data);
uint8_t ccastles_bitmode_r();
void ccastles_bitmode_w(uint8_t data);
void ccastles_bitmode_addr_w(offs_t offset, uint8_t data);
virtual void machine_start() override;
virtual void machine_reset() override;
virtual void video_start() override;

16
src/mame/includes/cchasm.h
View File

@ -58,14 +58,14 @@ public:
int m_ycenter;
emu_timer *m_refresh_end_timer;
DECLARE_WRITE16_MEMBER(led_w);
DECLARE_WRITE16_MEMBER(refresh_control_w);
DECLARE_WRITE8_MEMBER(reset_coin_flag_w);
DECLARE_READ8_MEMBER(coin_sound_r);
DECLARE_READ8_MEMBER(soundlatch2_r);
DECLARE_WRITE8_MEMBER(soundlatch4_w);
DECLARE_WRITE16_MEMBER(io_w);
DECLARE_READ16_MEMBER(io_r);
void led_w(offs_t offset, uint16_t data);
void refresh_control_w(offs_t offset, uint16_t data, uint16_t mem_mask = ~0);
void reset_coin_flag_w(uint8_t data);
uint8_t coin_sound_r();
uint8_t soundlatch2_r();
void soundlatch4_w(uint8_t data);
void io_w(offs_t offset, uint16_t data, uint16_t mem_mask = ~0);
uint16_t io_r(offs_t offset);
DECLARE_WRITE_LINE_MEMBER(ctc_timer_1_w);
DECLARE_WRITE_LINE_MEMBER(ctc_timer_2_w);

4
src/mame/includes/cdi.h
View File

@ -61,8 +61,8 @@ private:
void cdimono2_mem(address_map &map);
void cdi070_cpuspace(address_map &map);
DECLARE_READ16_MEMBER(dvc_r);
DECLARE_WRITE16_MEMBER(dvc_w);
uint16_t dvc_r(offs_t offset, uint16_t mem_mask = ~0);
void dvc_w(offs_t offset, uint16_t data, uint16_t mem_mask = ~0);
required_shared_ptr<uint16_t> m_planea;
optional_device<cdislave_hle_device> m_slave_hle;

44
src/mame/includes/centiped.h
View File

@ -82,39 +82,39 @@ private:
tilemap_t *m_bg_tilemap;
// drivers/centiped.cpp
DECLARE_WRITE8_MEMBER(irq_ack_w);
DECLARE_READ8_MEMBER(centiped_IN0_r);
DECLARE_READ8_MEMBER(centiped_IN2_r);
DECLARE_READ8_MEMBER(milliped_IN1_r);
DECLARE_READ8_MEMBER(milliped_IN2_r);
void irq_ack_w(uint8_t data);
uint8_t centiped_IN0_r();
uint8_t centiped_IN2_r();
uint8_t milliped_IN1_r();
uint8_t milliped_IN2_r();
DECLARE_WRITE_LINE_MEMBER(input_select_w);
DECLARE_WRITE_LINE_MEMBER(control_select_w);
DECLARE_READ8_MEMBER(mazeinv_input_r);
DECLARE_WRITE8_MEMBER(mazeinv_input_select_w);
DECLARE_READ8_MEMBER(bullsdrt_data_port_r);
uint8_t mazeinv_input_r();
void mazeinv_input_select_w(offs_t offset, uint8_t data);
uint8_t bullsdrt_data_port_r();
DECLARE_WRITE_LINE_MEMBER(coin_counter_left_w);
DECLARE_WRITE_LINE_MEMBER(coin_counter_center_w);
DECLARE_WRITE_LINE_MEMBER(coin_counter_right_w);
DECLARE_WRITE_LINE_MEMBER(bullsdrt_coin_count_w);
DECLARE_READ8_MEMBER(earom_read);
DECLARE_WRITE8_MEMBER(earom_write);
uint8_t earom_read();
void earom_write(offs_t offset, uint8_t data);
void earom_control_w(uint8_t data);
uint8_t caterplr_unknown_r();
DECLARE_WRITE8_MEMBER(caterplr_AY8910_w);
DECLARE_READ8_MEMBER(caterplr_AY8910_r);
DECLARE_READ8_MEMBER(multiped_eeprom_r);
DECLARE_WRITE8_MEMBER(multiped_eeprom_w);
DECLARE_WRITE8_MEMBER(multiped_prgbank_w);
void caterplr_AY8910_w(offs_t offset, uint8_t data);
uint8_t caterplr_AY8910_r(offs_t offset);
uint8_t multiped_eeprom_r();
void multiped_eeprom_w(offs_t offset, uint8_t data);
void multiped_prgbank_w(uint8_t data);
// video/centiped.cpp
DECLARE_WRITE8_MEMBER(centiped_videoram_w);
void centiped_videoram_w(offs_t offset, uint8_t data);
DECLARE_WRITE_LINE_MEMBER(flip_screen_w);
DECLARE_WRITE8_MEMBER(multiped_gfxbank_w);
DECLARE_WRITE8_MEMBER(bullsdrt_tilesbank_w);
DECLARE_WRITE8_MEMBER(bullsdrt_sprites_bank_w);
DECLARE_WRITE8_MEMBER(centiped_paletteram_w);
DECLARE_WRITE8_MEMBER(milliped_paletteram_w);
DECLARE_WRITE8_MEMBER(mazeinv_paletteram_w);
void multiped_gfxbank_w(uint8_t data);
void bullsdrt_tilesbank_w(offs_t offset, uint8_t data);
void bullsdrt_sprites_bank_w(uint8_t data);
void centiped_paletteram_w(offs_t offset, uint8_t data);
void milliped_paletteram_w(offs_t offset, uint8_t data);
void mazeinv_paletteram_w(offs_t offset, uint8_t data);
TILE_GET_INFO_MEMBER(centiped_get_tile_info);
TILE_GET_INFO_MEMBER(warlords_get_tile_info);
TILE_GET_INFO_MEMBER(milliped_get_tile_info);

56
src/mame/includes/cgc7900.h
View File

@ -61,20 +61,20 @@ public:
required_device<palette_device> m_palette;
required_device<screen_device> m_screen;
required_memory_region m_char_rom;
required_shared_ptr<uint16_t> m_chrom_ram;
required_shared_ptr<uint16_t> m_plane_ram;
required_shared_ptr<uint16_t> m_clut_ram;
required_shared_ptr<uint16_t> m_overlay_ram;
required_shared_ptr<uint16_t> m_roll_bitmap;
required_shared_ptr<uint16_t> m_pan_x;
required_shared_ptr<uint16_t> m_pan_y;
required_shared_ptr<uint16_t> m_zoom;
required_shared_ptr<uint16_t> m_blink_select;
required_shared_ptr<uint16_t> m_plane_select;
required_shared_ptr<uint16_t> m_plane_switch;
required_shared_ptr<uint16_t> m_color_status_fg;
required_shared_ptr<uint16_t> m_color_status_bg;
required_shared_ptr<uint16_t> m_roll_overlay;
required_shared_ptr<u16> m_chrom_ram;
required_shared_ptr<u16> m_plane_ram;
required_shared_ptr<u16> m_clut_ram;
required_shared_ptr<u16> m_overlay_ram;
required_shared_ptr<u16> m_roll_bitmap;
required_shared_ptr<u16> m_pan_x;
required_shared_ptr<u16> m_pan_y;
required_shared_ptr<u16> m_zoom;
required_shared_ptr<u16> m_blink_select;
required_shared_ptr<u16> m_plane_select;
required_shared_ptr<u16> m_plane_switch;
required_shared_ptr<u16> m_color_status_fg;
required_shared_ptr<u16> m_color_status_bg;
required_shared_ptr<u16> m_roll_overlay;
required_device<i8251_device> m_i8251_0;
required_device<i8251_device> m_i8251_1;
@ -82,20 +82,20 @@ public:
virtual void machine_reset() override;
void cgc7900_palette(palette_device &palette) const;
uint32_t screen_update(screen_device &screen, bitmap_rgb32 &bitmap, const rectangle &cliprect);
u32 screen_update(screen_device &screen, bitmap_rgb32 &bitmap, const rectangle &cliprect);
DECLARE_READ16_MEMBER( keyboard_r );
DECLARE_WRITE16_MEMBER( keyboard_w );
DECLARE_WRITE16_MEMBER( interrupt_mask_w );
DECLARE_READ16_MEMBER( disk_data_r );
DECLARE_WRITE16_MEMBER( disk_data_w );
DECLARE_READ16_MEMBER( disk_status_r );
DECLARE_WRITE16_MEMBER( disk_command_w );
DECLARE_READ16_MEMBER( z_mode_r );
DECLARE_WRITE16_MEMBER( z_mode_w );
DECLARE_WRITE16_MEMBER( color_status_w );
DECLARE_READ16_MEMBER( sync_r );
DECLARE_READ16_MEMBER( unmapped_r );
u16 keyboard_r();
void keyboard_w(u16 data);
void interrupt_mask_w(u16 data);
u16 disk_data_r();
void disk_data_w(u16 data);
u16 disk_status_r();
void disk_command_w(u16 data);
u16 z_mode_r();
void z_mode_w(u16 data);
void color_status_w(u16 data);
u16 sync_r();
u16 unmapped_r();
template <unsigned N> DECLARE_WRITE_LINE_MEMBER(irq) { irq_encoder(N, state); }
@ -104,7 +104,7 @@ public:
void draw_overlay(screen_device *screen, bitmap_rgb32 &bitmap);
/* interrupt state */
uint16_t m_int_mask, m_int_active;
u16 m_int_mask, m_int_active;
/* video state */
rgb_t m_clut[256];

12
src/mame/includes/chaknpop.h
View File

@ -44,15 +44,15 @@ public:
uint8_t m_flip_x;
uint8_t m_flip_y;
DECLARE_WRITE8_MEMBER(coinlock_w);
DECLARE_READ8_MEMBER(gfxmode_r);
DECLARE_WRITE8_MEMBER(gfxmode_w);
DECLARE_WRITE8_MEMBER(txram_w);
DECLARE_WRITE8_MEMBER(attrram_w);
void coinlock_w(uint8_t data);
uint8_t gfxmode_r();
void gfxmode_w(uint8_t data);
void txram_w(offs_t offset, uint8_t data);
void attrram_w(offs_t offset, uint8_t data);
void unknown_port_1_w(uint8_t data);
void unknown_port_2_w(uint8_t data);
void unknown_port_3_w(uint8_t data);
DECLARE_READ8_MEMBER(mcu_status_r);
uint8_t mcu_status_r();
TILE_GET_INFO_MEMBER(get_tx_tile_info);
virtual void machine_start() override;

4
src/mame/includes/champbas.h
View File

@ -52,11 +52,11 @@ public:
protected:
// handlers
DECLARE_WRITE_LINE_MEMBER(irq_enable_w);
DECLARE_READ8_MEMBER(champbja_protection_r);
uint8_t champbja_protection_r(offs_t offset);
DECLARE_WRITE_LINE_MEMBER(vblank_irq);
DECLARE_WRITE8_MEMBER(tilemap_w);
void tilemap_w(offs_t offset, uint8_t data);
DECLARE_WRITE_LINE_MEMBER(gfxbank_w);
DECLARE_WRITE_LINE_MEMBER(palette_bank_w);
DECLARE_WRITE_LINE_MEMBER(flipscreen_w);

28
src/mame/includes/changela.h
View File

@ -54,27 +54,27 @@ public:
int m_dir_31;
/* devices */
DECLARE_READ8_MEMBER(mcu_r);
DECLARE_WRITE8_MEMBER(mcu_w);
uint8_t mcu_r();
void mcu_w(uint8_t data);
void changela_68705_port_a_w(uint8_t data);
void changela_68705_port_c_w(uint8_t data);
DECLARE_READ8_MEMBER(changela_24_r);
DECLARE_READ8_MEMBER(changela_25_r);
DECLARE_READ8_MEMBER(changela_30_r);
DECLARE_READ8_MEMBER(changela_31_r);
DECLARE_READ8_MEMBER(changela_2c_r);
DECLARE_READ8_MEMBER(changela_2d_r);
uint8_t changela_24_r();
uint8_t changela_25_r();
uint8_t changela_30_r();
uint8_t changela_31_r();
uint8_t changela_2c_r();
uint8_t changela_2d_r();
DECLARE_WRITE_LINE_MEMBER(mcu_pc_0_w);
DECLARE_WRITE_LINE_MEMBER(collision_reset_0_w);
DECLARE_WRITE_LINE_MEMBER(collision_reset_1_w);
DECLARE_WRITE_LINE_MEMBER(coin_counter_1_w);
DECLARE_WRITE_LINE_MEMBER(coin_counter_2_w);
DECLARE_WRITE8_MEMBER(changela_colors_w);
DECLARE_WRITE8_MEMBER(changela_mem_device_select_w);
DECLARE_WRITE8_MEMBER(changela_mem_device_w);
DECLARE_READ8_MEMBER(changela_mem_device_r);
DECLARE_WRITE8_MEMBER(changela_slope_rom_addr_hi_w);
DECLARE_WRITE8_MEMBER(changela_slope_rom_addr_lo_w);
void changela_colors_w(offs_t offset, uint8_t data);
void changela_mem_device_select_w(uint8_t data);
void changela_mem_device_w(offs_t offset, uint8_t data);
uint8_t changela_mem_device_r(offs_t offset);
void changela_slope_rom_addr_hi_w(uint8_t data);
void changela_slope_rom_addr_lo_w(uint8_t data);
virtual void machine_start() override;
virtual void machine_reset() override;
virtual void video_start() override;

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