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Cleanups and version bump

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This commit is contained in:
Miodrag Milanovic 2016-05-25 08:19:21 +02:00
parent c1230f8b9b
commit 68785dccfe
200 changed files with 5692 additions and 5747 deletions
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4
android-project/app/src/main/AndroidManifest.xml
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@ -4,8 +4,8 @@
-->
<manifest xmlns:android="http://schemas.android.com/apk/res/android"
package="org.mamedev.mame"
android:versionCode="173"
android:versionName="0.173"
android:versionCode="174"
android:versionName="0.174"
android:installLocation="auto">
<!-- Android 4.0 -->

2
hash/fmtowns_cd.xml
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@ -741,7 +741,7 @@ User/save disks that can be created from the game itself are not included.
<!--
The collection includes two Dalk images, one marked as "Trurip" and one marked as
"freeware". Analysis of the tracks shows that the data track is exactly the same, and
"freeware". Analysis of the tracks shows that the data track is exactly the same, and
audio tracks are the same but shifted forwards by 5980 bytes in the "freeware"
image. This difference is probably due to the read offset of the drive used
to dump the disk.

362
hash/gameboy.xml
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File diff suppressed because it is too large Load Diff

6
hash/gameking.xml
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@ -7,9 +7,9 @@
the 3-in-1 internal ROM of the system is not yet dumped: it contains the games
* 2003
* Drifter
* Miner
* 2003
* Drifter
* Miner
-->
<softwarelist name="gameking" description="TimeTop GameKing cartridges">

2
hash/gbcolor.xml
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@ -23151,7 +23151,7 @@ List of unconfirmed non retail roms
<software name="pocknaka">
<!-- Notes: GBC only -->
<description>Pocket no Naka no Ookoku (Jpn, Prototype)</description>
<year>2000</year> <!-- scheduled to be released January 2001 (3/11/2000 Famitsu) -->
<year>2000</year> <!-- scheduled to be released January 2001 (3/11/2000 Famitsu) -->
<publisher>Hector</publisher>
<info name="alt_title" value="ポケットの中の王国"/>
<part name="cart" interface="gameboy_cart">

4786
hash/neogeo.xml
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File diff suppressed because it is too large Load Diff

12
hash/nes.xml
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@ -61814,7 +61814,7 @@ preliminary proto for the PAL version, still running on NTSC systems) or the gfx
<year>19??</year>
<publisher>&lt;unknown&gt;</publisher>
<part name="cart" interface="nes_cart">
<feature name="slot" value="waixing_sgzlz" /> <!-- Mapper 178 in header, is it really? -->
<feature name="slot" value="waixing_sgzlz" /> <!-- Mapper 178 in header, is it really? -->
<feature name="pcb" value="WAIXING-SGZLZ" />
<dataarea name="prg" size="524288">
<rom name="gameinis pingpong (unl)[!].prg" size="524288" crc="d065b311" sha1="a74cddff12eb57735c770542b87af38171d54e8a" offset="00000" status="baddump" />
@ -69195,7 +69195,7 @@ Also notice that VRAM & WRAM are probably incorrect for some of these sets, at t
<year>19??</year>
<publisher>&lt;unknown&gt;</publisher>
<part name="cart" interface="nes_cart">
<feature name="slot" value="edu2k" /> <!-- Marked as mapper 178 in header -->
<feature name="slot" value="edu2k" /> <!-- Marked as mapper 178 in header -->
<feature name="pcb" value="UNL-EDU2000" />
<dataarea name="prg" size="524288">
<rom name="bravesoft windows 2000 (r)[!].prg" size="524288" crc="305d75b1" sha1="b6ccfab2c38786e09da662b3488dab2431894dd2" offset="00000" status="baddump" />
@ -76426,7 +76426,7 @@ be better to redump them properly. -->
<year>19??</year>
<publisher>&lt;unknown&gt;</publisher>
<part name="cart" interface="nes_cart">
<feature name="slot" value="xiaozy" /> <!-- header give 176, but is it correct? -->
<feature name="slot" value="xiaozy" /> <!-- header give 176, but is it correct? -->
<feature name="pcb" value="UNL-XZY" />
<dataarea name="chr" size="1048576">
<rom name="125-in-1 [p1][!].chr" size="1048576" crc="56520c13" sha1="9490fdcc34bbf5905098835d748c56ec89d3d5ba" offset="00000" status="baddump" />
@ -76918,7 +76918,7 @@ be better to redump them properly. -->
<year>19??</year>
<publisher>&lt;pirate&gt;</publisher>
<part name="cart" interface="nes_cart">
<feature name="slot" value="bmc_hik300" /> <!-- header gives 212, but is it correct? -->
<feature name="slot" value="bmc_hik300" /> <!-- header gives 212, but is it correct? -->
<feature name="pcb" value="BMC-SUPERHIK-300IN1" />
<dataarea name="chr" size="65536">
<rom name="200-in-1 (unchained melody)[p1][!].chr" size="65536" crc="aa97eff7" sha1="68ffcb379e3c3ad44b0b5ea4df47118c811d9d0d" offset="00000" status="baddump" />
@ -76934,7 +76934,7 @@ be better to redump them properly. -->
<year>19??</year>
<publisher>&lt;pirate&gt;</publisher>
<part name="cart" interface="nes_cart">
<feature name="slot" value="bmc_gc6in1" /> <!-- header gives 217, but is it correct? -->
<feature name="slot" value="bmc_gc6in1" /> <!-- header gives 217, but is it correct? -->
<feature name="pcb" value="BMC-GOLDENCARD-6IN1" />
<dataarea name="chr" size="65536">
<rom name="2000-in-1 (no splash, no rev, alt mapper)[p1][!].chr" size="65536" crc="4a0611c1" sha1="8a1869ce3aff1c34a743c9cc3f22f01df5be2c77" offset="00000" status="baddump" />
@ -79024,7 +79024,7 @@ be better to redump them properly. -->
<year>19??</year>
<publisher>&lt;pirate&gt;</publisher>
<part name="cart" interface="nes_cart">
<feature name="slot" value="bmc_hik300" /> <!-- header gives 212, but is it correct? -->
<feature name="slot" value="bmc_hik300" /> <!-- header gives 212, but is it correct? -->
<feature name="pcb" value="BMC-SUPERHIK-300IN1" />
<dataarea name="chr" size="65536">
<rom name="9999-in-1 (anim splash, rev 13)[p1][!].chr" size="65536" crc="9b6e8be7" sha1="4c53a3d5e510c4355041b9ad88f1e633ce85f916" offset="00000" status="baddump" />

12
hash/pockchalv2.xml
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@ -7,19 +7,19 @@
List of software from ja.wikipedia.org (which might miss some later re-release)
* 進研ゼミ 中学講座
中1数学 [dumped]
中1数学 [dumped]
中2数学
実技4教科 [dumped x 2]
実技4教科 [dumped x 2]
中学理科 (1分野)
中学理科 (2分野)
中学理科パック [dumped x 2]
中学理科パック [dumped x 2]
中学地理
中学歴史
中学地理・歴史パック [dumped x 3]
中1 ENGLISH [dumped]
中学地理・歴史パック [dumped x 3]
中1 ENGLISH [dumped]
中2 ENGLISH
中学公民
中一国語・百人一首 [dumped]
中一国語・百人一首 [dumped]
中1 英数国パック
中2 英数国パック
中3 英・数・公民パック

38
hash/pockchalw.xml
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@ -9,9 +9,9 @@
* Shinkenzemi Koukou Kouza ~ 進研ゼミ 高校講座
頻出英単語
頻出英熟語 [dumped]
頻出英熟語 [dumped]
重要英語構文
重要古文攻略 [dumped]
重要古文攻略 [dumped]
頻出世界史攻略
頻出日本史攻略
@ -22,14 +22,14 @@
中三英語
中学理科(1分野)
中学理科(2分野)
中学理科パック [dumped]
中学理科パック [dumped]
中学歴史
中学地理 [dumped]
中学地理・歴史パック [dumped]
中学公民 [dumped x2]
高校受験(国・数) [dumped]
高校受験(英・社・理) [dumped]
実技4教科 [dumped]
中学地理 [dumped]
中学地理・歴史パック [dumped]
中学公民 [dumped x2]
高校受験(国・数) [dumped]
高校受験(英・社・理) [dumped]
実技4教科 [dumped]
-->
@ -112,12 +112,12 @@
<feature name="u2" value="74HC139A" />
<feature name="u3" value="7W32F" />
<feature name="u4" value="7W00F" />
<feature name="u5" value="[unpopulated]" /> <!-- space for a TC7W04 -->
<feature name="u6" value="[unpopulated]" /> <!-- space for a 74HC125 -->
<feature name="u7" value="[unpopulated]" /> <!-- space for a TC7W08 -->
<feature name="u5" value="[unpopulated]" /> <!-- space for a TC7W04 -->
<feature name="u6" value="[unpopulated]" /> <!-- space for a 74HC125 -->
<feature name="u7" value="[unpopulated]" /> <!-- space for a TC7W08 -->
<feature name="u8" value="74HC573A" />
<feature name="u9" value="PS 0BD400 00REPCS C1D1" /> <!-- mask ROM -->
<feature name="u10" value="[unpopulated]" /> <!-- space for a second mask ROM? -->
<feature name="u9" value="PS 0BD400 00REPCS C1D1" /> <!-- mask ROM -->
<feature name="u10" value="[unpopulated]" /> <!-- space for a second mask ROM? -->
<feature name="u11" value="LH52256CN-70LL" />
<feature name="u12" value="7W00F" />
<feature name="u13" value="946 80B" />
@ -140,12 +140,12 @@
<feature name="u2" value="74HC139A" />
<feature name="u3" value="7W32F" />
<feature name="u4" value="7W00F" />
<feature name="u5" value="[unpopulated]" /> <!-- space for a TC7W04 -->
<feature name="u6" value="[unpopulated]" /> <!-- space for a 74HC125 -->
<feature name="u7" value="[unpopulated]" /> <!-- space for a TC7W08 -->
<feature name="u5" value="[unpopulated]" /> <!-- space for a TC7W04 -->
<feature name="u6" value="[unpopulated]" /> <!-- space for a 74HC125 -->
<feature name="u7" value="[unpopulated]" /> <!-- space for a TC7W08 -->
<feature name="u8" value="74HC573A" />
<feature name="u9" value="PL 0BF400 00PCR C1/D1" /> <!-- mask ROM -->
<feature name="u10" value="[unpopulated]" /> <!-- space for a second mask ROM? -->
<feature name="u9" value="PL 0BF400 00PCR C1/D1" /> <!-- mask ROM -->
<feature name="u10" value="[unpopulated]" /> <!-- space for a second mask ROM? -->
<feature name="u11" value="LH52256CN-70LL" />
<feature name="u12" value="7W00F" />
<feature name="u13" value="012 80B" />

2
hash/r9751.xml
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@ -194,7 +194,7 @@
<part name="flop6" interface="floppy_3_5">
<feature name="part_id" value="Disk 6" />
<dataarea name="flop" size="1474560">
<rom name="Siemens.9751.CBX.Release.9005.2.79.Disk6.img" size="1474560" crc="e750915c" sha1="70cd126b465ce38520808fd9e8285411c9d4875c" offset="0" />
<rom name="Siemens.9751.CBX.Release.9005.2.79.Disk6.img" size="1474560" crc="e750915c" sha1="70cd126b465ce38520808fd9e8285411c9d4875c" offset="0" />
</dataarea>
</part>
<part name="flop7" interface="floppy_3_5">

24
hash/sat_vccart.xml
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@ -9,20 +9,20 @@
Note from zyrobs (the dumper):
Note that the standard Saturn ROM header is preceded by
20 kbyte of encrypted SH1 code. This code is uploaded to
the CD Block and provides the commands necessary for the
cart to work.
Special Thanks to James Laird for figuring out what
this very important piece of code was.
Note that the standard Saturn ROM header is preceded by
20 kbyte of encrypted SH1 code. This code is uploaded to
the CD Block and provides the commands necessary for the
cart to work.
Special Thanks to James Laird for figuring out what
this very important piece of code was.
The Saturn sees the ROM with a 20kbyte offset shift, putting
the standard Saturn ROM header at position 0 and the
encrypted code looping back to the end of the ROM data.
The Saturn sees the ROM with a 20kbyte offset shift, putting
the standard Saturn ROM header at position 0 and the
encrypted code looping back to the end of the ROM data.
If you are dumping your MPEG cart through the Saturn, make
sure to take account of this offset shift when calculating
checksums.
If you are dumping your MPEG cart through the Saturn, make
sure to take account of this offset shift when calculating
checksums.
-->

22
hash/snes_bspack.xml
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@ -7,15 +7,15 @@
fix our Satellaview emulation
1. games which come in pair GOOD + HACK are in most cases games whose header or some block
was corrupted making the memory pack not working. the "good" dump in this case is the original
version (because in most cases these are dumps made by Kiddo Cabbusses and his group
from real data pack and can be considered as 'proper')
was corrupted making the memory pack not working. the "good" dump in this case is the original
version (because in most cases these are dumps made by Kiddo Cabbusses and his group
from real data pack and can be considered as 'proper')
2. games which come in pair GOOD + BAD HEADER? are in most cases games whose header has been
cleaned up / restored by no-intro guys using investigation from various devs. the "good"
dump is the version in the no-intro set, the "bad header?" dump is the older version. This choice
is the opposite of the above one, but in this case the dumps with corrupted headers have not been
traced back to their origin, so that we cannot guarantee that the data was removed on the early
days of BS-X dumping...
cleaned up / restored by no-intro guys using investigation from various devs. the "good"
dump is the version in the no-intro set, the "bad header?" dump is the older version. This choice
is the opposite of the above one, but in this case the dumps with corrupted headers have not been
traced back to their origin, so that we cannot guarantee that the data was removed on the early
days of BS-X dumping...
In the end, we shall only keep the proper dumps, possibly patching the header on load, if necessary with
a ROM_LOAD overlay in the rom definitions...
@ -5109,9 +5109,9 @@
</software>
<!-- This comes from a memory pack whose data don't work, as if some content was missing.
Kiddo Cabbusses managed to fix it, by manually comparing the data with the other set
and 'transplanting' a bank of data which seemed blanked out. This is the result:
'broken' file first, hacked one afterwards.
Kiddo Cabbusses managed to fix it, by manually comparing the data with the other set
and 'transplanting' a bank of data which seemed blanked out. This is the result:
'broken' file first, hacked one afterwards.
-->
<software name="bsexbik1a" cloneof="bsexbik1" supported="no">
<description>Excitebike - Bunbun Mario Battle - Stadium 1 (Alt Data?)</description>

40
hash/to7_cart.xml
View File

@ -150,17 +150,17 @@
</software>
<!--
<software name="colorpnta" cloneof="colorpnt" supported="no">
<description>Colorpaint (Bad)</description>
<year>1985</year>
<publisher>France Image Logiciel (FIL)</publisher>
<software name="colorpnta" cloneof="colorpnt" supported="no">
<description>Colorpaint (Bad)</description>
<year>1985</year>
<publisher>France Image Logiciel (FIL)</publisher>
<part name="cart" interface="to_cart">
<dataarea name="rom" size="32768">
<rom name="colorpeint_memo7.rom" size="32768" crc="e1234738" sha1="3f170f1b7bc39e32edc8fa9b4a02d70d4d0a8ee2" offset="0" status="baddump" />
</dataarea>
</part>
</software>
<part name="cart" interface="to_cart">
<dataarea name="rom" size="32768">
<rom name="colorpeint_memo7.rom" size="32768" crc="e1234738" sha1="3f170f1b7bc39e32edc8fa9b4a02d70d4d0a8ee2" offset="0" status="baddump" />
</dataarea>
</part>
</software>
-->
<software name="colorpnt_de" cloneof="colorpnt">
@ -394,17 +394,17 @@
</software>
<!--
<software name="scriptora" cloneof="scriptor">
<description>Scriptor (Extra Data)</description>
<year>1984</year>
<publisher>TO TEK International</publisher>
<software name="scriptora" cloneof="scriptor">
<description>Scriptor (Extra Data)</description>
<year>1984</year>
<publisher>TO TEK International</publisher>
<part name="cart" interface="to_cart">
<dataarea name="rom" size="16394">
<rom name="scriptor (totek) (inconnus) (1986) (memo7).bin" size="16394" crc="46d4e43a" sha1="90c1e35468f7d629babbd529cd22116e086adb44" offset="0" status="baddump" />
</dataarea>
</part>
</software>
<part name="cart" interface="to_cart">
<dataarea name="rom" size="16394">
<rom name="scriptor (totek) (inconnus) (1986) (memo7).bin" size="16394" crc="46d4e43a" sha1="90c1e35468f7d629babbd529cd22116e086adb44" offset="0" status="baddump" />
</dataarea>
</part>
</software>
-->
<software name="studio">

55
src/devices/bus/a2bus/pc_xporter.cpp
View File

@ -39,20 +39,20 @@
Fxxxx on the V30 so that it can boot.
RAM from 0xB8000-0xBFFFF is the CGA framebuffer as usual.
C800-CFFE: RAM / registers, locations as follows
C828-C82A: bi-directional mailslots used to allow the PC to make ProDOS MLI calls,
likely for the HDD emulation (which uses a file on a ProDOS volume
as the PC).
$C828 = hi 8 bits of ptr to ProDOS call info, $C829 = middle 8 bits, $C82A = lower 8 bits
If bit 7 of $C828 is set, then the 6502 will take action.
C832: current CGA mode index, used by 6502 @ $6869 to setup 6845, or 6845 reg index
C833: 6845 data to write in the case where C832 is the reg index rather than a mode offset
C860-C864: PC ports 60h-64h, used for keyboard comms
CAC1: year for PC real-time clock
CAC2: month for PC real-time clock
CAC3: day for PC real-time clock
CAC4: hour for PC real-time clock
CAC5: minute for PC real-time clock
C800-CFFE: RAM / registers, locations as follows
C828-C82A: bi-directional mailslots used to allow the PC to make ProDOS MLI calls,
likely for the HDD emulation (which uses a file on a ProDOS volume
as the PC).
$C828 = hi 8 bits of ptr to ProDOS call info, $C829 = middle 8 bits, $C82A = lower 8 bits
If bit 7 of $C828 is set, then the 6502 will take action.
C832: current CGA mode index, used by 6502 @ $6869 to setup 6845, or 6845 reg index
C833: 6845 data to write in the case where C832 is the reg index rather than a mode offset
C860-C864: PC ports 60h-64h, used for keyboard comms
CAC1: year for PC real-time clock
CAC2: month for PC real-time clock
CAC3: day for PC real-time clock
CAC4: hour for PC real-time clock
CAC5: minute for PC real-time clock
CF00: PC memory pointer (bits 0-7)
CF01: PC memory pointer (bits 8-15)
CF02: PC memory pointer (bits 16-23)
@ -65,15 +65,15 @@
CF30: control/flags: bit 4 = 1 to release reset on V30, 5 = 1 to release halt on V30
bit 7: read for card IRQ status, write 1 to clear/disable? card IRQ
CF31: control/flags: bit 4 = 1 to assert reset on V30, 5 = 1 to assert halt on V30
if bit 3 is set on an IRQ, the 6502 will force color 80x25 CGA text mode.
bit 7: write 1 to enable card IRQ
if bit 3 is set on an IRQ, the 6502 will force color 80x25 CGA text mode.
bit 7: write 1 to enable card IRQ
TODO:
- Code at $70b0-$70c5 waits for the V30 to answer FPU presence.
- Code at $70b0-$70c5 waits for the V30 to answer FPU presence.
- What's going on at CF0E/CF0F? One value set for normal operation, another during
ProDOS calls. Probably safe to ignore.
- The manual indicates there is no ROM; special drivers installed into ProDOS 8
provide the RAMdisk and A2-accessing-PC-drives functionality.
- The manual indicates there is no ROM; special drivers installed into ProDOS 8
provide the RAMdisk and A2-accessing-PC-drives functionality.
*********************************************************************/
@ -104,7 +104,7 @@ static ADDRESS_MAP_START(pc_io, AS_IO, 16, a2bus_pcxporter_device )
ADDRESS_MAP_END
MACHINE_CONFIG_FRAGMENT( pcxporter )
MCFG_CPU_ADD("v30", V30, XTAL_14_31818MHz/2) // 7.16 MHz as per manual
MCFG_CPU_ADD("v30", V30, XTAL_14_31818MHz/2) // 7.16 MHz as per manual
MCFG_CPU_PROGRAM_MAP(pc_map)
MCFG_CPU_IO_MAP(pc_io)
MCFG_CPU_IRQ_ACKNOWLEDGE_DEVICE("pic8259", pic8259_device, inta_cb)
@ -382,12 +382,12 @@ void a2bus_pcxporter_device::write_c800(address_space &space, UINT16 offset, UIN
else if (m_offset >= 0xbc000 && m_offset <= 0xbffff) m_pcmem_space->write_byte(m_offset-0x4000, data);
break;
case 0x72c: // CGA 6845 register select
case 0x72c: // CGA 6845 register select
m_pcio_space->write_byte(0x3d6, data);
m_6845_reg = data;
break;
case 0x72d: // CGA 6845 data read/write
case 0x72d: // CGA 6845 data read/write
// HACK: adjust the 40 column mode the 6502 sets to
// be more within specs.
switch (m_6845_reg)
@ -417,7 +417,7 @@ void a2bus_pcxporter_device::write_c800(address_space &space, UINT16 offset, UIN
m_pcio_space->write_byte(0x3d7, data);
break;
case 0x72e: // CGA mode select
case 0x72e: // CGA mode select
m_pcio_space->write_byte(0x3d8, data);
break;
@ -425,7 +425,7 @@ void a2bus_pcxporter_device::write_c800(address_space &space, UINT16 offset, UIN
m_pcio_space->write_byte(0x3d9, data);
break;
case 0x730: // control 1
case 0x730: // control 1
if (data & 0x10) { m_v30->set_input_line(INPUT_LINE_RESET, CLEAR_LINE); m_reset_during_halt = true; }
if (data & 0x20)
{
@ -440,13 +440,13 @@ void a2bus_pcxporter_device::write_c800(address_space &space, UINT16 offset, UIN
}
break;
case 0x731: // control 2
case 0x731: // control 2
if (data & 0x10) m_v30->set_input_line(INPUT_LINE_RESET, ASSERT_LINE);
if (data & 0x20) m_v30->set_input_line(INPUT_LINE_HALT, ASSERT_LINE);
break;
default:
// printf("%02x to C800 at %x\n", data, offset + 0xc800);
// printf("%02x to C800 at %x\n", data, offset + 0xc800);
m_regs[offset] = data;
break;
}
@ -646,6 +646,3 @@ WRITE8_MEMBER( a2bus_pcxporter_device::nmi_enable_w )
m_nmi_enabled = BIT(data,7);
m_isabus->set_nmi_state(m_nmi_enabled);
}

2
src/devices/bus/gba/rom.cpp
View File

@ -492,7 +492,7 @@ WRITE32_MEMBER(gba_rom_3dmatrix_device::write_mapper)
switch (offset & 3)
{
case 0:
if (data == 0x1) // transfer data
if (data == 0x1) // transfer data
memcpy((UINT8 *)m_romhlp + m_dst, (UINT8 *)m_rom + m_src, m_nblock * 0x200);
else
printf("Unknown mapper command 0x%X\n", data);

1
src/devices/bus/megadrive/eeprom.cpp
View File

@ -635,4 +635,3 @@ WRITE16_MEMBER(md_eeprom_nbajam_device_alt::write)
eeprom_i2c_update();
}
}

10
src/devices/bus/megadrive/eeprom.h
View File

@ -164,7 +164,7 @@ public:
md_eeprom_nbajam_device_alt(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
// device-level overrides
// virtual machine_config_constructor device_mconfig_additions() const override;
// virtual machine_config_constructor device_mconfig_additions() const override;
virtual void device_start() override;
// reading and writing
@ -180,13 +180,13 @@ public:
private:
// EEPROM runtime vars
UINT8 m_eeprom_sda; // current SDA
UINT8 m_eeprom_prev_sda; // previous SDA
UINT8 m_eeprom_scl; // current SCL
UINT8 m_eeprom_sda; // current SDA
UINT8 m_eeprom_prev_sda; // previous SDA
UINT8 m_eeprom_scl; // current SCL
UINT8 m_eeprom_prev_scl; // previous SCL
UINT8 m_eeprom_cnt; // operation count in 0-9
UINT8 m_eeprom_readwrite; // read/write bit
UINT16 m_eeprom_slave_mask; // dev addr
UINT16 m_eeprom_slave_mask; // dev addr
UINT16 m_eeprom_word_address; // memory addr
UINT16 m_eeprom_devsel; // selected device
UINT16 m_eeprom_byte; // byte to be written

1
src/devices/bus/megadrive/rom.cpp
View File

@ -1532,4 +1532,3 @@ WRITE16_MEMBER(md_rom_starodys_device::write_a13)
m_nvram_handlers_installed = 1;
}
}

1
src/devices/bus/neogeo/boot_cthd.cpp
View File

@ -133,4 +133,3 @@ machine_config_constructor neogeo_matrimbl_cart::device_mconfig_additions() cons
{
return MACHINE_CONFIG_NAME( matrimbl_cart );
}

4
src/devices/bus/neogeo/boot_kof10th.cpp
View File

@ -103,9 +103,9 @@ WRITE16_MEMBER(neogeo_kof10th_cart::protection_w)
if (offset < 0x40000/2)
{
if (!m_cart_ram[0xffe])
COMBINE_DATA(&m_cart_ram2[(0x00000/2) + (offset & 0xffff)]); // Write to RAM bank A
COMBINE_DATA(&m_cart_ram2[(0x00000/2) + (offset & 0xffff)]); // Write to RAM bank A
else
m_fixed[offset] = BITSWAP8(data, 7,6,0,4,3,2,1,5); // Write S data on-the-fly
m_fixed[offset] = BITSWAP8(data, 7,6,0,4,3,2,1,5); // Write S data on-the-fly
}
else if (offset >= 0xfe000/2)
{

2
src/devices/bus/neogeo/boot_kof2k2.cpp
View File

@ -106,5 +106,3 @@ void neogeo_kf2k2mp2_cart::decrypt_all(DECRYPT_ALL_PARAMS)
m_prot->sx_decrypt(fix_region, fix_region_size, 1);
m_cmc_prot->cmc50_gfx_decrypt(spr_region, spr_region_size, KOF2002_GFX_KEY);
}

1
src/devices/bus/neogeo/boot_misc.cpp
View File

@ -286,4 +286,3 @@ void neogeo_kog_cart::decrypt_all(DECRYPT_ALL_PARAMS)
m_prot->sx_decrypt(fix_region, fix_region_size, 1);
m_prot->cx_decrypt(spr_region, spr_region_size);
}

22
src/devices/bus/neogeo/carts.cpp
View File

@ -24,12 +24,12 @@
SLOT_INTERFACE_START(neogeo_cart)
SLOT_INTERFACE_INTERNAL("rom", NEOGEO_ROM) // Standard cart with banking
SLOT_INTERFACE_INTERNAL("rom", NEOGEO_ROM) // Standard cart with banking
SLOT_INTERFACE_INTERNAL("rom_vliner", NEOGEO_VLINER_CART) // Standard cart + RAM
SLOT_INTERFACE_INTERNAL("rom_fatfur2", NEOGEO_FATFURY2_CART) // Custom Fatal Fury 2 protection
SLOT_INTERFACE_INTERNAL("rom_kof98", NEOGEO_KOF98_CART) // Custom King of Fighters 98 protection
SLOT_INTERFACE_INTERNAL("rom_mslugx", NEOGEO_MSLUGX_CART) // Custom Metal Slug X protection
SLOT_INTERFACE_INTERNAL("rom_vliner", NEOGEO_VLINER_CART) // Standard cart + RAM
SLOT_INTERFACE_INTERNAL("rom_fatfur2", NEOGEO_FATFURY2_CART) // Custom Fatal Fury 2 protection
SLOT_INTERFACE_INTERNAL("rom_kof98", NEOGEO_KOF98_CART) // Custom King of Fighters 98 protection
SLOT_INTERFACE_INTERNAL("rom_mslugx", NEOGEO_MSLUGX_CART) // Custom Metal Slug X protection
// only CMC42 for gfx
SLOT_INTERFACE_INTERNAL("cmc42_zupapa", NEOGEO_CMC_ZUPAPA_CART)
@ -45,7 +45,7 @@ SLOT_INTERFACE_START(neogeo_cart)
// only CMC50 for gfx + audiocpu
SLOT_INTERFACE_INTERNAL("cmc50_kof2001", NEOGEO_CMC_KOF2001_CART)
SLOT_INTERFACE_INTERNAL("cmc50_kof2000n", NEOGEO_CMC_KOF2000N_CART)
SLOT_INTERFACE_INTERNAL("cmc50_jockeygp", NEOGEO_CMC_JOCKEYGP_CART) // CMC50 + RAM
SLOT_INTERFACE_INTERNAL("cmc50_jockeygp", NEOGEO_CMC_JOCKEYGP_CART) // CMC50 + RAM
// These use SMA for prg & CMC42 for gfx
SLOT_INTERFACE_INTERNAL("sma_kof99", NEOGEO_SMA_KOF99_CART)
@ -78,13 +78,13 @@ SLOT_INTERFACE_START(neogeo_cart)
SLOT_INTERFACE_INTERNAL("boot_cthd2k3", NEOGEO_CTHD2K3_CART)
SLOT_INTERFACE_INTERNAL("boot_ct2k3sp", NEOGEO_CT2K3SP_CART)
SLOT_INTERFACE_INTERNAL("boot_ct2k3sa", NEOGEO_CT2K3SA_CART)
SLOT_INTERFACE_INTERNAL("boot_matrimbl", NEOGEO_MATRIMBL_CART) // this also uses a CMC for SFIX & addditional prg scramble from kof2002
SLOT_INTERFACE_INTERNAL("boot_matrimbl", NEOGEO_MATRIMBL_CART) // this also uses a CMC for SFIX & addditional prg scramble from kof2002
// Bootleg logic for SVC clones
SLOT_INTERFACE_INTERNAL("boot_svcboot", NEOGEO_SVCBOOT_CART) // this also uses a PVC protection/encryption
SLOT_INTERFACE_INTERNAL("boot_svcboot", NEOGEO_SVCBOOT_CART) // this also uses a PVC protection/encryption
SLOT_INTERFACE_INTERNAL("boot_svcplus", NEOGEO_SVCPLUS_CART)
SLOT_INTERFACE_INTERNAL("boot_svcplusa", NEOGEO_SVCPLUSA_CART)
SLOT_INTERFACE_INTERNAL("boot_svcsplus", NEOGEO_SVCSPLUS_CART) // this also uses a PVC protection/encryption
SLOT_INTERFACE_INTERNAL("boot_svcsplus", NEOGEO_SVCSPLUS_CART) // this also uses a PVC protection/encryption
// Bootleg logic for KOF2002 clones
SLOT_INTERFACE_INTERNAL("boot_kf2k2b", NEOGEO_KOF2002B_CART)
@ -104,8 +104,8 @@ SLOT_INTERFACE_START(neogeo_cart)
SLOT_INTERFACE_INTERNAL("boot_kf2k4se", NEOGEO_KF2K4SE_CART)
SLOT_INTERFACE_INTERNAL("boot_lans2004", NEOGEO_LANS2004_CART)
SLOT_INTERFACE_INTERNAL("boot_samsho5b", NEOGEO_SAMSHO5B_CART)
SLOT_INTERFACE_INTERNAL("boot_mslug3b6", NEOGEO_MSLUG3B6_CART) // this also uses a CMC42 for gfx
SLOT_INTERFACE_INTERNAL("boot_ms5plus", NEOGEO_MS5PLUS_CART) // this also uses a CMC50 for gfx + audiocpu & NEOPCM2 for YM scramble
SLOT_INTERFACE_INTERNAL("boot_mslug3b6", NEOGEO_MSLUG3B6_CART) // this also uses a CMC42 for gfx
SLOT_INTERFACE_INTERNAL("boot_ms5plus", NEOGEO_MS5PLUS_CART) // this also uses a CMC50 for gfx + audiocpu & NEOPCM2 for YM scramble
SLOT_INTERFACE_INTERNAL("boot_kog", NEOGEO_KOG_CART)
SLOT_INTERFACE_INTERNAL("boot_kf10th", NEOGEO_KOF10TH_CART)

1
src/devices/bus/neogeo/cmc.cpp
View File

@ -264,4 +264,3 @@ void neogeo_cmc_jockeygp_cart::decrypt_all(DECRYPT_ALL_PARAMS)
m_prot->cmc50_gfx_decrypt(spr_region, spr_region_size, JOCKEYGP_GFX_KEY);
m_prot->sfix_decrypt(spr_region, spr_region_size, fix_region, fix_region_size);
}

1
src/devices/bus/neogeo/fatfury2.cpp
View File

@ -50,4 +50,3 @@ machine_config_constructor neogeo_fatfury2_cart::device_mconfig_additions() cons
{
return MACHINE_CONFIG_NAME( fatfury2_cart );
}

1
src/devices/bus/neogeo/mslugx.cpp
View File

@ -50,4 +50,3 @@ machine_config_constructor neogeo_mslugx_cart::device_mconfig_additions() const
{
return MACHINE_CONFIG_NAME( mslugx_cart );
}

1
src/devices/bus/neogeo/pcm2.cpp
View File

@ -132,4 +132,3 @@ void neogeo_pcm2_pnyaa_cart::decrypt_all(DECRYPT_ALL_PARAMS)
m_cmc_prot->sfix_decrypt(spr_region, spr_region_size, fix_region, fix_region_size);
m_pcm2_prot->decrypt(ym_region, ym_region_size, 4);
}

4
src/devices/bus/neogeo/pcm2.h
View File

@ -23,9 +23,9 @@ public:
virtual machine_config_constructor device_mconfig_additions() const override;
// reading and writing
// virtual DECLARE_READ16_MEMBER(read_rom) override;
// virtual DECLARE_READ16_MEMBER(read_rom) override;
// virtual void activate_cart(ACTIVATE_CART_PARAMS) override { m_banked_cart->install_banks(machine, maincpu, cpuregion, cpuregion_size); }
// virtual void activate_cart(ACTIVATE_CART_PARAMS) override { m_banked_cart->install_banks(machine, maincpu, cpuregion, cpuregion_size); }
virtual void decrypt_all(DECRYPT_ALL_PARAMS) override {}
virtual int get_fixed_bank_type(void) override { return 0; }

20
src/devices/bus/neogeo/prot_cthd.cpp
View File

@ -119,16 +119,16 @@ void cthd_prot_device::decrypt_cthd2003(UINT8* sprrom, UINT32 sprrom_size, UINT8
/*
WRITE16_MEMBER( ngbootleg_prot_device::cthd2003_bankswitch_w )
{
int bankaddress;
static const int cthd2003_banks[8] =
{
1,0,1,0,1,0,3,2,
};
if (offset == 0)
{
bankaddress = 0x100000 + cthd2003_banks[data&7]*0x100000;
m_bankdev->neogeo_set_main_cpu_bank_address(bankaddress);
}
int bankaddress;
static const int cthd2003_banks[8] =
{
1,0,1,0,1,0,3,2,
};
if (offset == 0)
{
bankaddress = 0x100000 + cthd2003_banks[data&7]*0x100000;
m_bankdev->neogeo_set_main_cpu_bank_address(bankaddress);
}
}
*/

1
src/devices/bus/neogeo/prot_fatfury2.cpp
View File

@ -99,4 +99,3 @@ WRITE16_MEMBER( fatfury2_prot_device::protection_w )
break;
}
}

1
src/devices/bus/neogeo/prot_kof2k3bl.cpp
View File

@ -130,4 +130,3 @@ void kof2k3bl_prot_device::upl_px_decrypt(UINT8* cpurom, UINT32 cpurom_size)
UINT16* rom16 = (UINT16*)cpurom;
m_overlay = rom16[0x58196 / 2];
}

1
src/devices/bus/neogeo/prot_kof98.cpp
View File

@ -125,4 +125,3 @@ WRITE16_MEMBER( kof98_prot_device::protection_w )
break;
}
}

39
src/devices/bus/neogeo/prot_misc.cpp
View File

@ -276,22 +276,22 @@ READ16_MEMBER( neoboot_prot_device::mslug5p_prot_r )
/*
WRITE16_MEMBER( neoboot_prot_device::ms5plus_bankswitch_w )
{
int bankaddress;
logerror("offset: %06x PC %06x: set banking %04x\n",offset,space.device().safe_pc(),data);
if ((offset == 0) && (data == 0xa0))
{
bankaddress = 0xa0;
m_bankdev->neogeo_set_main_cpu_bank_address(bankaddress);
logerror("offset: %06x PC %06x: set banking %04x\n\n",offset,space.device().safe_pc(),bankaddress);
}
else if(offset == 2)
{
data = data >> 4;
//data = data & 7;
bankaddress = data * 0x100000;
m_bankdev->neogeo_set_main_cpu_bank_address(bankaddress);
logerror("offset: %06x PC %06x: set banking %04x\n\n",offset,space.device().safe_pc(),bankaddress);
}
int bankaddress;
logerror("offset: %06x PC %06x: set banking %04x\n",offset,space.device().safe_pc(),data);
if ((offset == 0) && (data == 0xa0))
{
bankaddress = 0xa0;
m_bankdev->neogeo_set_main_cpu_bank_address(bankaddress);
logerror("offset: %06x PC %06x: set banking %04x\n\n",offset,space.device().safe_pc(),bankaddress);
}
else if(offset == 2)
{
data = data >> 4;
//data = data & 7;
bankaddress = data * 0x100000;
m_bankdev->neogeo_set_main_cpu_bank_address(bankaddress);
logerror("offset: %06x PC %06x: set banking %04x\n\n",offset,space.device().safe_pc(),bankaddress);
}
}
*/
@ -429,8 +429,8 @@ void neoboot_prot_device::svcplus_px_decrypt(UINT8* cpurom, UINT32 cpurom_size)
for (int i = 0; i < size / 2; i++)
{
int ofst = BITSWAP24((i & 0xfffff), 0x17, 0x16, 0x15, 0x14, 0x13, 0x00, 0x01, 0x02,
0x0f, 0x0e, 0x0d, 0x0c, 0x0b, 0x0a, 0x09, 0x08,
0x07, 0x06, 0x05, 0x04, 0x03, 0x10, 0x11, 0x12);
0x0f, 0x0e, 0x0d, 0x0c, 0x0b, 0x0a, 0x09, 0x08,
0x07, 0x06, 0x05, 0x04, 0x03, 0x10, 0x11, 0x12);
ofst ^= 0x0f0007;
ofst += (i & 0xff00000);
memcpy(&src[i * 0x02], &dst[ofst * 0x02], 0x02);
@ -478,7 +478,7 @@ void neoboot_prot_device::svcsplus_px_decrypt(UINT8* cpurom, UINT32 cpurom_size)
for (int i = 0; i < size / 2; i++)
{
int ofst = BITSWAP16((i & 0x007fff), 0x0f, 0x00, 0x08, 0x09, 0x0b, 0x0a, 0x0c, 0x0d,
0x04, 0x03, 0x01, 0x07, 0x06, 0x02, 0x05, 0x0e);
0x04, 0x03, 0x01, 0x07, 0x06, 0x02, 0x05, 0x0e);
ofst += (i & 0x078000);
ofst += sec[(i & 0xf80000) >> 19] << 19;
@ -591,4 +591,3 @@ void neoboot_prot_device::kof10th_decrypt(UINT8* cpurom, UINT32 cpurom_size)
((UINT16*)src)[0x8bf6/2] = 0x000d;
((UINT16*)src)[0x8bf8/2] = 0xf980;
}

1
src/devices/bus/neogeo/prot_mslugx.cpp
View File

@ -84,4 +84,3 @@ READ16_MEMBER( mslugx_prot_device::protection_r )
return res;
}

13
src/devices/bus/neogeo/prot_pvc.cpp
View File

@ -59,10 +59,10 @@ void pvc_prot_device::pvc_write_pack_color()
/*void pvc_prot_device::pvc_write_bankswitch()
{
UINT32 bankaddress = ((m_cart_ram[0xff8] >> 8)|(m_cart_ram[0xff9] << 8));
m_cart_ram[0xff8] = (m_cart_ram[0xff8] & 0xfe00) | 0x00a0;
m_cart_ram[0xff9] &= 0x7fff;
m_bankdev->neogeo_set_main_cpu_bank_address(bankaddress + 0x100000);
UINT32 bankaddress = ((m_cart_ram[0xff8] >> 8)|(m_cart_ram[0xff9] << 8));
m_cart_ram[0xff8] = (m_cart_ram[0xff8] & 0xfe00) | 0x00a0;
m_cart_ram[0xff9] &= 0x7fff;
m_bankdev->neogeo_set_main_cpu_bank_address(bankaddress + 0x100000);
}
*/
@ -87,8 +87,8 @@ WRITE16_MEMBER( pvc_prot_device::protection_w )
else if (offset >= 0xff4 && offset <= 0xff5)
pvc_write_pack_color();
// FIXME: temporarily moved to the driver, through get_bank_base() above
// else if(offset >= 0xff8)
// pvc_write_bankswitch(space);
// else if(offset >= 0xff8)
// pvc_write_bankswitch(space);
}
@ -289,4 +289,3 @@ void pvc_prot_device::kof2003h_decrypt_68k(UINT8* rom, UINT32 size)
memcpy(&rom[0x100000], &buf[0x800000], 0x100000);
memcpy(&rom[0x200000], &buf[0x100000], 0x700000);
}

2
src/devices/bus/neogeo/prot_pvc.h
View File

@ -20,7 +20,7 @@ public:
void pvc_write_unpack_color();
void pvc_write_pack_color();
// void pvc_write_bankswitch(address_space &space);
// void pvc_write_bankswitch(address_space &space);
UINT32 get_bank_base();
DECLARE_READ16_MEMBER(protection_r);
DECLARE_WRITE16_MEMBER(protection_w);

2
src/devices/bus/neogeo/prot_sma.cpp
View File

@ -516,5 +516,3 @@ void sma_prot_device::kof2000_decrypt_68k(UINT8* base)
for (int i = 0; i < 0x0c0000/2; i++)
rom[i] = rom[0x73a000/2 + BITSWAP24(i,23,22,21,20,19,18,8,4,15,13,3,14,16,2,6,17,7,12,10,0,5,11,1,9)];
}

1
src/devices/bus/neogeo/rom.cpp
View File

@ -85,4 +85,3 @@ void neogeo_vliner_cart::device_reset()
{
memset(m_cart_ram, 0, 0x2000);
}

16
src/devices/bus/neogeo/slot.h
View File

@ -228,7 +228,7 @@ public:
}
return nullptr;
}
UINT32 get_rom_size() {
UINT32 get_rom_size() {
if (m_cart) {
if (!user_loadable()) return m_cart->get_region_rom_size(); else return m_cart->get_rom_size();
}
@ -240,7 +240,7 @@ public:
}
return nullptr;
}
UINT32 get_fixed_size() {
UINT32 get_fixed_size() {
if (m_cart) {
if (!user_loadable()) return m_cart->get_region_fixed_size(); else return m_cart->get_fixed_size();
}
@ -252,7 +252,7 @@ public:
}
return nullptr;
}
UINT32 get_sprites_size() {
UINT32 get_sprites_size() {
if (m_cart) {
if (!user_loadable()) return m_cart->get_region_sprites_size(); else return m_cart->get_sprites_size();
}
@ -264,7 +264,7 @@ public:
}
return nullptr;
}
UINT32 get_audio_size() {
UINT32 get_audio_size() {
if (m_cart) {
if (!user_loadable()) return m_cart->get_region_audio_size(); else return m_cart->get_audio_size();
}
@ -276,7 +276,7 @@ public:
}
return nullptr;
}
UINT32 get_audiocrypt_size() {
UINT32 get_audiocrypt_size() {
if (m_cart) {
if (!user_loadable()) return m_cart->get_region_audiocrypt_size(); else return m_cart->get_audiocrypt_size();
}
@ -288,7 +288,7 @@ public:
}
return nullptr;
}
UINT32 get_ym_size() {
UINT32 get_ym_size() {
if (m_cart) {
if (!user_loadable()) return m_cart->get_region_ym_size(); else return m_cart->get_ym_size();
}
@ -300,7 +300,7 @@ public:
}
return nullptr;
}
UINT32 get_ymdelta_size() {
UINT32 get_ymdelta_size() {
if (m_cart) {
if (!user_loadable()) return m_cart->get_region_ymdelta_size(); else return m_cart->get_ymdelta_size();
}
@ -310,7 +310,7 @@ public:
UINT8* get_sprites_opt_base() {
if (m_cart) return m_cart->get_sprites_opt_base(); else return nullptr;
}
UINT32 get_sprites_opt_size() {
UINT32 get_sprites_opt_size() {
if (m_cart) return m_cart->get_sprites_opt_size(); else return 0;
}

1
src/devices/bus/neogeo/sma.cpp
View File

@ -149,4 +149,3 @@ void neogeo_sma_kof2000_cart::decrypt_all(DECRYPT_ALL_PARAMS)
m_cmc_prot->cmc50_gfx_decrypt(spr_region, spr_region_size, KOF2000_GFX_KEY);
m_cmc_prot->sfix_decrypt(spr_region, spr_region_size, fix_region, fix_region_size);
}

6
src/devices/bus/nes/mmc3_clones.h
View File

@ -663,15 +663,15 @@ public:
nes_coolboy_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
// device-level overrides
// virtual void device_start() override;
// virtual void device_start() override;
virtual DECLARE_WRITE8_MEMBER(write_m) override;
virtual void prg_cb(int start, int bank) override;
virtual void chr_cb(int start, int bank, int source) override;
// virtual void pcb_reset() override;
// virtual void pcb_reset() override;
private:
// inline void set_base_mask();
// inline void set_base_mask();
UINT8 m_reg[4];
};

4
src/devices/cpu/drcbec.cpp
View File

@ -1070,7 +1070,7 @@ int drcbe_c::execute(code_handle &entry)
PARAM0 = temp32;
break;
case MAKE_OPCODE_SHORT(OP_TZCNT, 4, 0): // TZCNT dst,src
case MAKE_OPCODE_SHORT(OP_TZCNT, 4, 0): // TZCNT dst,src
PARAM0 = tzcount32(PARAM1);
break;
@ -1689,7 +1689,7 @@ int drcbe_c::execute(code_handle &entry)
DPARAM0 = temp64;
break;
case MAKE_OPCODE_SHORT(OP_TZCNT, 8, 0): // DTZCNT dst,src
case MAKE_OPCODE_SHORT(OP_TZCNT, 8, 0): // DTZCNT dst,src
DPARAM0 = tzcount64(DPARAM1);
break;

34
src/devices/cpu/drcbex64.cpp
View File

@ -4303,7 +4303,7 @@ void drcbe_x64::op_add(x86code *&dst, const instruction &inst)
// dstp == src2p in memory
else if (dstp.is_memory() && dstp == src2p)
emit_add_m32_p32(dst, MABS(dstp.memory()), src1p, inst); // add [dstp],src1p
emit_add_m32_p32(dst, MABS(dstp.memory()), src1p, inst); // add [dstp],src1p
// reg = reg + imm
else if (dstp.is_int_register() && src1p.is_int_register() && src2p.is_immediate() && inst.flags() == 0)
@ -4331,7 +4331,7 @@ void drcbe_x64::op_add(x86code *&dst, const instruction &inst)
// dstp == src2p in memory
else if (dstp.is_memory() && dstp == src2p)
emit_add_m64_p64(dst, MABS(dstp.memory()), src1p, inst); // add [dstp],src1p
emit_add_m64_p64(dst, MABS(dstp.memory()), src1p, inst); // add [dstp],src1p
// reg = reg + imm
else if (dstp.is_int_register() && src1p.is_int_register() && src2p.is_immediate() && short_immediate(src2p.immediate()) && inst.flags() == 0)
@ -5216,7 +5216,7 @@ void drcbe_x64::op_or(x86code *&dst, const instruction &inst)
// dstp == src2p in memory
else if (dstp.is_memory() && dstp == src2p)
emit_or_m32_p32(dst, MABS(dstp.memory()), src1p, inst); // or [dstp],src1p
emit_or_m32_p32(dst, MABS(dstp.memory()), src1p, inst); // or [dstp],src1p
// general case
else
@ -5236,7 +5236,7 @@ void drcbe_x64::op_or(x86code *&dst, const instruction &inst)
// dstp == src2p in memory
else if (dstp.is_memory() && dstp == src2p)
emit_or_m64_p64(dst, MABS(dstp.memory()), src1p, inst); // or [dstp],src1p
emit_or_m64_p64(dst, MABS(dstp.memory()), src1p, inst); // or [dstp],src1p
// general case
else
@ -5278,11 +5278,11 @@ void drcbe_x64::op_xor(x86code *&dst, const instruction &inst)
// dstp == src2p in memory
else if (dstp.is_memory() && dstp == src2p)
emit_xor_m32_p32(dst, MABS(dstp.memory()), src1p, inst); // xor [dstp],src1p
emit_xor_m32_p32(dst, MABS(dstp.memory()), src1p, inst); // xor [dstp],src1p
// dstp == src1p register
else if (dstp.is_int_register() && dstp == src1p)
emit_xor_r32_p32(dst, dstp.ireg(), src2p, inst); // xor dstp,src2p
emit_xor_r32_p32(dst, dstp.ireg(), src2p, inst); // xor dstp,src2p
// general case
else
@ -5302,11 +5302,11 @@ void drcbe_x64::op_xor(x86code *&dst, const instruction &inst)
// dstp == src2p in memory
else if (dstp.is_memory() && dstp == src2p)
emit_xor_m64_p64(dst, MABS(dstp.memory()), src1p, inst); // xor [dstp],src1p
emit_xor_m64_p64(dst, MABS(dstp.memory()), src1p, inst); // xor [dstp],src1p
// dstp == src1p register
else if (dstp.is_int_register() && dstp == src1p)
emit_xor_r64_p64(dst, dstp.ireg(), src2p, inst); // xor dstp,src2p
emit_xor_r64_p64(dst, dstp.ireg(), src2p, inst); // xor dstp,src2p
// general case
else
@ -5380,10 +5380,10 @@ void drcbe_x64::op_tzcnt(x86code *&dst, const instruction &inst)
if (inst.size() == 4)
{
int dstreg = dstp.select_register(REG_EAX);
emit_mov_r32_p32(dst, dstreg, srcp); // mov dstreg,srcp
emit_mov_r32_imm(dst, REG_ECX, 32); // mov ecx,32
emit_bsf_r32_r32(dst, dstreg, dstreg); // bsf dstreg,dstreg
emit_cmovcc_r32_r32(dst, x64emit::COND_Z, dstreg, REG_ECX); // cmovz dstreg,ecx
emit_mov_r32_p32(dst, dstreg, srcp); // mov dstreg,srcp
emit_mov_r32_imm(dst, REG_ECX, 32); // mov ecx,32
emit_bsf_r32_r32(dst, dstreg, dstreg); // bsf dstreg,dstreg
emit_cmovcc_r32_r32(dst, x64emit::COND_Z, dstreg, REG_ECX); // cmovz dstreg,ecx
emit_mov_p32_r32(dst, dstp, dstreg); // mov dstp,dstreg
}
@ -5391,11 +5391,11 @@ void drcbe_x64::op_tzcnt(x86code *&dst, const instruction &inst)
else if (inst.size() == 8)
{
int dstreg = dstp.select_register(REG_RAX);
emit_mov_r64_p64(dst, dstreg, srcp); // mov dstreg,srcp
emit_mov_r64_imm(dst, REG_RCX, 64); // mov rcx,64
emit_bsf_r64_r64(dst, dstreg, dstreg); // bsf dstreg,dstreg
emit_cmovcc_r64_r64(dst, x64emit::COND_Z, dstreg, REG_RCX); // cmovz dstreg,rcx
emit_mov_p64_r64(dst, dstp, dstreg); // mov dstp,dstreg
emit_mov_r64_p64(dst, dstreg, srcp); // mov dstreg,srcp
emit_mov_r64_imm(dst, REG_RCX, 64); // mov rcx,64
emit_bsf_r64_r64(dst, dstreg, dstreg); // bsf dstreg,dstreg
emit_cmovcc_r64_r64(dst, x64emit::COND_Z, dstreg, REG_RCX); // cmovz dstreg,rcx
emit_mov_p64_r64(dst, dstp, dstreg); // mov dstp,dstreg
}
}

30
src/devices/cpu/drcbex86.cpp
View File

@ -5496,27 +5496,27 @@ void drcbe_x86::op_tzcnt(x86code *&dst, const instruction &inst)
// 32-bit form
if (inst.size() == 4)
{
emit_mov_r32_p32(dst, dstreg, srcp); // mov dstreg,src1p
emit_mov_r32_imm(dst, REG_ECX, 32); // mov ecx,32
emit_bsf_r32_r32(dst, dstreg, dstreg); // bsf dstreg,dstreg
emit_cmovcc_r32_r32(dst, x86emit::COND_Z, dstreg, REG_ECX); // cmovz dstreg,ecx
emit_mov_p32_r32(dst, dstp, dstreg); // mov dstp,dstreg
emit_mov_r32_p32(dst, dstreg, srcp); // mov dstreg,src1p
emit_mov_r32_imm(dst, REG_ECX, 32); // mov ecx,32
emit_bsf_r32_r32(dst, dstreg, dstreg); // bsf dstreg,dstreg
emit_cmovcc_r32_r32(dst, x86emit::COND_Z, dstreg, REG_ECX); // cmovz dstreg,ecx
emit_mov_p32_r32(dst, dstp, dstreg); // mov dstp,dstreg
}
// 64-bit form
else if (inst.size() == 8)
{
emit_link skip;
emit_mov_r64_p64(dst, REG_EDX, dstreg, srcp); // mov dstreg:edx,srcp
emit_bsf_r32_r32(dst, dstreg, dstreg); // bsf dstreg,dstreg
emit_jcc_short_link(dst, x86emit::COND_NZ, skip); // jnz skip
emit_mov_r32_imm(dst, REG_ECX, 32); // mov ecx,32
emit_bsf_r32_r32(dst, dstreg, REG_EDX); // bsf dstreg,edx
emit_cmovcc_r32_r32(dst, x86emit::COND_Z, dstreg, REG_ECX); // cmovz dstreg,ecx
emit_add_r32_imm(dst, dstreg, 32); // add dstreg,32
track_resolve_link(dst, skip); // skip:
emit_xor_r32_r32(dst, REG_EDX, REG_EDX); // xor edx,edx
emit_mov_p64_r64(dst, dstp, dstreg, REG_EDX); // mov dstp,edx:dstreg
emit_mov_r64_p64(dst, REG_EDX, dstreg, srcp); // mov dstreg:edx,srcp
emit_bsf_r32_r32(dst, dstreg, dstreg); // bsf dstreg,dstreg
emit_jcc_short_link(dst, x86emit::COND_NZ, skip); // jnz skip
emit_mov_r32_imm(dst, REG_ECX, 32); // mov ecx,32
emit_bsf_r32_r32(dst, dstreg, REG_EDX); // bsf dstreg,edx
emit_cmovcc_r32_r32(dst, x86emit::COND_Z, dstreg, REG_ECX); // cmovz dstreg,ecx
emit_add_r32_imm(dst, dstreg, 32); // add dstreg,32
track_resolve_link(dst, skip); // skip:
emit_xor_r32_r32(dst, REG_EDX, REG_EDX); // xor edx,edx
emit_mov_p64_r64(dst, dstp, dstreg, REG_EDX); // mov dstp,edx:dstreg
}
}

4
src/devices/cpu/h8/h8.cpp
View File

@ -146,8 +146,8 @@ void h8_device::set_current_dma(h8_dma_state *state)
logerror("DMA done\n");
else
logerror("New current dma s=%x d=%x is=%d id=%d count=%x m=%d\n",
state->source, state->dest, state->incs, state->incd,
state->count, state->mode_16 ? 16 : 8);
state->source, state->dest, state->incs, state->incd,
state->count, state->mode_16 ? 16 : 8);
}

2
src/devices/cpu/h8/h8_dma.h
View File

@ -25,7 +25,7 @@ struct h8_dma_state {
#define MCFG_H8_DMA_ADD( _tag ) \
MCFG_DEVICE_ADD( _tag, H8_DMA, 0 )
#define MCFG_H8_DMA_CHANNEL_ADD( _tag, intc, irq_base, v0, v1, v2, v3, v4, v5, v6, v7, v8, v9, va, vb, vc, vd, ve, vf ) \
#define MCFG_H8_DMA_CHANNEL_ADD( _tag, intc, irq_base, v0, v1, v2, v3, v4, v5, v6, v7, v8, v9, va, vb, vc, vd, ve, vf ) \
MCFG_DEVICE_ADD( _tag, H8_DMA_CHANNEL, 0 ) \
downcast<h8_dma_channel_device *>(device)->set_info(intc, irq_base, v0, v1, v2, v3, v4, v5, v6, v7, v8, v9, va, vb, vc, vd, ve, vf);

5
src/devices/cpu/h8/h8_dtc.cpp
View File

@ -131,7 +131,7 @@ void h8_dtc_device::vector_done(int vector)
UINT32 mode = sra & 0x0c000000;
if(V>=1) logerror("regs at %08x sra=%08x dar=%08x cr=%08x %s mode\n", state->base, sra, dar, cr,
mode == 0x00000000 || mode == 0x0c000000 ? "normal" : mode == 0x04000000 ? "repeat" : "block");
mode == 0x00000000 || mode == 0x0c000000 ? "normal" : mode == 0x04000000 ? "repeat" : "block");
state->incs = sra & 0x80000000 ?
sra & 0x40000000 ? sra & 0x01000000 ? -2 : -1 :
sra & 0x01000000 ? 2 : 1 :
@ -215,7 +215,7 @@ bool h8_dtc_device::trigger_dtc(int vector)
{
int slot = vector_to_enable[vector];
if(slot == -1)
return false;
return false;
if(dtcer[slot >> 3] & (0x01 << (7-(slot & 7)))) {
edge(vector);
return true;
@ -266,4 +266,3 @@ void h8_dtc_device::count_done(int id)
cpu->request_state(h8_device::STATE_DTC_WRITEBACK);
waiting_writeback.push_back(id);
}

30
src/devices/cpu/h8/h8_sci.cpp
View File

@ -44,13 +44,13 @@ WRITE8_MEMBER(h8_sci_device::smr_w)
{
smr = data;
if(V>=2) logerror("smr_w %02x %s %c%c%c%s /%d (%06x)\n", data,
data & SMR_CA ? "sync" : "async",
data & SMR_CHR ? '7' : '8',
data & SMR_PE ? data & SMR_OE ? 'o' : 'e' : 'n',
data & SMR_STOP ? '2' : '1',
data & SMR_MP ? " mp" : "",
1 << 2*(data & SMR_CKS),
cpu->pc());
data & SMR_CA ? "sync" : "async",
data & SMR_CHR ? '7' : '8',
data & SMR_PE ? data & SMR_OE ? 'o' : 'e' : 'n',
data & SMR_STOP ? '2' : '1',
data & SMR_MP ? " mp" : "",
1 << 2*(data & SMR_CKS),
cpu->pc());
clock_update();
}
@ -86,14 +86,14 @@ bool h8_sci_device::has_recv_error() const
WRITE8_MEMBER(h8_sci_device::scr_w)
{
if(V>=2) logerror("scr_w %02x%s%s%s%s%s%s clk=%d (%06x)\n", data,
data & SCR_TIE ? " txi" : "",
data & SCR_RIE ? " rxi" : "",
data & SCR_TE ? " tx" : "",
data & SCR_RE ? " rx" : "",
data & SCR_MPIE ? " mpi" : "",
data & SCR_TEIE ? " tei" : "",
data & SCR_CKE,
cpu->pc());
data & SCR_TIE ? " txi" : "",
data & SCR_RIE ? " rxi" : "",
data & SCR_TE ? " tx" : "",
data & SCR_RE ? " rx" : "",
data & SCR_MPIE ? " mpi" : "",
data & SCR_TEIE ? " tei" : "",
data & SCR_CKE,
cpu->pc());
UINT8 delta = scr ^ data;
scr = data;

14
src/devices/cpu/h8/h8_timer16.cpp
View File

@ -103,13 +103,13 @@ WRITE8_MEMBER(h8_timer16_channel_device::tier_w)
tier = data;
tier_update();
if(V>=1) logerror("irq %c%c%c%c%c%c trigger=%d\n",
ier & IRQ_A ? 'a' : '.',
ier & IRQ_B ? 'b' : '.',
ier & IRQ_C ? 'c' : '.',
ier & IRQ_D ? 'd' : '.',
ier & IRQ_V ? 'v' : '.',
ier & IRQ_U ? 'u' : '.',
ier & IRQ_TRIG ? 1 : 0);
ier & IRQ_A ? 'a' : '.',
ier & IRQ_B ? 'b' : '.',
ier & IRQ_C ? 'c' : '.',
ier & IRQ_D ? 'd' : '.',
ier & IRQ_V ? 'v' : '.',
ier & IRQ_U ? 'u' : '.',
ier & IRQ_TRIG ? 1 : 0);
recalc_event();
}

6
src/devices/cpu/h8/h8_timer8.cpp
View File

@ -130,9 +130,9 @@ void h8_timer8_channel_device::update_tcr()
}
if(V>=1) p += sprintf(p, ", irq=%c%c%c\n",
tcr & TCR_CMIEB ? 'b' : '-',
tcr & TCR_CMIEA ? 'a' : '-',
tcr & TCR_OVIE ? 'o' : '-');
tcr & TCR_CMIEB ? 'b' : '-',
tcr & TCR_CMIEA ? 'a' : '-',
tcr & TCR_OVIE ? 'o' : '-');
logerror(buf);
}

4
src/devices/cpu/h8/h8_watchdog.cpp
View File

@ -44,7 +44,7 @@ void h8_watchdog_device::tcnt_update(UINT64 cur_time)
int next_tcnt = tcnt + int(epos - spos);
tcnt = next_tcnt;
tcnt_cycle_base = cur_time;
// logerror("%10lld tcnt %02x -> %03x shift=%d\n", cur_time, tcnt, next_tcnt, shift);
// logerror("%10lld tcnt %02x -> %03x shift=%d\n", cur_time, tcnt, next_tcnt, shift);
if(next_tcnt >= 0x100) {
logerror("watchdog triggered\n");
@ -91,7 +91,7 @@ WRITE16_MEMBER(h8_watchdog_device::wd_w)
if(tcsr & TCSR_TME) {
tcnt = data & 0xff;
tcnt_cycle_base = cpu->total_cycles();
// logerror("%10lld tcnt = %02x\n", tcnt_cycle_base, tcnt);
// logerror("%10lld tcnt = %02x\n", tcnt_cycle_base, tcnt);
}
cpu->internal_update();
}

2
src/devices/cpu/h8/h8_watchdog.h
View File

@ -43,7 +43,7 @@
#include "h8.h"
#include "h8_intc.h"
#define MCFG_H8_WATCHDOG_ADD( _tag, intc, irq, type ) \
#define MCFG_H8_WATCHDOG_ADD( _tag, intc, irq, type ) \
MCFG_DEVICE_ADD( _tag, H8_WATCHDOG, 0 ) \
downcast<h8_watchdog_device *>(device)->set_info(intc, irq, type);

4
src/devices/cpu/hphybrid/hphybrid.cpp
View File

@ -133,7 +133,7 @@ WRITE_LINE_MEMBER(hp_hybrid_cpu_device::flag_w)
UINT8 hp_hybrid_cpu_device::pa_r(void) const
{
return CURRENT_PA;
return CURRENT_PA;
}
hp_hybrid_cpu_device::hp_hybrid_cpu_device(const machine_config &mconfig, device_type type, const char *name, const char *tag, device_t *owner, UINT32 clock, const char *shortname , UINT8 addrwidth)
@ -1092,7 +1092,7 @@ void hp_hybrid_cpu_device::handle_dma(void)
m_icount -= 9;
}
// Mystery solved: DMA is not automatically disabled at TC (test of 9845's graphic memory relies on this to work)
// Mystery solved: DMA is not automatically disabled at TC (test of 9845's graphic memory relies on this to work)
}
UINT16 hp_hybrid_cpu_device::RIO(UINT8 pa , UINT8 ic)

2
src/devices/cpu/hphybrid/hphybrid.h
View File

@ -87,7 +87,7 @@ public:
DECLARE_WRITE_LINE_MEMBER(status_w);
DECLARE_WRITE_LINE_MEMBER(flag_w);
UINT8 pa_r(void) const;
UINT8 pa_r(void) const;
template<class _Object> static devcb_base &set_pa_changed_func(device_t &device, _Object object) { return downcast<hp_hybrid_cpu_device &>(device).m_pa_changed_func.set_callback(object); }

2
src/devices/machine/gt64xxx.h
View File

@ -47,7 +47,7 @@
#define TIMER_PERIOD attotime::from_hz(m_clock)
#define PCI_BUS_CLOCK 33000000
// Number of dma words to transfer at a time, real hardware configurable between 8-32
#define DMA_BURST_SIZE 32
#define DMA_BURST_SIZE 32
#define DMA_TIMER_PERIOD attotime::from_hz(PCI_BUS_CLOCK / 48)
/* Galileo registers - 0x000-0x3ff */

2
src/devices/machine/pci-ide.h
View File

@ -8,7 +8,7 @@ Generic PCI IDE controller implementation.
Based on datasheet for National Semiconductor PC87415
TODO:
Add pci configuration write to PIF byte
Add pci configuration write to PIF byte
***************************************************************************/
#ifndef PCI_IDE_H

1
src/devices/machine/stvcd.h
View File

@ -1,3 +1,2 @@
// license:LGPL-2.1+
// copyright-holders:Angelo Salese, R. Belmont

2
src/devices/machine/vrc4373.h
View File

@ -50,7 +50,7 @@
#define PCI_BUS_CLOCK 33000000
// Number of dma words to transfer at a time, real hardware bursts 8
#define DMA_BURST_SIZE 128
#define DMA_BURST_SIZE 128
#define DMA_TIMER_PERIOD attotime::from_hz(PCI_BUS_CLOCK / 32)
#define DMA_BUSY 0x80000000

24
src/devices/machine/z80scc.cpp
View File

@ -854,9 +854,9 @@ void z80scc_channel::device_timer(emu_timer &timer, device_timer_id id, int para
//int brconst = m_wr13 << 8 | m_wr12 | 1; // If the counter is 1 the effect is passthrough ehh?! To avoid div0...
if (m_wr14 & WR14_BRG_ENABLE)
{
// int rate = m_owner->clock() / brconst;
// attotime attorate = attotime::from_hz(rate);
// timer.adjust(attorate, id, attorate);
// int rate = m_owner->clock() / brconst;
// attotime attorate = attotime::from_hz(rate);
// timer.adjust(attorate, id, attorate);
txc_w(m_brg_counter & 1);
rxc_w(m_brg_counter & 1);
m_brg_counter++; // Will just keep track of state in timer mode, not hardware counter value.
@ -869,11 +869,11 @@ void z80scc_channel::device_timer(emu_timer &timer, device_timer_id id, int para
}
break;
default:
logerror("Spurious timer %d event\n", id);
logerror("Spurious timer %d event\n", id);
}
#else
// TODO: Hmmm, either the above default clause is called OR the bellow call is not needed since we handled our local event anyway...?!
// and the above default is not called unless we implement the BRG timer using diserial timer interfaces...
// and the above default is not called unless we implement the BRG timer using diserial timer interfaces...
device_serial_interface::device_timer(timer, id, param, ptr);
#endif
}
@ -1131,7 +1131,7 @@ int z80scc_channel::get_tx_word_length()
* Break/Abort latch. */
UINT8 z80scc_channel::do_sccreg_rr0()
{
LOGR(("%s %s <- %02x\n",tag(), FUNCNAME, m_rr0));
LOGR(("%s %s <- %02x\n",tag(), FUNCNAME, m_rr0));
return m_rr0;
}
@ -1999,7 +1999,7 @@ UINT8 z80scc_channel::data_read()
// trigger interrup and lock the fifo if an error is present
if (m_rr1 & (RR1_CRC_FRAMING_ERROR | RR1_RX_OVERRUN_ERROR | RR1_PARITY_ERROR))
{
logerror("Rx Error %02x\n", m_rr1 & (RR1_CRC_FRAMING_ERROR | RR1_RX_OVERRUN_ERROR | RR1_PARITY_ERROR));
logerror("Rx Error %02x\n", m_rr1 & (RR1_CRC_FRAMING_ERROR | RR1_RX_OVERRUN_ERROR | RR1_PARITY_ERROR));
switch (m_wr1 & WR1_RX_INT_MODE_MASK)
{
case WR1_RX_INT_FIRST:
@ -2074,7 +2074,7 @@ void z80scc_channel::data_write(UINT8 data)
if ((m_wr5 & WR5_TX_ENABLE) && is_transmit_register_empty())
{
LOG(("%s(%02x) \"%s\": %c : Transmit Data Byte '%02x' %c\n", FUNCNAME, data, m_owner->tag(), 'A' + m_index, m_tx_data, m_tx_data));
LOG(("%s(%02x) \"%s\": %c : Transmit Data Byte '%02x' %c\n", FUNCNAME, data, m_owner->tag(), 'A' + m_index, m_tx_data, m_tx_data));
transmit_register_setup(m_tx_data);
// empty transmit buffer
@ -2103,7 +2103,7 @@ void z80scc_channel::receive_data(UINT8 data)
{
LOG(("\"%s\": %c : Receive Data Byte '%02x'\n", m_owner->tag(), 'A' + m_index, data));
if (m_rx_fifo_wp + 1 == m_rx_fifo_rp || ( (m_rx_fifo_wp + 1 == m_rx_fifo_sz) && (m_rx_fifo_rp == 0) ))
if (m_rx_fifo_wp + 1 == m_rx_fifo_rp || ( (m_rx_fifo_wp + 1 == m_rx_fifo_sz) && (m_rx_fifo_rp == 0) ))
{
// receive overrun error detected
m_rx_error_fifo[m_rx_fifo_wp] |= RR1_RX_OVERRUN_ERROR; // = m_rx_error;
@ -2308,7 +2308,7 @@ WRITE_LINE_MEMBER( z80scc_channel::rxc_w )
rx_clock_w(state);
else if(state)
{
if (m_rx_clock == clocks/2 && m_rcv_mode == RCV_SAMPLING)
if (m_rx_clock == clocks/2 && m_rcv_mode == RCV_SAMPLING)
rx_clock_w(m_rx_clock < clocks/2);
m_rx_clock++;
@ -2359,8 +2359,8 @@ void z80scc_channel::update_serial()
else
parity = PARITY_NONE;
LOG((LLFORMAT " %s() \"%s \"Channel %c setting data frame %d+%d%c%d\n", machine().firstcpu->total_cycles(), FUNCNAME, m_owner->tag(), 'A' + m_index, 1,
data_bit_count, parity == PARITY_NONE ? 'N' : parity == PARITY_EVEN ? 'E' : 'O', (stop_bits + 1) / 2));
LOG((LLFORMAT " %s() \"%s \"Channel %c setting data frame %d+%d%c%d\n", machine().firstcpu->total_cycles(), FUNCNAME, m_owner->tag(), 'A' + m_index, 1,
data_bit_count, parity == PARITY_NONE ? 'N' : parity == PARITY_EVEN ? 'E' : 'O', (stop_bits + 1) / 2));
set_data_frame(1, data_bit_count, parity, stop_bits);
#if START_BIT_HUNT

382
src/devices/machine/z80scc.h
View File

@ -229,7 +229,7 @@ public:
UINT8 m_rr6; // REG_RR6_LSB_OR_RR2
UINT8 m_rr7; // REG_RR7_MSB_OR_RR3
UINT8 m_rr8; // REG_RR8_RECEIVE_DATA
UINT8 m_rr9; // REG_RR9_WR3_OR_RR13
UINT8 m_rr9; // REG_RR9_WR3_OR_RR13
UINT8 m_rr10; // REG_RR10_MISC_STATUS
UINT8 m_rr11; // REG_RR11_WR10_OR_RR15
UINT8 m_rr12; // REG_RR12_LO_TIME_CONST
@ -274,239 +274,239 @@ protected:
// Read registers
enum
{
REG_RR0_STATUS = 0,
REG_RR1_SPEC_RCV_COND = 1,
REG_RR2_INTERRUPT_VECT = 2,
REG_RR3_INTERUPPT_PEND = 3,
REG_RR4_WR4_OR_RR0 = 4,
REG_RR5_WR5_OR_RR0 = 5,
REG_RR6_LSB_OR_RR2 = 6,
REG_RR7_MSB_OR_RR3 = 7,
REG_RR8_RECEIVE_DATA = 8,
REG_RR9_WR3_OR_RR13 = 9,
REG_RR10_MISC_STATUS = 10,
REG_RR11_WR10_OR_RR15 = 11,
REG_RR12_LO_TIME_CONST = 12,
REG_RR13_HI_TIME_CONST = 13,
REG_RR14_WR7_OR_R10 = 14,
REG_RR15_WR15_EXT_STAT = 15
REG_RR0_STATUS = 0,
REG_RR1_SPEC_RCV_COND = 1,
REG_RR2_INTERRUPT_VECT = 2,
REG_RR3_INTERUPPT_PEND = 3,
REG_RR4_WR4_OR_RR0 = 4,
REG_RR5_WR5_OR_RR0 = 5,
REG_RR6_LSB_OR_RR2 = 6,
REG_RR7_MSB_OR_RR3 = 7,
REG_RR8_RECEIVE_DATA = 8,
REG_RR9_WR3_OR_RR13 = 9,
REG_RR10_MISC_STATUS = 10,
REG_RR11_WR10_OR_RR15 = 11,
REG_RR12_LO_TIME_CONST = 12,
REG_RR13_HI_TIME_CONST = 13,
REG_RR14_WR7_OR_R10 = 14,
REG_RR15_WR15_EXT_STAT = 15
};
// Write registers
enum
{
REG_WR0_COMMAND_REGPT = 0,
REG_WR1_INT_DMA_ENABLE = 1,
REG_WR2_INT_VECTOR = 2,
REG_WR3_RX_CONTROL = 3,
REG_WR4_RX_TX_MODES = 4,
REG_WR5_TX_CONTROL = 5,
REG_WR6_SYNC_OR_SDLC_A = 6,
REG_WR7_SYNC_OR_SDLC_F = 7,
REG_WR8_TRANSMIT_DATA = 8,
REG_WR0_COMMAND_REGPT = 0,
REG_WR1_INT_DMA_ENABLE = 1,
REG_WR2_INT_VECTOR = 2,
REG_WR3_RX_CONTROL = 3,
REG_WR4_RX_TX_MODES = 4,
REG_WR5_TX_CONTROL = 5,
REG_WR6_SYNC_OR_SDLC_A = 6,
REG_WR7_SYNC_OR_SDLC_F = 7,
REG_WR8_TRANSMIT_DATA = 8,
REG_WR9_MASTER_INT_CTRL = 9,
REG_WR10_MSC_RX_TX_CTRL = 10,
REG_WR11_CLOCK_MODES = 11,
REG_WR12_LO_BAUD_GEN = 12,
REG_WR13_HI_BAUD_GEN = 13,
REG_WR14_MISC_CTRL = 14,
REG_WR11_CLOCK_MODES = 11,
REG_WR12_LO_BAUD_GEN = 12,
REG_WR13_HI_BAUD_GEN = 13,
REG_WR14_MISC_CTRL = 14,
REG_WR15_EXT_ST_INT_CTRL= 15
};
enum
{
RR0_RX_CHAR_AVAILABLE = 0x01, // SIO bit
RR0_ZC = 0x02, // SCC bit
RR0_TX_BUFFER_EMPTY = 0x04, // SIO
RR0_DCD = 0x08, // SIO
RR0_RI = 0x10, // DART bit? TODO: investigate function and remove
RR0_SYNC_HUNT = 0x10, // SIO bit, not supported
RR0_CTS = 0x20, // SIO bit
RR0_TX_UNDERRUN = 0x40, // SIO bit, not supported
RR0_BREAK_ABORT = 0x80 // SIO bit, not supported
RR0_RX_CHAR_AVAILABLE = 0x01, // SIO bit
RR0_ZC = 0x02, // SCC bit
RR0_TX_BUFFER_EMPTY = 0x04, // SIO
RR0_DCD = 0x08, // SIO
RR0_RI = 0x10, // DART bit? TODO: investigate function and remove
RR0_SYNC_HUNT = 0x10, // SIO bit, not supported
RR0_CTS = 0x20, // SIO bit
RR0_TX_UNDERRUN = 0x40, // SIO bit, not supported
RR0_BREAK_ABORT = 0x80 // SIO bit, not supported
};
enum
{
RR1_ALL_SENT = 0x01, // SIO/SCC bit
RR1_RESIDUE_CODE_MASK = 0x0e, // SIO/SCC bits, not supported
RR1_PARITY_ERROR = 0x10, // SIO/SCC bits
RR1_RX_OVERRUN_ERROR = 0x20, // SIO/SCC bits
RR1_CRC_FRAMING_ERROR = 0x40, // SIO/SCC bits
RR1_END_OF_FRAME = 0x80 // SIO/SCC bits, not supported
RR1_ALL_SENT = 0x01, // SIO/SCC bit
RR1_RESIDUE_CODE_MASK = 0x0e, // SIO/SCC bits, not supported
RR1_PARITY_ERROR = 0x10, // SIO/SCC bits
RR1_RX_OVERRUN_ERROR = 0x20, // SIO/SCC bits
RR1_CRC_FRAMING_ERROR = 0x40, // SIO/SCC bits
RR1_END_OF_FRAME = 0x80 // SIO/SCC bits, not supported
};
enum
{ // TODO: overload SIO functionality
RR2_INT_VECTOR_MASK = 0xff, // SCC channel A, SIO channel B (special case)
RR2_INT_VECTOR_V1 = 0x02, // SIO (special case) /SCC Channel B
RR2_INT_VECTOR_V2 = 0x04, // SIO (special case) /SCC Channel B
RR2_INT_VECTOR_V3 = 0x08 // SIO (special case) /SCC Channel B
{ // TODO: overload SIO functionality
RR2_INT_VECTOR_MASK = 0xff, // SCC channel A, SIO channel B (special case)
RR2_INT_VECTOR_V1 = 0x02, // SIO (special case) /SCC Channel B
RR2_INT_VECTOR_V2 = 0x04, // SIO (special case) /SCC Channel B
RR2_INT_VECTOR_V3 = 0x08 // SIO (special case) /SCC Channel B
};
enum
{
RR3_CHANB_EXT_IP = 0x01, // SCC IP pending registers
RR3_CHANB_TX_IP = 0x02, // only read in Channel A (for both channels)
RR3_CHANB_RX_IP = 0x04, // channel B return all zero
RR3_CHANA_EXT_IP = 0x08,
RR3_CHANA_TX_IP = 0x10,
RR3_CHANA_RX_IP = 0x20
RR3_CHANB_EXT_IP = 0x01, // SCC IP pending registers
RR3_CHANB_TX_IP = 0x02, // only read in Channel A (for both channels)
RR3_CHANB_RX_IP = 0x04, // channel B return all zero
RR3_CHANA_EXT_IP = 0x08,
RR3_CHANA_TX_IP = 0x10,
RR3_CHANA_RX_IP = 0x20
};
enum // Universal Bus WR0 commands for 85X30
{
WR0_REGISTER_MASK = 0x07,
WR0_COMMAND_MASK = 0x38, // COMMANDS
WR0_NULL = 0x00, // 0 0 0
WR0_POINT_HIGH = 0x08, // 0 0 1
WR0_RESET_EXT_STATUS = 0x10, // 0 1 0
WR0_SEND_ABORT = 0x18, // 0 1 1
WR0_ENABLE_INT_NEXT_RX = 0x20, // 1 0 0
WR0_RESET_TX_INT = 0x28, // 1 0 1
WR0_ERROR_RESET = 0x30, // 1 1 0
WR0_RESET_HIGHEST_IUS = 0x38, // 1 1 1
WR0_CRC_RESET_CODE_MASK = 0xc0, // RESET
WR0_CRC_RESET_NULL = 0x00, // 0 0
WR0_CRC_RESET_RX = 0x40, // 0 1
WR0_CRC_RESET_TX = 0x80, // 1 0
WR0_REGISTER_MASK = 0x07,
WR0_COMMAND_MASK = 0x38, // COMMANDS
WR0_NULL = 0x00, // 0 0 0
WR0_POINT_HIGH = 0x08, // 0 0 1
WR0_RESET_EXT_STATUS = 0x10, // 0 1 0
WR0_SEND_ABORT = 0x18, // 0 1 1
WR0_ENABLE_INT_NEXT_RX = 0x20, // 1 0 0
WR0_RESET_TX_INT = 0x28, // 1 0 1
WR0_ERROR_RESET = 0x30, // 1 1 0
WR0_RESET_HIGHEST_IUS = 0x38, // 1 1 1
WR0_CRC_RESET_CODE_MASK = 0xc0, // RESET
WR0_CRC_RESET_NULL = 0x00, // 0 0
WR0_CRC_RESET_RX = 0x40, // 0 1
WR0_CRC_RESET_TX = 0x80, // 1 0
WR0_CRC_RESET_TX_UNDERRUN = 0xc0 // 1 1
};
enum // ZBUS WR0 commands or 80X30
{
WR0_Z_COMMAND_MASK = 0x38, // COMMANDS
WR0_Z_NULL_1 = 0x00, // 0 0 0
WR0_Z_NULL_2 = 0x08, // 0 0 1
WR0_Z_RESET_EXT_STATUS = 0x10, // 0 1 0
WR0_Z_SEND_ABORT = 0x18, // 0 1 1
WR0_Z_COMMAND_MASK = 0x38, // COMMANDS
WR0_Z_NULL_1 = 0x00, // 0 0 0
WR0_Z_NULL_2 = 0x08, // 0 0 1
WR0_Z_RESET_EXT_STATUS = 0x10, // 0 1 0
WR0_Z_SEND_ABORT = 0x18, // 0 1 1
WR0_Z_ENABLE_INT_NEXT_RX= 0x20, // 1 0 0
WR0_Z_RESET_TX_INT = 0x28, // 1 0 1
WR0_Z_ERROR_RESET = 0x30, // 1 1 0
WR0_Z_RESET_TX_INT = 0x28, // 1 0 1
WR0_Z_ERROR_RESET = 0x30, // 1 1 0
WR0_Z_RESET_HIGHEST_IUS = 0x38, // 1 1 1
WR0_Z_SHIFT_MASK = 0x03, // SHIFT mode SDLC chan B
WR0_Z_SEL_SHFT_LEFT = 0x02, // 1 0
WR0_Z_SEL_SHFT_RIGHT = 0x03 // 1 1
WR0_Z_SHIFT_MASK = 0x03, // SHIFT mode SDLC chan B
WR0_Z_SEL_SHFT_LEFT = 0x02, // 1 0
WR0_Z_SEL_SHFT_RIGHT = 0x03 // 1 1
};
enum
{
WR1_EXT_INT_ENABLE = 0x01,
WR1_TX_INT_ENABLE = 0x02,
WR1_PARITY_IS_SPEC_COND = 0x04,
WR1_RX_INT_MODE_MASK = 0x18,
WR1_RX_INT_DISABLE = 0x00,
WR1_RX_INT_FIRST = 0x08,
WR1_RX_INT_ALL_PARITY = 0x10, // not supported
WR1_RX_INT_ALL = 0x18,
WR1_WRDY_ON_RX_TX = 0x20, // not supported
WR1_WRDY_FUNCTION = 0x40, // not supported
WR1_WRDY_ENABLE = 0x80 // not supported
WR1_EXT_INT_ENABLE = 0x01,
WR1_TX_INT_ENABLE = 0x02,
WR1_PARITY_IS_SPEC_COND = 0x04,
WR1_RX_INT_MODE_MASK = 0x18,
WR1_RX_INT_DISABLE = 0x00,
WR1_RX_INT_FIRST = 0x08,
WR1_RX_INT_ALL_PARITY = 0x10, // not supported
WR1_RX_INT_ALL = 0x18,
WR1_WRDY_ON_RX_TX = 0x20, // not supported
WR1_WRDY_FUNCTION = 0x40, // not supported
WR1_WRDY_ENABLE = 0x80 // not supported
};
enum
{
WR3_RX_ENABLE = 0x01,
WR3_SYNC_CHAR_LOAD_INHIBIT = 0x02, // not supported
WR3_ADDRESS_SEARCH_MODE = 0x04, // not supported
WR3_RX_CRC_ENABLE = 0x08, // not supported
WR3_ENTER_HUNT_PHASE = 0x10, // not supported
WR3_AUTO_ENABLES = 0x20,
WR3_RX_WORD_LENGTH_MASK = 0xc0,
WR3_RX_WORD_LENGTH_5 = 0x00,
WR3_RX_WORD_LENGTH_7 = 0x40,
WR3_RX_WORD_LENGTH_6 = 0x80,
WR3_RX_WORD_LENGTH_8 = 0xc0
WR3_RX_ENABLE = 0x01,
WR3_SYNC_CHAR_LOAD_INHIBIT = 0x02, // not supported
WR3_ADDRESS_SEARCH_MODE = 0x04, // not supported
WR3_RX_CRC_ENABLE = 0x08, // not supported
WR3_ENTER_HUNT_PHASE = 0x10, // not supported
WR3_AUTO_ENABLES = 0x20,
WR3_RX_WORD_LENGTH_MASK = 0xc0,
WR3_RX_WORD_LENGTH_5 = 0x00,
WR3_RX_WORD_LENGTH_7 = 0x40,
WR3_RX_WORD_LENGTH_6 = 0x80,
WR3_RX_WORD_LENGTH_8 = 0xc0
};
enum
{
WR4_PARITY_ENABLE = 0x01,
WR4_PARITY_EVEN = 0x02,
WR4_STOP_BITS_MASK = 0x0c,
WR4_STOP_BITS_1 = 0x04,
WR4_STOP_BITS_1_5 = 0x08, // not supported
WR4_STOP_BITS_2 = 0x0c,
WR4_SYNC_MODE_MASK = 0x30, // not supported
WR4_SYNC_MODE_8_BIT = 0x00, // not supported
WR4_SYNC_MODE_16_BIT = 0x10, // not supported
WR4_SYNC_MODE_SDLC = 0x20, // not supported
WR4_SYNC_MODE_EXT = 0x30, // not supported
WR4_CLOCK_RATE_MASK = 0xc0,
WR4_CLOCK_RATE_X1 = 0x00,
WR4_CLOCK_RATE_X16 = 0x40,
WR4_CLOCK_RATE_X32 = 0x80,
WR4_CLOCK_RATE_X64 = 0xc0
WR4_PARITY_ENABLE = 0x01,
WR4_PARITY_EVEN = 0x02,
WR4_STOP_BITS_MASK = 0x0c,
WR4_STOP_BITS_1 = 0x04,
WR4_STOP_BITS_1_5 = 0x08, // not supported
WR4_STOP_BITS_2 = 0x0c,
WR4_SYNC_MODE_MASK = 0x30, // not supported
WR4_SYNC_MODE_8_BIT = 0x00, // not supported
WR4_SYNC_MODE_16_BIT = 0x10, // not supported
WR4_SYNC_MODE_SDLC = 0x20, // not supported
WR4_SYNC_MODE_EXT = 0x30, // not supported
WR4_CLOCK_RATE_MASK = 0xc0,
WR4_CLOCK_RATE_X1 = 0x00,
WR4_CLOCK_RATE_X16 = 0x40,
WR4_CLOCK_RATE_X32 = 0x80,
WR4_CLOCK_RATE_X64 = 0xc0
};
enum
{
WR5_TX_CRC_ENABLE = 0x01, // not supported
WR5_RTS = 0x02,
WR5_CRC16 = 0x04, // not supported
WR5_TX_ENABLE = 0x08,
WR5_SEND_BREAK = 0x10,
WR5_TX_WORD_LENGTH_MASK = 0x60,
WR5_TX_WORD_LENGTH_5 = 0x00,
WR5_TX_WORD_LENGTH_6 = 0x40,
WR5_TX_WORD_LENGTH_7 = 0x20,
WR5_TX_WORD_LENGTH_8 = 0x60,
WR5_DTR = 0x80
WR5_TX_CRC_ENABLE = 0x01, // not supported
WR5_RTS = 0x02,
WR5_CRC16 = 0x04, // not supported
WR5_TX_ENABLE = 0x08,
WR5_SEND_BREAK = 0x10,
WR5_TX_WORD_LENGTH_MASK = 0x60,
WR5_TX_WORD_LENGTH_5 = 0x00,
WR5_TX_WORD_LENGTH_6 = 0x40,
WR5_TX_WORD_LENGTH_7 = 0x20,
WR5_TX_WORD_LENGTH_8 = 0x60,
WR5_DTR = 0x80
};
/* SCC specifics */
enum
{
WR9_CMD_MASK = 0xC0,
WR9_CMD_NORESET = 0x00,
WR9_CMD_CHNB_RESET = 0x40,
WR9_CMD_CHNA_RESET = 0x80,
WR9_CMD_HW_RESET = 0xC0,
WR9_BIT_VIS = 0x01,
WR9_BIT_NV = 0x02,
WR9_BIT_DLC = 0x04,
WR9_BIT_MIE = 0x08,
WR9_BIT_SHSL = 0x10,
WR9_BIT_IACK = 0x20
WR9_CMD_MASK = 0xC0,
WR9_CMD_NORESET = 0x00,
WR9_CMD_CHNB_RESET = 0x40,
WR9_CMD_CHNA_RESET = 0x80,
WR9_CMD_HW_RESET = 0xC0,
WR9_BIT_VIS = 0x01,
WR9_BIT_NV = 0x02,
WR9_BIT_DLC = 0x04,
WR9_BIT_MIE = 0x08,
WR9_BIT_SHSL = 0x10,
WR9_BIT_IACK = 0x20
};
enum
{
WR11_RCVCLK_TYPE = 0x80,
WR11_RCVCLK_SRC_MASK = 0x60, // RCV CLOCK
WR11_RCVCLK_SRC_RTXC = 0x00, // 0 0
WR11_RCVCLK_SRC_TRXC = 0x20, // 0 1
WR11_RCVCLK_SRC_BR = 0x40, // 1 0
WR11_RCVCLK_SRC_DPLL = 0x60, // 1 1
WR11_TRACLK_SRC_MASK = 0x18, // TRA CLOCK
WR11_TRACLK_SRC_RTXC = 0x00, // 0 0
WR11_TRACLK_SRC_TRXC = 0x08, // 0 1
WR11_TRACLK_SRC_BR = 0x10, // 1 0
WR11_TRACLK_SRC_DPLL = 0x18, // 1 1
WR11_TRXC_DIRECTION = 0x04,
WR11_TRXSRC_SRC_MASK = 0x03, // TRXX CLOCK
WR11_TRXSRC_SRC_XTAL = 0x00, // 0 0
WR11_TRXSRC_SRC_TRA = 0x01, // 0 1
WR11_TRXSRC_SRC_BR = 0x02, // 1 0
WR11_TRXSRC_SRC_DPLL = 0x03 // 1 1
WR11_RCVCLK_TYPE = 0x80,
WR11_RCVCLK_SRC_MASK = 0x60, // RCV CLOCK
WR11_RCVCLK_SRC_RTXC = 0x00, // 0 0
WR11_RCVCLK_SRC_TRXC = 0x20, // 0 1
WR11_RCVCLK_SRC_BR = 0x40, // 1 0
WR11_RCVCLK_SRC_DPLL = 0x60, // 1 1
WR11_TRACLK_SRC_MASK = 0x18, // TRA CLOCK
WR11_TRACLK_SRC_RTXC = 0x00, // 0 0
WR11_TRACLK_SRC_TRXC = 0x08, // 0 1
WR11_TRACLK_SRC_BR = 0x10, // 1 0
WR11_TRACLK_SRC_DPLL = 0x18, // 1 1
WR11_TRXC_DIRECTION = 0x04,
WR11_TRXSRC_SRC_MASK = 0x03, // TRXX CLOCK
WR11_TRXSRC_SRC_XTAL = 0x00, // 0 0
WR11_TRXSRC_SRC_TRA = 0x01, // 0 1
WR11_TRXSRC_SRC_BR = 0x02, // 1 0
WR11_TRXSRC_SRC_DPLL = 0x03 // 1 1
};
enum
{
WR14_DPLL_CMD_MASK = 0xe0, // Command
WR14_CMD_NULL = 0x00, // 0 0 0
WR14_CMD_ESM = 0x20, // 0 0 1
WR14_CMD_RMC = 0x40, // 0 1 0
WR14_CMD_DISABLE_DPLL = 0x60, // 0 1 1
WR14_CMD_SS_BRG = 0x80, // 1 0 0
WR14_CMD_SS_RTXC = 0xa0, // 1 0 1
WR14_CMD_SET_FM = 0xc0, // 1 1 0
WR14_CMD_SET_NRZI = 0xe0, // 1 1 1
WR14_BRG_ENABLE = 0x01,
WR14_BRG_SOURCE = 0x02,
WR14_DTR_REQ_FUNC = 0x04,
WR14_AUTO_ECHO = 0x08,
WR14_LOCAL_LOOPBACK = 0x010
WR14_DPLL_CMD_MASK = 0xe0, // Command
WR14_CMD_NULL = 0x00, // 0 0 0
WR14_CMD_ESM = 0x20, // 0 0 1
WR14_CMD_RMC = 0x40, // 0 1 0
WR14_CMD_DISABLE_DPLL = 0x60, // 0 1 1
WR14_CMD_SS_BRG = 0x80, // 1 0 0
WR14_CMD_SS_RTXC = 0xa0, // 1 0 1
WR14_CMD_SET_FM = 0xc0, // 1 1 0
WR14_CMD_SET_NRZI = 0xe0, // 1 1 1
WR14_BRG_ENABLE = 0x01,
WR14_BRG_SOURCE = 0x02,
WR14_DTR_REQ_FUNC = 0x04,
WR14_AUTO_ECHO = 0x08,
WR14_LOCAL_LOOPBACK = 0x010
};
enum
@ -536,40 +536,40 @@ protected:
int get_tx_word_length();
// receiver state
UINT8 m_rx_data_fifo[8]; // receive data FIFO
UINT8 m_rx_error_fifo[8]; // receive error FIFO
UINT8 m_rx_error; // current receive error
//int m_rx_fifo // receive FIFO pointer
int m_rx_fifo_rp; // receive FIFO read pointer
int m_rx_fifo_wp; // receive FIFO write pointer
int m_rx_fifo_sz; // receive FIFO size
UINT8 m_rx_data_fifo[8]; // receive data FIFO
UINT8 m_rx_error_fifo[8]; // receive error FIFO
UINT8 m_rx_error; // current receive error
//int m_rx_fifo // receive FIFO pointer
int m_rx_fifo_rp; // receive FIFO read pointer
int m_rx_fifo_wp; // receive FIFO write pointer
int m_rx_fifo_sz; // receive FIFO size
int m_rx_clock; // receive clock pulse count
int m_rx_first; // first character received
int m_rx_break; // receive break condition
UINT8 m_rx_rr0_latch; // read register 0 latched
int m_rx_clock; // receive clock pulse count
int m_rx_first; // first character received
int m_rx_break; // receive break condition
UINT8 m_rx_rr0_latch; // read register 0 latched
int m_rxd;
int m_ri; // ring indicator latch
int m_cts; // clear to send latch
int m_dcd; // data carrier detect latch
int m_ri; // ring indicator latch
int m_cts; // clear to send latch
int m_dcd; // data carrier detect latch
// transmitter state
UINT8 m_tx_data; // transmit data register
int m_tx_clock; // transmit clock pulse count
UINT8 m_tx_data; // transmit data register
int m_tx_clock; // transmit clock pulse count
int m_dtr; // data terminal ready
int m_rts; // request to send
int m_dtr; // data terminal ready
int m_rts; // request to send
// synchronous state
UINT16 m_sync; // sync character
UINT16 m_sync; // sync character
int m_rcv_mode;
int m_index;
z80scc_device *m_uart;
// SCC specifics
int m_ph; // Point high command to access regs 08-0f
int m_ph; // Point high command to access regs 08-0f
UINT8 m_zc;
};

4
src/emu/digfx.h
View File

@ -71,8 +71,8 @@ const gfx_layout name = { width, height, RGN_FRAC(1,1), 8, { GFX_RAW }, { 0 }, {
#define STEP1024(START,STEP) STEP512(START,STEP),STEP512((START)+512*(STEP),STEP)
#define STEP2048(START,STEP) STEP1024(START,STEP),STEP1024((START)+1024*(STEP),STEP)
#define STEP2_INV(START,STEP) (START)+(STEP),(START)
#define STEP4_INV(START,STEP) STEP2_INV(START+2*STEP,STEP),STEP2_INV(START,STEP)
#define STEP2_INV(START,STEP) (START)+(STEP),(START)
#define STEP4_INV(START,STEP) STEP2_INV(START+2*STEP,STEP),STEP2_INV(START,STEP)
//**************************************************************************
// GRAPHICS INFO MACROS

18
src/emu/screen.cpp
View File

@ -361,9 +361,9 @@ bool screen_device_svg_renderer::compute_mask_intersection_bbox(int key1, int ke
const cached_bitmap &c1 = m_cache[key1];
const cached_bitmap &c2 = m_cache[key2];
if(c1.x >= c2.x + c2.sx ||
c1.x + c1.sx <= c2.x ||
c1.y >= c2.y + c2.sy ||
c1.y + c1.sy <= c2.y)
c1.x + c1.sx <= c2.x ||
c1.y >= c2.y + c2.sy ||
c1.y + c1.sy <= c2.y)
return false;
int cx0 = c1.x > c2.x ? c1.x : c2.x;
int cy0 = c1.y > c2.y ? c1.y : c2.y;
@ -457,9 +457,9 @@ void screen_device_svg_renderer::rebuild_cache()
for(int okey : doing) {
// The bounding boxes include x1/y1, so the comparisons must be strict
if(!(bboxes[key].x0 > bboxes[okey].x1 ||
bboxes[key].x1 < bboxes[okey].x0 ||
bboxes[key].y0 > bboxes[okey].y1 ||
bboxes[key].y1 < bboxes[okey].y0))
bboxes[key].x1 < bboxes[okey].x0 ||
bboxes[key].y0 > bboxes[okey].y1 ||
bboxes[key].y1 < bboxes[okey].y0))
goto conflict;
}
doing.push_back(key);
@ -511,9 +511,9 @@ void screen_device_svg_renderer::rebuild_cache()
for(int okey : doing) {
// The bounding boxes include x1/y1, so the comparisons must be strict
if(!(bboxes[key].x0 > bboxes[okey].x1 ||
bboxes[key].x1 < bboxes[okey].x0 ||
bboxes[key].y0 > bboxes[okey].y1 ||
bboxes[key].y1 < bboxes[okey].y0))
bboxes[key].x1 < bboxes[okey].x0 ||
bboxes[key].y0 > bboxes[okey].y1 ||
bboxes[key].y1 < bboxes[okey].y0))
goto conflict2;
}
doing.push_back(key);

10
src/lib/netlist/analog/nld_bjt.h
View File

@ -152,11 +152,11 @@ NETLIB_OBJECT_DERIVED(QBJT_EB, QBJT)
{
public:
NETLIB_CONSTRUCTOR_DERIVED(QBJT_EB, QBJT)
, m_D_CB(owner, "m_D_CB")
, m_D_EB(owner, "m_D_EB")
, m_D_EC(owner, "m_D_EC")
, m_alpha_f(0)
, m_alpha_r(0)
, m_D_CB(owner, "m_D_CB")
, m_D_EB(owner, "m_D_EB")
, m_D_EC(owner, "m_D_EC")
, m_alpha_f(0)
, m_alpha_r(0)
{
enregister("E", m_D_EB.m_P); // Cathode
enregister("B", m_D_EB.m_N); // Anode

1
src/lib/netlist/devices/nld_4020.h
View File

@ -91,7 +91,6 @@ NETLIB_OBJECT(CD4020)
, m_sub(*this, "sub")
, m_supply(*this, "supply")
{
enregister("RESET", m_RESET);
register_subalias("IP", m_sub.m_IP);
register_subalias("Q1", m_sub.m_Q[0]);

2
src/lib/netlist/devices/nld_74107.h
View File

@ -115,7 +115,6 @@ NETLIB_OBJECT(74107A)
NETLIB_CONSTRUCTOR(74107A)
, m_sub(*this, "sub")
{
register_subalias("CLK", m_sub.m_clk);
enregister("J", m_J);
enregister("K", m_K);
@ -148,7 +147,6 @@ NETLIB_OBJECT(74107_dip)
, m_1(*this, "1")
, m_2(*this, "2")
{
register_subalias("1", m_1.m_J);
register_subalias("2", m_1.m_sub.m_QQ);
register_subalias("3", m_1.m_sub.m_Q);

2
src/lib/netlist/devices/nld_74153.h
View File

@ -95,7 +95,6 @@ NETLIB_OBJECT(74153)
NETLIB_CONSTRUCTOR(74153)
, m_sub(*this, "sub")
{
register_subalias("C0", m_sub.m_C[0]);
register_subalias("C1", m_sub.m_C[1]);
register_subalias("C2", m_sub.m_C[2]);
@ -120,7 +119,6 @@ NETLIB_OBJECT(74153_dip)
, m_1(*this, "1")
, m_2(*this, "2")
{
register_subalias("1", m_1.m_G);
enregister("2", m_B); // m_2.m_B
register_subalias("3", m_1.m_C[3]);

3
src/lib/netlist/devices/nld_7448.h
View File

@ -46,7 +46,7 @@ NETLIB_NAMESPACE_DEVICES_START()
* FIXME: Using truthtable is a lot slower than the explicit device
*/
#define USE_TRUTHTABLE_7448 (0)
#define USE_TRUTHTABLE_7448 (0)
#if (USE_TRUTHTABLE_7448 && USE_TRUTHTABLE)
@ -100,7 +100,6 @@ NETLIB_OBJECT(7448)
NETLIB_CONSTRUCTOR(7448)
, m_sub(*this, "sub")
{
register_subalias("A", m_sub.m_A);
register_subalias("B", m_sub.m_B);
register_subalias("C", m_sub.m_C);

1
src/lib/netlist/devices/nld_7450.h
View File

@ -65,7 +65,6 @@ NETLIB_OBJECT(7450_dip)
, m_1(*this, "1")
, m_2(*this, "2")
{
register_subalias("1", m_1.m_A);
register_subalias("2", m_2.m_A);
register_subalias("3", m_2.m_B);

2
src/lib/netlist/devices/nld_7474.cpp
View File

@ -68,7 +68,7 @@ NETLIB_RESET(7474sub)
NETLIB_RESET(7474_dip)
{
// m_1.do_reset();
// m_1.do_reset();
//m_2.do_reset();
}

1
src/lib/netlist/devices/nld_7474.h
View File

@ -115,7 +115,6 @@ NETLIB_OBJECT(7474_dip)
, m_1(*this, "1")
, m_2(*this, "2")
{
register_subalias("1", m_1.m_CLRQ);
register_subalias("2", m_1.m_D);
register_subalias("3", m_1.sub.m_CLK);

1
src/lib/netlist/devices/nld_ne555.h
View File

@ -37,7 +37,6 @@ NETLIB_OBJECT(NE555)
, m_last_out(false)
, m_ff(false)
{
register_subalias("GND", m_R3.m_N); // Pin 1
enregister("TRIG", m_TRIG); // Pin 2
enregister("OUT", m_OUT); // Pin 3

2
src/lib/netlist/devices/nld_system.h
View File

@ -525,7 +525,7 @@ public:
protected:
NETLIB_RESETI() { }
NETLIB_RESETI() { }
NETLIB_UPDATEI()
{

22
src/lib/netlist/macro/nlm_ttl74xx.cpp
View File

@ -79,7 +79,7 @@ NETLIST_START(TTL_7402_DIP)
s2.A, /* A2 |5 10| Y3 */ s3.Q,
s2.B, /* B2 |6 9| B3 */ s3.B,
GND.I, /* GND |7 8| A3 */ s3.A
/* +--------------+ */
/* +--------------+ */
)
NETLIST_END()
@ -117,7 +117,7 @@ NETLIST_START(TTL_7404_DIP)
s3.A, /* A3 |5 10| Y5 */ s5.Q,
s3.Q, /* Y3 |6 9| A4 */ s4.A,
GND.I, /* GND |7 8| Y4 */ s4.Q
/* +--------------+ */
/* +--------------+ */
)
NETLIST_END()
@ -156,7 +156,7 @@ NETLIST_START(TTL_7408_DIP)
s2.B, /* B2 |5 10| B3 */ s3.B,
s2.Q, /* Y2 |6 9| A3 */ s3.A,
GND.I, /* GND |7 8| Y3 */ s3.Q
/* +--------------+ */
/* +--------------+ */
)
NETLIST_END()
@ -193,7 +193,7 @@ NETLIST_START(TTL_7410_DIP)
s2.C, /* C2 |5 10| B3 */ s3.B,
s2.Q, /* Y2 |6 9| A3 */ s3.A,
GND.I, /* GND |7 8| Y3 */ s3.Q
/* +--------------+ */
/* +--------------+ */
)
NETLIST_END()
@ -230,7 +230,7 @@ NETLIST_START(TTL_7411_DIP)
s2.C, /* C2 |5 10| B3 */ s3.B,
s2.Q, /* Y2 |6 9| A3 */ s3.A,
GND.I, /* GND |7 8| Y3 */ s3.Q
/* +--------------+ */
/* +--------------+ */
)
NETLIST_END()
@ -297,7 +297,7 @@ NETLIST_START(TTL_7420_DIP)
s1.D, /* D1 |5 10| B2 */ s2.B,
s1.Q, /* Y1 |6 9| A2 */ s2.A,
GND.I, /* GND |7 8| Y2 */ s2.Q
/* +--------------+ */
/* +--------------+ */
)
NETLIST_END()
@ -334,12 +334,12 @@ NETLIST_START(TTL_7425_DIP)
DIPPINS( /* +--------------+ */
s1.A, /* A1 |1 ++ 14| VCC */ VCC.I,
s1.B, /* B1 |2 13| D2 */ s2.D,
X.I, /* X1 |3 12| C2 */ s2.C,
X.I, /* X1 |3 12| C2 */ s2.C,
s1.C, /* C1 |4 7425 11| X2 */ X.I,
s1.D, /* D1 |5 10| B2 */ s2.B,
s1.Q, /* Y1 |6 9| A2 */ s2.A,
GND.I, /* GND |7 8| Y2 */ s2.Q
/* +--------------+ */
/* +--------------+ */
)
NETLIST_END()
@ -377,7 +377,7 @@ NETLIST_START(TTL_7427_DIP)
s2.C, /* C2 |5 10| B3 */ s3.B,
s2.Q, /* Y2 |6 9| A3 */ s3.A,
GND.I, /* GND |7 8| Y3 */ s3.Q
/* +--------------+ */
/* +--------------+ */
)
NETLIST_END()
@ -417,7 +417,7 @@ NETLIST_START(TTL_7430_DIP)
s1.E, /* E |5 10| NC */ NC.I,
s1.F, /* F |6 9| NC */ NC.I,
GND.I, /* GND |7 8| Y */ s1.Q
/* +--------------+ */
/* +--------------+ */
)
NETLIST_END()
@ -456,7 +456,7 @@ NETLIST_START(TTL_7432_DIP)
s2.B, /* B2 |5 10| B3 */ s3.B,
s2.Q, /* Y2 |6 9| A3 */ s3.A,
GND.I, /* GND |7 8| Y3 */ s3.Q
/* +--------------+ */
/* +--------------+ */
)
NETLIST_END()

12
src/lib/netlist/macro/nlm_ttl74xx.h
View File

@ -15,8 +15,8 @@
NET_REGISTER_DEV(TTL_7400_GATE, _name)
#define TTL_7400_NAND(_name, _A, _B) \
NET_REGISTER_DEV(TTL_7400_NAND, _name) \
NET_CONNECT(_name, A, _A) \
NET_REGISTER_DEV(TTL_7400_NAND, _name) \
NET_CONNECT(_name, A, _A) \
NET_CONNECT(_name, B, _B)
#define TTL_7400_DIP(_name) \
@ -50,8 +50,8 @@
NET_REGISTER_DEV(TTL_7408_GATE, _name)
#define TTL_7408_AND(_name, _A, _B) \
NET_REGISTER_DEV(TTL_7408_AND, _name) \
NET_CONNECT(_name, A, _A) \
NET_REGISTER_DEV(TTL_7408_AND, _name) \
NET_CONNECT(_name, A, _A) \
NET_CONNECT(_name, B, _B)
#define TTL_7408_DIP(_name) \
@ -166,8 +166,8 @@
NET_REGISTER_DEV(TTL_7437_GATE, _name)
#define TTL_7437_NAND(_name, _A, _B) \
NET_REGISTER_DEV(TTL_7437_NAND, _name) \
NET_CONNECT(_name, A, _A) \
NET_REGISTER_DEV(TTL_7437_NAND, _name) \
NET_CONNECT(_name, A, _A) \
NET_CONNECT(_name, B, _B)
#define TTL_7437_DIP(_name) \

13
src/lib/netlist/nl_base.cpp
View File

@ -20,7 +20,6 @@ const netlist::netlist_time netlist::netlist_time::zero = netlist::netlist_time(
namespace netlist
{
#if 0
static pmempool p(65536, 16);
@ -31,8 +30,8 @@ void * object_t::operator new (size_t size)
void object_t::operator delete (void * mem)
{
if (mem)
p.free(mem);
if (mem)
p.free(mem);
}
#else
void * object_t::operator new (size_t size)
@ -42,8 +41,8 @@ void * object_t::operator new (size_t size)
void object_t::operator delete (void * mem)
{
if (mem)
::operator delete(mem);
if (mem)
::operator delete(mem);
}
#endif
@ -234,7 +233,6 @@ netlist_t::netlist_t(const pstring &aname)
netlist_t::~netlist_t()
{
m_nets.clear();
m_devices.clear();
@ -619,7 +617,7 @@ ATTR_COLD net_t::~net_t()
// FIXME: move somewhere central
struct do_nothing_deleter{
template<typename T> void operator()(T*){}
template<typename T> void operator()(T*){}
};
ATTR_COLD void net_t::init_object(netlist_t &nl, const pstring &aname, core_terminal_t *mr)
@ -1058,4 +1056,3 @@ ATTR_HOT /* inline */ void NETLIB_NAME(mainclock)::mc_update(logic_net_t &net)
NETLIB_NAMESPACE_DEVICES_END()

14
src/lib/netlist/nl_base.h
View File

@ -176,9 +176,9 @@
*/
using netlist_sig_t = std::uint32_t;
//============================================================
// MACROS / New Syntax
//============================================================
//============================================================
// MACROS / New Syntax
//============================================================
#define NETLIB_NAMESPACE_DEVICES_START() namespace netlist { namespace devices {
#define NETLIB_NAMESPACE_DEVICES_END() }}
@ -208,10 +208,10 @@ class NETLIB_NAME(_name) : public device_t
public: template <class _CLASS> ATTR_COLD NETLIB_NAME(_name)(_CLASS &owner, const pstring name, __VA_ARGS__) \
: device_t(owner, name)
#define NETLIB_DYNAMIC() \
#define NETLIB_DYNAMIC() \
public: ATTR_HOT virtual bool is_dynamic1() const override { return true; }
#define NETLIB_TIMESTEP() \
#define NETLIB_TIMESTEP() \
public: ATTR_HOT virtual bool is_timestep() const override { return true; } \
public: ATTR_HOT virtual void step_time(const nl_double step) override
@ -403,8 +403,8 @@ namespace netlist
#if 1
public:
void * operator new (size_t size);
void operator delete (void * mem);
void * operator new (size_t size);
void operator delete (void * mem);
#endif
};

2
src/lib/netlist/plib/pdynlib.cpp
View File

@ -41,7 +41,7 @@ pdynlib::pdynlib(const pstring libname)
pdynlib::pdynlib(const pstring path, const pstring libname)
: m_isLoaded(false), m_lib(nullptr)
{
// printf("win: loading <%s>\n", libname.cstr());
// printf("win: loading <%s>\n", libname.cstr());
#ifdef _WIN32
if (libname != "")
m_lib = LoadLibrary(libname.cstr());

2
src/lib/netlist/solver/nld_matrix_solver.h
View File

@ -87,7 +87,7 @@ public:
matrix_solver_t(netlist_t &anetlist, const pstring &name,
const eSortType sort, const solver_parameters_t *params)
: device_t(anetlist, name),
m_stat_calculations(0),
m_stat_calculations(0),
m_stat_newton_raphson(0),
m_stat_vsolver_calls(0),
m_iterative_fail(0),

4
src/lib/netlist/solver/nld_ms_sm.h
View File

@ -13,9 +13,9 @@
* In this specific implementation, u is a unit vector specifying the row which
* changed. Thus v contains the changed column.
*
* Than z = A⁻¹ u , w = transpose(A⁻¹) v , lambda = v z
* Than z = A^-1 u , w = transpose(A^-1) v , lambda = v z
*
* A⁻¹ <- 1.0 / (1.0 + lambda) * (z x w)
* A^-1 <- 1.0 / (1.0 + lambda) * (z x w)
*
* The approach is iterative and applied for each row changed.
*

2
src/lib/netlist/solver/nld_ms_w.h
View File

@ -15,7 +15,7 @@
* Whilst the book proposes to invert the matrix R=(I+transpose(V)*Z) we define
*
* w = transpose(V)*y
* a = R⁻¹ * w
* a = R^-1 * w
*
* and consequently
*

6
src/mame/drivers/1942.cpp
View File

@ -794,9 +794,9 @@ ROM_END
/* set contained only three program ROMs, other ROMs should be checked against a real PCB */
ROM_START( 1942h )
ROM_REGION( 0x20000, "maincpu", ROMREGION_ERASEFF ) /* 64k for code + 3*16k for the banked ROMs images */
ROM_LOAD( "Supercharger_1942_#3.m3", 0x00000, 0x4000, CRC(ec70785f) SHA1(2010a945e1d5c984a14cf7f47a883d04bd71567d) ) /* label confirmed from auction post */
ROM_LOAD( "Supercharger_1942_#4.m4", 0x04000, 0x4000, CRC(cc11355f) SHA1(44fceb449f406f657494eeee4e6b43bf063f2013) ) /* label confirmed from auction post */
ROM_LOAD( "Supercharger_1942_#5.m5", 0x10000, 0x4000, CRC(42746d75) SHA1(ede6919b84653b94fddeb40b3004e44336880ba2) ) /* label confirmed from auction post */
ROM_LOAD( "Supercharger_1942_#3.m3", 0x00000, 0x4000, CRC(ec70785f) SHA1(2010a945e1d5c984a14cf7f47a883d04bd71567d) ) /* label confirmed from auction post */
ROM_LOAD( "Supercharger_1942_#4.m4", 0x04000, 0x4000, CRC(cc11355f) SHA1(44fceb449f406f657494eeee4e6b43bf063f2013) ) /* label confirmed from auction post */
ROM_LOAD( "Supercharger_1942_#5.m5", 0x10000, 0x4000, CRC(42746d75) SHA1(ede6919b84653b94fddeb40b3004e44336880ba2) ) /* label confirmed from auction post */
ROM_LOAD( "srb-06.m6", 0x14000, 0x2000, CRC(466f8248) SHA1(2ccc8fc59962d3001fbc10e8d2f20a254a74f251) )
ROM_LOAD( "srb-07.m7", 0x18000, 0x4000, CRC(0d31038c) SHA1(b588eaf6fddd66ecb2d9832dc197f286f1ccd846) )

1
src/mame/drivers/altos486.cpp
View File

@ -220,4 +220,3 @@ ROM_START( altos486 )
ROM_END
COMP( 1984, altos486, 0, 0, altos486, 0, driver_device, 0, "Altos Computer Systems", "Altos 486", MACHINE_NOT_WORKING | MACHINE_NO_SOUND)

2
src/mame/drivers/apple2e.cpp
View File

@ -3457,7 +3457,7 @@ static MACHINE_CONFIG_DERIVED( apple2c, apple2ee )
MCFG_RS232_CTS_HANDLER(DEVWRITELINE(IIC_ACIA2_TAG, mos6551_device, write_cts))
// TODO: populate the IIc's other virtual slots with ONBOARD_ADD
MCFG_A2BUS_ONBOARD_ADD("a2bus", "sl4", A2BUS_MOCKINGBOARD, NOOP ) // Mockingboard 4C
MCFG_A2BUS_ONBOARD_ADD("a2bus", "sl4", A2BUS_MOCKINGBOARD, NOOP ) // Mockingboard 4C
MCFG_A2BUS_ONBOARD_ADD("a2bus", "sl6", A2BUS_DISKIING, NOOP)
MCFG_A2EAUXSLOT_SLOT_REMOVE("aux")

49
src/mame/drivers/crgolf.cpp
View File

@ -48,35 +48,35 @@
Pin 19 - Pin 22 of F1 (2764 on cpu/sound board), Output
Pin 20 - VCC
-------------------------------------------------------------------
-------------------------------------------------------------------
Master's Golf is a different PCB, but appears to operate in a similar way
Master's Golf is a different PCB, but appears to operate in a similar way
PCB X-081-PC-A
PCB X-081-PC-A
contains a large box marked
contains a large box marked
|-----------------------\_/--------------------|
| NASCO-9000 |
| |
| /- NASCO -\ |
| /\ | ORIGINAL | |
| NASCO\/YUVO \- 0001941 -/ |
| |
| PAT.P |
| |---------------------------------------| |
| | MASTER'S GOLF vers JAPAN | |
| | | |
| | CUSTOM BOARD | |
| |---------------------------------------| |
| |
| YUVO CO., LTD |
|-----------------------------------------------
|-----------------------\_/--------------------|
| NASCO-9000 |
| |
| /- NASCO -\ |
| /\ | ORIGINAL | |
| NASCO\/YUVO \- 0001941 -/ |
| |
| PAT.P |
| |---------------------------------------| |
| | MASTER'S GOLF vers JAPAN | |
| | | |
| | CUSTOM BOARD | |
| |---------------------------------------| |
| |
| YUVO CO., LTD |
|-----------------------------------------------
next to rom M-GF_A10.12K
the box must contain at least a Z80
next to rom M-GF_A10.12K
the box must contain at least a Z80
DASM Notes:
- main CPU currently stalls with a RAM buffer check ($63fe), then it
@ -289,7 +289,7 @@ WRITE8_MEMBER(crgolf_state::crgolfhi_sample_w)
WRITE8_MEMBER(crgolf_state::screen_select_w)
{
// if (data & 0xfe) printf("vram_page_select_w %02x\n", data);
// if (data & 0xfe) printf("vram_page_select_w %02x\n", data);
m_vrambank->set_bank(data & 0x1);
}
@ -361,7 +361,7 @@ static ADDRESS_MAP_START( mastrglf_io, AS_IO, 8, crgolf_state )
AM_RANGE(0x06, 0x06) AM_WRITEONLY AM_SHARE("screenb_enable")
AM_RANGE(0x07, 0x07) AM_WRITEONLY AM_SHARE("screena_enable")
// AM_RANGE(0x20, 0x20) AM_WRITE( main_to_sound_w )
// AM_RANGE(0x20, 0x20) AM_WRITE( main_to_sound_w )
AM_RANGE(0x40, 0x40) AM_WRITE( main_to_sound_w )
AM_RANGE(0xa0, 0xa0) AM_READ( sound_to_main_r )
ADDRESS_MAP_END
@ -391,7 +391,6 @@ READ8_MEMBER(crgolf_state::unk_sub_07_r)
WRITE8_MEMBER(crgolf_state::unk_sub_0c_w)
{
}

2
src/mame/drivers/cybiko.cpp
View File

@ -60,7 +60,7 @@ ToDo:
static ADDRESS_MAP_START( cybikov1_mem, AS_PROGRAM, 16, cybiko_state )
AM_RANGE( 0x000000, 0x007fff ) AM_ROM
AM_RANGE( 0x600000, 0x600001 ) AM_READWRITE( cybiko_lcd_r, cybiko_lcd_w )
// AM_RANGE( 0xe00000, 0xe07fff ) AM_READ( cybikov1_key_r )
// AM_RANGE( 0xe00000, 0xe07fff ) AM_READ( cybikov1_key_r )
ADDRESS_MAP_END
/*

16
src/mame/drivers/goldstar.cpp
View File

@ -887,16 +887,16 @@ static ADDRESS_MAP_START( flaming7_map, AS_PROGRAM, 8, goldstar_state )
AM_RANGE(0x9000, 0x97ff) AM_RAM_WRITE(goldstar_fg_atrram_w) AM_SHARE("fg_atrram")
AM_RANGE(0x9800, 0x99ff) AM_RAM_WRITE(goldstar_reel1_ram_w) AM_SHARE("reel1_ram")
// AM_RANGE(0x9a00, 0x9fff) AM_RAM
// AM_RANGE(0x9a00, 0x9fff) AM_RAM
AM_RANGE(0xa000, 0xa1ff) AM_RAM_WRITE(goldstar_reel2_ram_w) AM_SHARE("reel2_ram")
// AM_RANGE(0xa200, 0xa7ff) AM_RAM
// AM_RANGE(0xa200, 0xa7ff) AM_RAM
AM_RANGE(0xa800, 0xa9ff) AM_RAM_WRITE(goldstar_reel3_ram_w) AM_SHARE("reel3_ram")
// AM_RANGE(0xaa00, 0xafff) AM_RAM
// AM_RANGE(0xaa00, 0xafff) AM_RAM
// AM_RANGE(0xb000, 0xb03f) AM_RAM
// AM_RANGE(0xb000, 0xb03f) AM_RAM
AM_RANGE(0xb040, 0xb07f) AM_RAM AM_SHARE("reel1_scroll")
AM_RANGE(0xb080, 0xb0bf) AM_RAM AM_SHARE("reel2_scroll")
// AM_RANGE(0xb0c0, 0xb0ff) AM_RAM
// AM_RANGE(0xb0c0, 0xb0ff) AM_RAM
AM_RANGE(0xb100, 0xb17f) AM_RAM AM_SHARE("reel3_scroll")
AM_RANGE(0xb180, 0xb7ff) AM_RAM
@ -908,7 +908,7 @@ static ADDRESS_MAP_START( flaming7_map, AS_PROGRAM, 8, goldstar_state )
AM_RANGE(0xb850, 0xb850) AM_WRITE(p1_lamps_w)
AM_RANGE(0xb860, 0xb860) AM_WRITE(p2_lamps_w)
AM_RANGE(0xb870, 0xb870) AM_DEVWRITE("snsnd", sn76489_device, write) /* sound */
// AM_RANGE(0xc000, 0xd3ff) AM_RAM
// AM_RANGE(0xc000, 0xd3ff) AM_RAM
AM_RANGE(0xf800, 0xffff) AM_RAM
ADDRESS_MAP_END
/*
@ -8179,7 +8179,7 @@ static MACHINE_CONFIG_DERIVED( flaming7, lucky8 )
/* basic machine hardware */
MCFG_CPU_MODIFY("maincpu")
MCFG_CPU_PROGRAM_MAP(flaming7_map)
// MCFG_CPU_IO_MAP(flaming7_readport)
// MCFG_CPU_IO_MAP(flaming7_readport)
MACHINE_CONFIG_END
@ -10836,7 +10836,7 @@ ROM_END
1x uPC1181 (0a) - Audio Amplifier - sound.
ROMs
4x AM27C64 (1-4) dumped.
4x AM27C64 (1-4) dumped.
4x M27C256B (5-8) dumped.
3x AM27S21APC (1, 2, 3) dumped.
3x N82S123AN (4, 5) dumped.

2
src/mame/drivers/harddriv.cpp
View File

@ -5010,7 +5010,7 @@ void harddriv_state::init_racedrivc_panorama_side()
// m_gsp->space(AS_PROGRAM).install_write_handler(0xfff76f60, 0xfff76f6f, write16_delegate(FUNC(harddriv_state::rdgsp_speedup1_w), this));
// m_gsp->space(AS_PROGRAM).install_read_handler(0xfff76f60, 0xfff76f6f, read16_delegate(FUNC(harddriv_state::rdgsp_speedup1_r), this));
// m_gsp_speedup_pc = 0xfff43a00;
// m_gsp_speedup_addr[0] = (UINT16 *)(m_gsp_vram + ((0xfff76f60 - 0xffc00000) >> 3));
// m_gsp_speedup_addr[0] = (UINT16 *)(m_gsp_vram + ((0xfff76f60 - 0xffc00000) >> 3));
/* set up adsp speedup handlers */
m_adsp->space(AS_DATA).install_read_handler(0x1fff, 0x1fff, read16_delegate(FUNC(harddriv_state::hdadsp_speedup_r), this));

728
src/mame/drivers/hp9845.cpp
View File

@ -104,9 +104,9 @@ public:
driver_device(mconfig, type, tag),
m_lpu(*this , "lpu"),
m_ppu(*this , "ppu"),
m_screen(*this , "screen"),
m_screen(*this , "screen"),
m_palette(*this , "palette"),
m_gv_timer(*this , "gv_timer"),
m_gv_timer(*this , "gv_timer"),
m_io_key0(*this , "KEY0"),
m_io_key1(*this , "KEY1"),
m_io_key2(*this , "KEY2"),
@ -120,16 +120,16 @@ public:
virtual void machine_reset() override;
TIMER_DEVICE_CALLBACK_MEMBER(scanline_timer);
TIMER_DEVICE_CALLBACK_MEMBER(gv_timer);
TIMER_DEVICE_CALLBACK_MEMBER(gv_timer);
void vblank_w(screen_device &screen, bool state);
void set_graphic_mode(bool graphic);
void set_graphic_mode(bool graphic);
DECLARE_READ16_MEMBER(graphic_r);
DECLARE_WRITE16_MEMBER(graphic_w);
attotime time_to_gv_mem_availability(void) const;
void advance_gv_fsm(bool ds , bool trigger);
void update_graphic_bits(void);
attotime time_to_gv_mem_availability(void) const;
void advance_gv_fsm(bool ds , bool trigger);
void update_graphic_bits(void);
IRQ_CALLBACK_MEMBER(irq_callback);
void update_irq(void);
@ -148,9 +148,9 @@ public:
private:
required_device<hp_5061_3001_cpu_device> m_lpu;
required_device<hp_5061_3001_cpu_device> m_ppu;
required_device<screen_device> m_screen;
required_device<screen_device> m_screen;
required_device<palette_device> m_palette;
required_device<timer_device> m_gv_timer;
required_device<timer_device> m_gv_timer;
required_ioport m_io_key0;
required_ioport m_io_key1;
required_ioport m_io_key2;
@ -160,7 +160,7 @@ private:
void set_video_mar(UINT16 mar);
void video_fill_buff(bool buff_idx);
void video_render_buff(unsigned video_scanline , unsigned line_in_row, bool buff_idx);
void graphic_video_render(unsigned video_scanline);
void graphic_video_render(unsigned video_scanline);
// Character generator
const UINT8 *m_chargen;
@ -176,41 +176,41 @@ private:
offs_t m_video_mar;
UINT16 m_video_word;
bool m_video_load_mar;
bool m_video_first_mar;
bool m_video_first_mar;
bool m_video_byte_idx;
UINT8 m_video_attr;
bool m_video_buff_idx;
bool m_video_blanked;
video_buffer_t m_video_buff[ 2 ];
// Graphic video
typedef enum {
GV_STAT_RESET,
GV_STAT_WAIT_DS_0 = GV_STAT_RESET,
GV_STAT_WAIT_TRIG_0,
GV_STAT_WAIT_MEM_0,
GV_STAT_WAIT_DS_1,
GV_STAT_WAIT_DS_2,
GV_STAT_WAIT_TRIG_1,
GV_STAT_WAIT_MEM_1,
GV_STAT_WAIT_MEM_2
} gv_fsm_state_t;
// Graphic video
typedef enum {
GV_STAT_RESET,
GV_STAT_WAIT_DS_0 = GV_STAT_RESET,
GV_STAT_WAIT_TRIG_0,
GV_STAT_WAIT_MEM_0,
GV_STAT_WAIT_DS_1,
GV_STAT_WAIT_DS_2,
GV_STAT_WAIT_TRIG_1,
GV_STAT_WAIT_MEM_1,
GV_STAT_WAIT_MEM_2
} gv_fsm_state_t;
bool m_graphic_sel;
gv_fsm_state_t m_gv_fsm_state;
bool m_gv_int_en;
bool m_gv_dma_en;
bool m_gv_ready;
UINT8 m_gv_cmd; // U65 (GC)
UINT16 m_gv_data_w; // U29, U45, U28 & U44 (GC)
UINT16 m_gv_data_r; // U59 & U60 (GC)
UINT16 m_gv_io_counter; // U1, U2, U14 & U15 (GC)
UINT16 m_gv_cursor_w; // U38 & U39 (GS)
UINT16 m_gv_cursor_x; // U31 & U23 (GS)
UINT16 m_gv_cursor_y; // U15 & U8 (GS)
bool m_gv_cursor_gc; // U8 (GS)
bool m_gv_cursor_fs; // U8 (GS)
std::vector<UINT16> m_graphic_mem;
bool m_graphic_sel;
gv_fsm_state_t m_gv_fsm_state;
bool m_gv_int_en;
bool m_gv_dma_en;
bool m_gv_ready;
UINT8 m_gv_cmd; // U65 (GC)
UINT16 m_gv_data_w; // U29, U45, U28 & U44 (GC)
UINT16 m_gv_data_r; // U59 & U60 (GC)
UINT16 m_gv_io_counter; // U1, U2, U14 & U15 (GC)
UINT16 m_gv_cursor_w; // U38 & U39 (GS)
UINT16 m_gv_cursor_x; // U31 & U23 (GS)
UINT16 m_gv_cursor_y; // U15 & U8 (GS)
bool m_gv_cursor_gc; // U8 (GS)
bool m_gv_cursor_fs; // U8 (GS)
std::vector<UINT16> m_graphic_mem;
// Interrupt handling
UINT8 m_irl_pending;
@ -373,11 +373,11 @@ UINT32 hp9845_state::screen_update(screen_device &screen, bitmap_rgb32 &bitmap,
UINT32 hp9845b_state::screen_update(screen_device &screen, bitmap_rgb32 &bitmap, const rectangle &cliprect)
{
if (m_graphic_sel) {
copybitmap(bitmap, m_bitmap, 0, 0, GVIDEO_HBEND, GVIDEO_VBEND, cliprect);
} else {
copybitmap(bitmap, m_bitmap, 0, 0, 0, 0, cliprect);
}
if (m_graphic_sel) {
copybitmap(bitmap, m_bitmap, 0, 0, GVIDEO_HBEND, GVIDEO_VBEND, cliprect);
} else {
copybitmap(bitmap, m_bitmap, 0, 0, 0, 0, cliprect);
}
return 0;
}
@ -388,7 +388,7 @@ void hp9845b_state::machine_start()
m_chargen = memregion("chargen")->base();
m_graphic_mem.resize(GVIDEO_MEM_SIZE);
m_graphic_mem.resize(GVIDEO_MEM_SIZE);
}
void hp9845b_state::machine_reset()
@ -399,16 +399,16 @@ void hp9845b_state::machine_reset()
// Some sensible defaults
m_video_mar = VIDEO_BUFFER_BASE;
m_video_load_mar = false;
m_video_first_mar = false;
m_video_first_mar = false;
m_video_byte_idx = false;
m_video_attr = 0;
m_video_buff_idx = false;
m_video_blanked = false;
m_graphic_sel = false;
m_gv_fsm_state = GV_STAT_RESET;
m_gv_int_en = false;
m_gv_dma_en = false;
m_gv_ready = true;
m_graphic_sel = false;
m_gv_fsm_state = GV_STAT_RESET;
m_gv_int_en = false;
m_gv_dma_en = false;
m_gv_ready = true;
m_irl_pending = 0;
m_irh_pending = 0;
@ -441,10 +441,10 @@ void hp9845b_state::video_fill_buff(bool buff_idx)
m_video_word = prog_space.read_word(m_video_mar << 1);
if (m_video_load_mar) {
// Load new address into MAR after start of a new frame or NWA instruction
if (m_video_first_mar) {
set_graphic_mode(!BIT(m_video_word , 15));
m_video_first_mar = false;
}
if (m_video_first_mar) {
set_graphic_mode(!BIT(m_video_word , 15));
m_video_first_mar = false;
}
set_video_mar(~m_video_word);
m_video_load_mar = false;
continue;
@ -492,17 +492,17 @@ void hp9845b_state::video_render_buff(unsigned video_scanline , unsigned line_in
m_video_blanked = true;
}
const pen_t *pen = m_palette->pens();
const pen_t *pen = m_palette->pens();
if (m_video_blanked) {
// Blank scanline
for (unsigned i = 0; i < VIDEO_HBSTART; i++) {
m_bitmap.pix32(video_scanline , i) = pen[ 0 ];
}
// Blank scanline
for (unsigned i = 0; i < VIDEO_HBSTART; i++) {
m_bitmap.pix32(video_scanline , i) = pen[ 0 ];
}
} else {
bool cursor_line = line_in_row == 12;
bool ul_line = line_in_row == 14;
unsigned video_frame = (unsigned)m_screen->frame_number();
unsigned video_frame = (unsigned)m_screen->frame_number();
bool cursor_blink = BIT(video_frame , 3);
bool char_blink = BIT(video_frame , 4);
@ -539,375 +539,375 @@ void hp9845b_state::video_render_buff(unsigned video_scanline , unsigned line_in
TIMER_DEVICE_CALLBACK_MEMBER(hp9845b_state::scanline_timer)
{
unsigned video_scanline = param;
unsigned video_scanline = param;
if (m_graphic_sel) {
if (video_scanline >= GVIDEO_VBEND && video_scanline < GVIDEO_VBSTART) {
graphic_video_render(video_scanline);
}
} else if (video_scanline < VIDEO_ACTIVE_SCANLINES) {
unsigned row = video_scanline / VIDEO_CHAR_HEIGHT;
unsigned line_in_row = video_scanline - row * VIDEO_CHAR_HEIGHT;
if (m_graphic_sel) {
if (video_scanline >= GVIDEO_VBEND && video_scanline < GVIDEO_VBSTART) {
graphic_video_render(video_scanline);
}
} else if (video_scanline < VIDEO_ACTIVE_SCANLINES) {
unsigned row = video_scanline / VIDEO_CHAR_HEIGHT;
unsigned line_in_row = video_scanline - row * VIDEO_CHAR_HEIGHT;
if (line_in_row == 0) {
// Start of new row, swap buffers
m_video_buff_idx = !m_video_buff_idx;
video_fill_buff(!m_video_buff_idx);
}
if (line_in_row == 0) {
// Start of new row, swap buffers
m_video_buff_idx = !m_video_buff_idx;
video_fill_buff(!m_video_buff_idx);
}
video_render_buff(video_scanline , line_in_row , m_video_buff_idx);
}
video_render_buff(video_scanline , line_in_row , m_video_buff_idx);
}
}
TIMER_DEVICE_CALLBACK_MEMBER(hp9845b_state::gv_timer)
{
advance_gv_fsm(false , false);
advance_gv_fsm(false , false);
}
void hp9845b_state::vblank_w(screen_device &screen, bool state)
{
// VBlank signal is fed into HALT flag of PPU
m_ppu->halt_w(state);
// VBlank signal is fed into HALT flag of PPU
m_ppu->halt_w(state);
if (state) {
// Start of V blank
set_video_mar(0);
m_video_load_mar = true;
m_video_first_mar = true;
m_video_byte_idx = false;
m_video_blanked = false;
m_video_buff_idx = !m_video_buff_idx;
video_fill_buff(!m_video_buff_idx);
}
if (state) {
// Start of V blank
set_video_mar(0);
m_video_load_mar = true;
m_video_first_mar = true;
m_video_byte_idx = false;
m_video_blanked = false;
m_video_buff_idx = !m_video_buff_idx;
video_fill_buff(!m_video_buff_idx);
}
}
void hp9845b_state::set_graphic_mode(bool graphic)
{
if (graphic != m_graphic_sel) {
m_graphic_sel = graphic;
logerror("GS=%d\n" , graphic);
if (m_graphic_sel) {
m_screen->configure(GVIDEO_HTOTAL , GVIDEO_VTOTAL , rectangle(GVIDEO_HBEND , GVIDEO_HBSTART - 1 , GVIDEO_VBEND , GVIDEO_VBSTART - 1) , HZ_TO_ATTOSECONDS(VIDEO_PIXEL_CLOCK) * GVIDEO_HTOTAL * GVIDEO_VTOTAL);
} else {
m_screen->configure(VIDEO_HTOTAL , VIDEO_VTOTAL , rectangle(0 , VIDEO_HBSTART - 1 , 0 , VIDEO_ACTIVE_SCANLINES - 1) , HZ_TO_ATTOSECONDS(VIDEO_PIXEL_CLOCK) * VIDEO_HTOTAL * VIDEO_VTOTAL);
}
}
if (graphic != m_graphic_sel) {
m_graphic_sel = graphic;
logerror("GS=%d\n" , graphic);
if (m_graphic_sel) {
m_screen->configure(GVIDEO_HTOTAL , GVIDEO_VTOTAL , rectangle(GVIDEO_HBEND , GVIDEO_HBSTART - 1 , GVIDEO_VBEND , GVIDEO_VBSTART - 1) , HZ_TO_ATTOSECONDS(VIDEO_PIXEL_CLOCK) * GVIDEO_HTOTAL * GVIDEO_VTOTAL);
} else {
m_screen->configure(VIDEO_HTOTAL , VIDEO_VTOTAL , rectangle(0 , VIDEO_HBSTART - 1 , 0 , VIDEO_ACTIVE_SCANLINES - 1) , HZ_TO_ATTOSECONDS(VIDEO_PIXEL_CLOCK) * VIDEO_HTOTAL * VIDEO_VTOTAL);
}
}
}
READ16_MEMBER(hp9845b_state::graphic_r)
{
UINT16 res = 0;
UINT16 res = 0;
switch (offset) {
case 0:
// R4: data register
res = m_gv_data_r;
advance_gv_fsm(true , false);
break;
switch (offset) {
case 0:
// R4: data register
res = m_gv_data_r;
advance_gv_fsm(true , false);
break;
case 1:
// R5: status register
if (m_gv_int_en) {
BIT_SET(res, 7);
}
if (m_gv_dma_en) {
BIT_SET(res, 6);
}
BIT_SET(res, 5);
break;
case 1:
// R5: status register
if (m_gv_int_en) {
BIT_SET(res, 7);
}
if (m_gv_dma_en) {
BIT_SET(res, 6);
}
BIT_SET(res, 5);
break;
case 2:
// R6: data register with DMA TC
m_gv_dma_en = false;
res = m_gv_data_r;
advance_gv_fsm(true , false);
break;
case 2:
// R6: data register with DMA TC
m_gv_dma_en = false;
res = m_gv_data_r;
advance_gv_fsm(true , false);
break;
case 3:
// R7: not mapped
break;
}
case 3:
// R7: not mapped
break;
}
//logerror("rd gv R%u = %04x\n", 4 + offset , res);
//logerror("rd gv R%u = %04x\n", 4 + offset , res);
return res;
return res;
}
WRITE16_MEMBER(hp9845b_state::graphic_w)
{
//logerror("wr gv R%u = %04x\n", 4 + offset , data);
//logerror("wr gv R%u = %04x\n", 4 + offset , data);
switch (offset) {
case 0:
// R4: data register
m_gv_data_w = data;
m_gv_cursor_w = data;
advance_gv_fsm(true , false);
break;
switch (offset) {
case 0:
// R4: data register
m_gv_data_w = data;
m_gv_cursor_w = data;
advance_gv_fsm(true , false);
break;
case 1:
// R5: command register
m_gv_cmd = (UINT8)(data & 0xf);
if (BIT(data , 5)) {
m_gv_fsm_state = GV_STAT_RESET;
}
m_gv_dma_en = BIT(data , 6) != 0;
m_gv_int_en = BIT(data , 7) != 0;
advance_gv_fsm(false , false);
break;
case 1:
// R5: command register
m_gv_cmd = (UINT8)(data & 0xf);
if (BIT(data , 5)) {
m_gv_fsm_state = GV_STAT_RESET;
}
m_gv_dma_en = BIT(data , 6) != 0;
m_gv_int_en = BIT(data , 7) != 0;
advance_gv_fsm(false , false);
break;
case 2:
// R6: data register with DMA TC
m_gv_dma_en = false;
m_gv_data_w = data;
m_gv_cursor_w = data;
advance_gv_fsm(true , false);
break;
case 2:
// R6: data register with DMA TC
m_gv_dma_en = false;
m_gv_data_w = data;
m_gv_cursor_w = data;
advance_gv_fsm(true , false);
break;
case 3:
// R7: trigger
advance_gv_fsm(false , true);
break;
}
case 3:
// R7: trigger
advance_gv_fsm(false , true);
break;
}
}
attotime hp9845b_state::time_to_gv_mem_availability(void) const
{
if (m_graphic_sel) {
int hpos = m_screen->hpos();
if (hpos < (34 - GVIDEO_HCNT_OFF) || hpos >= (628 - GVIDEO_HCNT_OFF)) {
// Access to graphic memory available now
return attotime::zero;
} else {
// Wait until start of hblank
return m_screen->time_until_pos(m_screen->vpos() , 628);
}
} else {
// TODO:
return attotime::zero;
}
if (m_graphic_sel) {
int hpos = m_screen->hpos();
if (hpos < (34 - GVIDEO_HCNT_OFF) || hpos >= (628 - GVIDEO_HCNT_OFF)) {
// Access to graphic memory available now
return attotime::zero;
} else {
// Wait until start of hblank
return m_screen->time_until_pos(m_screen->vpos() , 628);
}
} else {
// TODO:
return attotime::zero;
}
}
void hp9845b_state::advance_gv_fsm(bool ds , bool trigger)
{
bool get_out = false;
bool get_out = false;
attotime time_mem_av;
attotime time_mem_av;
do {
bool act_trig = trigger || m_gv_dma_en || !BIT(m_gv_cmd , 2);
do {
bool act_trig = trigger || m_gv_dma_en || !BIT(m_gv_cmd , 2);
switch (m_gv_fsm_state) {
case GV_STAT_WAIT_DS_0:
if ((m_gv_cmd & 0xc) == 0xc) {
// Read command (11xx)
m_gv_fsm_state = GV_STAT_WAIT_MEM_0;
} else if (ds) {
// Wait for data strobe (r/w on r4 or r6)
m_gv_fsm_state = GV_STAT_WAIT_TRIG_0;
} else {
get_out = true;
}
break;
switch (m_gv_fsm_state) {
case GV_STAT_WAIT_DS_0:
if ((m_gv_cmd & 0xc) == 0xc) {
// Read command (11xx)
m_gv_fsm_state = GV_STAT_WAIT_MEM_0;
} else if (ds) {
// Wait for data strobe (r/w on r4 or r6)
m_gv_fsm_state = GV_STAT_WAIT_TRIG_0;
} else {
get_out = true;
}
break;
case GV_STAT_WAIT_TRIG_0:
// Wait for trigger
if (act_trig) {
if (BIT(m_gv_cmd , 3)) {
// Not a cursor command
// Load memory address
m_gv_io_counter = ~m_gv_data_w & GVIDEO_ADDR_MASK;
// Write commands (10xx)
m_gv_fsm_state = GV_STAT_WAIT_DS_2;
} else {
// Cursor command (0xxx)
if (BIT(m_gv_cmd , 2)) {
// Write X cursor position (01xx)
m_gv_cursor_x = (~m_gv_cursor_w >> 6) & 0x3ff;
//logerror("gv x curs pos = %u\n" , m_gv_cursor_x);
} else {
// Write Y cursor position and type (00xx)
m_gv_cursor_y = (~m_gv_cursor_w >> 6) & 0x1ff;
m_gv_cursor_gc = BIT(m_gv_cmd , 1) == 0;
m_gv_cursor_fs = BIT(m_gv_cmd , 0) != 0;
//logerror("gv y curs pos = %u gc = %d fs = %d\n" , m_gv_cursor_y , m_gv_cursor_gc , m_gv_cursor_fs);
}
m_gv_fsm_state = GV_STAT_WAIT_DS_0;
}
} else {
get_out = true;
}
break;
case GV_STAT_WAIT_TRIG_0:
// Wait for trigger
if (act_trig) {
if (BIT(m_gv_cmd , 3)) {
// Not a cursor command
// Load memory address
m_gv_io_counter = ~m_gv_data_w & GVIDEO_ADDR_MASK;
// Write commands (10xx)
m_gv_fsm_state = GV_STAT_WAIT_DS_2;
} else {
// Cursor command (0xxx)
if (BIT(m_gv_cmd , 2)) {
// Write X cursor position (01xx)
m_gv_cursor_x = (~m_gv_cursor_w >> 6) & 0x3ff;
//logerror("gv x curs pos = %u\n" , m_gv_cursor_x);
} else {
// Write Y cursor position and type (00xx)
m_gv_cursor_y = (~m_gv_cursor_w >> 6) & 0x1ff;
m_gv_cursor_gc = BIT(m_gv_cmd , 1) == 0;
m_gv_cursor_fs = BIT(m_gv_cmd , 0) != 0;
//logerror("gv y curs pos = %u gc = %d fs = %d\n" , m_gv_cursor_y , m_gv_cursor_gc , m_gv_cursor_fs);
}
m_gv_fsm_state = GV_STAT_WAIT_DS_0;
}
} else {
get_out = true;
}
break;
case GV_STAT_WAIT_MEM_0:
time_mem_av = time_to_gv_mem_availability();
if (time_mem_av.is_zero()) {
// Read a word from graphic memory
m_gv_data_r = m_graphic_mem[ m_gv_io_counter ];
//logerror("rd gv mem @%04x = %04x\n" , m_gv_io_counter , m_gv_data_r);
m_gv_io_counter = (m_gv_io_counter + 1) & GVIDEO_ADDR_MASK;
m_gv_fsm_state = GV_STAT_WAIT_DS_1;
} else {
m_gv_timer->adjust(time_mem_av);
get_out = true;
}
break;
case GV_STAT_WAIT_MEM_0:
time_mem_av = time_to_gv_mem_availability();
if (time_mem_av.is_zero()) {
// Read a word from graphic memory
m_gv_data_r = m_graphic_mem[ m_gv_io_counter ];
//logerror("rd gv mem @%04x = %04x\n" , m_gv_io_counter , m_gv_data_r);
m_gv_io_counter = (m_gv_io_counter + 1) & GVIDEO_ADDR_MASK;
m_gv_fsm_state = GV_STAT_WAIT_DS_1;
} else {
m_gv_timer->adjust(time_mem_av);
get_out = true;
}
break;
case GV_STAT_WAIT_DS_1:
if (ds) {
m_gv_fsm_state = GV_STAT_WAIT_MEM_0;
} else {
get_out = true;
}
break;
case GV_STAT_WAIT_DS_1:
if (ds) {
m_gv_fsm_state = GV_STAT_WAIT_MEM_0;
} else {
get_out = true;
}
break;
case GV_STAT_WAIT_DS_2:
// Wait for data word to be written
if (ds) {
m_gv_fsm_state = GV_STAT_WAIT_TRIG_1;
} else {
get_out = true;
}
break;
case GV_STAT_WAIT_DS_2:
// Wait for data word to be written
if (ds) {
m_gv_fsm_state = GV_STAT_WAIT_TRIG_1;
} else {
get_out = true;
}
break;
case GV_STAT_WAIT_TRIG_1:
// Wait for trigger
if (act_trig) {
if (BIT(m_gv_cmd , 1)) {
// Clear words (101x)
m_gv_data_w = 0;
m_gv_fsm_state = GV_STAT_WAIT_MEM_1;
} else if (BIT(m_gv_cmd , 0)) {
// Write a single pixel (1001)
m_gv_fsm_state = GV_STAT_WAIT_MEM_2;
} else {
// Write words (1000)
m_gv_fsm_state = GV_STAT_WAIT_MEM_1;
}
} else {
get_out = true;
}
break;
case GV_STAT_WAIT_TRIG_1:
// Wait for trigger
if (act_trig) {
if (BIT(m_gv_cmd , 1)) {
// Clear words (101x)
m_gv_data_w = 0;
m_gv_fsm_state = GV_STAT_WAIT_MEM_1;
} else if (BIT(m_gv_cmd , 0)) {
// Write a single pixel (1001)
m_gv_fsm_state = GV_STAT_WAIT_MEM_2;
} else {
// Write words (1000)
m_gv_fsm_state = GV_STAT_WAIT_MEM_1;
}
} else {
get_out = true;
}
break;
case GV_STAT_WAIT_MEM_1:
time_mem_av = time_to_gv_mem_availability();
if (time_mem_av.is_zero()) {
// Write a full word to graphic memory
//logerror("wr gv mem @%04x = %04x\n" , m_gv_io_counter , m_gv_data_w);
m_graphic_mem[ m_gv_io_counter ] = m_gv_data_w;
m_gv_io_counter = (m_gv_io_counter + 1) & GVIDEO_ADDR_MASK;
m_gv_fsm_state = GV_STAT_WAIT_DS_2;
} else {
m_gv_timer->adjust(time_mem_av);
get_out = true;
}
break;
case GV_STAT_WAIT_MEM_1:
time_mem_av = time_to_gv_mem_availability();
if (time_mem_av.is_zero()) {
// Write a full word to graphic memory
//logerror("wr gv mem @%04x = %04x\n" , m_gv_io_counter , m_gv_data_w);
m_graphic_mem[ m_gv_io_counter ] = m_gv_data_w;
m_gv_io_counter = (m_gv_io_counter + 1) & GVIDEO_ADDR_MASK;
m_gv_fsm_state = GV_STAT_WAIT_DS_2;
} else {
m_gv_timer->adjust(time_mem_av);
get_out = true;
}
break;
case GV_STAT_WAIT_MEM_2:
time_mem_av = time_to_gv_mem_availability();
if (time_mem_av.is_zero()) {
// Write a single pixel to graphic memory
//logerror("wr gv pixel @%04x:%x = %d\n" , m_gv_io_counter , m_gv_data_w & 0xf , BIT(m_gv_data_w , 15));
UINT16 mask = 0x8000 >> (m_gv_data_w & 0xf);
if (BIT(m_gv_data_w , 15)) {
// Set pixel
m_graphic_mem[ m_gv_io_counter ] |= mask;
} else {
// Clear pixel
m_graphic_mem[ m_gv_io_counter ] &= ~mask;
}
// Not really needed
m_gv_io_counter = (m_gv_io_counter + 1) & GVIDEO_ADDR_MASK;
m_gv_fsm_state = GV_STAT_WAIT_DS_0;
} else {
m_gv_timer->adjust(time_mem_av);
get_out = true;
}
break;
case GV_STAT_WAIT_MEM_2:
time_mem_av = time_to_gv_mem_availability();
if (time_mem_av.is_zero()) {
// Write a single pixel to graphic memory
//logerror("wr gv pixel @%04x:%x = %d\n" , m_gv_io_counter , m_gv_data_w & 0xf , BIT(m_gv_data_w , 15));
UINT16 mask = 0x8000 >> (m_gv_data_w & 0xf);
if (BIT(m_gv_data_w , 15)) {
// Set pixel
m_graphic_mem[ m_gv_io_counter ] |= mask;
} else {
// Clear pixel
m_graphic_mem[ m_gv_io_counter ] &= ~mask;
}
// Not really needed
m_gv_io_counter = (m_gv_io_counter + 1) & GVIDEO_ADDR_MASK;
m_gv_fsm_state = GV_STAT_WAIT_DS_0;
} else {
m_gv_timer->adjust(time_mem_av);
get_out = true;
}
break;
default:
logerror("Invalid state reached %d\n" , m_gv_fsm_state);
m_gv_fsm_state = GV_STAT_RESET;
}
default:
logerror("Invalid state reached %d\n" , m_gv_fsm_state);
m_gv_fsm_state = GV_STAT_RESET;
}
ds = false;
trigger = false;
} while (!get_out);
ds = false;
trigger = false;
} while (!get_out);
update_graphic_bits();
update_graphic_bits();
}
void hp9845b_state::update_graphic_bits(void)
{
m_gv_ready = m_gv_fsm_state == GV_STAT_WAIT_DS_0 ||
m_gv_fsm_state == GV_STAT_WAIT_DS_1 ||
m_gv_fsm_state == GV_STAT_WAIT_DS_2;
m_gv_ready = m_gv_fsm_state == GV_STAT_WAIT_DS_0 ||
m_gv_fsm_state == GV_STAT_WAIT_DS_1 ||
m_gv_fsm_state == GV_STAT_WAIT_DS_2;
bool irq = m_gv_int_en && !m_gv_dma_en && m_gv_ready;
bool irq = m_gv_int_en && !m_gv_dma_en && m_gv_ready;
if (irq) {
BIT_SET(m_irh_pending, GVIDEO_PA - 8);
} else {
BIT_CLR(m_irh_pending, GVIDEO_PA - 8);
}
if (irq) {
BIT_SET(m_irh_pending, GVIDEO_PA - 8);
} else {
BIT_CLR(m_irh_pending, GVIDEO_PA - 8);
}
update_irq();
update_irq();
bool dmar = m_gv_ready && m_gv_dma_en;
bool dmar = m_gv_ready && m_gv_dma_en;
m_ppu->dmar_w(dmar);
m_ppu->dmar_w(dmar);
if (m_ppu->pa_r() == GVIDEO_PA) {
m_ppu->flag_w(m_gv_ready);
}
if (m_ppu->pa_r() == GVIDEO_PA) {
m_ppu->flag_w(m_gv_ready);
}
}
void hp9845b_state::graphic_video_render(unsigned video_scanline)
{
const pen_t *pen = m_palette->pens();
bool yc = (video_scanline + GVIDEO_VCNT_OFF) == (m_gv_cursor_y + 6);
bool yw;
bool blink;
const pen_t *pen = m_palette->pens();
bool yc = (video_scanline + GVIDEO_VCNT_OFF) == (m_gv_cursor_y + 6);
bool yw;
bool blink;
if (m_gv_cursor_fs) {
yw = true;
// Steady cursor
blink = true;
} else {
yw = (video_scanline + GVIDEO_VCNT_OFF) >= (m_gv_cursor_y + 2) &&
(video_scanline + GVIDEO_VCNT_OFF) <= (m_gv_cursor_y + 10);
// Blinking cursor (frame freq. / 16)
blink = BIT(m_screen->frame_number() , 3) != 0;
}
if (m_gv_cursor_fs) {
yw = true;
// Steady cursor
blink = true;
} else {
yw = (video_scanline + GVIDEO_VCNT_OFF) >= (m_gv_cursor_y + 2) &&
(video_scanline + GVIDEO_VCNT_OFF) <= (m_gv_cursor_y + 10);
// Blinking cursor (frame freq. / 16)
blink = BIT(m_screen->frame_number() , 3) != 0;
}
unsigned mem_idx = 36 * (video_scanline - GVIDEO_VBEND);
for (unsigned i = 0; i < GVIDEO_HPIXELS; i += 16) {
UINT16 word = m_graphic_mem[ mem_idx++ ];
unsigned x = i;
for (UINT16 mask = 0x8000; mask != 0; mask >>= 1) {
unsigned cnt_h = x + GVIDEO_HBEND + GVIDEO_HCNT_OFF;
bool xc = cnt_h == (m_gv_cursor_x + 6);
bool xw = m_gv_cursor_fs || (cnt_h >= (m_gv_cursor_x + 2) && cnt_h <= (m_gv_cursor_x + 10));
unsigned pixel;
if (blink && ((xw && yc) || (yw && xc && m_gv_cursor_gc))) {
// Cursor
pixel = 2;
} else {
// Normal pixel
pixel = (word & mask) != 0;
}
m_bitmap.pix32(video_scanline - GVIDEO_VBEND , x++) = pen[ pixel ];
}
}
unsigned mem_idx = 36 * (video_scanline - GVIDEO_VBEND);
for (unsigned i = 0; i < GVIDEO_HPIXELS; i += 16) {
UINT16 word = m_graphic_mem[ mem_idx++ ];
unsigned x = i;
for (UINT16 mask = 0x8000; mask != 0; mask >>= 1) {
unsigned cnt_h = x + GVIDEO_HBEND + GVIDEO_HCNT_OFF;
bool xc = cnt_h == (m_gv_cursor_x + 6);
bool xw = m_gv_cursor_fs || (cnt_h >= (m_gv_cursor_x + 2) && cnt_h <= (m_gv_cursor_x + 10));
unsigned pixel;
if (blink && ((xw && yc) || (yw && xc && m_gv_cursor_gc))) {
// Cursor
pixel = 2;
} else {
// Normal pixel
pixel = (word & mask) != 0;
}
m_bitmap.pix32(video_scanline - GVIDEO_VBEND , x++) = pen[ pixel ];
}
}
}
IRQ_CALLBACK_MEMBER(hp9845b_state::irq_callback)
{
if (irqline == HPHYBRID_IRL) {
logerror("irq ack L %02x\n" , m_irl_pending);
logerror("irq ack L %02x\n" , m_irl_pending);
return m_irl_pending;
} else {
logerror("irq ack H %02x\n" , m_irh_pending);
logerror("irq ack H %02x\n" , m_irh_pending);
return m_irh_pending;
}
}
@ -1013,10 +1013,10 @@ WRITE8_MEMBER(hp9845b_state::pa_w)
// RHS tape drive (T15)
m_ppu->status_w(m_t15->sts_r());
m_ppu->flag_w(m_t15->flg_r());
} else if (data == GVIDEO_PA) {
// Graphic video
m_ppu->status_w(1);
m_ppu->flag_w(m_gv_ready);
} else if (data == GVIDEO_PA) {
// Graphic video
m_ppu->status_w(1);
m_ppu->flag_w(m_gv_ready);
} else {
m_ppu->status_w(0);
m_ppu->flag_w(0);
@ -1035,14 +1035,14 @@ WRITE_LINE_MEMBER(hp9845b_state::t15_irq_w)
WRITE_LINE_MEMBER(hp9845b_state::t15_flg_w)
{
if (m_ppu->pa_r() == T15_PA) {
if (m_ppu->pa_r() == T15_PA) {
m_ppu->flag_w(state);
}
}
WRITE_LINE_MEMBER(hp9845b_state::t15_sts_w)
{
if (m_ppu->pa_r() == T15_PA) {
if (m_ppu->pa_r() == T15_PA) {
m_ppu->status_w(state);
}
}
@ -1082,9 +1082,9 @@ static ADDRESS_MAP_START(global_mem_map , AS_PROGRAM , 16 , hp9845b_state)
ADDRESS_MAP_UNMAP_LOW
AM_RANGE(0x000000 , 0x007fff) AM_RAM AM_SHARE("lpu_ram")
AM_RANGE(0x014000 , 0x017fff) AM_RAM AM_SHARE("ppu_ram")
AM_RANGE(0x020000 , 0x027fff) AM_RAM AM_SHARE("lpu_02_ram")
AM_RANGE(0x020000 , 0x027fff) AM_RAM AM_SHARE("lpu_02_ram")
AM_RANGE(0x030000 , 0x037fff) AM_ROM AM_REGION("lpu" , 0)
AM_RANGE(0x040000 , 0x047fff) AM_RAM AM_SHARE("lpu_04_ram")
AM_RANGE(0x040000 , 0x047fff) AM_RAM AM_SHARE("lpu_04_ram")
AM_RANGE(0x050000 , 0x057fff) AM_ROM AM_REGION("ppu" , 0)
ADDRESS_MAP_END
@ -1096,9 +1096,9 @@ static ADDRESS_MAP_START(ppu_io_map , AS_IO , 16 , hp9845b_state)
// PA = 0, IC = 3
// Keyboard status input & keyboard interrupt clear
AM_RANGE(HP_MAKE_IOADDR(0 , 3) , HP_MAKE_IOADDR(0 , 3)) AM_READWRITE(kb_status_r , kb_irq_clear_w)
// PA = 13, IC = 0..3
// Graphic video
AM_RANGE(HP_MAKE_IOADDR(GVIDEO_PA , 0) , HP_MAKE_IOADDR(GVIDEO_PA , 3)) AM_READWRITE(graphic_r , graphic_w)
// PA = 13, IC = 0..3
// Graphic video
AM_RANGE(HP_MAKE_IOADDR(GVIDEO_PA , 0) , HP_MAKE_IOADDR(GVIDEO_PA , 3)) AM_READWRITE(graphic_r , graphic_w)
// PA = 15, IC = 0..3
// Right-hand side tape drive (T15)
AM_RANGE(HP_MAKE_IOADDR(T15_PA , 0) , HP_MAKE_IOADDR(T15_PA , 3)) AM_DEVREADWRITE("t15" , hp_taco_device , reg_r , reg_w)
@ -1118,13 +1118,13 @@ static MACHINE_CONFIG_START( hp9845b, hp9845b_state )
// video hardware
MCFG_SCREEN_ADD_MONOCHROME("screen", RASTER, rgb_t::green)
MCFG_SCREEN_UPDATE_DRIVER(hp9845b_state, screen_update)
// These parameters are for alpha video
// These parameters are for alpha video
MCFG_SCREEN_RAW_PARAMS(VIDEO_PIXEL_CLOCK , VIDEO_HTOTAL , 0 , VIDEO_HBSTART , VIDEO_VTOTAL , 0 , VIDEO_ACTIVE_SCANLINES)
MCFG_SCREEN_VBLANK_DRIVER(hp9845b_state, vblank_w)
MCFG_PALETTE_ADD_MONOCHROME_HIGHLIGHT("palette")
MCFG_TIMER_DRIVER_ADD_SCANLINE("scantimer", hp9845b_state, scanline_timer, "screen", 0, 1)
MCFG_TIMER_DRIVER_ADD("gv_timer", hp9845b_state, gv_timer)
MCFG_TIMER_DRIVER_ADD("gv_timer", hp9845b_state, gv_timer)
// Actual keyboard refresh rate should be KEY_SCAN_OSCILLATOR / 128 (2560 Hz)
MCFG_TIMER_DRIVER_ADD_PERIODIC("kb_timer" , hp9845b_state , kb_scan , attotime::from_hz(100))

4
src/mame/drivers/igspoker.cpp
View File

@ -2332,9 +2332,9 @@ ROM_END
CPUs
1x Z0840006PSC-Z80 CPU (u13) - 8-bit Microprocessor - main.
1x PIC16C65A-20/P (u1) - 8bit CMOS Microcontroller (internal ROM not dumped).
1x CP82C55A (u29) - Programmable Peripheral Interface.
1x CP82C55A (u29) - Programmable Peripheral Interface.
1x YM2413 (u3) - FM Operator Type-M (OPM) - sound.
1x LM358 (u4) - Dual Operational Amplifier - sound.
1x LM358 (u4) - Dual Operational Amplifier - sound.
1x TDA2003 (u6) - Audio Amplifier - sound.
1x 24.000000 MHz oscillator (x2).

2
src/mame/drivers/itt3030.cpp
View File

@ -467,7 +467,7 @@ WRITE8_MEMBER(itt3030_state::kbd_matrix_w)
int rd_masks[8] = { 1, 2, 4, 8, 0x10, 0x20, 0x40, 0x80 };
int tmp_read;
// printf("matrix_w: %02x (col %d row %d clk %d)\n", data, m_kbdcol, m_kbdrow, (data & 0x80) ? 1 : 0);
// printf("matrix_w: %02x (col %d row %d clk %d)\n", data, m_kbdcol, m_kbdrow, (data & 0x80) ? 1 : 0);
if ((data & 0x80) && (!m_kbdclk))
{

2
src/mame/drivers/mcr68.cpp
View File

@ -1022,7 +1022,7 @@ static MACHINE_CONFIG_START( zwackery, mcr68_state )
MCFG_CPU_PROGRAM_MAP(zwackery_map)
MCFG_CPU_VBLANK_INT_DRIVER("screen", mcr68_state, mcr68_interrupt)
MCFG_WATCHDOG_ADD("watchdog")
MCFG_WATCHDOG_ADD("watchdog")
// MCFG_WATCHDOG_VBLANK_INIT("screen", 8)
MCFG_MACHINE_START_OVERRIDE(mcr68_state,zwackery)
MCFG_MACHINE_RESET_OVERRIDE(mcr68_state,zwackery)

4
src/mame/drivers/merit.cpp
View File

@ -731,8 +731,8 @@ static INPUT_PORTS_START( iowapp )
PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_POKER_HOLD1 )
PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_POKER_HOLD5 )
// PORT_MODIFY("IN1") /* Pins #57 through #51 of J3 in decending order */
// PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_UNKNOWN ) /* If HIGH triggers a "TOKEN LOW" error - Hopper releated */
// PORT_MODIFY("IN1") /* Pins #57 through #51 of J3 in decending order */
// PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_UNKNOWN ) /* If HIGH triggers a "TOKEN LOW" error - Hopper releated */
PORT_MODIFY("DSW")
PORT_DIPNAME( 0x01, 0x00, "Auto Hold" ) PORT_DIPLOCATION("SW1:1")

50
src/mame/drivers/metlfrzr.cpp
View File

@ -2,18 +2,18 @@
// copyright-holders:Angelo Salese
/****************************************
Metal Freezer (c) 1989 Seibu
Metal Freezer (c) 1989 Seibu
preliminary driver by Angelo Salese
preliminary driver by Angelo Salese
HW seems the natural evolution of Dark Mist type.
HW seems the natural evolution of Dark Mist type.
TODO:
- Video registers needs better understanding.
- Nuke legacy video code and re-do it by using tilemap system.
- sprites are ahead of 1/2 frames;
- Writes at 0xb800-0xbfff at attract mode gameplay demo transition?
- DIPs need work - Flip Screen does not function. Still playable
TODO:
- Video registers needs better understanding.
- Nuke legacy video code and re-do it by using tilemap system.
- sprites are ahead of 1/2 frames;
- Writes at 0xb800-0xbfff at attract mode gameplay demo transition?
- DIPs need work - Flip Screen does not function. Still playable
****************************************/
@ -64,12 +64,12 @@ void metlfrzr_state::video_start()
/*
- video regs format:
[0x06] ---- --x- used during title screen transition, unknown purpose
[0x06] ---- ---x
[0x15] always 0?
[0x16] always 0?
[0x17] xxxx xxxx X scrolling base value
Notice that it's currently unknown how the game is really supposed to NOT enable scrolling during gameplay.
[0x06] ---- --x- used during title screen transition, unknown purpose
[0x06] ---- ---x
[0x15] always 0?
[0x16] always 0?
[0x17] xxxx xxxx X scrolling base value
Notice that it's currently unknown how the game is really supposed to NOT enable scrolling during gameplay.
*/
void metlfrzr_state::legacy_bg_draw(bitmap_ind16 &bitmap,const rectangle &cliprect)
{
@ -107,16 +107,16 @@ void metlfrzr_state::legacy_bg_draw(bitmap_ind16 &bitmap,const rectangle &clipre
/*
sprite DMA:
0xfe00-0xffff contains buffer for data to be copied.
Sprites are currently lagging (noticeable during scrolling) therefore there must be either an automatic or manual trigger.
Sprite seems to traverse from top to bottom priority-wise, other than that format is almost 1:1 with darkmist.cpp.
0xfe00-0xffff contains buffer for data to be copied.
Sprites are currently lagging (noticeable during scrolling) therefore there must be either an automatic or manual trigger.
Sprite seems to traverse from top to bottom priority-wise, other than that format is almost 1:1 with darkmist.cpp.
sprite format:
[0] tttt tttt tile number
[1] x--- ---- if 1 sprite is disabled
[1] -ttt ---- tile bank
[1] ---- cccc palette number
[2] yyyy yyyy Y offset
[3] xxxx xxxx X offset
[0] tttt tttt tile number
[1] x--- ---- if 1 sprite is disabled
[1] -ttt ---- tile bank
[1] ---- cccc palette number
[2] yyyy yyyy Y offset
[3] xxxx xxxx X offset
*/
void metlfrzr_state::legacy_obj_draw(bitmap_ind16 &bitmap,const rectangle &cliprect)
{
@ -162,7 +162,7 @@ WRITE8_MEMBER(metlfrzr_state::output_w)
m_fg_tilebank = (data & 0x10) >> 4;
membank("bank1")->set_entry((data & 0xc) >> 2);
// popmessage("%02x",data & 3);
// popmessage("%02x",data & 3);
}
static ADDRESS_MAP_START( metlfrzr_map, AS_PROGRAM, 8, metlfrzr_state )

357
src/mame/drivers/mvme147.cpp
View File

@ -212,37 +212,37 @@ private:
required_device<scc85C30_device> m_sccterm2;
// Pointer to System ROMs needed by bootvect_r and masking RAM buffer for post reset accesses
UINT32 *m_sysrom;
UINT32 m_sysram[2];
UINT32 *m_sysrom;
UINT32 m_sysram[2];
// PCC registers
UINT8 m_genpurp_stat;
UINT8 m_genpurp_stat;
// VME chip registers
UINT8 m_vc_cntl_conf;
UINT8 m_vc_cntl_conf;
};
static ADDRESS_MAP_START (mvme147_mem, AS_PROGRAM, 32, mvme147_state)
ADDRESS_MAP_UNMAP_HIGH
AM_RANGE (0x00000000, 0x00000007) AM_ROM AM_READ (bootvect_r) /* ROM mirror just during reset */
AM_RANGE (0x00000000, 0x00000007) AM_RAM AM_WRITE (bootvect_w) /* After first write we act as RAM */
AM_RANGE (0x00000000, 0x00000007) AM_ROM AM_READ (bootvect_r) /* ROM mirror just during reset */
AM_RANGE (0x00000000, 0x00000007) AM_RAM AM_WRITE (bootvect_w) /* After first write we act as RAM */
AM_RANGE (0x00000008, 0x003fffff) AM_RAM /* 4 Mb RAM */
AM_RANGE (0xff800000, 0xff9fffff) AM_ROM AM_REGION("maincpu", 0xff800000) //AM_MIRROR(0x00780000) /* ROM/EEPROM bank 1 - 147bug */
AM_RANGE (0xffa00000, 0xffbfffff) AM_ROM AM_REGION("maincpu", 0xffa00000) //AM_MIRROR(0x00780000) /* ROM/EEPROM bank 2 - unpopulated */
/* SGS-Thompson M48T18 RAM and clock chip, only 4088 bytes used, and 8 bytes for the RTC, out of 8Kb though */
/* SGS-Thompson M48T18 RAM and clock chip, only 4088 bytes used, and 8 bytes for the RTC, out of 8Kb though */
AM_RANGE (0xfffe0000, 0xfffe0fff) AM_DEVREADWRITE8("m48t18", timekeeper_device, read, write, 0xffffffff)
//AM_RANGE (0xfffe1000, 0xfffe100f) AM_READWRITE32(pcc32_r, pcc32_w, 0xffffffff) /* PCC 32 bits registers - needs U64 cast defined to work */
//AM_RANGE (0xfffe1000, 0xfffe100f) AM_READWRITE32(pcc32_r, pcc32_w, 0xffffffff) /* PCC 32 bits registers - needs U64 cast defined to work */
AM_RANGE (0xfffe1010, 0xfffe1017) AM_READWRITE16(pcc16_r, pcc16_w, 0xffffffff) /* PCC 16 bits registers */
AM_RANGE (0xfffe1018, 0xfffe102f) AM_READWRITE8(pcc8_r, pcc8_w, 0xffffffff) /* PCC 8 bits registers */
AM_RANGE (0xfffe1018, 0xfffe102f) AM_READWRITE8(pcc8_r, pcc8_w, 0xffffffff) /* PCC 8 bits registers */
AM_RANGE (0xfffe2000, 0xfffe201b) AM_READWRITE8(vmechip_r, vmechip_w, 0x00ff00ff) /* VMEchip 8 bits registers on odd adresses */
AM_RANGE (0xfffe3000, 0xfffe3003) AM_DEVREADWRITE8("scc", scc85C30_device, ba_cd_inv_r, ba_cd_inv_w, 0xffffffff) /* Port 1&2 - Dual serial port Z80-SCC */
AM_RANGE (0xfffe3800, 0xfffe3803) AM_DEVREADWRITE8("scc2", scc85C30_device, ba_cd_inv_r, ba_cd_inv_w, 0xffffffff) /* Port 3&4 - Dual serial port Z80-SCC */
//AM_RANGE(0x100000, 0xfeffff) AM_READWRITE(vme_a24_r, vme_a24_w) /* VMEbus Rev B addresses (24 bits) - not verified */
//AM_RANGE(0xff0000, 0xffffff) AM_READWRITE(vme_a16_r, vme_a16_w) /* VMEbus Rev B addresses (16 bits) - not verified */
//AM_RANGE(0x100000, 0xfeffff) AM_READWRITE(vme_a24_r, vme_a24_w) /* VMEbus Rev B addresses (24 bits) - not verified */
//AM_RANGE(0xff0000, 0xffffff) AM_READWRITE(vme_a16_r, vme_a16_w) /* VMEbus Rev B addresses (16 bits) - not verified */
ADDRESS_MAP_END
/* Input ports */
@ -312,16 +312,15 @@ WRITE32_MEMBER (mvme147_state::pcc32_w){
#define P16_TIMER2_COUNT (P16BASE + 6)
READ16_MEMBER (mvme147_state::pcc16_r){
UINT16 ret = 0;
LOG(("Call to %s[%04x]", FUNCNAME, offset));
switch(offset)
{
case P16_TIMER1_PRELOAD - P16BASE : LOG((" -> %02x Timer 1 preload - not implemented\n", ret)); break;
case P16_TIMER1_COUNT - P16BASE : LOG((" -> %02x Timer 1 count - not implemented\n", ret)); break;
case P16_TIMER1_COUNT - P16BASE : LOG((" -> %02x Timer 1 count - not implemented\n", ret)); break;
case P16_TIMER2_PRELOAD - P16BASE : LOG((" -> %02x Timer 2 preload - not implemented\n", ret)); break;
case P16_TIMER2_COUNT - P16BASE : LOG((" -> %02x Timer 2 count - not implemented\n", ret)); break;
case P16_TIMER2_COUNT - P16BASE : LOG((" -> %02x Timer 2 count - not implemented\n", ret)); break;
default:
LOG((" -> %02x unsupported register\n", ret));
}
@ -329,145 +328,144 @@ READ16_MEMBER (mvme147_state::pcc16_r){
}
WRITE16_MEMBER (mvme147_state::pcc16_w){
LOG(("Call to %s[%04x] <- %04x - ", FUNCNAME, offset, data));
switch(offset)
{
case P16_TIMER1_PRELOAD - P16BASE : LOG(("Timer 1 preload - not implemented\n")); break;
case P16_TIMER1_COUNT - P16BASE : LOG(("Timer 1 count - not implemented\n")); break;
case P16_TIMER2_PRELOAD - P16BASE : LOG(("Timer 2 preload - not implemented\n")); break;
case P16_TIMER2_COUNT - P16BASE : LOG(("Timer 2 count - not implemented\n")); break;
default:
LOG(("Call to %s[%04x] <- %04x - ", FUNCNAME, offset, data));
switch(offset)
{
case P16_TIMER1_PRELOAD - P16BASE : LOG(("Timer 1 preload - not implemented\n")); break;
case P16_TIMER1_COUNT - P16BASE : LOG(("Timer 1 count - not implemented\n")); break;
case P16_TIMER2_PRELOAD - P16BASE : LOG(("Timer 2 preload - not implemented\n")); break;
case P16_TIMER2_COUNT - P16BASE : LOG(("Timer 2 count - not implemented\n")); break;
default:
LOG(("unsupported register\n"));
}
}
}
#define P8BASE 0xfffe1018
#define P8_TIMER1_INT_CNTL 0xfffe1018
#define P8_TIMER1_CNTL 0xfffe1019
#define P8_TIMER1_CNTL 0xfffe1019
#define P8_TIMER2_INT_CNTL 0xfffe101A
#define P8_TIMER2_CNTL 0xfffe101B
#define P8_TIMER2_CNTL 0xfffe101B
#define P8_ACFAIL_INT_CNTL 0xfffe101C
#define P8_WDOG_TIMER_CNTL 0xfffe101D
#define P8_PRINTER_INT_CNTL 0xfffe101E
#define P8_PRINTER_CNTL 0xfffe101F
#define P8_DMA_INT_CNTL 0xfffe1020
#define P8_PRINTER_CNTL 0xfffe101F
#define P8_DMA_INT_CNTL 0xfffe1020
#define P8_DMA_CNTL_STAT 0xfffe1021
#define P8_BUSERR_CNTL 0xfffe1022
#define P8_DMA_STATUS 0xfffe1023
#define P8_BUSERR_CNTL 0xfffe1022
#define P8_DMA_STATUS 0xfffe1023
#define P8_ABORT_INT_CNTL 0xfffe1024
#define P8_TABADD_FC_CNTL 0xfffe1025
#define P8_SERIAL_INT_CNTL 0xfffe1026
#define P8_GEN_PURP_CNTL 0xfffe1027
#define P8_LAN_INT_CNTL 0xfffe1028
#define P8_LAN_INT_CNTL 0xfffe1028
#define P8_GEN_PURP_STAT 0xfffe1029
#define P8_SCSI_INT_CNTL 0xfffe102A
#define P8_SLAVE_BASE_ADDR 0xfffe102B
#define P8_SWI_1_CNTL 0xfffe102C
#define P8_SWI_1_CNTL 0xfffe102C
#define P8_INT_VECT_BASE 0xfffe102D
#define P8_SWI_2_CNTL 0xfffe102E
#define P8_SWI_2_CNTL 0xfffe102E
#define P8_REVISION_LEVEL 0xfffe102F
#define P8_PRINTER_DATA 0xfffe2800
#define P8_PRINTER_DATA 0xfffe2800
#define P8_PRINTER_STATUS 0xfffe2800
READ8_MEMBER (mvme147_state::pcc8_r){
UINT8 ret = 0;
LOG(("Call to %s[%04x] ", FUNCNAME, offset));
LOG(("Call to %s[%04x] ", FUNCNAME, offset));
switch(offset + P8BASE)
{
case P8_TIMER1_INT_CNTL : LOG((" -> %02x - Timer 1 Interrupt Control - not implemented\n", ret)); break;
case P8_TIMER1_CNTL : LOG((" -> %02x - Timer 1 Control - not implemented\n", ret)); break;
case P8_TIMER2_INT_CNTL : LOG((" -> %02x - Timer 2 Interrupt Control - not implemented\n", ret)); break;
case P8_TIMER2_CNTL : LOG((" -> %02x - Timer 2 Control - not implemented\n", ret)); break;
case P8_ACFAIL_INT_CNTL : LOG((" -> %02x - AC Fail Interrupt Control Register - not implemented\n", ret)); break;
case P8_WDOG_TIMER_CNTL : LOG((" -> %02x - Watchdog Timer Control Register - not implemented\n", ret)); break;
case P8_TIMER1_INT_CNTL : LOG((" -> %02x - Timer 1 Interrupt Control - not implemented\n", ret)); break;
case P8_TIMER1_CNTL : LOG((" -> %02x - Timer 1 Control - not implemented\n", ret)); break;
case P8_TIMER2_INT_CNTL : LOG((" -> %02x - Timer 2 Interrupt Control - not implemented\n", ret)); break;
case P8_TIMER2_CNTL : LOG((" -> %02x - Timer 2 Control - not implemented\n", ret)); break;
case P8_ACFAIL_INT_CNTL : LOG((" -> %02x - AC Fail Interrupt Control Register - not implemented\n", ret)); break;
case P8_WDOG_TIMER_CNTL : LOG((" -> %02x - Watchdog Timer Control Register - not implemented\n", ret)); break;
case P8_PRINTER_INT_CNTL : LOG((" -> %02x - Printer Interrupt Control Register - not implemented\n", ret)); break;
case P8_PRINTER_CNTL : LOG((" -> %02x - Printer Control Register - not implemented\n", ret)); break;
case P8_DMA_INT_CNTL : LOG((" -> %02x - DMA Interrupt Control Register - not implemented\n", ret)); break;
case P8_DMA_CNTL_STAT : LOG((" -> %02x - DMA Control and Status Register - not implemented\n", ret)); break;
case P8_BUSERR_CNTL : LOG((" -> %02x - Bus Error Interrupt Control Register - not implemented\n", ret)); break;
case P8_DMA_STATUS : LOG((" -> %02x - DMA Status Register - not implemented\n", ret)); break;
case P8_ABORT_INT_CNTL : LOG((" -> %02x - Abort Interrupt Control Register - not fully implemented\n", ret));
/* Bit 3 When this bit is high, the interrupt is enabled. The interrupt is disabled when this bit is low. This bit is cleared by reset.
Bit 6 This bit indicates the current state of the ABORT switch. When this bit is low, the ABORT switch is not pressed. When this bit is
case P8_PRINTER_CNTL : LOG((" -> %02x - Printer Control Register - not implemented\n", ret)); break;
case P8_DMA_INT_CNTL : LOG((" -> %02x - DMA Interrupt Control Register - not implemented\n", ret)); break;
case P8_DMA_CNTL_STAT : LOG((" -> %02x - DMA Control and Status Register - not implemented\n", ret)); break;
case P8_BUSERR_CNTL : LOG((" -> %02x - Bus Error Interrupt Control Register - not implemented\n", ret)); break;
case P8_DMA_STATUS : LOG((" -> %02x - DMA Status Register - not implemented\n", ret)); break;
case P8_ABORT_INT_CNTL : LOG((" -> %02x - Abort Interrupt Control Register - not fully implemented\n", ret));
/* Bit 3 When this bit is high, the interrupt is enabled. The interrupt is disabled when this bit is low. This bit is cleared by reset.
Bit 6 This bit indicates the current state of the ABORT switch. When this bit is low, the ABORT switch is not pressed. When this bit is
high, the ABORT switch is pressed.
Bit 7 When this bit is high, an abort interrupt is being generated at Level 7. This bit is edge sensitive and it is set on the leading
Bit 7 When this bit is high, an abort interrupt is being generated at Level 7. This bit is edge sensitive and it is set on the leading
edge of interrupt enable and abort. This bit is cleared when a 1 is written to it or when the interrupt is disabled. When cleared,
it remains cleared until the next leading edge of interrupt enable and abort. This bit is cleared by reset. */
ret = 0; /* Always return reset values for now */
break;
case P8_TABADD_FC_CNTL : LOG((" -> %02x - Table Address Function Code Register - not implemented\n", ret)); break;
case P8_SERIAL_INT_CNTL : LOG((" -> %02x - Serial Port Interrupt Control Register - not implemented\n", ret)); break;
case P8_GEN_PURP_CNTL : LOG((" -> %02x - General Purpose Control Register - not implemented\n", ret)); break;
case P8_LAN_INT_CNTL : LOG((" -> %02x - LAN Interrupt Control Register - not implemented\n", ret)); break;
case P8_GEN_PURP_STAT : LOG((" -> %02x - General Purpose Status Register\n", ret));
case P8_TABADD_FC_CNTL : LOG((" -> %02x - Table Address Function Code Register - not implemented\n", ret)); break;
case P8_SERIAL_INT_CNTL : LOG((" -> %02x - Serial Port Interrupt Control Register - not implemented\n", ret)); break;
case P8_GEN_PURP_CNTL : LOG((" -> %02x - General Purpose Control Register - not implemented\n", ret)); break;
case P8_LAN_INT_CNTL : LOG((" -> %02x - LAN Interrupt Control Register - not implemented\n", ret)); break;
case P8_GEN_PURP_STAT : LOG((" -> %02x - General Purpose Status Register\n", ret));
ret = m_genpurp_stat;
break;
case P8_SCSI_INT_CNTL : LOG((" -> %02x - SCSI Port Interrupt Control Register - not implemented\n", ret)); break;
case P8_SLAVE_BASE_ADDR : LOG((" -> %02x - Slave Base Address Register - not implemented\n", ret)); break;
case P8_SWI_1_CNTL : LOG((" -> %02x - Software Interrupt 1 Control Register - not implemented\n", ret)); break;
case P8_INT_VECT_BASE : LOG((" -> %02x - Interrupt Vector Base - not implemented\n", ret)); break;
case P8_SWI_2_CNTL : LOG((" -> %02x - Software Interrupt 2 Control Register - not implemented\n", ret)); break;
case P8_REVISION_LEVEL : LOG((" -> %02x - PCC Revision Level Register - not implemented\n", ret)); break;
case P8_PRINTER_STATUS : LOG((" -> %02x - Printer Status Register - not implemented\n", ret)); break;
case P8_SCSI_INT_CNTL : LOG((" -> %02x - SCSI Port Interrupt Control Register - not implemented\n", ret)); break;
case P8_SLAVE_BASE_ADDR : LOG((" -> %02x - Slave Base Address Register - not implemented\n", ret)); break;
case P8_SWI_1_CNTL : LOG((" -> %02x - Software Interrupt 1 Control Register - not implemented\n", ret)); break;
case P8_INT_VECT_BASE : LOG((" -> %02x - Interrupt Vector Base - not implemented\n", ret)); break;
case P8_SWI_2_CNTL : LOG((" -> %02x - Software Interrupt 2 Control Register - not implemented\n", ret)); break;
case P8_REVISION_LEVEL : LOG((" -> %02x - PCC Revision Level Register - not implemented\n", ret)); break;
case P8_PRINTER_STATUS : LOG((" -> %02x - Printer Status Register - not implemented\n", ret)); break;
default:
LOG((" -> %02x - unsupported register\n", ret));
LOG((" -> %02x - unsupported register\n", ret));
}
return ret;
}
WRITE8_MEMBER (mvme147_state::pcc8_w){
LOG(("Call to %s[%04x] <- %02x - ", FUNCNAME, offset, data));
LOG(("Call to %s[%04x] <- %02x - ", FUNCNAME, offset, data));
switch(offset + P8BASE)
{
case P8_TIMER1_INT_CNTL : LOG(("Timer 1 Interrupt Control - not implemented\n")); break;
case P8_TIMER1_CNTL : LOG(("Timer 1 Control - not implemented\n")); break;
case P8_TIMER2_INT_CNTL : LOG(("Timer 2 Interrupt Control - not implemented\n")); break;
case P8_TIMER2_CNTL : LOG(("Timer 2 Control - not implemented\n")); break;
case P8_ACFAIL_INT_CNTL : LOG(("AC Fail Interrupt Control Register - not implemented\n")); break;
case P8_WDOG_TIMER_CNTL : LOG(("Watchdog Timer Control Register - not implemented\n")); break;
case P8_TIMER1_INT_CNTL : LOG(("Timer 1 Interrupt Control - not implemented\n")); break;
case P8_TIMER1_CNTL : LOG(("Timer 1 Control - not implemented\n")); break;
case P8_TIMER2_INT_CNTL : LOG(("Timer 2 Interrupt Control - not implemented\n")); break;
case P8_TIMER2_CNTL : LOG(("Timer 2 Control - not implemented\n")); break;
case P8_ACFAIL_INT_CNTL : LOG(("AC Fail Interrupt Control Register - not implemented\n")); break;
case P8_WDOG_TIMER_CNTL : LOG(("Watchdog Timer Control Register - not implemented\n")); break;
case P8_PRINTER_INT_CNTL : LOG(("Printer Interrupt Control Register - not implemented\n")); break;
case P8_PRINTER_CNTL : LOG(("Printer Control Register - not implemented\n")); break;
case P8_DMA_INT_CNTL : LOG(("DMA Interrupt Control Register - not implemented\n")); break;
case P8_DMA_CNTL_STAT : LOG(("DMA Control and Status Register - not implemented\n")); break;
case P8_BUSERR_CNTL : LOG(("Bus Error Interrupt Control Register - not implemented\n")); break;
case P8_DMA_STATUS : LOG(("DMA Status Register - not implemented\n")); break;
case P8_ABORT_INT_CNTL : LOG(("Abort Interrupt Control Register - not implemented\n")); break;
case P8_TABADD_FC_CNTL : LOG(("Table Address Function Code Register - not implemented\n")); break;
case P8_SERIAL_INT_CNTL : LOG(("Serial Port Interrupt Control Register - not implemented\n")); break;
case P8_GEN_PURP_CNTL : LOG(("General Purpose Control Register - not implemented\n"));
/*Bits 0-1 These bits control local RAM parity checking. These bits should not be enabled on the MVME147-010.
case P8_PRINTER_CNTL : LOG(("Printer Control Register - not implemented\n")); break;
case P8_DMA_INT_CNTL : LOG(("DMA Interrupt Control Register - not implemented\n")); break;
case P8_DMA_CNTL_STAT : LOG(("DMA Control and Status Register - not implemented\n")); break;
case P8_BUSERR_CNTL : LOG(("Bus Error Interrupt Control Register - not implemented\n")); break;
case P8_DMA_STATUS : LOG(("DMA Status Register - not implemented\n")); break;
case P8_ABORT_INT_CNTL : LOG(("Abort Interrupt Control Register - not implemented\n")); break;
case P8_TABADD_FC_CNTL : LOG(("Table Address Function Code Register - not implemented\n")); break;
case P8_SERIAL_INT_CNTL : LOG(("Serial Port Interrupt Control Register - not implemented\n")); break;
case P8_GEN_PURP_CNTL : LOG(("General Purpose Control Register - not implemented\n"));
/*Bits 0-1 These bits control local RAM parity checking. These bits should not be enabled on the MVME147-010.
These bits are cleared by reset. x0 = parity disabled, x1 = parity enabled
Bit 2 This bit is used to test the parity generating and checking logic. When this bit is low, correct parity is written to the DRAM;
Bit 2 This bit is used to test the parity generating and checking logic. When this bit is low, correct parity is written to the DRAM;
when high, incorrect parity is written to the DRAM. This bit is cleared by reset.
NOTE: We really don't care about DRAM parity!
Bit 3 When set, this bit is used to enable the local bus timer that is part of the PCC. Because the VMEchip also contains a local bus
NOTE: We really don't care about DRAM parity!
Bit 3 When set, this bit is used to enable the local bus timer that is part of the PCC. Because the VMEchip also contains a local bus
timer, this bit should be cleared, turning off the PCC local bus timer. This bit is cleared by reset.
Bit 4 This bit is the master interrupt enable. When this bit is low, all interrupts on the MVME147 are disabled; when high, all
Bit 4 This bit is the master interrupt enable. When this bit is low, all interrupts on the MVME147 are disabled; when high, all
interrupts are enabled. This bit is cleared by reset
Bits 5-7 When the pattern %101 is written to these bits, the front panel RESET switch is disabled. The RESET switch is enabled for any
Bits 5-7 When the pattern %101 is written to these bits, the front panel RESET switch is disabled. The RESET switch is enabled for any
other pattern. These bits are cleared by reset.
TODO: Bit 4-7 needs to be implemented
*/
TODO: Bit 4-7 needs to be implemented
*/
break;
case P8_LAN_INT_CNTL : LOG(("LAN Interrupt Control Register - not implemented\n")); break;
case P8_GEN_PURP_STAT : LOG(("General Purpose Status Register\n"));
/* Bit 0 This bit is set when a parity error occurs while the local processor is accessing RAM. This bit is cleared by writing a 1 to it.
case P8_LAN_INT_CNTL : LOG(("LAN Interrupt Control Register - not implemented\n")); break;
case P8_GEN_PURP_STAT : LOG(("General Purpose Status Register\n"));
/* Bit 0 This bit is set when a parity error occurs while the local processor is accessing RAM. This bit is cleared by writing a 1 to it.
This bit is cleared by reset.
Bit 1 This bit is set when a power-up reset occurs. It is cleared by writing a 1 to it.
Bit 1 This bit is set when a power-up reset occurs. It is cleared by writing a 1 to it.
When the MVME147BUG is installed, its initialization code clears this bit.
*/
*/
m_genpurp_stat &= ((data & 1) ? ~1 : 0xff); // Check if parity error bit needs to be cleared
m_genpurp_stat &= ((data & 2) ? ~2 : 0xff); // Check if power up reset bit needs to be cleared
break;
case P8_SCSI_INT_CNTL : LOG(("SCSI Port Interrupt Control Register - not implemented\n")); break;
case P8_SLAVE_BASE_ADDR : LOG(("Slave Base Address Register - not implemented\n")); break;
case P8_SWI_1_CNTL : LOG(("Software Interrupt 1 Control Register - not implemented\n")); break;
case P8_INT_VECT_BASE : LOG(("Interrupt Vector Base - not implemented\n")); break;
case P8_SWI_2_CNTL : LOG(("Software Interrupt 2 Control Register - not implemented\n")); break;
case P8_REVISION_LEVEL : LOG(("PCC Revision Level Register - not implemented\n")); break;
case P8_PRINTER_DATA : LOG(("Printer Data Register - not implemented\n")); break;
case P8_SCSI_INT_CNTL : LOG(("SCSI Port Interrupt Control Register - not implemented\n")); break;
case P8_SLAVE_BASE_ADDR : LOG(("Slave Base Address Register - not implemented\n")); break;
case P8_SWI_1_CNTL : LOG(("Software Interrupt 1 Control Register - not implemented\n")); break;
case P8_INT_VECT_BASE : LOG(("Interrupt Vector Base - not implemented\n")); break;
case P8_SWI_2_CNTL : LOG(("Software Interrupt 2 Control Register - not implemented\n")); break;
case P8_REVISION_LEVEL : LOG(("PCC Revision Level Register - not implemented\n")); break;
case P8_PRINTER_DATA : LOG(("Printer Data Register - not implemented\n")); break;
default:
LOG(("unsupported register\n"));
}
@ -479,129 +477,128 @@ WRITE8_MEMBER (mvme147_state::pcc8_w){
#define VCBASE 0xfffe2001
#define VC_SYS_CNTL_CONF 0xfffe2001
#define VC_VMEBUS_REQ_CONF 0xfffe2003
#define VC_MASTER_CONF 0xfffe2005
#define VC_SLAVE_CONF 0xfffe2007
#define VC_TIMER_CONF 0xfffe2009
#define VC_MASTER_CONF 0xfffe2005
#define VC_SLAVE_CONF 0xfffe2007
#define VC_TIMER_CONF 0xfffe2009
#define VC_SLAVE_ADR_MOD 0xfffe200B
#define VC_MASTER_ADR_MOD 0xfffe200D
#define VC_INT_HNDL_MASK 0xfffe200F
#define VC_UTIL_INT_MASK 0xfffe2011
#define VC_UTIL_INT_VECT 0xfffe2013
#define VC_INT_REQUEST 0xfffe2015
#define VC_INT_REQUEST 0xfffe2015
#define VC_VMEBUS_STAT_ID 0xfffe2017
#define VC_BUS_ERR_STATUS 0xfffe2019
#define VC_GCSR_BASE_ADR 0xfffe201B
READ8_MEMBER (mvme147_state::vmechip_r){
UINT8 ret = 0;
LOG(("Call to %s[%04x] ", FUNCNAME, offset));
LOG(("Call to %s[%04x] ", FUNCNAME, offset));
switch(offset * 2 + VCBASE)
{
case VC_SYS_CNTL_CONF :
case VC_SYS_CNTL_CONF :
LOG((" -> %02x - System Controller Configuration Register - not implemented\n", ret));
ret = m_vc_cntl_conf;
break;
case VC_VMEBUS_REQ_CONF :
/*
Bits 0-1 These control bits configure the VMEbus requester level as shown in the table below:
case VC_VMEBUS_REQ_CONF :
/*
Bits 0-1 These control bits configure the VMEbus requester level as shown in the table below:
RQLEV1 RQLEV0 Level
0 0 0
0 1 1
1 0 2
1 1 3
These bits are set to 1, 1 by any reset. Note that writes to REQLEV1,0 do not change the actual
requester level until the MVME147 goes through the action of having VMEbus mastership and releasing it. This means that
there are times when the value written into REQLEV1,0 do not match the current requester level (the request level is lagging).
During such times, reads to REQLEV1,0 reflect the actual requester level, not the value written into REQLEV1,0.
Bit 3 Setting this bit to 1 prevents the requester from releasing the VMEbus. However, unlike the DWB control bit, setting the
RNEVER bit does not cause the requester to request the VMEbus. Clearing the RNEVER bit allows the requester to
relinquish the VMEbus in accordance with the other control bits of the requester configuration register.
This bit is cleared by any reset.
Bit 4 The RWD bit allows software to configure the requester release mode. When the bit is set, if RNEVER and DWB are both
cleared to 0, the requester releases the VMEbus after the MC68030 completes a VMEbus cycle. When the bit is cleared, if
RNEVER and DWB are both cleared to 0, the requester operates in the Release-On-Request (ROR) mode. After acquiring control
of the VMEbus, it maintains control until it detects another request pending on the VMEbus. This bit is cleared by any reset.
Bit 5 The RONR bit controls the manner in which the VMEchip requests the VMEbus. When the bit is set; anytime the
MVME147 has bus mastership, then gives it up, the VMEchip does not request the VMEbus again until it detects the bus
request signal BR*, on its level, negated for at least 150 ns. When the VMEchip detects BR* negated, it refrains from
driving it again for at least 200 ns. This bit is cleared by any reset.
Bit 6 The DHB status bit is 1 when the MVME147 is VMEbus master and 0 when it is not.
Bit 7 Setting the DWB control bit to 1 causes the VMEchip to request the VMEbus (if not already bus master). When VMEbus
mastership has been obtained, it is not relinquished until after the DWB and RNEVER bits are both cleared.
This bit is cleared by any reset.
*/
0 0 0
0 1 1
1 0 2
1 1 3
These bits are set to 1, 1 by any reset. Note that writes to REQLEV1,0 do not change the actual
requester level until the MVME147 goes through the action of having VMEbus mastership and releasing it. This means that
there are times when the value written into REQLEV1,0 do not match the current requester level (the request level is lagging).
During such times, reads to REQLEV1,0 reflect the actual requester level, not the value written into REQLEV1,0.
Bit 3 Setting this bit to 1 prevents the requester from releasing the VMEbus. However, unlike the DWB control bit, setting the
RNEVER bit does not cause the requester to request the VMEbus. Clearing the RNEVER bit allows the requester to
relinquish the VMEbus in accordance with the other control bits of the requester configuration register.
This bit is cleared by any reset.
Bit 4 The RWD bit allows software to configure the requester release mode. When the bit is set, if RNEVER and DWB are both
cleared to 0, the requester releases the VMEbus after the MC68030 completes a VMEbus cycle. When the bit is cleared, if
RNEVER and DWB are both cleared to 0, the requester operates in the Release-On-Request (ROR) mode. After acquiring control
of the VMEbus, it maintains control until it detects another request pending on the VMEbus. This bit is cleared by any reset.
Bit 5 The RONR bit controls the manner in which the VMEchip requests the VMEbus. When the bit is set; anytime the
MVME147 has bus mastership, then gives it up, the VMEchip does not request the VMEbus again until it detects the bus
request signal BR*, on its level, negated for at least 150 ns. When the VMEchip detects BR* negated, it refrains from
driving it again for at least 200 ns. This bit is cleared by any reset.
Bit 6 The DHB status bit is 1 when the MVME147 is VMEbus master and 0 when it is not.
Bit 7 Setting the DWB control bit to 1 causes the VMEchip to request the VMEbus (if not already bus master). When VMEbus
mastership has been obtained, it is not relinquished until after the DWB and RNEVER bits are both cleared.
This bit is cleared by any reset.
*/
ret = 1 << 6; /* Let BUG147 think we are bus master. TODO: Implement proper VME bus signalling */
LOG((" -> %02x - VMEbus Requester Configuration Register - not implemented\n", ret));
break;
case VC_MASTER_CONF : LOG((" -> %02x - Master Configuration Register - not implemented\n", ret)); break;
case VC_SLAVE_CONF : LOG((" -> %02x - Slave Configuration Register - not implemented\n", ret)); break;
case VC_TIMER_CONF : LOG((" -> %02x - Timer Configuration Register - not implemented\n", ret));
/*Bits 0-1 These two bits configure the local time-out period. They are set to 1 by any reset.
case VC_MASTER_CONF : LOG((" -> %02x - Master Configuration Register - not implemented\n", ret)); break;
case VC_SLAVE_CONF : LOG((" -> %02x - Slave Configuration Register - not implemented\n", ret)); break;
case VC_TIMER_CONF : LOG((" -> %02x - Timer Configuration Register - not implemented\n", ret));
/*Bits 0-1 These two bits configure the local time-out period. They are set to 1 by any reset.
LBTO1 LBTO0 Time-Out Period
0 0 102 microseconds
0 1 205 microseconds
1 0 410 microseconds
1 1 Timer disabled
0 0 102 microseconds
0 1 205 microseconds
1 0 410 microseconds
1 1 Timer disabled
The local bus timer activates bus error to the MC68030 when it tries to access nonexistent locations in the local memory map
Bits 2-3 These two bits configure the VMEbus access time-out period. They are set to 1 by any reset.
Bits 2-3 These two bits configure the VMEbus access time-out period. They are set to 1 by any reset.
ACTO1 ACTO0 Time-Out Period
0 0 102 microseconds
0 1 1.6 millisecond
1 0 51 milliseconds
1 1 Timer disabled
0 0 102 microseconds
0 1 1.6 millisecond
1 0 51 milliseconds
1 1 Timer disabled
The VMEbus access timer activates bus error to the MC68030 (except on write posted time-outs) when the VMEchip is
unsuccessful in obtaining the VMEbus within the time-out period
Bits 4-5 These two bits configure the VMEbus global time-out period. VBTO1 is set to 1 and VBTO0 is cleared to 0 by SYSRESET.
Bits 4-5 These two bits configure the VMEbus global time-out period. VBTO1 is set to 1 and VBTO0 is cleared to 0 by SYSRESET.
VBTO1 VBTO0 Time-Out Period
0 0 102 microseconds
0 1 205 microseconds
1 0 410 microseconds
1 1 Timer disabled
0 0 102 microseconds
0 1 205 microseconds
1 0 410 microseconds
1 1 Timer disabled
The VMEbus global timer activates BERR* on the VMEbus.
Bit 6 Setting ARBTO to 1 enables the VMEbus arbitration timer. The VMEbus arbitration timer activates BBSY* if it is not activated
within 410 µs after the MVME147 arbiter issues a bus grant. The timer deactivates BBSY* as specified in the VMEbus specification.
Bit 6 Setting ARBTO to 1 enables the VMEbus arbitration timer. The VMEbus arbitration timer activates BBSY* if it is not activated
within 410 us after the MVME147 arbiter issues a bus grant. The timer deactivates BBSY* as specified in the VMEbus specification.
This causes the arbiter to arbitrate any pending requests for the bus. This bit is set to 1 by SYSRESET.
*/
*/
break;
case VC_SLAVE_ADR_MOD : LOG((" -> %02x - Slave Address Modifier Register - not implemented\n", ret)); break;
case VC_MASTER_ADR_MOD : LOG((" -> %02x - Master Address Modifier Register - not implemented\n", ret)); break;
case VC_INT_HNDL_MASK : LOG((" -> %02x - Interrupt Handler Mask Register - not implemented\n", ret)); break;
case VC_UTIL_INT_MASK : LOG((" -> %02x - Utility Interrupt Mask Register - not implemented\n", ret)); break;
case VC_UTIL_INT_VECT : LOG((" -> %02x - Utility Interrupt Vector Register - not implemented\n", ret)); break;
case VC_INT_REQUEST : LOG((" -> %02x - Interrupt Request Register - not implemented\n", ret)); break;
case VC_VMEBUS_STAT_ID : LOG((" -> %02x - VMEbus Status/ID Register - not implemented\n", ret)); break;
case VC_BUS_ERR_STATUS : LOG((" -> %02x - Bus Error Status Register - not implemented\n", ret)); break;
case VC_GCSR_BASE_ADR : LOG((" -> %02x - GCSR Base Address Configuration Register - not implemented\n", ret)); break;
case VC_SLAVE_ADR_MOD : LOG((" -> %02x - Slave Address Modifier Register - not implemented\n", ret)); break;
case VC_MASTER_ADR_MOD : LOG((" -> %02x - Master Address Modifier Register - not implemented\n", ret)); break;
case VC_INT_HNDL_MASK : LOG((" -> %02x - Interrupt Handler Mask Register - not implemented\n", ret)); break;
case VC_UTIL_INT_MASK : LOG((" -> %02x - Utility Interrupt Mask Register - not implemented\n", ret)); break;
case VC_UTIL_INT_VECT : LOG((" -> %02x - Utility Interrupt Vector Register - not implemented\n", ret)); break;
case VC_INT_REQUEST : LOG((" -> %02x - Interrupt Request Register - not implemented\n", ret)); break;
case VC_VMEBUS_STAT_ID : LOG((" -> %02x - VMEbus Status/ID Register - not implemented\n", ret)); break;
case VC_BUS_ERR_STATUS : LOG((" -> %02x - Bus Error Status Register - not implemented\n", ret)); break;
case VC_GCSR_BASE_ADR : LOG((" -> %02x - GCSR Base Address Configuration Register - not implemented\n", ret)); break;
default:
LOG(("unsupported register"));
}
return ret;
}
return ret;
}
WRITE8_MEMBER (mvme147_state::vmechip_w){
LOG(("Call to %s[%04x] <- %02x - ", FUNCNAME, offset, data));
switch(offset * 2 + VCBASE)
{
case VC_SYS_CNTL_CONF :
case VC_SYS_CNTL_CONF :
LOG(("System Controller Configuration Register - not implemented\n"));
m_vc_cntl_conf = data & 0xff;
break;
case VC_VMEBUS_REQ_CONF : LOG(("VMEbus Requester Configuration Register - not implemented\n")); break;
case VC_MASTER_CONF : LOG(("Master Configuration Register - not implemented\n")); break;
case VC_SLAVE_CONF : LOG(("Slave Configuration Register - not implemented\n")); break;
case VC_TIMER_CONF : LOG(("Timer Configuration Register - not implemented\n")); break;
case VC_SLAVE_ADR_MOD : LOG(("Slave Address Modifier Register - not implemented\n")); break;
case VC_MASTER_ADR_MOD : LOG(("Master Address Modifier Register - not implemented\n")); break;
case VC_INT_HNDL_MASK : LOG(("Interrupt Handler Mask Register - not implemented\n")); break;
case VC_UTIL_INT_MASK : LOG(("Utility Interrupt Mask Register - not implemented\n")); break;
case VC_UTIL_INT_VECT : LOG(("Utility Interrupt Vector Register - not implemented\n")); break;
case VC_INT_REQUEST : LOG(("Interrupt Request Register - not implemented\n")); break;
case VC_VMEBUS_STAT_ID : LOG(("VMEbus Status/ID Register - not implemented\n")); break;
case VC_BUS_ERR_STATUS : LOG(("Bus Error Status Register - not implemented\n")); break;
case VC_GCSR_BASE_ADR : LOG(("GCSR Base Address Configuration Register - not implemented\n")); break;
case VC_VMEBUS_REQ_CONF : LOG(("VMEbus Requester Configuration Register - not implemented\n")); break;
case VC_MASTER_CONF : LOG(("Master Configuration Register - not implemented\n")); break;
case VC_SLAVE_CONF : LOG(("Slave Configuration Register - not implemented\n")); break;
case VC_TIMER_CONF : LOG(("Timer Configuration Register - not implemented\n")); break;
case VC_SLAVE_ADR_MOD : LOG(("Slave Address Modifier Register - not implemented\n")); break;
case VC_MASTER_ADR_MOD : LOG(("Master Address Modifier Register - not implemented\n")); break;
case VC_INT_HNDL_MASK : LOG(("Interrupt Handler Mask Register - not implemented\n")); break;
case VC_UTIL_INT_MASK : LOG(("Utility Interrupt Mask Register - not implemented\n")); break;
case VC_UTIL_INT_VECT : LOG(("Utility Interrupt Vector Register - not implemented\n")); break;
case VC_INT_REQUEST : LOG(("Interrupt Request Register - not implemented\n")); break;
case VC_VMEBUS_STAT_ID : LOG(("VMEbus Status/ID Register - not implemented\n")); break;
case VC_BUS_ERR_STATUS : LOG(("Bus Error Status Register - not implemented\n")); break;
case VC_GCSR_BASE_ADR : LOG(("GCSR Base Address Configuration Register - not implemented\n")); break;
default:
LOG(("unsupported register\n"));
}

23
src/mame/drivers/neogeo.cpp
View File

@ -452,7 +452,7 @@
****************************************************************************
AES driver (home version of MVS)
AES driver (home version of MVS)
Current emulation status:
- Cartridges run.
- Riding Hero runs in slow-mo due to the unemulated comm link MCU in the cartridge.
@ -1129,7 +1129,7 @@ void neogeo_state::init_ym()
if (m_slots[m_curr_slot] && m_slots[m_curr_slot]->get_ymdelta_size())
{
ROM = m_slots[m_curr_slot]->get_ymdelta_base();
len = m_slots[m_curr_slot]->get_ymdelta_size();
len = m_slots[m_curr_slot]->get_ymdelta_size();
machine().memory().region_alloc(":ymsnd.deltat", len, 1, ENDIANNESS_LITTLE);
memcpy(memregion(":ymsnd.deltat")->base(), ROM, len);
}
@ -1700,23 +1700,23 @@ MACHINE_CONFIG_END
// two cartslots (MV-2F)
#define NEOGEO_CONFIG_TWO_CARTSLOTS \
NEOGEO_CONFIG_CARTSLOT("cslot1") \
NEOGEO_CONFIG_CARTSLOT("cslot1") \
NEOGEO_CONFIG_CARTSLOT("cslot2")
// four cartslots (MV-4F)
#define NEOGEO_CONFIG_FOUR_CARTSLOTS \
NEOGEO_CONFIG_CARTSLOT("cslot1") \
NEOGEO_CONFIG_CARTSLOT("cslot2") \
NEOGEO_CONFIG_CARTSLOT("cslot3") \
NEOGEO_CONFIG_CARTSLOT("cslot1") \
NEOGEO_CONFIG_CARTSLOT("cslot2") \
NEOGEO_CONFIG_CARTSLOT("cslot3") \
NEOGEO_CONFIG_CARTSLOT("cslot4")
// six cartslots (MV-6F)
#define NEOGEO_CONFIG_SIX_CARTSLOTS \
NEOGEO_CONFIG_CARTSLOT("cslot1") \
NEOGEO_CONFIG_CARTSLOT("cslot2") \
NEOGEO_CONFIG_CARTSLOT("cslot3") \
NEOGEO_CONFIG_CARTSLOT("cslot4") \
NEOGEO_CONFIG_CARTSLOT("cslot5") \
NEOGEO_CONFIG_CARTSLOT("cslot1") \
NEOGEO_CONFIG_CARTSLOT("cslot2") \
NEOGEO_CONFIG_CARTSLOT("cslot3") \
NEOGEO_CONFIG_CARTSLOT("cslot4") \
NEOGEO_CONFIG_CARTSLOT("cslot5") \
NEOGEO_CONFIG_CARTSLOT("cslot6")
@ -2036,4 +2036,3 @@ CONS( 1990, aes, 0, 0, aes, aes, driver_device, 0,
// Include standalone drivers for the single games
#include "neodriv.hxx"

3
src/mame/drivers/neopcb.cpp
View File

@ -327,7 +327,7 @@ void neopcb_state::kf2k3pcb_decrypt_s1data()
src = memregion("sprites")->base() + srom_size - 0x80000;
dst = memregion("fixed")->base() + 0x80000;
for (int i = 0; i < tx_size / 2; i++)
for (int i = 0; i < tx_size / 2; i++)
dst[i] = src[(i & ~0x1f) + ((i & 7) << 2) + ((~i & 8) >> 2) + ((i & 0x10) >> 4)];
dst = memregion("fixed")->base();
@ -513,4 +513,3 @@ GAME( 2003, ms5pcb, 0, neopcb, dualbios, neopcb_state, ms5pcb, RO
GAME( 2003, svcpcb, 0, neopcb, dualbios, neopcb_state, svcpcb, ROT0, "SNK Playmore", "SNK vs. Capcom - SVC Chaos (JAMMA PCB, set 1)", MACHINE_SUPPORTS_SAVE )
GAME( 2003, svcpcba, svcpcb, neopcb, dualbios, neopcb_state, svcpcb, ROT0, "SNK Playmore", "SNK vs. Capcom - SVC Chaos (JAMMA PCB, set 2)" , MACHINE_SUPPORTS_SAVE ) /* Encrypted Code */
GAME( 2003, kf2k3pcb, 0, neopcb, neogeo, neopcb_state, kf2k3pcb, ROT0, "SNK Playmore", "The King of Fighters 2003 (Japan, JAMMA PCB)", MACHINE_SUPPORTS_SAVE )

8
src/mame/drivers/seattle.cpp
View File

@ -2701,7 +2701,7 @@ MACHINE_CONFIG_END
static MACHINE_CONFIG_DERIVED( blitz99, seattle150 )
MCFG_DEVICE_ADD("dcs", DCS2_AUDIO_2115, 0)
MCFG_DCS2_AUDIO_DRAM_IN_MB(2)
// MCFG_DCS2_AUDIO_POLLING_OFFSET(0x0afb) -- Not in ram???
// MCFG_DCS2_AUDIO_POLLING_OFFSET(0x0afb) -- Not in ram???
MCFG_DEVICE_ADD("ioasic", MIDWAY_IOASIC, 0)
MCFG_MIDWAY_IOASIC_SHUFFLE(MIDWAY_IOASIC_BLITZ99)
@ -2713,7 +2713,7 @@ MACHINE_CONFIG_END
static MACHINE_CONFIG_DERIVED( blitz2k, seattle150 )
MCFG_DEVICE_ADD("dcs", DCS2_AUDIO_2115, 0)
MCFG_DCS2_AUDIO_DRAM_IN_MB(2)
// MCFG_DCS2_AUDIO_POLLING_OFFSET(0x0b5d) -- Not in ram???
// MCFG_DCS2_AUDIO_POLLING_OFFSET(0x0b5d) -- Not in ram???
MCFG_DEVICE_ADD("ioasic", MIDWAY_IOASIC, 0)
MCFG_MIDWAY_IOASIC_SHUFFLE(MIDWAY_IOASIC_BLITZ99)
@ -2725,7 +2725,7 @@ MACHINE_CONFIG_END
static MACHINE_CONFIG_DERIVED( carnevil, seattle150 )
MCFG_DEVICE_ADD("dcs", DCS2_AUDIO_2115, 0)
MCFG_DCS2_AUDIO_DRAM_IN_MB(2)
// MCFG_DCS2_AUDIO_POLLING_OFFSET(0x0af7) -- Not in ram???
// MCFG_DCS2_AUDIO_POLLING_OFFSET(0x0af7) -- Not in ram???
MCFG_DEVICE_ADD("ioasic", MIDWAY_IOASIC, 0)
MCFG_MIDWAY_IOASIC_SHUFFLE(MIDWAY_IOASIC_CARNEVIL)
@ -2737,7 +2737,7 @@ MACHINE_CONFIG_END
static MACHINE_CONFIG_DERIVED( hyprdriv, seattle200_widget )
MCFG_DEVICE_ADD("dcs", DCS2_AUDIO_2115, 0)
MCFG_DCS2_AUDIO_DRAM_IN_MB(2)
// MCFG_DCS2_AUDIO_POLLING_OFFSET(0x0af7) -- Not in ram???
// MCFG_DCS2_AUDIO_POLLING_OFFSET(0x0af7) -- Not in ram???
MCFG_DEVICE_ADD("ioasic", MIDWAY_IOASIC, 0)
MCFG_MIDWAY_IOASIC_SHUFFLE(MIDWAY_IOASIC_HYPRDRIV)

2
src/mame/drivers/tourvis.cpp
View File

@ -381,7 +381,7 @@ static INPUT_PORTS_START( tourvision )
PORT_DIPSETTING( 0x10, "120" )
PORT_DIPSETTING( 0x08, "90" )
PORT_DIPSETTING( 0x00, "60" )
PORT_DIPNAME( 0x80, 0x00, DEF_STR( Demo_Sounds ) )
PORT_DIPNAME( 0x80, 0x00, DEF_STR( Demo_Sounds ) )
PORT_START( "DSW2" )
PORT_DIPNAME( 0x03, 0x03, "Coins needed 2" )

8
src/mame/drivers/unixpc.cpp
View File

@ -6,11 +6,11 @@
Skeleton driver by Dirk Best and R. Belmont
DIVS instruction at 0x801112 (the second time) causes a divide-by-zero
exception the system isn't ready for due to word at 0x5EA6 being zero.
DIVS instruction at 0x801112 (the second time) causes a divide-by-zero
exception the system isn't ready for due to word at 0x5EA6 being zero.
Code might not get there if the attempted FDC boot succeeds; FDC hookup
probably needs help. 2797 isn't asserting DRQ?
Code might not get there if the attempted FDC boot succeeds; FDC hookup
probably needs help. 2797 isn't asserting DRQ?
***************************************************************************/

8
src/mame/drivers/vegas.cpp
View File

@ -2313,7 +2313,7 @@ MACHINE_CONFIG_END
static MACHINE_CONFIG_DERIVED( gauntleg, vegas )
MCFG_DEVICE_ADD("dcs", DCS2_AUDIO_2104, 0)
MCFG_DCS2_AUDIO_DRAM_IN_MB(4)
// MCFG_DCS2_AUDIO_POLLING_OFFSET(0x0b5d) -- Not in ram???
// MCFG_DCS2_AUDIO_POLLING_OFFSET(0x0b5d) -- Not in ram???
MCFG_DEVICE_ADD("ioasic", MIDWAY_IOASIC, 0)
MCFG_MIDWAY_IOASIC_SHUFFLE(MIDWAY_IOASIC_CALSPEED)
@ -2326,7 +2326,7 @@ MACHINE_CONFIG_END
static MACHINE_CONFIG_DERIVED( gauntdl, vegas )
MCFG_DEVICE_ADD("dcs", DCS2_AUDIO_2104, 0)
MCFG_DCS2_AUDIO_DRAM_IN_MB(4)
// MCFG_DCS2_AUDIO_POLLING_OFFSET(0x0b5d) -- Not in ram???
// MCFG_DCS2_AUDIO_POLLING_OFFSET(0x0b5d) -- Not in ram???
MCFG_DEVICE_ADD("ioasic", MIDWAY_IOASIC, 0)
MCFG_MIDWAY_IOASIC_SHUFFLE(MIDWAY_IOASIC_GAUNTDL)
@ -2339,7 +2339,7 @@ MACHINE_CONFIG_END
static MACHINE_CONFIG_DERIVED( warfa, vegas250 )
MCFG_DEVICE_ADD("dcs", DCS2_AUDIO_2104, 0)
MCFG_DCS2_AUDIO_DRAM_IN_MB(4)
// MCFG_DCS2_AUDIO_POLLING_OFFSET(0x0b5d) -- Not in ram???
// MCFG_DCS2_AUDIO_POLLING_OFFSET(0x0b5d) -- Not in ram???
MCFG_DEVICE_ADD("ioasic", MIDWAY_IOASIC, 0)
MCFG_MIDWAY_IOASIC_SHUFFLE(MIDWAY_IOASIC_MACE)
@ -2352,7 +2352,7 @@ MACHINE_CONFIG_END
static MACHINE_CONFIG_DERIVED( tenthdeg, vegas )
MCFG_DEVICE_ADD("dcs", DCS2_AUDIO_2104, 0)
MCFG_DCS2_AUDIO_DRAM_IN_MB(4)
// MCFG_DCS2_AUDIO_POLLING_OFFSET(0x0afb) -- Not in ram???
// MCFG_DCS2_AUDIO_POLLING_OFFSET(0x0afb) -- Not in ram???
MCFG_DEVICE_ADD("ioasic", MIDWAY_IOASIC, 0)
MCFG_MIDWAY_IOASIC_SHUFFLE(MIDWAY_IOASIC_GAUNTDL)

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