m37710.c: Modernized cpu core (nw)

src/emu/cpu/m37710/m37710cm.h

@@ -21,12 +21,12 @@
 
 #undef M37710_CALL_DEBUGGER
 
-#define M37710_CALL_DEBUGGER(x)         debugger_instruction_hook(cpustate->device, x)
+#define M37710_CALL_DEBUGGER(x)         debugger_instruction_hook(this, x)
-#define m37710_read_8(addr)             cpustate->program->read_byte(addr)
+#define m37710_read_8(addr)             m_program->read_byte(addr)
-#define m37710_write_8(addr,data)       cpustate->program->write_byte(addr,data)
+#define m37710_write_8(addr,data)       m_program->write_byte(addr,data)
-#define m37710_read_8_immediate(A)      cpustate->program->read_byte(A)
+#define m37710_read_8_immediate(A)      m_program->read_byte(A)
-#define m37710_read_16(addr)            cpustate->program->read_word(addr)
+#define m37710_read_16(addr)            m_program->read_word(addr)
-#define m37710_write_16(addr,data)      cpustate->program->write_word(addr,data)
+#define m37710_write_16(addr,data)      m_program->write_word(addr,data)
 #define m37710_jumping(A)
 #define m37710_branching(A)
 
@@ -35,13 +35,6 @@
 /* ================================ GENERAL =============================== */
 /* ======================================================================== */
 
-/* This should be set to the default size of your processor (min 16 bit) */
-#undef uint
-#define uint unsigned int
-
-#undef uint8
-#define uint8 unsigned char
-
 #undef int8
 
 /* Allow for architectures that don't have 8-bit sizes */
@@ -71,121 +64,50 @@ INLINE int MAKE_INT_8(int A) {return (A & 0x80) ? A | ~0xff : A & 0xff;}
 /* ================================== CPU ================================= */
 /* ======================================================================== */
 
-/* CPU Structure */
-struct m37710i_cpu_struct
-{
-	uint a;         /* Accumulator */
-	uint b;         /* holds high byte of accumulator */
-	uint ba;        /* Secondary Accumulator */
-	uint bb;        /* holds high byte of secondary accumulator */
-	uint x;         /* Index Register X */
-	uint y;         /* Index Register Y */
-	uint xh;        /* holds high byte of x */
-	uint yh;        /* holds high byte of y */
-	uint s;         /* Stack Pointer */
-	uint pc;        /* Program Counter */
-	uint ppc;       /* Previous Program Counter */
-	uint pb;        /* Program Bank (shifted left 16) */
-	uint db;        /* Data Bank (shifted left 16) */
-	uint d;         /* Direct Register */
-	uint flag_e;        /* Emulation Mode Flag */
-	uint flag_m;        /* Memory/Accumulator Select Flag */
-	uint flag_x;        /* Index Select Flag */
-	uint flag_n;        /* Negative Flag */
-	uint flag_v;        /* Overflow Flag */
-	uint flag_d;        /* Decimal Mode Flag */
-	uint flag_i;        /* Interrupt Mask Flag */
-	uint flag_z;        /* Zero Flag (inverted) */
-	uint flag_c;        /* Carry Flag */
-	uint line_irq;      /* Bitmask of pending IRQs */
-	uint ipl;       /* Interrupt priority level (top of PSW) */
-	uint ir;        /* Instruction Register */
-	uint im;        /* Immediate load value */
-	uint im2;       /* Immediate load target */
-	uint im3;       /* Immediate load target */
-	uint im4;       /* Immediate load target */
-	uint irq_delay;     /* delay 1 instruction before checking irq */
-	uint irq_level;     /* irq level */
-	int ICount;     /* cycle count */
-	uint source;        /* temp register */
-	uint destination;   /* temp register */
-	device_irq_acknowledge_callback int_ack;
-	legacy_cpu_device *device;
-	address_space *program;
-	address_space *io;
-	uint stopped;       /* Sets how the CPU is stopped */
-	void (*const *opcodes)(m37710i_cpu_struct *cpustate);       /* opcodes with no prefix */
-	void (*const *opcodes42)(m37710i_cpu_struct *cpustate); /* opcodes with 0x42 prefix */
-	void (*const *opcodes89)(m37710i_cpu_struct *cpustate); /* opcodes with 0x89 prefix */
-	uint (*get_reg)(m37710i_cpu_struct *cpustate, int regnum);
-	void (*set_reg)(m37710i_cpu_struct *cpustate, int regnum, uint val);
-	void (*set_line)(m37710i_cpu_struct *cpustate, int line, int state);
-	int  (*execute)(m37710i_cpu_struct *cpustate, int cycles);
 
-	// on-board peripheral stuff
+extern UINT32 m37710i_adc_tbl[];
-	UINT8 m37710_regs[128];
+extern UINT32 m37710i_sbc_tbl[];
-	attotime reload[8];
-	emu_timer *timers[8];
-};
 
-INLINE m37710i_cpu_struct *get_safe_token(device_t *device)
-{
-	assert(device != NULL);
-	assert(device->type() == M37710 ||
-			device->type() == M37702);
-	return (m37710i_cpu_struct *)downcast<legacy_cpu_device *>(device)->token();
-}
 
-extern uint m37710i_adc_tbl[];
+#define REG_A           m_a     /* Accumulator */
-extern uint m37710i_sbc_tbl[];
+#define REG_B           m_b     /* Accumulator hi byte */
+#define REG_BA          m_ba        /* Secondary Accumulator */
+#define REG_BB          m_bb        /* Secondary Accumulator hi byte */
+#define REG_X           m_x     /* Index X Register */
+#define REG_Y           m_y     /* Index Y Register */
+#define REG_XH          m_xh        /* X high byte */
+#define REG_YH          m_yh        /* Y high byte */
+#define REG_S           m_s     /* Stack Pointer */
+#define REG_PC          m_pc        /* Program Counter */
+#define REG_PPC         m_ppc       /* Previous Program Counter */
+#define REG_PB          m_pb        /* Program Bank */
+#define REG_DB          m_db        /* Data Bank */
+#define REG_D           m_d     /* Direct Register */
+#define FLAG_M          m_flag_m    /* Memory/Accumulator Select Flag */
+#define FLAG_X          m_flag_x    /* Index Select Flag */
+#define FLAG_N          m_flag_n    /* Negative Flag */
+#define FLAG_V          m_flag_v    /* Overflow Flag */
+#define FLAG_D          m_flag_d    /* Decimal Mode Flag */
+#define FLAG_I          m_flag_i    /* Interrupt Mask Flag */
+#define FLAG_Z          m_flag_z    /* Zero Flag (inverted) */
+#define FLAG_C          m_flag_c    /* Carry Flag */
+#define LINE_IRQ        m_line_irq  /* Status of the IRQ line */
+#define REG_IR          m_ir        /* Instruction Register */
+#define REG_IM          m_im        /* Immediate load value */
+#define REG_IM2         m_im2       /* Immediate load target */
+#define REG_IM3         m_im3       /* Immediate load target */
+#define REG_IM4         m_im4       /* Immediate load target */
+#define INT_ACK         m_int_ack   /* Interrupt Acknowledge function pointer */
+#define CLOCKS          m_ICount        /* Clock cycles remaining */
+#define IRQ_DELAY       m_irq_delay /* Delay 1 instruction before checking IRQ */
+#define CPU_STOPPED     m_stopped   /* Stopped status of the CPU */
 
-extern void (*const *const m37710i_opcodes[])(m37710i_cpu_struct *cpustate);
+#define FTABLE_GET_REG  m_get_reg
-extern void (*const *const m37710i_opcodes2[])(m37710i_cpu_struct *cpustate);
+#define FTABLE_SET_REG  m_set_reg
-extern void (*const *const m37710i_opcodes3[])(m37710i_cpu_struct *cpustate);
+#define FTABLE_SET_LINE m_set_line
-extern uint (*const m37710i_get_reg[])(m37710i_cpu_struct *cpustate,int regnum);
-extern void (*const m37710i_set_reg[])(m37710i_cpu_struct *cpustate,int regnum, uint val);
-extern void (*const m37710i_set_line[])(m37710i_cpu_struct *cpustate,int line, int state);
-extern int (*const m37710i_execute[])(m37710i_cpu_struct *cpustate, int cycles);
 
-#define REG_A           cpustate->a     /* Accumulator */
+#define SRC         m_source        /* Source Operand */
-#define REG_B           cpustate->b     /* Accumulator hi byte */
+#define DST         m_destination   /* Destination Operand */
-#define REG_BA          cpustate->ba        /* Secondary Accumulator */
-#define REG_BB          cpustate->bb        /* Secondary Accumulator hi byte */
-#define REG_X           cpustate->x     /* Index X Register */
-#define REG_Y           cpustate->y     /* Index Y Register */
-#define REG_XH          cpustate->xh        /* X high byte */
-#define REG_YH          cpustate->yh        /* Y high byte */
-#define REG_S           cpustate->s     /* Stack Pointer */
-#define REG_PC          cpustate->pc        /* Program Counter */
-#define REG_PPC         cpustate->ppc       /* Previous Program Counter */
-#define REG_PB          cpustate->pb        /* Program Bank */
-#define REG_DB          cpustate->db        /* Data Bank */
-#define REG_D           cpustate->d     /* Direct Register */
-#define FLAG_M          cpustate->flag_m    /* Memory/Accumulator Select Flag */
-#define FLAG_X          cpustate->flag_x    /* Index Select Flag */
-#define FLAG_N          cpustate->flag_n    /* Negative Flag */
-#define FLAG_V          cpustate->flag_v    /* Overflow Flag */
-#define FLAG_D          cpustate->flag_d    /* Decimal Mode Flag */
-#define FLAG_I          cpustate->flag_i    /* Interrupt Mask Flag */
-#define FLAG_Z          cpustate->flag_z    /* Zero Flag (inverted) */
-#define FLAG_C          cpustate->flag_c    /* Carry Flag */
-#define LINE_IRQ        cpustate->line_irq  /* Status of the IRQ line */
-#define REG_IR          cpustate->ir        /* Instruction Register */
-#define REG_IM          cpustate->im        /* Immediate load value */
-#define REG_IM2         cpustate->im2       /* Immediate load target */
-#define REG_IM3         cpustate->im3       /* Immediate load target */
-#define REG_IM4         cpustate->im4       /* Immediate load target */
-#define INT_ACK         cpustate->int_ack   /* Interrupt Acknowledge function pointer */
-#define CLOCKS          cpustate->ICount        /* Clock cycles remaining */
-#define IRQ_DELAY       cpustate->irq_delay /* Delay 1 instruction before checking IRQ */
-#define CPU_STOPPED     cpustate->stopped   /* Stopped status of the CPU */
-
-#define FTABLE_GET_REG  cpustate->get_reg
-#define FTABLE_SET_REG  cpustate->set_reg
-#define FTABLE_SET_LINE cpustate->set_line
-
-#define SRC         cpustate->source        /* Source Operand */
-#define DST         cpustate->destination   /* Destination Operand */
 
 #define STOP_LEVEL_WAI  1
 #define STOP_LEVEL_STOP 2
@@ -195,16 +117,6 @@ extern int (*const m37710i_execute[])(m37710i_cpu_struct *cpustate, int cycles);
 #define EXECUTION_MODE_M1X0 2
 #define EXECUTION_MODE_M1X1 3
 
-INLINE void m37710i_set_execution_mode(m37710i_cpu_struct *cpustate, uint mode)
-{
-	cpustate->opcodes = m37710i_opcodes[mode];
-	cpustate->opcodes42 = m37710i_opcodes2[mode];
-	cpustate->opcodes89 = m37710i_opcodes3[mode];
-	FTABLE_GET_REG = m37710i_get_reg[mode];
-	FTABLE_SET_REG = m37710i_set_reg[mode];
-	FTABLE_SET_LINE = m37710i_set_line[mode];
-	cpustate->execute = m37710i_execute[mode];
-}
 
 /* ======================================================================== */
 /* ================================= CLOCK ================================ */
@@ -330,8 +242,174 @@ INLINE void m37710i_set_execution_mode(m37710i_cpu_struct *cpustate, uint mode)
 
 #define CFLAG_AS_1()    ((FLAG_C>>8)&1)
 
-/* update IRQ state (internal use only) */
+/* ======================================================================== */
-void m37710i_update_irqs(m37710i_cpu_struct *cpustate);
+/* ========================== EFFECTIVE ADDRESSES ========================= */
+/* ======================================================================== */
+
+/* Effective-address based memory access macros */
+#define read_8_NORM(A)      m37710i_read_8_normal(A)
+#define read_8_IMM(A)       m37710i_read_8_immediate(A)
+#define read_8_D(A)     m37710i_read_8_direct(A)
+#define read_8_A(A)     m37710i_read_8_normal(A)
+#define read_8_AL(A)        m37710i_read_8_normal(A)
+#define read_8_DX(A)        m37710i_read_8_direct(A)
+#define read_8_DY(A)        m37710i_read_8_direct(A)
+#define read_8_AX(A)        m37710i_read_8_normal(A)
+#define read_8_ALX(A)       m37710i_read_8_normal(A)
+#define read_8_AY(A)        m37710i_read_8_normal(A)
+#define read_8_DI(A)        m37710i_read_8_normal(A)
+#define read_8_DLI(A)       m37710i_read_8_normal(A)
+#define read_8_AI(A)        m37710i_read_8_normal(A)
+#define read_8_ALI(A)       m37710i_read_8_normal(A)
+#define read_8_DXI(A)       m37710i_read_8_normal(A)
+#define read_8_DIY(A)       m37710i_read_8_normal(A)
+#define read_8_DLIY(A)      m37710i_read_8_normal(A)
+#define read_8_AXI(A)       m37710i_read_8_normal(A)
+#define read_8_S(A)     m37710i_read_8_normal(A)
+#define read_8_SIY(A)       m37710i_read_8_normal(A)
+
+#define read_16_NORM(A)     m37710i_read_16_normal(A)
+#define read_16_IMM(A)      m37710i_read_16_immediate(A)
+#define read_16_D(A)        m37710i_read_16_direct(A)
+#define read_16_A(A)        m37710i_read_16_normal(A)
+#define read_16_AL(A)       m37710i_read_16_normal(A)
+#define read_16_DX(A)       m37710i_read_16_direct(A)
+#define read_16_DY(A)       m37710i_read_16_direct(A)
+#define read_16_AX(A)       m37710i_read_16_normal(A)
+#define read_16_ALX(A)      m37710i_read_16_normal(A)
+#define read_16_AY(A)       m37710i_read_16_normal(A)
+#define read_16_DI(A)       m37710i_read_16_normal(A)
+#define read_16_DLI(A)      m37710i_read_16_normal(A)
+#define read_16_AI(A)       m37710i_read_16_normal(A)
+#define read_16_ALI(A)      m37710i_read_16_normal(A)
+#define read_16_DXI(A)      m37710i_read_16_normal(A)
+#define read_16_DIY(A)      m37710i_read_16_normal(A)
+#define read_16_DLIY(A)     m37710i_read_16_normal(A)
+#define read_16_AXI(A)      m37710i_read_16_normal(A)
+#define read_16_S(A)        m37710i_read_16_normal(A)
+#define read_16_SIY(A)      m37710i_read_16_normal(A)
+
+#define read_24_NORM(A)     m37710i_read_24_normal(A)
+#define read_24_IMM(A)      m37710i_read_24_immediate(A)
+#define read_24_D(A)        m37710i_read_24_direct(A)
+#define read_24_A(A)        m37710i_read_24_normal(A)
+#define read_24_AL(A)       m37710i_read_24_normal(A)
+#define read_24_DX(A)       m37710i_read_24_direct(A)
+#define read_24_DY(A)       m37710i_read_24_direct(A)
+#define read_24_AX(A)       m37710i_read_24_normal(A)
+#define read_24_ALX(A)      m37710i_read_24_normal(A)
+#define read_24_AY(A)       m37710i_read_24_normal(A)
+#define read_24_DI(A)       m37710i_read_24_normal(A)
+#define read_24_DLI(A)      m37710i_read_24_normal(A)
+#define read_24_AI(A)       m37710i_read_24_normal(A)
+#define read_24_ALI(A)      m37710i_read_24_normal(A)
+#define read_24_DXI(A)      m37710i_read_24_normal(A)
+#define read_24_DIY(A)      m37710i_read_24_normal(A)
+#define read_24_DLIY(A)     m37710i_read_24_normal(A)
+#define read_24_AXI(A)      m37710i_read_24_normal(A)
+#define read_24_S(A)        m37710i_read_24_normal(A)
+#define read_24_SIY(A)      m37710i_read_24_normal(A)
+
+#define write_8_NORM(A, V)  m37710i_write_8_normal(A, V)
+#define write_8_D(A, V)     m37710i_write_8_direct(A, V)
+#define write_8_A(A, V)     m37710i_write_8_normal(A, V)
+#define write_8_AL(A, V)    m37710i_write_8_normal(A, V)
+#define write_8_DX(A, V)    m37710i_write_8_direct(A, V)
+#define write_8_DY(A, V)    m37710i_write_8_direct(A, V)
+#define write_8_AX(A, V)    m37710i_write_8_normal(A, V)
+#define write_8_ALX(A, V)   m37710i_write_8_normal(A, V)
+#define write_8_AY(A, V)    m37710i_write_8_normal(A, V)
+#define write_8_DI(A, V)    m37710i_write_8_normal(A, V)
+#define write_8_DLI(A, V)   m37710i_write_8_normal(A, V)
+#define write_8_AI(A, V)    m37710i_write_8_normal(A, V)
+#define write_8_ALI(A, V)   m37710i_write_8_normal(A, V)
+#define write_8_DXI(A, V)   m37710i_write_8_normal(A, V)
+#define write_8_DIY(A, V)   m37710i_write_8_normal(A, V)
+#define write_8_DLIY(A, V)  m37710i_write_8_normal(A, V)
+#define write_8_AXI(A, V)   m37710i_write_8_normal(A, V)
+#define write_8_S(A, V)     m37710i_write_8_normal(A, V)
+#define write_8_SIY(A, V)   m37710i_write_8_normal(A, V)
+
+#define write_16_NORM(A, V) m37710i_write_16_normal(A, V)
+#define write_16_D(A, V)    m37710i_write_16_direct(A, V)
+#define write_16_A(A, V)    m37710i_write_16_normal(A, V)
+#define write_16_AL(A, V)   m37710i_write_16_normal(A, V)
+#define write_16_DX(A, V)   m37710i_write_16_direct(A, V)
+#define write_16_DY(A, V)   m37710i_write_16_direct(A, V)
+#define write_16_AX(A, V)   m37710i_write_16_normal(A, V)
+#define write_16_ALX(A, V)  m37710i_write_16_normal(A, V)
+#define write_16_AY(A, V)   m37710i_write_16_normal(A, V)
+#define write_16_DI(A, V)   m37710i_write_16_normal(A, V)
+#define write_16_DLI(A, V)  m37710i_write_16_normal(A, V)
+#define write_16_AI(A, V)   m37710i_write_16_normal(A, V)
+#define write_16_ALI(A, V)  m37710i_write_16_normal(A, V)
+#define write_16_DXI(A, V)  m37710i_write_16_normal(A, V)
+#define write_16_DIY(A, V)  m37710i_write_16_normal(A, V)
+#define write_16_DLIY(A, V) m37710i_write_16_normal(A, V)
+#define write_16_AXI(A, V)  m37710i_write_16_normal(A, V)
+#define write_16_S(A, V)    m37710i_write_16_normal(A, V)
+#define write_16_SIY(A, V)  m37710i_write_16_normal(A, V)
+
+
+#define OPER_8_IMM()        read_8_IMM(EA_IMM8())
+#define OPER_8_D()      read_8_D(EA_D())
+#define OPER_8_A()      read_8_A(EA_A())
+#define OPER_8_AL()     read_8_AL(EA_AL())
+#define OPER_8_DX()     read_8_DX(EA_DX())
+#define OPER_8_DY()     read_8_DY(EA_DY())
+#define OPER_8_AX()     read_8_AX(EA_AX())
+#define OPER_8_ALX()        read_8_ALX(EA_ALX())
+#define OPER_8_AY()     read_8_AY(EA_AY())
+#define OPER_8_DI()     read_8_DI(EA_DI())
+#define OPER_8_DLI()        read_8_DLI(EA_DLI())
+#define OPER_8_AI()     read_8_AI(EA_AI())
+#define OPER_8_ALI()        read_8_ALI(EA_ALI())
+#define OPER_8_DXI()        read_8_DXI(EA_DXI())
+#define OPER_8_DIY()        read_8_DIY(EA_DIY())
+#define OPER_8_DLIY()   read_8_DLIY(EA_DLIY())
+#define OPER_8_AXI()        read_8_AXI(EA_AXI())
+#define OPER_8_S()      read_8_S(EA_S())
+#define OPER_8_SIY()        read_8_SIY(EA_SIY())
+
+#define OPER_16_IMM()   read_16_IMM(EA_IMM16())
+#define OPER_16_D()     read_16_D(EA_D())
+#define OPER_16_A()     read_16_A(EA_A())
+#define OPER_16_AL()        read_16_AL(EA_AL())
+#define OPER_16_DX()        read_16_DX(EA_DX())
+#define OPER_16_DY()        read_16_DY(EA_DY())
+#define OPER_16_AX()        read_16_AX(EA_AX())
+#define OPER_16_ALX()   read_16_ALX(EA_ALX())
+#define OPER_16_AY()        read_16_AY(EA_AY())
+#define OPER_16_DI()        read_16_DI(EA_DI())
+#define OPER_16_DLI()   read_16_DLI(EA_DLI())
+#define OPER_16_AI()        read_16_AI(EA_AI())
+#define OPER_16_ALI()   read_16_ALI(EA_ALI())
+#define OPER_16_DXI()   read_16_DXI(EA_DXI())
+#define OPER_16_DIY()   read_16_DIY(EA_DIY())
+#define OPER_16_DLIY()  read_16_DLIY(EA_DLIY())
+#define OPER_16_AXI()   read_16_AXI(EA_AXI())
+#define OPER_16_S()     read_16_S(EA_S())
+#define OPER_16_SIY()   read_16_SIY(EA_SIY())
+
+#define OPER_24_IMM()   read_24_IMM(EA_IMM24())
+#define OPER_24_D()     read_24_D(EA_D())
+#define OPER_24_A()     read_24_A(EA_A())
+#define OPER_24_AL()        read_24_AL(EA_AL())
+#define OPER_24_DX()        read_24_DX(EA_DX())
+#define OPER_24_DY()        read_24_DY(EA_DY())
+#define OPER_24_AX()        read_24_AX(EA_AX())
+#define OPER_24_ALX()   read_24_ALX(EA_ALX())
+#define OPER_24_AY()        read_24_AY(EA_AY())
+#define OPER_24_DI()        read_24_DI(EA_DI())
+#define OPER_24_DLI()   read_24_DLI(EA_DLI())
+#define OPER_24_AI()        read_24_AI(EA_AI())
+#define OPER_24_ALI()   read_24_ALI(EA_ALI())
+#define OPER_24_DXI()   read_24_DXI(EA_DXI())
+#define OPER_24_DIY()   read_24_DIY(EA_DIY())
+#define OPER_24_DLIY()  read_24_DLIY(EA_DLIY())
+#define OPER_24_AXI()   read_24_AXI(EA_AXI())
+#define OPER_24_S()     read_24_S(EA_S())
+#define OPER_24_SIY()   read_24_SIY(EA_SIY())
 
 /* ======================================================================== */
 /* ================================== CPU ================================= */