mirror of
https://github.com/holub/mame
synced 2025-04-25 09:50:04 +03:00
Port from MESS, nw
This commit is contained in:
Angelo Salese
parent
4993418b5f
commit
6de70f86b9
@ -115,7 +115,7 @@ also has a DSP;
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/* TODO: do this in a verboselog style */
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#define LOG_CDB 0
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#define LOG_SCU 0
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#define LOG_SCU 1
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#define LOG_IRQ 0
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#define LOG_IOGA 0
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@ -520,25 +520,23 @@ static void scu_do_transfer(running_machine &machine,UINT8 event)
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static READ32_HANDLER( saturn_scu_r )
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{
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saturn_state *state = space->machine().driver_data<saturn_state>();
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UINT32 res;
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/*TODO: write only registers must return 0...*/
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//popmessage("%02x",DMA_STATUS);
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//if (offset == 23)
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//{
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switch(offset)
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{
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//case 0x5c/4:
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// Super Major League reads here???
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//}
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if (offset == 31)
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{
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// break;
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case 0x7c/4:
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if(LOG_SCU) logerror("(PC=%08x) DMA status reg read\n",cpu_get_pc(&space->device()));
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return state->m_scu_regs[offset];
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}
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else if ( offset == 35 )
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{
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res = state->m_scu_regs[offset];
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break;
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case 0x8c/4:
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if(LOG_SCU) logerror( "DSP mem read at %08X\n", state->m_scu_regs[34]);
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return dsp_ram_addr_r();
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}
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else if( offset == 41) /*IRQ reg status read*/
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{
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res = dsp_ram_addr_r();
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break;
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case 0xa4/4:
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if(LOG_SCU) logerror("(PC=%08x) IRQ status reg read %08x\n",cpu_get_pc(&space->device()),mem_mask);
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state->m_scu_regs[41] = (state->m_scu_irq.vblank_in & 1)<<0;
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@ -557,18 +555,19 @@ static READ32_HANDLER( saturn_scu_r )
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state->m_scu_regs[41]|= (state->m_scu_irq.vdp1_end & 1)<<13;
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state->m_scu_regs[41]|= (state->m_scu_irq.abus & 1)<<15;
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return state->m_scu_regs[41] ^ 0xffffffff; //TODO: this is WRONG (Choice Cuts is a good test case)
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}
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else if( offset == 50 )
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{
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res = state->m_scu_regs[41] ^ 0xffffffff; //TODO: this is WRONG (Choice Cuts is a good test case)
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break;
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case 0xc8/4:
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logerror("(PC=%08x) SCU version reg read\n",cpu_get_pc(&space->device()));
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return 0x00000000;/*SCU Version 0*/
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}
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else
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{
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res = 0x00000000;/*SCU Version 0, OK?*/
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break;
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default:
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if(LOG_SCU) logerror("(PC=%08x) SCU reg read at %d = %08x\n",cpu_get_pc(&space->device()),offset,state->m_scu_regs[offset]);
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return state->m_scu_regs[offset];
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res = state->m_scu_regs[offset];
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break;
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}
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return res;
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}
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#define DMA_CH ((offset & 0x18) / 8)
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@ -582,26 +581,17 @@ static WRITE32_HANDLER( saturn_scu_w )
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switch(offset)
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{
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/*LV 0 DMA*/
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case 0: case 8: case 16: state->m_scu.src[DMA_CH] = ((state->m_scu_regs[offset] & 0x07ffffff) >> 0); break;
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case 1: case 9: case 17: state->m_scu.dst[DMA_CH] = ((state->m_scu_regs[offset] & 0x07ffffff) >> 0); break;
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case 2: case 10: case 18: state->m_scu.size[DMA_CH] = ((state->m_scu_regs[offset] & ((offset == 2) ? 0x000fffff : 0x1fff)) >> 0); break;
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case 3: case 11: case 19:
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case 0x00/4: case 0x20/4: case 0x40/4: state->m_scu.src[DMA_CH] = ((state->m_scu_regs[offset] & 0x07ffffff) >> 0); break;
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case 0x04/4: case 0x24/4: case 0x44/4: state->m_scu.dst[DMA_CH] = ((state->m_scu_regs[offset] & 0x07ffffff) >> 0); break;
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case 0x08/4: case 0x28/4: case 0x48/4: state->m_scu.size[DMA_CH] = ((state->m_scu_regs[offset] & ((offset == 2) ? 0x000fffff : 0x1fff)) >> 0); break;
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case 0x0c/4: case 0x2c/4: case 0x4c/4:
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/*Read address add value for DMA lv 0*/
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state->m_scu.src_add[DMA_CH] = (state->m_scu_regs[offset] & 0x100) ? 4 : 1;
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/*Write address add value for DMA lv 0*/
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state->m_scu.dst_add[DMA_CH] = 2 << (state->m_scu_regs[offset] & 7);
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break;
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case 4: case 12: case 20:
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/*
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-state->m_scu_regs[4] bit 0 is DMA starting bit.
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Used when the start factor is 7.Toggle after execution.
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-state->m_scu_regs[4] bit 8 is DMA Enable bit.
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This is an execution mask flag.
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-state->m_scu_regs[5] bit 0,bit 1 and bit 2 is DMA starting factor.
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It must be 7 for this specific condition.
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-state->m_scu_regs[5] bit 24 is Indirect Mode/Direct Mode (0/1).
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*/
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case 0x10/4: case 0x30/4: case 0x50/4:
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state->m_scu.enable_mask[DMA_CH] = (data & 0x100) >> 8;
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if(state->m_scu.enable_mask[DMA_CH] && state->m_scu.start_factor[DMA_CH] == 7 && state->m_scu_regs[offset] & 1)
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{
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@ -610,7 +600,7 @@ static WRITE32_HANDLER( saturn_scu_w )
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state->m_scu_regs[offset]&=~1;//disable starting bit.
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}
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break;
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case 5: case 13: case 21:
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case 0x14/4: case 0x34/4: case 0x54/4:
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if(INDIRECT_MODE(DMA_CH))
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{
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if(LOG_SCU) logerror("Indirect Mode DMA lv %d set\n",DMA_CH);
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@ -621,101 +611,105 @@ static WRITE32_HANDLER( saturn_scu_w )
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state->m_scu.start_factor[DMA_CH] = state->m_scu_regs[offset] & 7;
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break;
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case 24:
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case 0x60/4:
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if(LOG_SCU) logerror("DMA Forced Stop Register set = %02x\n",state->m_scu_regs[24]);
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break;
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case 31: if(LOG_SCU) logerror("Warning: DMA status WRITE! Offset %02x(%d)\n",offset*4,offset); break;
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case 0x7c/4: if(LOG_SCU) logerror("Warning: DMA status WRITE! Offset %02x(%d)\n",offset*4,offset); break;
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/*DSP section*/
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/*Use functions so it is easier to work out*/
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case 32:
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case 0x80/4:
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dsp_prg_ctrl(space, data);
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if(LOG_SCU) logerror("SCU DSP: Program Control Port Access %08x\n",data);
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break;
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case 33:
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case 0x84/4:
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dsp_prg_data(data);
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if(LOG_SCU) logerror("SCU DSP: Program RAM Data Port Access %08x\n",data);
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break;
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case 34:
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case 0x88/4:
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dsp_ram_addr_ctrl(data);
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if(LOG_SCU) logerror("SCU DSP: Data RAM Address Port Access %08x\n",data);
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break;
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case 35:
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case 0x8c/4:
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dsp_ram_addr_w(data);
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if(LOG_SCU) logerror("SCU DSP: Data RAM Data Port Access %08x\n",data);
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break;
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case 36: if(LOG_SCU) logerror("timer 0 compare data = %03x\n",state->m_scu_regs[36]);break;
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case 37: if(LOG_SCU) logerror("timer 1 set data = %08x\n",state->m_scu_regs[37]); break;
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case 38: if(LOG_SCU) logerror("timer 1 mode data = %08x\n",state->m_scu_regs[38]); break;
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case 40:
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case 0x90/4: if(LOG_SCU) logerror("timer 0 compare data = %03x\n",state->m_scu_regs[36]);break;
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case 0x94/4: if(LOG_SCU) logerror("timer 1 set data = %08x\n",state->m_scu_regs[37]); break;
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case 0x98/4: if(LOG_SCU) logerror("timer 1 mode data = %08x\n",state->m_scu_regs[38]); break;
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case 0xa0/4:
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/*An interrupt is masked when his specific bit is 1.*/
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/*Are bit 16-bit 31 for External A-Bus irq mask like the status register?*/
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state->m_scu_irq.vblank_in = (((state->m_scu_regs[40] & 0x0001)>>0) ^ 1);
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state->m_scu_irq.vblank_out = (((state->m_scu_regs[40] & 0x0002)>>1) ^ 1);
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state->m_scu_irq.hblank_in = (((state->m_scu_regs[40] & 0x0004)>>2) ^ 1);
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state->m_scu_irq.timer_0 = (((state->m_scu_regs[40] & 0x0008)>>3) ^ 1);
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state->m_scu_irq.timer_1 = (((state->m_scu_regs[40] & 0x0010)>>4) ^ 1);
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state->m_scu_irq.dsp_end = (((state->m_scu_regs[40] & 0x0020)>>5) ^ 1);
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state->m_scu_irq.sound_req = (((state->m_scu_regs[40] & 0x0040)>>6) ^ 1);
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state->m_scu_irq.smpc = (((state->m_scu_regs[40] & 0x0080)>>7) ^ 1); //NOTE: SCU bug
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state->m_scu_irq.pad = (((state->m_scu_regs[40] & 0x0100)>>8) ^ 1);
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state->m_scu_irq.dma_end[2] = (((state->m_scu_regs[40] & 0x0200)>>9) ^ 1);
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state->m_scu_irq.dma_end[1] = (((state->m_scu_regs[40] & 0x0400)>>10) ^ 1);
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state->m_scu_irq.dma_end[0] = (((state->m_scu_regs[40] & 0x0800)>>11) ^ 1);
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state->m_scu_irq.dma_ill = (((state->m_scu_regs[40] & 0x1000)>>12) ^ 1);
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state->m_scu_irq.vdp1_end = (((state->m_scu_regs[40] & 0x2000)>>13) ^ 1);
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state->m_scu_irq.abus = (((state->m_scu_regs[40] & 0x8000)>>15) ^ 1);
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state->m_scu_irq.vblank_in = (((state->m_scu_regs[0xa0/4] & 0x0001)>>0) ^ 1);
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state->m_scu_irq.vblank_out = (((state->m_scu_regs[0xa0/4] & 0x0002)>>1) ^ 1);
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state->m_scu_irq.hblank_in = (((state->m_scu_regs[0xa0/4] & 0x0004)>>2) ^ 1);
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state->m_scu_irq.timer_0 = (((state->m_scu_regs[0xa0/4] & 0x0008)>>3) ^ 1);
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state->m_scu_irq.timer_1 = (((state->m_scu_regs[0xa0/4] & 0x0010)>>4) ^ 1);
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state->m_scu_irq.dsp_end = (((state->m_scu_regs[0xa0/4] & 0x0020)>>5) ^ 1);
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state->m_scu_irq.sound_req = (((state->m_scu_regs[0xa0/4] & 0x0040)>>6) ^ 1);
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state->m_scu_irq.smpc = (((state->m_scu_regs[0xa0/4] & 0x0080)>>7) ^ 1);
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state->m_scu_irq.pad = (((state->m_scu_regs[0xa0/4] & 0x0100)>>8) ^ 1);
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state->m_scu_irq.dma_end[2] = (((state->m_scu_regs[0xa0/4] & 0x0200)>>9) ^ 1);
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state->m_scu_irq.dma_end[1] = (((state->m_scu_regs[0xa0/4] & 0x0400)>>10) ^ 1);
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state->m_scu_irq.dma_end[0] = (((state->m_scu_regs[0xa0/4] & 0x0800)>>11) ^ 1);
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state->m_scu_irq.dma_ill = (((state->m_scu_regs[0xa0/4] & 0x1000)>>12) ^ 1);
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state->m_scu_irq.vdp1_end = (((state->m_scu_regs[0xa0/4] & 0x2000)>>13) ^ 1);
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state->m_scu_irq.abus = (((state->m_scu_regs[0xa0/4] & 0x8000)>>15) ^ 1);
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/*Take out the common settings to keep logging quiet.*/
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if(state->m_scu_regs[40] != 0xfffffffe &&
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state->m_scu_regs[40] != 0xfffffffc &&
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state->m_scu_regs[40] != 0xffffffff)
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if(state->m_scu_regs[0xa0/4] != 0xfffffffe &&
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state->m_scu_regs[0xa0/4] != 0xfffffffc &&
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state->m_scu_regs[0xa0/4] != 0xffffffff)
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{
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if(LOG_SCU) logerror("cpu %s (PC=%08X) IRQ mask reg set %08x = %d%d%d%d|%d%d%d%d|%d%d%d%d|%d%d%d%d\n",
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if(0) logerror("cpu %s (PC=%08X) IRQ mask reg set %08x = %d%d%d%d|%d%d%d%d|%d%d%d%d|%d%d%d%d\n",
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space->device().tag(), cpu_get_pc(&space->device()),
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state->m_scu_regs[offset],
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state->m_scu_regs[offset] & 0x8000 ? 1 : 0, /*A-Bus irq*/
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state->m_scu_regs[offset] & 0x4000 ? 1 : 0, /*<reserved>*/
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state->m_scu_regs[offset] & 0x2000 ? 1 : 0, /*Sprite draw end irq(VDP1)*/
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state->m_scu_regs[offset] & 0x1000 ? 1 : 0, /*Illegal DMA irq*/
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state->m_scu_regs[offset] & 0x0800 ? 1 : 0, /*Lv 0 DMA end irq*/
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state->m_scu_regs[offset] & 0x0400 ? 1 : 0, /*Lv 1 DMA end irq*/
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state->m_scu_regs[offset] & 0x0200 ? 1 : 0, /*Lv 2 DMA end irq*/
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state->m_scu_regs[offset] & 0x0100 ? 1 : 0, /*PAD irq*/
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state->m_scu_regs[offset] & 0x0080 ? 1 : 0, /*System Manager(SMPC) irq*/
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state->m_scu_regs[offset] & 0x0040 ? 1 : 0, /*Snd req*/
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state->m_scu_regs[offset] & 0x0020 ? 1 : 0, /*DSP irq end*/
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state->m_scu_regs[offset] & 0x0010 ? 1 : 0, /*Timer 1 irq*/
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state->m_scu_regs[offset] & 0x0008 ? 1 : 0, /*Timer 0 irq*/
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state->m_scu_regs[offset] & 0x0004 ? 1 : 0, /*HBlank-IN*/
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state->m_scu_regs[offset] & 0x0002 ? 1 : 0, /*VBlank-OUT*/
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state->m_scu_regs[offset] & 0x0001 ? 1 : 0);/*VBlank-IN*/
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state->m_scu_regs[0xa0/4],
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state->m_scu_regs[0xa0/4] & 0x8000 ? 1 : 0, /*A-Bus irq*/
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state->m_scu_regs[0xa0/4] & 0x4000 ? 1 : 0, /*<reserved>*/
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state->m_scu_regs[0xa0/4] & 0x2000 ? 1 : 0, /*Sprite draw end irq(VDP1)*/
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state->m_scu_regs[0xa0/4] & 0x1000 ? 1 : 0, /*Illegal DMA irq*/
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state->m_scu_regs[0xa0/4] & 0x0800 ? 1 : 0, /*Lv 0 DMA end irq*/
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state->m_scu_regs[0xa0/4] & 0x0400 ? 1 : 0, /*Lv 1 DMA end irq*/
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state->m_scu_regs[0xa0/4] & 0x0200 ? 1 : 0, /*Lv 2 DMA end irq*/
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state->m_scu_regs[0xa0/4] & 0x0100 ? 1 : 0, /*PAD irq*/
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state->m_scu_regs[0xa0/4] & 0x0080 ? 1 : 0, /*System Manager(SMPC) irq*/
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state->m_scu_regs[0xa0/4] & 0x0040 ? 1 : 0, /*Snd req*/
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state->m_scu_regs[0xa0/4] & 0x0020 ? 1 : 0, /*DSP irq end*/
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state->m_scu_regs[0xa0/4] & 0x0010 ? 1 : 0, /*Timer 1 irq*/
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state->m_scu_regs[0xa0/4] & 0x0008 ? 1 : 0, /*Timer 0 irq*/
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state->m_scu_regs[0xa0/4] & 0x0004 ? 1 : 0, /*HBlank-IN*/
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state->m_scu_regs[0xa0/4] & 0x0002 ? 1 : 0, /*VBlank-OUT*/
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state->m_scu_regs[0xa0/4] & 0x0001 ? 1 : 0);/*VBlank-IN*/
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}
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if((state->m_scu_regs[0xa0/4] ^ 0x1110) & 0x1110)
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popmessage("Enabled funky IRQ %08x, contact MAMEdev",state->m_scu_regs[0xa0/4] & 0x1110);
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break;
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/*Interrupt Control reg Set*/
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case 41:
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case 0xa4/4:
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/*This is r/w by introdon...*/
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if(LOG_SCU) logerror("IRQ status reg set:%08x %08x\n",state->m_scu_regs[41],mem_mask);
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if(LOG_SCU) logerror("PC=%08x IRQ status reg set:%08x %08x\n",cpu_get_pc(&space->device()),state->m_scu_regs[41],mem_mask);
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state->m_scu_irq.vblank_in = ((state->m_scu_regs[41] & 0x0001)>>0);
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state->m_scu_irq.vblank_out = ((state->m_scu_regs[41] & 0x0002)>>1);
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state->m_scu_irq.hblank_in = ((state->m_scu_regs[41] & 0x0004)>>2);
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state->m_scu_irq.timer_0 = ((state->m_scu_regs[41] & 0x0008)>>3);
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state->m_scu_irq.timer_1 = ((state->m_scu_regs[41] & 0x0010)>>4);
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state->m_scu_irq.dsp_end = ((state->m_scu_regs[41] & 0x0020)>>5);
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state->m_scu_irq.sound_req = ((state->m_scu_regs[41] & 0x0040)>>6);
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state->m_scu_irq.smpc = ((state->m_scu_regs[41] & 0x0080)>>7);
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state->m_scu_irq.pad = ((state->m_scu_regs[41] & 0x0100)>>8);
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state->m_scu_irq.dma_end[2] = ((state->m_scu_regs[41] & 0x0200)>>9);
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state->m_scu_irq.dma_end[1] = ((state->m_scu_regs[41] & 0x0400)>>10);
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state->m_scu_irq.dma_end[0] = ((state->m_scu_regs[41] & 0x0800)>>11);
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state->m_scu_irq.dma_ill = ((state->m_scu_regs[41] & 0x1000)>>12);
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state->m_scu_irq.vdp1_end = ((state->m_scu_regs[41] & 0x2000)>>13);
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state->m_scu_irq.abus = ((state->m_scu_regs[41] & 0x8000)>>15);
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state->m_scu_irq.vblank_in = ((state->m_scu_regs[0xa4/4] & 0x0001)>>0);
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state->m_scu_irq.vblank_out = ((state->m_scu_regs[0xa4/4] & 0x0002)>>1);
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state->m_scu_irq.hblank_in = ((state->m_scu_regs[0xa4/4] & 0x0004)>>2);
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state->m_scu_irq.timer_0 = ((state->m_scu_regs[0xa4/4] & 0x0008)>>3);
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state->m_scu_irq.timer_1 = ((state->m_scu_regs[0xa4/4] & 0x0010)>>4);
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state->m_scu_irq.dsp_end = ((state->m_scu_regs[0xa4/4] & 0x0020)>>5);
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state->m_scu_irq.sound_req = ((state->m_scu_regs[0xa4/4] & 0x0040)>>6);
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state->m_scu_irq.smpc = ((state->m_scu_regs[0xa4/4] & 0x0080)>>7);
|
||||
state->m_scu_irq.pad = ((state->m_scu_regs[0xa4/4] & 0x0100)>>8);
|
||||
state->m_scu_irq.dma_end[2] = ((state->m_scu_regs[0xa4/4] & 0x0200)>>9);
|
||||
state->m_scu_irq.dma_end[1] = ((state->m_scu_regs[0xa4/4] & 0x0400)>>10);
|
||||
state->m_scu_irq.dma_end[0] = ((state->m_scu_regs[0xa4/4] & 0x0800)>>11);
|
||||
state->m_scu_irq.dma_ill = ((state->m_scu_regs[0xa4/4] & 0x1000)>>12);
|
||||
state->m_scu_irq.vdp1_end = ((state->m_scu_regs[0xa4/4] & 0x2000)>>13);
|
||||
state->m_scu_irq.abus = ((state->m_scu_regs[0xa4/4] & 0x8000)>>15);
|
||||
|
||||
break;
|
||||
case 42: if(LOG_SCU) logerror("A-Bus IRQ ACK %08x\n",state->m_scu_regs[42]); break;
|
||||
case 49: if(LOG_SCU) logerror("SCU SDRAM set: %02x\n",state->m_scu_regs[49]); break;
|
||||
case 0xa8/4: if(LOG_SCU) logerror("A-Bus IRQ ACK %08x\n",state->m_scu_regs[42]); break;
|
||||
case 0xc4/4: if(LOG_SCU) logerror("SCU SDRAM set: %02x\n",state->m_scu_regs[49]); break;
|
||||
default: if(LOG_SCU) logerror("Warning: unused SCU reg set %d = %08x\n",offset,data);
|
||||
}
|
||||
}
|
||||
|
||||
@ -152,7 +152,7 @@ TODO:
|
||||
#include "machine/smpc.h"
|
||||
#include "machine/eeprom.h"
|
||||
|
||||
#define LOG_SMPC 1
|
||||
#define LOG_SMPC 0
|
||||
|
||||
READ8_HANDLER( stv_SMPC_r )
|
||||
{
|
||||
|
||||
Loading…
Reference in New Issue
Block a user