mirror of
https://github.com/holub/mame
synced 2025-04-24 09:20:02 +03:00
Started making 32x a device, by creating a device and moving the cpus there. From Haze. (nw)
This commit is contained in:
Scott Stone
parent
e8f1af1c00
commit
72fa59293f
1
.gitattributes
vendored
1
.gitattributes
vendored
@ -4519,6 +4519,7 @@ src/mame/machine/mcr.c svneol=native#text/plain
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src/mame/machine/mcr68.c svneol=native#text/plain
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src/mame/machine/md_cart.c svneol=native#text/plain
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src/mame/machine/mega32x.c svneol=native#text/plain
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src/mame/machine/mega32x.h svneol=native#text/plain
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src/mame/machine/megacd.c svneol=native#text/plain
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src/mame/machine/megadriv.c svneol=native#text/plain
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src/mame/machine/megasvp.c svneol=native#text/plain
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@ -15,6 +15,7 @@
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#include "cpu/ssp1601/ssp1601.h"
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#include "machine/megavdp.h"
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#include "machine/mega32x.h"
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#include "video/315_5124.h"
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#define MASTER_CLOCK_NTSC 53693175
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@ -420,10 +421,7 @@ public:
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};
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// Fifa96 needs the CPUs swapped for the gameplay to enter due to some race conditions
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// when using the DRC core. Needs further investigation, the non-DRC core works either
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// way
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#define _32X_SWAP_MASTER_SLAVE_HACK
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extern int _32x_is_connected;
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extern cpu_device *_32x_master_cpu;
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@ -431,12 +429,7 @@ extern cpu_device *_32x_slave_cpu;
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// called from out main scanline timers...
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extern int _32x_fifo_available_callback(device_t *device, UINT32 src, UINT32 dst, UINT32 data, int size);
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extern MACHINE_RESET( _32x );
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ADDRESS_MAP_EXTERN( sh2_main_map, driver_device );
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ADDRESS_MAP_EXTERN( sh2_slave_map, driver_device );
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extern emu_timer *_32x_pwm_timer;
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extern TIMER_CALLBACK( _32x_pwm_callback );
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extern int megadrive_vblank_flag;
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extern int genesis_scanline_counter;
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@ -195,10 +195,11 @@ GFX check (these don't explicitly fails):
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#161 Runlength Mode
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*/
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#include "emu.h"
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#include "includes/megadriv.h"
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/* the main Megadrive emulation needs to know this */
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int _32x_is_connected;
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cpu_device *_32x_master_cpu;
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@ -251,6 +252,31 @@ static UINT16* _32x_palette_lookup;
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const device_type SEGA_32X_NTSC = &device_creator<sega_32x_ntsc_device>;
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const device_type SEGA_32X_PAL = &device_creator<sega_32x_pal_device>;
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sega_32x_device::sega_32x_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock, device_type type)
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: device_t(mconfig, type, "sega_32x_device", tag, owner, clock),
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m_lch_pwm(*this, "lch_pwm"),
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m_rch_pwm(*this, "rch_pwm")
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{
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}
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sega_32x_ntsc_device::sega_32x_ntsc_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
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: sega_32x_device(mconfig, tag, owner, clock, SEGA_32X_NTSC)
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{
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}
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sega_32x_pal_device::sega_32x_pal_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
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: sega_32x_device(mconfig, tag, owner, clock, SEGA_32X_PAL)
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{
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}
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TIMER_CALLBACK( _32x_pwm_callback );
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/****************************************** 32X related ******************************************/
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/**********************************************************************************************/
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@ -607,8 +633,8 @@ static WRITE16_HANDLER( _32x_dreq_common_w )
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current_fifo_block = fifo_block_b;
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current_fifo_readblock = fifo_block_a;
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// incase we have a stalled DMA in progress, let the SH2 know there is data available
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sh2_notify_dma_data_available(space->machine().device("32x_master_sh2"));
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sh2_notify_dma_data_available(space->machine().device("32x_slave_sh2"));
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sh2_notify_dma_data_available(space->machine().device(_32X_MASTER_TAG));
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sh2_notify_dma_data_available(space->machine().device(_32X_SLAVE_TAG));
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}
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current_fifo_write_pos = 0;
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@ -622,8 +648,8 @@ static WRITE16_HANDLER( _32x_dreq_common_w )
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current_fifo_block = fifo_block_a;
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current_fifo_readblock = fifo_block_b;
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// incase we have a stalled DMA in progress, let the SH2 know there is data available
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sh2_notify_dma_data_available(space->machine().device("32x_master_sh2"));
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sh2_notify_dma_data_available(space->machine().device("32x_slave_sh2"));
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sh2_notify_dma_data_available(space->machine().device(_32X_MASTER_TAG));
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sh2_notify_dma_data_available(space->machine().device(_32X_SLAVE_TAG));
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}
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@ -847,35 +873,41 @@ static UINT8 pwm_timer_tick;
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static UINT8 lch_index_r,rch_index_r,lch_index_w,rch_index_w;
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static UINT16 lch_fifo_state,rch_fifo_state;
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emu_timer *_32x_pwm_timer;
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static void calculate_pwm_timer(void)
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static void calculate_pwm_timer(running_machine &machine)
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{
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sega_32x_device* _32xdev = (sega_32x_device*)machine.device(":sega32x");
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if(pwm_tm_reg == 0) { pwm_tm_reg = 16; } // zero gives max range
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if(pwm_cycle == 0) { pwm_cycle = 4095; } // zero gives max range
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/* if both RMD and LMD are set to OFF or pwm cycle register is one, then PWM timer ticks doesn't occur */
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if(pwm_cycle == 1 || ((pwm_ctrl & 0xf) == 0))
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_32x_pwm_timer->adjust(attotime::never);
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_32xdev->m_32x_pwm_timer->adjust(attotime::never);
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else
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{
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pwm_timer_tick = 0;
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lch_fifo_state = rch_fifo_state = 0x4000;
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lch_index_r = rch_index_r = 0;
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lch_index_w = rch_index_w = 0;
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_32x_pwm_timer->adjust(attotime::from_hz((PWM_CLOCK) / (pwm_cycle - 1)));
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_32xdev->m_32x_pwm_timer->adjust(attotime::from_hz((PWM_CLOCK) / (pwm_cycle - 1)));
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}
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}
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TIMER_CALLBACK( _32x_pwm_callback )
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{
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sega_32x_device* _32xdev = (sega_32x_device*)ptr;
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if(lch_index_r < PWM_FIFO_SIZE)
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{
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switch(pwm_ctrl & 3)
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{
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case 0: lch_index_r++; /*Speaker OFF*/ break;
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case 1: machine.device<dac_device>("lch_pwm")->write_signed16(cur_lch[lch_index_r++]); break;
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case 2: machine.device<dac_device>("rch_pwm")->write_signed16(cur_lch[lch_index_r++]); break;
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case 1: _32xdev->m_lch_pwm->write_signed16(cur_lch[lch_index_r++]); break;
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case 2: _32xdev->m_rch_pwm->write_signed16(cur_lch[lch_index_r++]); break;
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case 3: popmessage("Undefined PWM Lch value 3, contact MESSdev"); break;
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}
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@ -889,8 +921,8 @@ TIMER_CALLBACK( _32x_pwm_callback )
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switch((pwm_ctrl & 0xc) >> 2)
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{
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case 0: rch_index_r++; /*Speaker OFF*/ break;
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case 1: machine.device<dac_device>("rch_pwm")->write_signed16(cur_rch[rch_index_r++]); break;
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case 2: machine.device<dac_device>("lch_pwm")->write_signed16(cur_rch[rch_index_r++]); break;
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case 1: _32xdev->m_rch_pwm->write_signed16(cur_rch[rch_index_r++]); break;
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case 2: _32xdev->m_lch_pwm->write_signed16(cur_rch[rch_index_r++]); break;
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case 3: popmessage("Undefined PWM Rch value 3, contact MESSdev"); break;
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}
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@ -908,7 +940,7 @@ TIMER_CALLBACK( _32x_pwm_callback )
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if(sh2_slave_pwmint_enable) { device_set_input_line(_32x_slave_cpu, SH2_PINT_IRQ_LEVEL,ASSERT_LINE); }
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}
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_32x_pwm_timer->adjust(attotime::from_hz((PWM_CLOCK) / (pwm_cycle - 1)));
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_32xdev->m_32x_pwm_timer->adjust(attotime::from_hz((PWM_CLOCK) / (pwm_cycle - 1)));
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}
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static READ16_HANDLER( _32x_pwm_r )
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@ -928,16 +960,17 @@ static READ16_HANDLER( _32x_pwm_r )
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static WRITE16_HANDLER( _32x_pwm_w )
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{
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switch(offset)
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{
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case 0x00/2:
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pwm_ctrl = data & 0xffff;
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pwm_tm_reg = (pwm_ctrl & 0xf00) >> 8;
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calculate_pwm_timer();
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calculate_pwm_timer(space->machine());
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break;
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case 0x02/2:
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pwm_cycle = pwm_cycle_reg = data & 0xfff;
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calculate_pwm_timer();
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calculate_pwm_timer(space->machine());
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break;
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case 0x04/2:
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if(lch_index_w < PWM_FIFO_SIZE)
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@ -1426,8 +1459,7 @@ static WRITE16_HANDLER( _32x_sh2_slave_401e_w )
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// these just map through to the 68k functions
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/**********************************************************************************************/
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static READ16_HANDLER( _32x_sh2_commsram16_r ) { return _32x_68k_commsram_r(space, offset, mem_mask); }
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static WRITE16_HANDLER( _32x_sh2_commsram16_w ) { _32x_68k_commsram_w(space, offset, data, mem_mask); }
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/* handled directly */
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/**********************************************************************************************/
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// SH2 side 4030
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@ -1463,8 +1495,7 @@ static WRITE16_HANDLER( _32x_sh2_commsram16_w ) { _32x_68k_commsram_w(space, off
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// maps through to 68k at a15200 - a153ff
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/**********************************************************************************************/
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static READ16_HANDLER( _32x_sh2_paletteram16_r ) { return _32x_68k_palette_r(space,offset,mem_mask); }
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static WRITE16_HANDLER( _32x_sh2_paletteram16_w ) { _32x_68k_palette_w(space,offset,data,mem_mask); }
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/* handled directly */
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/**********************************************************************************************/
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// SH2 side 4000000 - 401ffff
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@ -1472,8 +1503,7 @@ static WRITE16_HANDLER( _32x_sh2_paletteram16_w ) { _32x_68k_palette_w(space,off
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// maps through to 68k at 840000 - 85ffff
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/**********************************************************************************************/
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static READ16_HANDLER( _32x_sh2_framebuffer_dram16_r ) { return _32x_68k_dram_r(space,offset,mem_mask); }
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static WRITE16_HANDLER( _32x_sh2_framebuffer_dram16_w ) { _32x_68k_dram_w(space,offset,data,mem_mask); }
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/* handled directly */
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/**********************************************************************************************/
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// SH2 side 4020000 - 403ffff
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@ -1481,10 +1511,7 @@ static WRITE16_HANDLER( _32x_sh2_framebuffer_dram16_w ) { _32x_68k_dram_w(space,
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// maps through to 68k at 860000 - 87ffff
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/**********************************************************************************************/
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static READ16_HANDLER( _32x_sh2_framebuffer_overwrite_dram16_r ) { return _32x_68k_dram_overwrite_r(space,offset,mem_mask); }
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static WRITE16_HANDLER( _32x_sh2_framebuffer_overwrite_dram16_w ) { _32x_68k_dram_overwrite_w(space,offset,data,mem_mask); }
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/* handled directly */
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/**********************************************************************************************/
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// SH2 access Macros
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@ -1495,17 +1522,17 @@ static WRITE16_HANDLER( _32x_sh2_framebuffer_overwrite_dram16_w ) { _32x_68k_dra
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to 2x 16-bit handlers here (TODO: nuke this eventually) */
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#define _32X_MAP_READHANDLERS(NAMEA,NAMEB) \
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static READ32_HANDLER( _32x_sh2_##NAMEA##_##NAMEB##_r ) \
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READ32_MEMBER( sega_32x_device::_32x_sh2_##NAMEA##_##NAMEB##_r ) \
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{ \
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UINT32 retvalue = 0x00000000; \
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if (ACCESSING_BITS_16_31) \
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{ \
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UINT16 ret = _32x_sh2_##NAMEA##_r(space,0,(mem_mask>>16)&0xffff); \
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UINT16 ret = _32x_sh2_##NAMEA##_r(&space,0,(mem_mask>>16)&0xffff); \
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retvalue |= ret << 16; \
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} \
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if (ACCESSING_BITS_0_15) \
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{ \
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UINT16 ret = _32x_sh2_##NAMEB##_r(space,0,(mem_mask>>0)&0xffff); \
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UINT16 ret = _32x_sh2_##NAMEB##_r(&space,0,(mem_mask>>0)&0xffff); \
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retvalue |= ret << 0; \
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} \
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\
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@ -1513,50 +1540,18 @@ static READ32_HANDLER( _32x_sh2_##NAMEA##_##NAMEB##_r )
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} \
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#define _32X_MAP_WRITEHANDLERS(NAMEA,NAMEB) \
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static WRITE32_HANDLER( _32x_sh2_##NAMEA##_##NAMEB##_w) \
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WRITE32_MEMBER( sega_32x_device::_32x_sh2_##NAMEA##_##NAMEB##_w) \
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{ \
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if (ACCESSING_BITS_16_31) \
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{ \
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_32x_sh2_##NAMEA##_w(space,0,(data>>16)&0xffff,(mem_mask>>16)&0xffff); \
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_32x_sh2_##NAMEA##_w(&space,0,(data>>16)&0xffff,(mem_mask>>16)&0xffff); \
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} \
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if (ACCESSING_BITS_0_15) \
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{ \
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_32x_sh2_##NAMEB##_w(space,0,(data>>0)&0xffff,(mem_mask>>0)&0xffff); \
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_32x_sh2_##NAMEB##_w(&space,0,(data>>0)&0xffff,(mem_mask>>0)&0xffff); \
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} \
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} \
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/* for RAM ranges, eg. Framebuffer, Comms RAM etc. */
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#define _32X_MAP_RAM_READHANDLERS(NAMEA) \
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static READ32_HANDLER( _32x_sh2_##NAMEA##_r ) \
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{ \
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UINT32 retvalue = 0x00000000; \
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if (ACCESSING_BITS_16_31) \
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{ \
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UINT16 ret = _32x_sh2_##NAMEA##16_r(space,offset*2,(mem_mask>>16)&0xffff); \
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retvalue |= ret << 16; \
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} \
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if (ACCESSING_BITS_0_15) \
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{ \
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UINT16 ret = _32x_sh2_##NAMEA##16_r(space,offset*2+1,(mem_mask>>0)&0xffff); \
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retvalue |= ret << 0; \
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} \
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\
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return retvalue; \
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} \
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#define _32X_MAP_RAM_WRITEHANDLERS(NAMEA) \
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static WRITE32_HANDLER( _32x_sh2_##NAMEA##_w) \
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{ \
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if (ACCESSING_BITS_16_31) \
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{ \
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_32x_sh2_##NAMEA##16_w(space,offset*2,(data>>16)&0xffff,(mem_mask>>16)&0xffff); \
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} \
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if (ACCESSING_BITS_0_15) \
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{ \
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_32x_sh2_##NAMEA##16_w(space,offset*2+1,(data>>0)&0xffff,(mem_mask>>0)&0xffff); \
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} \
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} \
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@ -1564,7 +1559,6 @@ static WRITE32_HANDLER( _32x_sh2_##NAMEA##_w)
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// SH2 access for Memory Map
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/**********************************************************************************************/
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_32X_MAP_READHANDLERS(master_4000,common_4002) // _32x_sh2_master_4000_common_4002_r
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_32X_MAP_WRITEHANDLERS(master_4000,common_4002) // _32x_sh2_master_4000_common_4002_w
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@ -1582,77 +1576,66 @@ _32X_MAP_WRITEHANDLERS(slave_4014,slave_4016) // _32x_sh2_slave_4014_slave_4016_
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_32X_MAP_WRITEHANDLERS(slave_4018,slave_401a) // _32x_sh2_slave_4018_slave_401a_w
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_32X_MAP_WRITEHANDLERS(slave_401c,slave_401e) // _32x_sh2_slave_401c_slave_401e_w
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_32X_MAP_RAM_READHANDLERS(commsram) // _32x_sh2_commsram_r
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_32X_MAP_RAM_WRITEHANDLERS(commsram) // _32x_sh2_commsram_w
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_32X_MAP_RAM_READHANDLERS(framebuffer_dram) // _32x_sh2_framebuffer_dram_r
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_32X_MAP_RAM_WRITEHANDLERS(framebuffer_dram) // _32x_sh2_framebuffer_dram_w
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_32X_MAP_RAM_READHANDLERS(framebuffer_overwrite_dram) // _32x_sh2_framebuffer_overwrite_dram_r
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_32X_MAP_RAM_WRITEHANDLERS(framebuffer_overwrite_dram) // _32x_sh2_framebuffer_overwrite_dram_w
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_32X_MAP_RAM_READHANDLERS(paletteram) // _32x_sh2_paletteram_r
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_32X_MAP_RAM_WRITEHANDLERS(paletteram) // _32x_sh2_paletteram_w
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/**********************************************************************************************/
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// SH2 memory maps
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/**********************************************************************************************/
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ADDRESS_MAP_START( sh2_main_map, AS_PROGRAM, 32, driver_device )
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AM_RANGE(0x00000000, 0x00003fff) AM_ROM
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ADDRESS_MAP_START( sh2_main_map, AS_PROGRAM, 32, sega_32x_device )
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AM_RANGE(0x00000000, 0x00003fff) AM_ROMBANK("masterbios")
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AM_RANGE(0x00004000, 0x00004003) AM_READWRITE_LEGACY(_32x_sh2_master_4000_common_4002_r, _32x_sh2_master_4000_common_4002_w )
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AM_RANGE(0x00004004, 0x00004007) AM_READWRITE_LEGACY(_32x_sh2_common_4004_common_4006_r, _32x_sh2_common_4004_common_4006_w)
|
||||
AM_RANGE(0x00004000, 0x00004003) AM_READWRITE(_32x_sh2_master_4000_common_4002_r, _32x_sh2_master_4000_common_4002_w )
|
||||
AM_RANGE(0x00004004, 0x00004007) AM_READWRITE(_32x_sh2_common_4004_common_4006_r, _32x_sh2_common_4004_common_4006_w)
|
||||
|
||||
AM_RANGE(0x00004008, 0x00004013) AM_READWRITE16_LEGACY(_32x_dreq_common_r, _32x_dreq_common_w, 0xffffffff )
|
||||
|
||||
AM_RANGE(0x00004014, 0x00004017) AM_READNOP AM_WRITE_LEGACY(_32x_sh2_master_4014_master_4016_w ) // IRQ clear
|
||||
AM_RANGE(0x00004018, 0x0000401b) AM_READNOP AM_WRITE_LEGACY(_32x_sh2_master_4018_master_401a_w ) // IRQ clear
|
||||
AM_RANGE(0x0000401c, 0x0000401f) AM_READNOP AM_WRITE_LEGACY(_32x_sh2_master_401c_master_401e_w ) // IRQ clear
|
||||
AM_RANGE(0x00004014, 0x00004017) AM_READNOP AM_WRITE(_32x_sh2_master_4014_master_4016_w ) // IRQ clear
|
||||
AM_RANGE(0x00004018, 0x0000401b) AM_READNOP AM_WRITE(_32x_sh2_master_4018_master_401a_w ) // IRQ clear
|
||||
AM_RANGE(0x0000401c, 0x0000401f) AM_READNOP AM_WRITE(_32x_sh2_master_401c_master_401e_w ) // IRQ clear
|
||||
|
||||
AM_RANGE(0x00004020, 0x0000402f) AM_READWRITE_LEGACY(_32x_sh2_commsram_r, _32x_sh2_commsram_w )
|
||||
AM_RANGE(0x00004020, 0x0000402f) AM_READWRITE16_LEGACY(_32x_68k_commsram_r, _32x_68k_commsram_w, 0xffffffff )
|
||||
AM_RANGE(0x00004030, 0x0000403f) AM_READWRITE16_LEGACY(_32x_pwm_r, _32x_pwm_w, 0xffffffff )
|
||||
|
||||
AM_RANGE(0x00004100, 0x0000410b) AM_READWRITE16_LEGACY(_32x_common_vdp_regs_r, _32x_common_vdp_regs_w , 0xffffffff)
|
||||
AM_RANGE(0x00004200, 0x000043ff) AM_READWRITE_LEGACY(_32x_sh2_paletteram_r, _32x_sh2_paletteram_w)
|
||||
AM_RANGE(0x00004200, 0x000043ff) AM_READWRITE16_LEGACY(_32x_68k_palette_r, _32x_68k_palette_w, 0xffffffff)
|
||||
|
||||
AM_RANGE(0x04000000, 0x0401ffff) AM_READWRITE_LEGACY(_32x_sh2_framebuffer_dram_r, _32x_sh2_framebuffer_dram_w)
|
||||
AM_RANGE(0x04020000, 0x0403ffff) AM_READWRITE_LEGACY(_32x_sh2_framebuffer_overwrite_dram_r, _32x_sh2_framebuffer_overwrite_dram_w)
|
||||
AM_RANGE(0x04000000, 0x0401ffff) AM_READWRITE16_LEGACY(_32x_68k_dram_r, _32x_68k_dram_w, 0xffffffff)
|
||||
AM_RANGE(0x04020000, 0x0403ffff) AM_READWRITE16_LEGACY(_32x_68k_dram_overwrite_r, _32x_68k_dram_overwrite_w, 0xffffffff)
|
||||
|
||||
AM_RANGE(0x06000000, 0x0603ffff) AM_RAM AM_SHARE("share10")
|
||||
AM_RANGE(0x02000000, 0x023fffff) AM_ROM AM_REGION("gamecart_sh2", 0) // program is writeable (wwfraw)
|
||||
AM_RANGE(0x06000000, 0x0603ffff) AM_RAM AM_SHARE("sh2_shared")
|
||||
AM_RANGE(0x02000000, 0x023fffff) AM_ROM AM_REGION(":gamecart_sh2", 0) // program is writeable (wwfraw)
|
||||
|
||||
AM_RANGE(0x22000000, 0x223fffff) AM_ROM AM_REGION("gamecart_sh2", 0) // cart mirror (fifa96)
|
||||
AM_RANGE(0x22000000, 0x223fffff) AM_ROM AM_REGION(":gamecart_sh2", 0) // cart mirror (fifa96)
|
||||
|
||||
AM_RANGE(0xc0000000, 0xc0000fff) AM_RAM
|
||||
ADDRESS_MAP_END
|
||||
|
||||
ADDRESS_MAP_START( sh2_slave_map, AS_PROGRAM, 32, driver_device )
|
||||
AM_RANGE(0x00000000, 0x00003fff) AM_ROM
|
||||
ADDRESS_MAP_START( sh2_slave_map, AS_PROGRAM, 32, sega_32x_device )
|
||||
AM_RANGE(0x00000000, 0x00003fff) AM_ROMBANK("slavebios")
|
||||
|
||||
AM_RANGE(0x00004000, 0x00004003) AM_READWRITE_LEGACY(_32x_sh2_slave_4000_common_4002_r, _32x_sh2_slave_4000_common_4002_w )
|
||||
AM_RANGE(0x00004004, 0x00004007) AM_READWRITE_LEGACY(_32x_sh2_common_4004_common_4006_r, _32x_sh2_common_4004_common_4006_w)
|
||||
AM_RANGE(0x00004000, 0x00004003) AM_READWRITE(_32x_sh2_slave_4000_common_4002_r, _32x_sh2_slave_4000_common_4002_w )
|
||||
AM_RANGE(0x00004004, 0x00004007) AM_READWRITE(_32x_sh2_common_4004_common_4006_r, _32x_sh2_common_4004_common_4006_w)
|
||||
|
||||
AM_RANGE(0x00004008, 0x00004013) AM_READWRITE16_LEGACY(_32x_dreq_common_r, _32x_dreq_common_w, 0xffffffff )
|
||||
|
||||
AM_RANGE(0x00004014, 0x00004017) AM_READNOP AM_WRITE_LEGACY(_32x_sh2_slave_4014_slave_4016_w ) // IRQ clear
|
||||
AM_RANGE(0x00004018, 0x0000401b) AM_READNOP AM_WRITE_LEGACY(_32x_sh2_slave_4018_slave_401a_w ) // IRQ clear
|
||||
AM_RANGE(0x0000401c, 0x0000401f) AM_READNOP AM_WRITE_LEGACY(_32x_sh2_slave_401c_slave_401e_w ) // IRQ clear
|
||||
AM_RANGE(0x00004014, 0x00004017) AM_READNOP AM_WRITE(_32x_sh2_slave_4014_slave_4016_w ) // IRQ clear
|
||||
AM_RANGE(0x00004018, 0x0000401b) AM_READNOP AM_WRITE(_32x_sh2_slave_4018_slave_401a_w ) // IRQ clear
|
||||
AM_RANGE(0x0000401c, 0x0000401f) AM_READNOP AM_WRITE(_32x_sh2_slave_401c_slave_401e_w ) // IRQ clear
|
||||
|
||||
AM_RANGE(0x00004020, 0x0000402f) AM_READWRITE_LEGACY(_32x_sh2_commsram_r, _32x_sh2_commsram_w )
|
||||
AM_RANGE(0x00004020, 0x0000402f) AM_READWRITE16_LEGACY(_32x_68k_commsram_r, _32x_68k_commsram_w, 0xffffffff )
|
||||
AM_RANGE(0x00004030, 0x0000403f) AM_READWRITE16_LEGACY(_32x_pwm_r, _32x_pwm_w, 0xffffffff )
|
||||
|
||||
AM_RANGE(0x00004100, 0x0000410b) AM_READWRITE16_LEGACY(_32x_common_vdp_regs_r, _32x_common_vdp_regs_w , 0xffffffff)
|
||||
AM_RANGE(0x00004200, 0x000043ff) AM_READWRITE_LEGACY(_32x_sh2_paletteram_r, _32x_sh2_paletteram_w)
|
||||
AM_RANGE(0x00004200, 0x000043ff) AM_READWRITE16_LEGACY(_32x_68k_palette_r, _32x_68k_palette_w, 0xffffffff)
|
||||
|
||||
AM_RANGE(0x04000000, 0x0401ffff) AM_READWRITE_LEGACY(_32x_sh2_framebuffer_dram_r, _32x_sh2_framebuffer_dram_w)
|
||||
AM_RANGE(0x04020000, 0x0403ffff) AM_READWRITE_LEGACY(_32x_sh2_framebuffer_overwrite_dram_r, _32x_sh2_framebuffer_overwrite_dram_w)
|
||||
AM_RANGE(0x04000000, 0x0401ffff) AM_READWRITE16_LEGACY(_32x_68k_dram_r, _32x_68k_dram_w, 0xffffffff)
|
||||
AM_RANGE(0x04020000, 0x0403ffff) AM_READWRITE16_LEGACY(_32x_68k_dram_overwrite_r, _32x_68k_dram_overwrite_w, 0xffffffff)
|
||||
|
||||
AM_RANGE(0x06000000, 0x0603ffff) AM_RAM AM_SHARE("share10")
|
||||
AM_RANGE(0x02000000, 0x023fffff) AM_ROM AM_REGION("gamecart_sh2", 0) // program is writeable (wwfraw)
|
||||
AM_RANGE(0x06000000, 0x0603ffff) AM_RAM AM_SHARE("sh2_shared")
|
||||
AM_RANGE(0x02000000, 0x023fffff) AM_ROM AM_REGION(":gamecart_sh2", 0) // program is writeable (wwfraw)
|
||||
|
||||
AM_RANGE(0x22000000, 0x223fffff) AM_ROM AM_REGION("gamecart_sh2", 0) // cart mirror (fifa96)
|
||||
AM_RANGE(0x22000000, 0x223fffff) AM_ROM AM_REGION(":gamecart_sh2", 0) // cart mirror (fifa96)
|
||||
|
||||
AM_RANGE(0xc0000000, 0xc0000fff) AM_RAM
|
||||
ADDRESS_MAP_END
|
||||
@ -1663,70 +1646,37 @@ ADDRESS_MAP_END
|
||||
|
||||
DRIVER_INIT_MEMBER(md_cons_state,_32x)
|
||||
{
|
||||
_32x_dram0 = auto_alloc_array(machine(), UINT16, 0x40000/2);
|
||||
_32x_dram1 = auto_alloc_array(machine(), UINT16, 0x40000/2);
|
||||
|
||||
memset(_32x_dram0, 0x00, 0x40000);
|
||||
memset(_32x_dram1, 0x00, 0x40000);
|
||||
|
||||
_32x_palette_lookup = auto_alloc_array(machine(), UINT16, 0x200/2);
|
||||
_32x_palette = auto_alloc_array(machine(), UINT16, 0x200/2);
|
||||
|
||||
memset(_32x_palette_lookup, 0x00, 0x200);
|
||||
memset(_32x_palette, 0x00, 0x200);
|
||||
|
||||
|
||||
_32x_display_dram = _32x_dram0;
|
||||
_32x_access_dram = _32x_dram1;
|
||||
|
||||
_32x_adapter_enabled = 0;
|
||||
|
||||
if (_32x_adapter_enabled == 0)
|
||||
{
|
||||
machine().device("maincpu")->memory().space(AS_PROGRAM)->install_rom(0x0000000, 0x03fffff, machine().root_device().memregion("gamecart")->base());
|
||||
machine().device("maincpu")->memory().space(AS_PROGRAM)->install_legacy_readwrite_handler(0x000070, 0x000073, FUNC(_32x_68k_hint_vector_r), FUNC(_32x_68k_hint_vector_w)); // h interrupt vector
|
||||
machine().device(":maincpu")->memory().space(AS_PROGRAM)->install_rom(0x0000000, 0x03fffff, machine().root_device().memregion(":gamecart")->base());
|
||||
machine().device(":maincpu")->memory().space(AS_PROGRAM)->install_legacy_readwrite_handler(0x000070, 0x000073, FUNC(_32x_68k_hint_vector_r), FUNC(_32x_68k_hint_vector_w)); // h interrupt vector
|
||||
};
|
||||
|
||||
|
||||
a15100_reg = 0x0000;
|
||||
machine().device("maincpu")->memory().space(AS_PROGRAM)->install_legacy_readwrite_handler(0xa15100, 0xa15101, FUNC(_32x_68k_a15100_r), FUNC(_32x_68k_a15100_w)); // framebuffer control regs
|
||||
machine().device("maincpu")->memory().space(AS_PROGRAM)->install_legacy_readwrite_handler(0xa15102, 0xa15103, FUNC(_32x_68k_a15102_r), FUNC(_32x_68k_a15102_w)); // send irq to sh2
|
||||
machine().device("maincpu")->memory().space(AS_PROGRAM)->install_legacy_readwrite_handler(0xa15104, 0xa15105, FUNC(_32x_68k_a15104_r), FUNC(_32x_68k_a15104_w)); // 68k BANK rom set
|
||||
machine().device("maincpu")->memory().space(AS_PROGRAM)->install_legacy_readwrite_handler(0xa15106, 0xa15107, FUNC(_32x_68k_a15106_r), FUNC(_32x_68k_a15106_w)); // dreq stuff
|
||||
machine().device("maincpu")->memory().space(AS_PROGRAM)->install_legacy_readwrite_handler(0xa15108, 0xa15113, FUNC(_32x_dreq_common_r), FUNC(_32x_dreq_common_w)); // dreq src / dst / length /fifo
|
||||
machine().device(":maincpu")->memory().space(AS_PROGRAM)->install_legacy_readwrite_handler(0xa15100, 0xa15101, FUNC(_32x_68k_a15100_r), FUNC(_32x_68k_a15100_w)); // framebuffer control regs
|
||||
machine().device(":maincpu")->memory().space(AS_PROGRAM)->install_legacy_readwrite_handler(0xa15102, 0xa15103, FUNC(_32x_68k_a15102_r), FUNC(_32x_68k_a15102_w)); // send irq to sh2
|
||||
machine().device(":maincpu")->memory().space(AS_PROGRAM)->install_legacy_readwrite_handler(0xa15104, 0xa15105, FUNC(_32x_68k_a15104_r), FUNC(_32x_68k_a15104_w)); // 68k BANK rom set
|
||||
machine().device(":maincpu")->memory().space(AS_PROGRAM)->install_legacy_readwrite_handler(0xa15106, 0xa15107, FUNC(_32x_68k_a15106_r), FUNC(_32x_68k_a15106_w)); // dreq stuff
|
||||
machine().device(":maincpu")->memory().space(AS_PROGRAM)->install_legacy_readwrite_handler(0xa15108, 0xa15113, FUNC(_32x_dreq_common_r), FUNC(_32x_dreq_common_w)); // dreq src / dst / length /fifo
|
||||
|
||||
machine().device("maincpu")->memory().space(AS_PROGRAM)->install_legacy_readwrite_handler(0xa1511a, 0xa1511b, FUNC(_32x_68k_a1511a_r), FUNC(_32x_68k_a1511a_w)); // SEGA TV
|
||||
machine().device(":maincpu")->memory().space(AS_PROGRAM)->install_legacy_readwrite_handler(0xa1511a, 0xa1511b, FUNC(_32x_68k_a1511a_r), FUNC(_32x_68k_a1511a_w)); // SEGA TV
|
||||
|
||||
machine().device("maincpu")->memory().space(AS_PROGRAM)->install_legacy_readwrite_handler(0xa15120, 0xa1512f, FUNC(_32x_68k_commsram_r), FUNC(_32x_68k_commsram_w)); // comms reg 0-7
|
||||
machine().device("maincpu")->memory().space(AS_PROGRAM)->install_legacy_readwrite_handler(0xa15130, 0xa1513f, FUNC(_32x_pwm_r), FUNC(_32x_68k_pwm_w));
|
||||
machine().device(":maincpu")->memory().space(AS_PROGRAM)->install_legacy_readwrite_handler(0xa15120, 0xa1512f, FUNC(_32x_68k_commsram_r), FUNC(_32x_68k_commsram_w)); // comms reg 0-7
|
||||
machine().device(":maincpu")->memory().space(AS_PROGRAM)->install_legacy_readwrite_handler(0xa15130, 0xa1513f, FUNC(_32x_pwm_r), FUNC(_32x_68k_pwm_w));
|
||||
|
||||
machine().device("maincpu")->memory().space(AS_PROGRAM)->install_legacy_read_handler(0x0a130ec, 0x0a130ef, FUNC(_32x_68k_MARS_r)); // system ID
|
||||
machine().device(":maincpu")->memory().space(AS_PROGRAM)->install_legacy_read_handler(0x0a130ec, 0x0a130ef, FUNC(_32x_68k_MARS_r)); // system ID
|
||||
|
||||
|
||||
/* Interrupts are masked / disabled at first */
|
||||
sh2_master_vint_enable = sh2_slave_vint_enable = 0;
|
||||
sh2_master_hint_enable = sh2_slave_hint_enable = 0;
|
||||
sh2_master_cmdint_enable = sh2_slave_cmdint_enable = 0;
|
||||
sh2_master_pwmint_enable = sh2_slave_pwmint_enable = 0;
|
||||
sh2_master_vint_pending = sh2_slave_vint_pending = 0;
|
||||
|
||||
// start in a reset state
|
||||
sh2_are_running = 0;
|
||||
|
||||
_32x_a1518a_reg = 0x00; // inital value
|
||||
_32x_68k_a15104_reg = 0x00;
|
||||
|
||||
_32x_autofill_length = 0;
|
||||
_32x_autofill_address = 0;
|
||||
_32x_autofill_data = 0;
|
||||
_32x_screenshift = 0;
|
||||
_32x_videopriority = 0; // MD priority
|
||||
_32x_displaymode = 0;
|
||||
_32x_240mode = 0;
|
||||
|
||||
// checking if these help brutal, they don't.
|
||||
sh2drc_set_options(machine().device("32x_master_sh2"), SH2DRC_COMPATIBLE_OPTIONS);
|
||||
sh2drc_set_options(machine().device("32x_slave_sh2"), SH2DRC_COMPATIBLE_OPTIONS);
|
||||
sh2drc_set_options(machine().device(_32X_MASTER_TAG), SH2DRC_COMPATIBLE_OPTIONS);
|
||||
sh2drc_set_options(machine().device(_32X_SLAVE_TAG), SH2DRC_COMPATIBLE_OPTIONS);
|
||||
|
||||
DRIVER_INIT_CALL(megadriv);
|
||||
}
|
||||
@ -1783,17 +1733,6 @@ int _32x_fifo_available_callback(device_t *device, UINT32 src, UINT32 dst, UINT3
|
||||
return 1;
|
||||
}
|
||||
|
||||
MACHINE_RESET( _32x )
|
||||
{
|
||||
current_fifo_block = fifo_block_a;
|
||||
current_fifo_readblock = fifo_block_b;
|
||||
current_fifo_write_pos = 0;
|
||||
current_fifo_read_pos = 0;
|
||||
fifo_block_a_full = 0;
|
||||
fifo_block_b_full = 0;
|
||||
|
||||
_32x_hcount_compare_val = -1;
|
||||
}
|
||||
|
||||
static UINT32 _32x_linerender[320+258]; // tmp buffer (bigger than it needs to be to simplify RLE decode)
|
||||
|
||||
@ -1906,3 +1845,168 @@ UINT32* _32x_render_videobuffer_to_screenbuffer_helper(running_machine &machine,
|
||||
|
||||
return _32x_linerender;
|
||||
}
|
||||
|
||||
static const sh2_cpu_core sh2_conf_master = { 0, NULL, _32x_fifo_available_callback };
|
||||
static const sh2_cpu_core sh2_conf_slave = { 1, NULL, _32x_fifo_available_callback };
|
||||
|
||||
#if 0
|
||||
// for now we just use the regular loading because we have 2 different BIOS roms, and you can't use -bios within a device for obvious reasons
|
||||
ROM_START( 32x )
|
||||
ROM_REGION( 0x400000, "32x_master_sh2", 0 )
|
||||
ROM_REGION( 0x400000, "32x_slave_sh2", 0 )
|
||||
ROM_END
|
||||
|
||||
const rom_entry *sega_32x_device::device_rom_region() const
|
||||
{
|
||||
return ROM_NAME( 32x );
|
||||
}
|
||||
|
||||
void sega_32x_device::device_config_complete()
|
||||
{
|
||||
m_shortname = "32x";
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
// brutal needs high levels of interleave or the background animations don't work
|
||||
// and some stages simply freeze the game, the is not good for performance however.
|
||||
//
|
||||
// some games appear to dislike 'perfect' levels of interleave, probably due to
|
||||
// non-emulated cache, ram waitstates and other issues?
|
||||
#define _32X_INTERLEAVE_LEVEL \
|
||||
MCFG_QUANTUM_TIME(attotime::from_hz(1800000)) \
|
||||
|
||||
|
||||
static MACHINE_CONFIG_FRAGMENT( _32x_ntsc )
|
||||
|
||||
#ifndef _32X_SWAP_MASTER_SLAVE_HACK
|
||||
MCFG_CPU_ADD("32x_master_sh2", SH2, (MASTER_CLOCK_NTSC*3)/7 )
|
||||
MCFG_CPU_PROGRAM_MAP(sh2_main_map)
|
||||
MCFG_CPU_CONFIG(sh2_conf_master)
|
||||
#endif
|
||||
|
||||
MCFG_CPU_ADD("32x_slave_sh2", SH2, (MASTER_CLOCK_NTSC*3)/7 )
|
||||
MCFG_CPU_PROGRAM_MAP(sh2_slave_map)
|
||||
MCFG_CPU_CONFIG(sh2_conf_slave)
|
||||
|
||||
#ifdef _32X_SWAP_MASTER_SLAVE_HACK
|
||||
MCFG_CPU_ADD("32x_master_sh2", SH2, (MASTER_CLOCK_NTSC*3)/7 )
|
||||
MCFG_CPU_PROGRAM_MAP(sh2_main_map)
|
||||
MCFG_CPU_CONFIG(sh2_conf_master)
|
||||
#endif
|
||||
|
||||
MCFG_DAC_ADD("lch_pwm")
|
||||
MCFG_SOUND_ROUTE(ALL_OUTPUTS, ":lspeaker", 0.40)
|
||||
|
||||
MCFG_DAC_ADD("rch_pwm")
|
||||
MCFG_SOUND_ROUTE(ALL_OUTPUTS, ":rspeaker", 0.40)
|
||||
|
||||
_32X_INTERLEAVE_LEVEL
|
||||
MACHINE_CONFIG_END
|
||||
|
||||
static MACHINE_CONFIG_FRAGMENT( _32x_pal )
|
||||
|
||||
#ifndef _32X_SWAP_MASTER_SLAVE_HACK
|
||||
MCFG_CPU_ADD("32x_master_sh2", SH2, (MASTER_CLOCK_PAL*3)/7 )
|
||||
MCFG_CPU_PROGRAM_MAP(sh2_main_map)
|
||||
MCFG_CPU_CONFIG(sh2_conf_master)
|
||||
#endif
|
||||
|
||||
MCFG_CPU_ADD("32x_slave_sh2", SH2, (MASTER_CLOCK_PAL*3)/7 )
|
||||
MCFG_CPU_PROGRAM_MAP(sh2_slave_map)
|
||||
MCFG_CPU_CONFIG(sh2_conf_slave)
|
||||
|
||||
#ifdef _32X_SWAP_MASTER_SLAVE_HACK
|
||||
MCFG_CPU_ADD("32x_master_sh2", SH2, (MASTER_CLOCK_PAL*3)/7 )
|
||||
MCFG_CPU_PROGRAM_MAP(sh2_main_map)
|
||||
MCFG_CPU_CONFIG(sh2_conf_master)
|
||||
#endif
|
||||
|
||||
MCFG_DAC_ADD("lch_pwm")
|
||||
MCFG_SOUND_ROUTE(ALL_OUTPUTS, ":lspeaker", 0.40)
|
||||
|
||||
MCFG_DAC_ADD("rch_pwm")
|
||||
MCFG_SOUND_ROUTE(ALL_OUTPUTS, ":rspeaker", 0.40)
|
||||
|
||||
_32X_INTERLEAVE_LEVEL
|
||||
MACHINE_CONFIG_END
|
||||
|
||||
|
||||
|
||||
machine_config_constructor sega_32x_device::device_mconfig_additions() const
|
||||
{
|
||||
return MACHINE_CONFIG_NAME( _32x_ntsc );
|
||||
}
|
||||
|
||||
machine_config_constructor sega_32x_pal_device::device_mconfig_additions() const
|
||||
{
|
||||
return MACHINE_CONFIG_NAME( _32x_pal );
|
||||
}
|
||||
|
||||
|
||||
void sega_32x_device::device_start()
|
||||
{
|
||||
m_32x_pwm_timer = machine().scheduler().timer_alloc(FUNC(_32x_pwm_callback), (void*)this);
|
||||
m_32x_pwm_timer->adjust(attotime::never);
|
||||
|
||||
_32x_dram0 = auto_alloc_array(machine(), UINT16, 0x40000/2);
|
||||
_32x_dram1 = auto_alloc_array(machine(), UINT16, 0x40000/2);
|
||||
|
||||
memset(_32x_dram0, 0x00, 0x40000);
|
||||
memset(_32x_dram1, 0x00, 0x40000);
|
||||
|
||||
_32x_palette_lookup = auto_alloc_array(machine(), UINT16, 0x200/2);
|
||||
_32x_palette = auto_alloc_array(machine(), UINT16, 0x200/2);
|
||||
|
||||
memset(_32x_palette_lookup, 0x00, 0x200);
|
||||
memset(_32x_palette, 0x00, 0x200);
|
||||
|
||||
_32x_display_dram = _32x_dram0;
|
||||
_32x_access_dram = _32x_dram1;
|
||||
}
|
||||
|
||||
void sega_32x_device::device_reset()
|
||||
{
|
||||
/* Interrupts are masked / disabled at first */
|
||||
sh2_master_vint_enable = sh2_slave_vint_enable = 0;
|
||||
sh2_master_hint_enable = sh2_slave_hint_enable = 0;
|
||||
sh2_master_cmdint_enable = sh2_slave_cmdint_enable = 0;
|
||||
sh2_master_pwmint_enable = sh2_slave_pwmint_enable = 0;
|
||||
sh2_master_vint_pending = sh2_slave_vint_pending = 0;
|
||||
|
||||
// start in a reset state
|
||||
sh2_are_running = 0;
|
||||
|
||||
_32x_a1518a_reg = 0x00; // inital value
|
||||
_32x_68k_a15104_reg = 0x00;
|
||||
|
||||
_32x_autofill_length = 0;
|
||||
_32x_autofill_address = 0;
|
||||
_32x_autofill_data = 0;
|
||||
_32x_screenshift = 0;
|
||||
_32x_videopriority = 0; // MD priority
|
||||
_32x_displaymode = 0;
|
||||
_32x_240mode = 0;
|
||||
|
||||
|
||||
current_fifo_block = fifo_block_a;
|
||||
current_fifo_readblock = fifo_block_b;
|
||||
current_fifo_write_pos = 0;
|
||||
current_fifo_read_pos = 0;
|
||||
fifo_block_a_full = 0;
|
||||
fifo_block_b_full = 0;
|
||||
|
||||
_32x_hcount_compare_val = -1;
|
||||
|
||||
// install these now, otherwise we'll get the following (incorrect) warnings on startup..
|
||||
// SH-2 device ':sega32x:32x_slave_sh2': program space memory map entry 0-3FFF references non-existant region ':slave'
|
||||
// SH-2 device ':sega32x:32x_master_sh2': program space memory map entry 0-3FFF references non-existant region ':master'
|
||||
UINT8* masterbios = (UINT8*)machine().root_device().memregion(":master")->base();
|
||||
UINT8* slavebios = (UINT8*)machine().root_device().memregion(":slave")->base();
|
||||
membank("masterbios")->configure_entries(0, 1, masterbios, 0x4000);
|
||||
membank("slavebios")->configure_entries(0, 1, slavebios, 0x4000);
|
||||
membank("masterbios")->set_entry(0);
|
||||
membank("slavebios")->set_entry(0);
|
||||
}
|
||||
|
||||
|
||||
|
||||
68
src/mame/machine/mega32x.h
Normal file
68
src/mame/machine/mega32x.h
Normal file
@ -0,0 +1,68 @@
|
||||
/* 32X */
|
||||
|
||||
|
||||
// Fifa96 needs the CPUs swapped for the gameplay to enter due to some race conditions
|
||||
// when using the DRC core. Needs further investigation, the non-DRC core works either
|
||||
// way
|
||||
#define _32X_SWAP_MASTER_SLAVE_HACK
|
||||
|
||||
|
||||
#include "sound/dac.h"
|
||||
|
||||
#define _32X_MASTER_TAG (":sega32x:32x_master_sh2")
|
||||
#define _32X_SLAVE_TAG (":sega32x:32x_slave_sh2")
|
||||
|
||||
|
||||
class sega_32x_device : public device_t
|
||||
{
|
||||
public:
|
||||
sega_32x_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock, device_type type);
|
||||
|
||||
required_device<dac_device> m_lch_pwm;
|
||||
required_device<dac_device> m_rch_pwm;
|
||||
|
||||
DECLARE_READ32_MEMBER( _32x_sh2_master_4000_common_4002_r );
|
||||
DECLARE_READ32_MEMBER( _32x_sh2_slave_4000_common_4002_r );
|
||||
DECLARE_READ32_MEMBER( _32x_sh2_common_4004_common_4006_r );
|
||||
DECLARE_WRITE32_MEMBER( _32x_sh2_master_4000_common_4002_w );
|
||||
DECLARE_WRITE32_MEMBER( _32x_sh2_slave_4000_common_4002_w );
|
||||
DECLARE_WRITE32_MEMBER( _32x_sh2_common_4004_common_4006_w );
|
||||
DECLARE_WRITE32_MEMBER( _32x_sh2_master_4014_master_4016_w );
|
||||
DECLARE_WRITE32_MEMBER( _32x_sh2_master_4018_master_401a_w );
|
||||
DECLARE_WRITE32_MEMBER( _32x_sh2_master_401c_master_401e_w );
|
||||
DECLARE_WRITE32_MEMBER( _32x_sh2_slave_4014_slave_4016_w );
|
||||
DECLARE_WRITE32_MEMBER( _32x_sh2_slave_4018_slave_401a_w );
|
||||
DECLARE_WRITE32_MEMBER( _32x_sh2_slave_401c_slave_401e_w );
|
||||
|
||||
|
||||
emu_timer *m_32x_pwm_timer;
|
||||
protected:
|
||||
virtual void device_start();
|
||||
virtual void device_reset();
|
||||
|
||||
// optional information overrides
|
||||
// virtual const rom_entry *device_rom_region() const;
|
||||
virtual machine_config_constructor device_mconfig_additions() const;
|
||||
private:
|
||||
// virtual void device_config_complete();
|
||||
};
|
||||
|
||||
|
||||
class sega_32x_ntsc_device : public sega_32x_device
|
||||
{
|
||||
public:
|
||||
sega_32x_ntsc_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
|
||||
|
||||
};
|
||||
|
||||
class sega_32x_pal_device : public sega_32x_device
|
||||
{
|
||||
public:
|
||||
sega_32x_pal_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
|
||||
protected:
|
||||
virtual machine_config_constructor device_mconfig_additions() const;
|
||||
};
|
||||
|
||||
|
||||
extern const device_type SEGA_32X_NTSC;
|
||||
extern const device_type SEGA_32X_PAL;
|
||||
@ -1032,11 +1032,6 @@ MACHINE_RESET( megadriv )
|
||||
MACHINE_RESET_CALL( segacd );
|
||||
}
|
||||
|
||||
|
||||
if(_32x_is_connected)
|
||||
{
|
||||
MACHINE_RESET_CALL(_32x);
|
||||
}
|
||||
}
|
||||
|
||||
void megadriv_stop_scanline_timer(running_machine &machine)
|
||||
@ -1237,46 +1232,22 @@ MACHINE_CONFIG_FRAGMENT( md_pal )
|
||||
MCFG_SOUND_ROUTE(ALL_OUTPUTS, "rspeaker",0.25) /* 3.58 MHz */
|
||||
MACHINE_CONFIG_END
|
||||
|
||||
MACHINE_CONFIG_START( megadpal, driver_device )
|
||||
MACHINE_CONFIG_START( megadpal, md_cons_state )
|
||||
MCFG_FRAGMENT_ADD(md_pal)
|
||||
MACHINE_CONFIG_END
|
||||
|
||||
|
||||
|
||||
static const sh2_cpu_core sh2_conf_master = { 0, NULL, _32x_fifo_available_callback };
|
||||
static const sh2_cpu_core sh2_conf_slave = { 1, NULL, _32x_fifo_available_callback };
|
||||
|
||||
MACHINE_CONFIG_DERIVED( genesis_32x, megadriv )
|
||||
|
||||
#ifndef _32X_SWAP_MASTER_SLAVE_HACK
|
||||
MCFG_CPU_ADD("32x_master_sh2", SH2, (MASTER_CLOCK_NTSC*3)/7 )
|
||||
MCFG_CPU_PROGRAM_MAP(sh2_main_map)
|
||||
MCFG_CPU_CONFIG(sh2_conf_master)
|
||||
#endif
|
||||
|
||||
MCFG_CPU_ADD("32x_slave_sh2", SH2, (MASTER_CLOCK_NTSC*3)/7 )
|
||||
MCFG_CPU_PROGRAM_MAP(sh2_slave_map)
|
||||
MCFG_CPU_CONFIG(sh2_conf_slave)
|
||||
|
||||
#ifdef _32X_SWAP_MASTER_SLAVE_HACK
|
||||
MCFG_CPU_ADD("32x_master_sh2", SH2, (MASTER_CLOCK_NTSC*3)/7 )
|
||||
MCFG_CPU_PROGRAM_MAP(sh2_main_map)
|
||||
MCFG_CPU_CONFIG(sh2_conf_master)
|
||||
#endif
|
||||
|
||||
// brutal needs at least 30000 or the backgrounds don't animate properly / lock up, and the game
|
||||
// freezes. Some stage seem to need as high as 80000 ? this *KILLS* performance
|
||||
//
|
||||
// boosting the interleave here actually makes Kolibri run incorrectly however, that
|
||||
// one works best just boosting the interleave on communications?!
|
||||
MCFG_QUANTUM_TIME(attotime::from_hz(1800000))
|
||||
MCFG_DEVICE_ADD("sega32x", SEGA_32X_NTSC, 0)
|
||||
|
||||
// we need to remove and re-add the sound system because the balance is different
|
||||
// due to MAME / MESS having severe issues if the dac output is > 0.40? (sound is corrupted even if DAC is slient?!)
|
||||
MCFG_DEVICE_REMOVE("ymsnd")
|
||||
MCFG_DEVICE_REMOVE("snsnd")
|
||||
|
||||
|
||||
MCFG_SOUND_ADD("ymsnd", YM2612, MASTER_CLOCK_NTSC/7)
|
||||
MCFG_SOUND_ROUTE(0, "lspeaker", (0.50)/2)
|
||||
MCFG_SOUND_ROUTE(1, "rspeaker", (0.50)/2)
|
||||
@ -1286,59 +1257,27 @@ MACHINE_CONFIG_DERIVED( genesis_32x, megadriv )
|
||||
MCFG_SOUND_ROUTE(ALL_OUTPUTS, "lspeaker", (0.25)/2)
|
||||
MCFG_SOUND_ROUTE(ALL_OUTPUTS, "rspeaker", (0.25)/2)
|
||||
|
||||
MCFG_DAC_ADD("lch_pwm")
|
||||
MCFG_SOUND_ROUTE(ALL_OUTPUTS, "lspeaker", 0.40)
|
||||
|
||||
MCFG_DAC_ADD("rch_pwm")
|
||||
MCFG_SOUND_ROUTE(ALL_OUTPUTS, "rspeaker", 0.40)
|
||||
MACHINE_CONFIG_END
|
||||
|
||||
|
||||
MACHINE_CONFIG_DERIVED( genesis_32x_pal, megadpal )
|
||||
|
||||
#ifndef _32X_SWAP_MASTER_SLAVE_HACK
|
||||
MCFG_CPU_ADD("32x_master_sh2", SH2, (MASTER_CLOCK_PAL*3)/7 )
|
||||
MCFG_CPU_PROGRAM_MAP(sh2_main_map)
|
||||
MCFG_CPU_CONFIG(sh2_conf_master)
|
||||
#endif
|
||||
|
||||
MCFG_CPU_ADD("32x_slave_sh2", SH2, (MASTER_CLOCK_PAL*3)/7 )
|
||||
MCFG_CPU_PROGRAM_MAP(sh2_slave_map)
|
||||
MCFG_CPU_CONFIG(sh2_conf_slave)
|
||||
|
||||
#ifdef _32X_SWAP_MASTER_SLAVE_HACK
|
||||
MCFG_CPU_ADD("32x_master_sh2", SH2, (MASTER_CLOCK_PAL*3)/7 )
|
||||
MCFG_CPU_PROGRAM_MAP(sh2_main_map)
|
||||
MCFG_CPU_CONFIG(sh2_conf_master)
|
||||
#endif
|
||||
|
||||
// brutal needs at least 30000 or the backgrounds don't animate properly / lock up, and the game
|
||||
// freezes. Some stage seem to need as high as 80000 ? this *KILLS* performance
|
||||
//
|
||||
// boosting the interleave here actually makes Kolibri run incorrectly however, that
|
||||
// one works best just boosting the interleave on communications?!
|
||||
MCFG_QUANTUM_TIME(attotime::from_hz(1800000))
|
||||
MCFG_DEVICE_ADD("sega32x", SEGA_32X_PAL, 0)
|
||||
|
||||
// we need to remove and re-add the sound system because the balance is different
|
||||
// due to MAME / MESS having severe issues if the dac output is > 0.40? (sound is corrupted even if DAC is slient?!)
|
||||
MCFG_DEVICE_REMOVE("ymsnd")
|
||||
MCFG_DEVICE_REMOVE("snsnd")
|
||||
|
||||
|
||||
MCFG_SOUND_ADD("ymsnd", YM2612, MASTER_CLOCK_PAL/7)
|
||||
MCFG_SOUND_ADD("ymsnd", YM2612, MASTER_CLOCK_NTSC/7)
|
||||
MCFG_SOUND_ROUTE(0, "lspeaker", (0.50)/2)
|
||||
MCFG_SOUND_ROUTE(1, "rspeaker", (0.50)/2)
|
||||
|
||||
/* sound hardware */
|
||||
MCFG_SOUND_ADD("snsnd", SEGAPSG, MASTER_CLOCK_PAL/15)
|
||||
MCFG_SOUND_ADD("snsnd", SEGAPSG, MASTER_CLOCK_NTSC/15)
|
||||
MCFG_SOUND_ROUTE(ALL_OUTPUTS, "lspeaker", (0.25)/2)
|
||||
MCFG_SOUND_ROUTE(ALL_OUTPUTS, "rspeaker", (0.25)/2)
|
||||
|
||||
MCFG_DAC_ADD("lch_pwm")
|
||||
MCFG_SOUND_ROUTE(ALL_OUTPUTS, "lspeaker", 0.40)
|
||||
|
||||
MCFG_DAC_ADD("rch_pwm")
|
||||
MCFG_SOUND_ROUTE(ALL_OUTPUTS, "rspeaker", 0.40)
|
||||
MACHINE_CONFIG_END
|
||||
|
||||
|
||||
@ -1410,7 +1349,7 @@ MACHINE_CONFIG_DERIVED( genesis_32x_scd, genesis_32x )
|
||||
MCFG_CDROM_ADD( "cdrom", scd_cdrom)
|
||||
MCFG_SOFTWARE_LIST_ADD("cd_list","segacd")
|
||||
|
||||
MCFG_QUANTUM_PERFECT_CPU("32x_master_sh2")
|
||||
//MCFG_QUANTUM_PERFECT_CPU("32x_master_sh2")
|
||||
MACHINE_CONFIG_END
|
||||
|
||||
|
||||
@ -1434,14 +1373,14 @@ static void megadriv_init_common(running_machine &machine)
|
||||
}
|
||||
|
||||
/* Look to see if this system has the 32x Master SH2 */
|
||||
_32x_master_cpu = machine.device<cpu_device>("32x_master_sh2");
|
||||
_32x_master_cpu = machine.device<cpu_device>(_32X_MASTER_TAG);
|
||||
if (_32x_master_cpu != NULL)
|
||||
{
|
||||
printf("32x MASTER SH2 cpu found '%s'\n", _32x_master_cpu->tag() );
|
||||
}
|
||||
|
||||
/* Look to see if this system has the 32x Slave SH2 */
|
||||
_32x_slave_cpu = machine.device<cpu_device>("32x_slave_sh2");
|
||||
_32x_slave_cpu = machine.device<cpu_device>(_32X_SLAVE_TAG);
|
||||
if (_32x_slave_cpu != NULL)
|
||||
{
|
||||
printf("32x SLAVE SH2 cpu found '%s'\n", _32x_slave_cpu->tag() );
|
||||
@ -1456,11 +1395,7 @@ static void megadriv_init_common(running_machine &machine)
|
||||
_32x_is_connected = 0;
|
||||
}
|
||||
|
||||
if(_32x_is_connected)
|
||||
{
|
||||
_32x_pwm_timer = machine.scheduler().timer_alloc(FUNC(_32x_pwm_callback));
|
||||
_32x_pwm_timer->adjust(attotime::never);
|
||||
}
|
||||
|
||||
|
||||
sega_cd_connected = 0;
|
||||
segacd_wordram_mapped = 0;
|
||||
|
||||
@ -487,12 +487,12 @@ MACHINE_CONFIG_END
|
||||
/* temp, rom should only be visible here when one of the regs is set, tempo needs it */ \
|
||||
/* ROM_CART_LOAD("cart", 0x000000, 0x400000, ROM_NOMIRROR) */ \
|
||||
ROM_COPY( "32x_68k_bios", 0x0, 0x0, 0x100) \
|
||||
ROM_REGION( 0x400000, "32x_master_sh2", 0 ) /* SH2 Code */ \
|
||||
ROM_REGION32_BE( 0x400000, "master", 0 ) /* SH2 Code */ \
|
||||
ROM_SYSTEM_BIOS( 0, "retail", "Mars Version 1.0 (retail)" ) \
|
||||
ROMX_LOAD( "32x_m_bios.bin", 0x000000, 0x000800, CRC(dd9c46b8) SHA1(1e5b0b2441a4979b6966d942b20cc76c413b8c5e), ROM_BIOS(1) ) \
|
||||
ROM_SYSTEM_BIOS( 1, "sdk", "Mars Version 1.0 (early sdk)" ) \
|
||||
ROMX_LOAD( "32x_m_bios_sdk.bin", 0x000000, 0x000800, BAD_DUMP CRC(c7102c53) SHA1(ed73a47f186b373b8eff765f84ef26c3d9ef6cb0), ROM_BIOS(2) ) \
|
||||
ROM_REGION( 0x400000, "32x_slave_sh2", 0 ) /* SH2 Code */ \
|
||||
ROM_REGION32_BE( 0x400000, "slave", 0 ) /* SH2 Code */ \
|
||||
ROM_LOAD( "32x_s_bios.bin", 0x000000, 0x000400, CRC(bfda1fe5) SHA1(4103668c1bbd66c5e24558e73d4f3f92061a109a) ) \
|
||||
|
||||
|
||||
@ -638,10 +638,10 @@ ROM_START( 32x_scd )
|
||||
ROM_REGION16_BE( 0x400000, "32x_68k_bios", 0 ) /* 68000 Code */
|
||||
ROM_LOAD( "32x_g_bios.bin", 0x000000, 0x000100, CRC(5c12eae8) SHA1(dbebd76a448447cb6e524ac3cb0fd19fc065d944) )
|
||||
|
||||
ROM_REGION( 0x400000, "32x_master_sh2", 0 ) /* SH2 Code */
|
||||
ROM_REGION32_BE( 0x400000, "32x_master_sh2", 0 ) /* SH2 Code */
|
||||
ROM_LOAD( "32x_m_bios.bin", 0x000000, 0x000800, CRC(dd9c46b8) SHA1(1e5b0b2441a4979b6966d942b20cc76c413b8c5e) )
|
||||
|
||||
ROM_REGION( 0x400000, "32x_slave_sh2", 0 ) /* SH2 Code */
|
||||
ROM_REGION32_BE( 0x400000, "32x_slave_sh2", 0 ) /* SH2 Code */
|
||||
ROM_LOAD( "32x_s_bios.bin", 0x000000, 0x000400, CRC(bfda1fe5) SHA1(4103668c1bbd66c5e24558e73d4f3f92061a109a) )
|
||||
ROM_END
|
||||
|
||||
|
||||
Loading…
Reference in New Issue
Block a user