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https://github.com/holub/mame
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Merge pull request #804 from JoakimLarsson/iscsi1
New driver for the Force Computers ISCSI-1 VME board, skeleton missin…
This commit is contained in:
R. Belmont
commit
736979c0be
359
src/mame/drivers/fcscsi.cpp
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359
src/mame/drivers/fcscsi.cpp
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@ -0,0 +1,359 @@
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// license:BSD-3-Clause
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// copyright-holders:Joakim Larsson Edstrom
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/***************************************************************************
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* Interrupt scheme and dmac hookup shamelessly based on esq5505.cpp
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*
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* 11/04/2016
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* Force SYS68K ISCSI-1 driver - This driver will be converted into a slot device once the VME bus driver exists.
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* The ISCSI-1 board is a VME slave board that reads command and returns results through dual ported RAM to the VME bus.
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*
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* http://bitsavers.trailing-edge.com/pdf/forceComputers/800114_Force_Introduction_to_the_SYS68K_ISCSI-1_Oct86.pdf
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*
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* Address Map
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* ----------------------------------------------------------
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* Address Range Description
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* ----------------------------------------------------------
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* 00 0000 - 00 0007 Initialisation vectors from system EPROM
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* 00 0008 - 00 1FFF Local SRAM
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* 00 2000 - 01 FFFF Dynamic Dual Port RAM
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* C4 0000 - C4 001F SCSIbus controller
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* C8 0000 - C8 00FF DMAC
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* CC 0000 - CC 0007 FDC
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* CC 0009 - CC 0009 Control Register
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* D0 0000 - D0 003F PI/T
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* E0 0000 - E7 0000 EPROMs
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* ----------------------------------------------------------
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*
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* Interrupt sources
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* ----------------------------------------------------------
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* Description Device Lvl IRQ VME board
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* /Board Vector Address
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* ----------------------------------------------------------
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* On board Sources
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* ABORT P3 p13 1 AV1
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* DMA controller 68450 2 DMAC/AV2
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* SCSI bus controller NCR 5386S 3 AV3
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* Floppy Disk controller WD 1772 4 AV4
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* Parallel interface and timer 68230 5 PIT timer
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* --- 6 ---
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* Parallel interface and timer 65230 7 PIT port
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* ----------------------------------------------------------
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*
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* TODO:
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* - Write and attach a NCR5386S SCSI device
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* - Find a floppy image and present it to the WD1772 floppy controller
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* - Add VME bus driver
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* - Let a controller CPU board (eg CPU-1 or CPU-30) boot from floppy or SCSI disk
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*
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****************************************************************************/
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#define TODO "Driver for SCSI NCR5386s device needed\n"
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#include "emu.h"
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#include "cpu/m68000/m68000.h"
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#include "machine/68230pit.h"
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#include "machine/wd_fdc.h"
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#include "machine/hd63450.h" // compatible with MC68450
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#include "machine/clock.h"
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#define VERBOSE 0
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#define LOG(x) do { if (VERBOSE) logerror x; } while (0)
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#if VERBOSE == 2
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#define logerror printf
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#endif
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#ifdef _MSC_VER
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#define FUNCNAME __func__
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#define LLFORMAT "%I64%"
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#else
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#define FUNCNAME __PRETTY_FUNCTION__
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#define LLFORMAT "%lld"
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#endif
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#define CPU_CRYSTAL XTAL_20MHz /* Jauch */
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#define PIT_CRYSTAL XTAL_16MHz /* Jauch */
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class fcscsi1_state : public driver_device
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{
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public:
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fcscsi1_state(const machine_config &mconfig, device_type type, const char *tag) :
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driver_device (mconfig, type, tag),
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m_maincpu (*this, "maincpu")
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,m_fdc (*this, "fdc")
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,m_pit (*this, "pit")
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,m_dmac(*this, "mc68450")
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,m_tcr (0)
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{
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}
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DECLARE_READ16_MEMBER (bootvect_r);
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DECLARE_READ8_MEMBER (tcr_r);
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DECLARE_WRITE8_MEMBER (tcr_w);
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IRQ_CALLBACK_MEMBER(maincpu_irq_acknowledge_callback);
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//dmac
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DECLARE_WRITE8_MEMBER(dma_end);
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DECLARE_WRITE8_MEMBER(dma_error);
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//fdc
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DECLARE_WRITE8_MEMBER(fdc_irq);
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DECLARE_READ8_MEMBER(fdc_read_byte);
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DECLARE_WRITE8_MEMBER(fdc_write_byte);
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/* Dummy driver routines */
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DECLARE_READ8_MEMBER (not_implemented_r);
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DECLARE_WRITE8_MEMBER (not_implemented_w);
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UINT8 fdc_irq_state;
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UINT8 dmac_irq_state;
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int dmac_irq_vector;
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virtual void machine_start () override;
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void update_irq_to_maincpu();
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protected:
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private:
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required_device<cpu_device> m_maincpu;
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required_device<wd1772_t> m_fdc;
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required_device<pit68230_device> m_pit;
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required_device<hd63450_device> m_dmac;
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UINT8 m_tcr;
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// Pointer to System ROMs needed by bootvect_r
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UINT16 *m_sysrom;
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};
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static ADDRESS_MAP_START (fcscsi1_mem, AS_PROGRAM, 16, fcscsi1_state)
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ADDRESS_MAP_UNMAP_HIGH
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AM_RANGE (0x000000, 0x000007) AM_ROM AM_READ (bootvect_r) /* Vectors mapped from System EPROM */
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AM_RANGE (0x000008, 0x001fff) AM_RAM /* SRAM */
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AM_RANGE (0x002000, 0x01ffff) AM_RAM /* Dual Ported RAM */
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AM_RANGE (0xe00000, 0xe7ffff) AM_ROM /* System EPROM Area 32Kb DEBUGGER supplied */
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AM_RANGE (0xd00000, 0xd0003f) AM_DEVREADWRITE8 ("pit", pit68230_device, read, write, 0x00ff)
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//AM_RANGE (0xc40000, 0xc4001f) AM_DEVREADWRITE8("scsi", ncr5386s_t, read, write, 0x00ff) /* SCSI Controller interface - device support not yet available*/
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AM_RANGE (0xc80000, 0xc800ff) AM_DEVREADWRITE("mc68450", hd63450_device, read, write) /* DMA Controller interface */
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AM_RANGE (0xc40000, 0xc800ff) AM_READWRITE8 (not_implemented_r, not_implemented_w, 0xffff) /* Dummy mapping af address area to display message */
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AM_RANGE (0xcc0000, 0xcc0007) AM_DEVREADWRITE8("fdc", wd1772_t, read, write, 0x00ff) /* Floppy Controller interface */
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AM_RANGE (0xcc0008, 0xcc0009) AM_READWRITE8 (tcr_r, tcr_w, 0x00ff) /* The Control Register, SCSI ID and FD drive select bits */
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ADDRESS_MAP_END
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/* Input ports */
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static INPUT_PORTS_START (fcscsi1)
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INPUT_PORTS_END
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/* Start it up */
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void fcscsi1_state::machine_start ()
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{
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LOG (("machine_start\n"));
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/* Setup pointer to bootvector in ROM for bootvector handler bootvect_r */
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m_sysrom = (UINT16*)(memregion ("maincpu")->base () + 0xe00000);
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}
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/* Boot vector handler, the PCB hardwires the first 8 bytes from 0x80000 to 0x0 */
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READ16_MEMBER (fcscsi1_state::bootvect_r){
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return m_sysrom [offset];
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}
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/* The Control Register - descretelly implemented on the PCB
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Bit #: 7 6 5 4 3 2 1 0
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\ \ \ \ \ \ \ \ Floppy Disk Side Select
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\ \ \ \ \ \ \ Floppy Disk Drive Select 0
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\ \ \ \ \ \ Floppy Disk Drive Select 1
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\ \ \ \ \ Floppy Disk Drive Select 2
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\ \ \ \ Floppy Disk Drive Select 3
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\ \ \ ISCSI-l I.D. Bit #0
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\ \ ISCSI-l I.D. Bit #1
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\ ISCSI-l 1.D. Bit #2
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*/
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READ8_MEMBER (fcscsi1_state::tcr_r){
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LOG(("%s\n", FUNCNAME));
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return (UINT8) m_tcr;
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}
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WRITE8_MEMBER (fcscsi1_state::tcr_w){
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LOG(("%s [%02x]\n", FUNCNAME, data));
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m_tcr = data;
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return;
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}
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WRITE8_MEMBER(fcscsi1_state::dma_end)
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{
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if (data != 0)
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{
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dmac_irq_state = 1;
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dmac_irq_vector = m_dmac->get_vector(offset);
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}
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else
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{
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dmac_irq_state = 0;
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}
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update_irq_to_maincpu();
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}
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WRITE8_MEMBER(fcscsi1_state::dma_error)
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{
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if(data != 0)
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{
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logerror("DMAC error, vector = %x\n", m_dmac->get_error_vector(offset));
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dmac_irq_state = 1;
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dmac_irq_vector = m_dmac->get_vector(offset);
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}
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else
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{
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dmac_irq_state = 0;
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}
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update_irq_to_maincpu();
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}
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WRITE8_MEMBER(fcscsi1_state::fdc_irq)
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{
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if (data != 0)
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{
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fdc_irq_state = 1;
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}
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else
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{
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fdc_irq_state = 0;
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}
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update_irq_to_maincpu();
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}
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READ8_MEMBER(fcscsi1_state::fdc_read_byte)
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{
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return m_fdc->data_r();
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}
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WRITE8_MEMBER(fcscsi1_state::fdc_write_byte)
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{
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m_fdc->data_w(data & 0xff);
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}
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READ8_MEMBER (fcscsi1_state::not_implemented_r){
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static int been_here = 0;
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if (!been_here++){
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logerror(TODO);
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printf(TODO);
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}
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return (UINT8) 0;
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}
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WRITE8_MEMBER (fcscsi1_state::not_implemented_w){
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static int been_here = 0;
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if (!been_here++){
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logerror(TODO);
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printf(TODO);
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}
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return;
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}
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/*
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----------------------------------------------------
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IRQ IRQ
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Level Source B4l inserted B4l removed (Def)
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-----------------------------------------------------
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1 P3 Pin #13 AV1 Autovector AV1 Autovector
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2 DMAC DMAC AV2 Autovector
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3 SCSIBC AV3 Autovector AV3 Autovector
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4 FDC AV4 Autovector AV4 Autovector
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5 PI/T Timer PI/T Timer Vect PI/T Timer Vect
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6 -- -- --
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7 PI/T Port PI/T Port Vect PI/T Port Vect
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------------------------------------------------------
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Default configuration: B41 jumper removed
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The PI/T port interrupt can be used under software control to
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cause non-maskable (Level 7) interrupts if the watchdog timer
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elapses and/or if the VMEbus interrupt trigger call occurs.
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*/
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/* TODO: Add configurable B41 jumper */
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#define B41 0
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void fcscsi1_state::update_irq_to_maincpu() {
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if (fdc_irq_state) {
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m_maincpu->set_input_line(M68K_IRQ_3, ASSERT_LINE);
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m_maincpu->set_input_line(M68K_IRQ_2, CLEAR_LINE);
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m_maincpu->set_input_line(M68K_IRQ_1, CLEAR_LINE);
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} else if (dmac_irq_state) {
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m_maincpu->set_input_line(M68K_IRQ_3, CLEAR_LINE);
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m_maincpu->set_input_line(M68K_IRQ_1, CLEAR_LINE);
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#if B41 == 1
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m_maincpu->set_input_line_and_vector(M68K_IRQ_2, ASSERT_LINE, dmac_irq_vector);
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#else
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m_maincpu->set_input_line(M68K_IRQ_2, ASSERT_LINE);
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#endif
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} else {
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m_maincpu->set_input_line(M68K_IRQ_3, CLEAR_LINE);
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m_maincpu->set_input_line(M68K_IRQ_2, CLEAR_LINE);
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m_maincpu->set_input_line(M68K_IRQ_1, CLEAR_LINE);
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}
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}
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IRQ_CALLBACK_MEMBER(fcscsi1_state::maincpu_irq_acknowledge_callback)
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{
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// We immediately update the interrupt presented to the CPU, so that it doesn't
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// end up retrying the same interrupt over and over. We then return the appropriate vector.
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int vector = 0;
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switch(irqline) {
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case 2:
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dmac_irq_state = 0;
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vector = dmac_irq_vector;
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break;
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default:
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logerror("\nUnexpected IRQ ACK Callback: IRQ %d\n", irqline);
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return 0;
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}
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update_irq_to_maincpu();
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return vector;
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}
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/*
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* Machine configuration
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*/
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static MACHINE_CONFIG_START (fcscsi1, fcscsi1_state)
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/* basic machine hardware */
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MCFG_CPU_ADD ("maincpu", M68010, CPU_CRYSTAL / 2) /* 7474 based frequency divide by 2 */
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MCFG_CPU_PROGRAM_MAP (fcscsi1_mem)
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MCFG_CPU_IRQ_ACKNOWLEDGE_DRIVER(fcscsi1_state, maincpu_irq_acknowledge_callback)
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/* FDC */
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MCFG_WD1772_ADD("fdc", CPU_CRYSTAL / 2) /* Same clock divider as for the CPU */
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MCFG_WD_FDC_INTRQ_CALLBACK(WRITE8(fcscsi1_state, fdc_irq))
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/* PIT Parallel Interface and Timer device */
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MCFG_DEVICE_ADD ("pit", PIT68230, PIT_CRYSTAL / 2) /* 7474 based frequency divide by 2 */
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/* DMAC it is really a M68450 but the HD63850 is upwards compatible */
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MCFG_DEVICE_ADD("mc68450", HD63450, 0) // MC68450 compatible
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MCFG_HD63450_CPU("maincpu") // CPU - 68010
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MCFG_HD63450_CLOCKS(attotime::from_usec(32), attotime::from_nsec(450), attotime::from_usec(4), attotime::from_hz(15625/2))
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MCFG_HD63450_BURST_CLOCKS(attotime::from_usec(32), attotime::from_nsec(450), attotime::from_nsec(50), attotime::from_nsec(50))
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MCFG_HD63450_DMA_END_CB(WRITE8(fcscsi1_state, dma_end))
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MCFG_HD63450_DMA_ERROR_CB(WRITE8(fcscsi1_state, dma_error))
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//MCFG_HD63450_DMA_READ_0_CB(READ8(fcscsi1_state, scsi_read_byte)) // ch 0 = SCSI
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//MCFG_HD63450_DMA_WRITE_0_CB(WRITE8(fcscsi1_state, scsi_write_byte))
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MCFG_HD63450_DMA_READ_1_CB(READ8(fcscsi1_state, fdc_read_byte)) // ch 1 = fdc
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MCFG_HD63450_DMA_WRITE_1_CB(WRITE8(fcscsi1_state, fdc_write_byte))
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MACHINE_CONFIG_END
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/* ROM definitions */
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ROM_START (fcscsi1)
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ROM_REGION (0x1000000, "maincpu", 0)
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/* Besta ROM:s */
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ROM_LOAD16_BYTE ("besta88_scsi_lower.ROM", 0xe00001, 0x4000, CRC (fb3ab364) SHA1 (d79112100f1c4beaf358e006efd4dde5e300b0ba))
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ROM_LOAD16_BYTE ("besta88_scsi_upper.ROM", 0xe00000, 0x4000, CRC (41f9cdf4) SHA1 (66b998bbf9459f0a613718260e05e97749532073))
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ROM_END
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/* Driver */
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/* YEAR NAME PARENT COMPAT MACHINE INPUT CLASS INIT COMPANY FULLNAME FLAGS */
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COMP( 1986, fcscsi1, 0, 0, fcscsi1, fcscsi1, driver_device, 0, "Force Computers Gmbh", "SYS68K/SCSI-1", MACHINE_IS_SKELETON )
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@ -12075,6 +12075,9 @@ fb01 // 1986 FB-01
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@source:fc100.cpp
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fc100 //
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@source:fcscsi.cpp
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fcscsi1 //
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@source:fcombat.cpp
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fcombat // (c) 1985 Jaleco
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