srcclean in preparation for branching release
This commit is contained in:
parent
051119c091
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78f6ff34a5
168
hash/wscolor.xml
168
hash/wscolor.xml
@ -100,27 +100,27 @@ See the wswan software list for the full game list.
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</software>
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<!--
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<software name="battlespa" cloneof="battlesp">
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<description>Battle Spirit - Digimon Frontier (Rev 0)</description>
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<year>2002</year>
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<publisher>Bandai</publisher>
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<info name="serial" value="SWJ-BANC31"/>
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<info name="release" value="20021207"/>
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<info name="alt_title" value="バトルスピリット デジモンフロンティア"/>
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<part name="cart" interface="wswan_cart">
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<feature name="pcb" value="PTS-0133A" />
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<feature name="u1" value="BANDAI 2003" />
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<feature name="u2" value="GIZA" />
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<feature name="u3" value="ROM" />
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<feature name="u4" value="HY62KT081ED70C SRAM" />
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<feature name="slot" value="ws_sram" />
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<dataarea name="rom" size="4194304" width="16" endianness="little">
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<rom name="sd32m256s222d.u3" size="4194304" crc="a28d3dc5" sha1="" offset="000000" />
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</dataarea>
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<dataarea name="sram" size="32768" width="16" endianness="little">
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</dataarea>
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</part>
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</software>
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<software name="battlespa" cloneof="battlesp">
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<description>Battle Spirit - Digimon Frontier (Rev 0)</description>
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<year>2002</year>
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<publisher>Bandai</publisher>
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<info name="serial" value="SWJ-BANC31"/>
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<info name="release" value="20021207"/>
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<info name="alt_title" value="バトルスピリット デジモンフロンティア"/>
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<part name="cart" interface="wswan_cart">
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<feature name="pcb" value="PTS-0133A" />
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<feature name="u1" value="BANDAI 2003" />
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<feature name="u2" value="GIZA" />
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<feature name="u3" value="ROM" />
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<feature name="u4" value="HY62KT081ED70C SRAM" />
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<feature name="slot" value="ws_sram" />
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<dataarea name="rom" size="4194304" width="16" endianness="little">
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<rom name="sd32m256s222d.u3" size="4194304" crc="a28d3dc5" sha1="" offset="000000" />
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</dataarea>
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<dataarea name="sram" size="32768" width="16" endianness="little">
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</dataarea>
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</part>
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</software>
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-->
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<software name="bluewing">
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@ -327,27 +327,27 @@ See the wswan software list for the full game list.
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</software>
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<!--
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<software name="digimdp">
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<description>Digital Monster - D-Project (Rev 2)</description>
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<year>2002</year>
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<publisher>Bandai</publisher>
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<info name="serial" value="SWJ-BANC2E"/>
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<info name="release" value="20020803"/>
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<info name="alt_title" value="デジタルモンスター ディープロジェクト"/>
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<part name="cart" interface="wswan_cart">
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<feature name="pcb" value="PTS-0133A" />
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<feature name="u1" value="BANDAI 2003" />
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<feature name="u2" value="GIZA" />
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<feature name="u3" value="ROM" />
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<feature name="u4" value="HY62KT081ED70C SRAM" />
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<feature name="slot" value="ws_sram" />
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<dataarea name="rom" size="4194304" width="16" endianness="little">
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<rom name="sd32m256s217d.u3" size="4194304" crc="0e40829c" sha1="" offset="000000" />
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</dataarea>
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<dataarea name="sram" size="32768" width="16" endianness="little">
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</dataarea>
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</part>
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</software>
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<software name="digimdp">
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<description>Digital Monster - D-Project (Rev 2)</description>
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<year>2002</year>
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<publisher>Bandai</publisher>
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<info name="serial" value="SWJ-BANC2E"/>
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<info name="release" value="20020803"/>
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<info name="alt_title" value="デジタルモンスター ディープロジェクト"/>
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<part name="cart" interface="wswan_cart">
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<feature name="pcb" value="PTS-0133A" />
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<feature name="u1" value="BANDAI 2003" />
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<feature name="u2" value="GIZA" />
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<feature name="u3" value="ROM" />
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<feature name="u4" value="HY62KT081ED70C SRAM" />
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<feature name="slot" value="ws_sram" />
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<dataarea name="rom" size="4194304" width="16" endianness="little">
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<rom name="sd32m256s217d.u3" size="4194304" crc="0e40829c" sha1="" offset="000000" />
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</dataarea>
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<dataarea name="sram" size="32768" width="16" endianness="little">
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</dataarea>
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</part>
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</software>
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-->
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<software name="digimdp">
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@ -1484,27 +1484,27 @@ See the wswan software list for the full game list.
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</software>
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<!--
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<software name="onepbatla" cloneof="onepbatl">
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<description>From TV Animation One Piece - Grand Battle Swan Colosseum Sample Edition</description>
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<year>2002</year>
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<publisher>Bandai</publisher>
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<info name="serial" value="SWC-BANC29"/>
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<info name="release" value="20020712"/>
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<info name="alt_title" value="フロムテレビアニメーション ワンピース グランドバトル スワンコロシアム"/>
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<part name="cart" interface="wswan_cart">
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<feature name="pcb" value="PTS-0133A" />
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<feature name="u1" value="BANDAI 2003" />
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<feature name="u2" value="GIZA" />
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<feature name="u3" value="ROM" />
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<feature name="u4" value="BS62LV256TC SRAM" />
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<feature name="slot" value="ws_sram" />
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<dataarea name="rom" size="8388608" width="16" endianness="little">
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<rom name="sd64m256s210d.u3" size="8388608" crc="23853305" sha1="" offset="000000" />
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</dataarea>
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<dataarea name="sram" size="32768" width="16" endianness="little">
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</dataarea>
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</part>
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</software>
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<software name="onepbatla" cloneof="onepbatl">
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<description>From TV Animation One Piece - Grand Battle Swan Colosseum Sample Edition</description>
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<year>2002</year>
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<publisher>Bandai</publisher>
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<info name="serial" value="SWC-BANC29"/>
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<info name="release" value="20020712"/>
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<info name="alt_title" value="フロムテレビアニメーション ワンピース グランドバトル スワンコロシアム"/>
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<part name="cart" interface="wswan_cart">
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<feature name="pcb" value="PTS-0133A" />
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<feature name="u1" value="BANDAI 2003" />
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<feature name="u2" value="GIZA" />
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<feature name="u3" value="ROM" />
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<feature name="u4" value="BS62LV256TC SRAM" />
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<feature name="slot" value="ws_sram" />
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<dataarea name="rom" size="8388608" width="16" endianness="little">
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<rom name="sd64m256s210d.u3" size="8388608" crc="23853305" sha1="" offset="000000" />
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</dataarea>
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<dataarea name="sram" size="32768" width="16" endianness="little">
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</dataarea>
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</part>
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</software>
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-->
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<software name="onepchop">
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@ -1923,27 +1923,27 @@ See the wswan software list for the full game list.
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</software>
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<!--
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<software name="sdgundg2">
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<description>SD Gundam G-Generation - Mono-Eye Gundams (Rev 2)</description>
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<year>2002</year>
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<publisher>Bandai</publisher>
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<info name="serial" value="SWJ-BANC2F"/>
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<info name="release" value="20020926"/>
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<info name="alt_title" value="SDガンダム ジージェネレーション モノアイガンダムズ"/>
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<part name="cart" interface="wswan_cart">
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<feature name="pcb" value="PTS-0133A" />
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<feature name="u1" value="BANDAI 2003" />
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<feature name="u2" value="GIZA" />
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<feature name="u3" value="ROM" />
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<feature name="u4" value="HY62KT081ED70C SRAM" />
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<feature name="slot" value="ws_sram" />
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<dataarea name="rom" size="8388608" width="16" endianness="little">
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<rom name="sd64m256s226d.u3" size="8388608" crc="a3ecc9ac" sha1="" offset="000000" />
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</dataarea>
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<dataarea name="sram" size="32768" width="16" endianness="little">
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</dataarea>
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</part>
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</software>
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<software name="sdgundg2">
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<description>SD Gundam G-Generation - Mono-Eye Gundams (Rev 2)</description>
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<year>2002</year>
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<publisher>Bandai</publisher>
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<info name="serial" value="SWJ-BANC2F"/>
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<info name="release" value="20020926"/>
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<info name="alt_title" value="SDガンダム ジージェネレーション モノアイガンダムズ"/>
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<part name="cart" interface="wswan_cart">
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<feature name="pcb" value="PTS-0133A" />
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<feature name="u1" value="BANDAI 2003" />
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<feature name="u2" value="GIZA" />
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<feature name="u3" value="ROM" />
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<feature name="u4" value="HY62KT081ED70C SRAM" />
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<feature name="slot" value="ws_sram" />
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<dataarea name="rom" size="8388608" width="16" endianness="little">
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<rom name="sd64m256s226d.u3" size="8388608" crc="a3ecc9ac" sha1="" offset="000000" />
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</dataarea>
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<dataarea name="sram" size="32768" width="16" endianness="little">
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</dataarea>
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</part>
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</software>
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-->
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<software name="sdgundg2">
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@ -742,23 +742,23 @@ The GIZA chip used on a lot of cartridges is a sram voltage switch.
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<!--
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<software name="digiadvc">
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<description>Digimon Adventure Campaign Limited Version</description>
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<year>2000</year>
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<publisher>Bandai</publisher>
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<info name="alt_title" value="デジモンアドベンチャー キャンペーン限定バージョン"/>
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<part name="cart" interface="wswan_cart">
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<feature name="pcb" value="PTE-0022A" />
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<feature name="u1" value="BANDAI 2001" />
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<feature name="u2" value="GIZA" />
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<feature name="u3" value="ROM" />
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<feature name="u4" value="BS62LV256TC SRAM" />
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<feature name="slot" value="ws_sram" />
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<dataarea name="rom" size="2097152" width="16" endianness="little">
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<rom name="m5m29ft160avp.u3" size="2097152" crc="7e03e8da" sha1="" offset="000000" />
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</dataarea>
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<dataarea name="sram" size="32768" width="16" endianness="little">
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</dataarea>
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</part>
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<description>Digimon Adventure Campaign Limited Version</description>
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<year>2000</year>
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<publisher>Bandai</publisher>
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<info name="alt_title" value="デジモンアドベンチャー キャンペーン限定バージョン"/>
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<part name="cart" interface="wswan_cart">
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<feature name="pcb" value="PTE-0022A" />
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<feature name="u1" value="BANDAI 2001" />
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<feature name="u2" value="GIZA" />
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<feature name="u3" value="ROM" />
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<feature name="u4" value="BS62LV256TC SRAM" />
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<feature name="slot" value="ws_sram" />
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<dataarea name="rom" size="2097152" width="16" endianness="little">
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<rom name="m5m29ft160avp.u3" size="2097152" crc="7e03e8da" sha1="" offset="000000" />
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</dataarea>
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<dataarea name="sram" size="32768" width="16" endianness="little">
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</dataarea>
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</part>
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</software>
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-->
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@ -23,7 +23,7 @@
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// ======================> databoard_4106_device
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class databoard_4106_device : public device_t,
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public device_abcbus_card_interface
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public device_abcbus_card_interface
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{
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public:
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// construction/destruction
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@ -24,7 +24,7 @@
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// ======================> databoard_4107_device
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class databoard_4107_device : public device_t,
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public device_abcbus_card_interface
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public device_abcbus_card_interface
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{
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public:
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// construction/destruction
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@ -23,7 +23,7 @@
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// ======================> abc_databoard_4112_device
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class abc_databoard_4112_device : public device_t,
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public device_abcbus_card_interface
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public device_abcbus_card_interface
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{
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public:
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// construction/destruction
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@ -43,12 +43,12 @@ Notes:
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- sector length error in read check after format (breakpoint @ 97ba)
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0C xx INITIALIZE DRIVE CHARACTERISTICS
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01 00 00 00 00 02 RECALIBRATE
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04 00 00 00 05 02 FORMAT UNIT
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08 00 00 00 11 02 READ
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...transfer 8704 (17*512) bytes...
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error
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0C xx INITIALIZE DRIVE CHARACTERISTICS
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01 00 00 00 00 02 RECALIBRATE
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04 00 00 00 05 02 FORMAT UNIT
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08 00 00 00 11 02 READ
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...transfer 8704 (17*512) bytes...
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error
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*/
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@ -453,20 +453,20 @@ void ws_rom_eeprom_device::write_io(offs_t offset, u16 data, u16 mem_mask)
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{
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case 0x06 / 2:
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/* EEPROM address lower bits port/EEPROM address and command port
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1KBit EEPROM:
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Bit 0-5 - EEPROM address bit 1-6
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Bit 6-7 - Command
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00 - Extended command address bit 4-5:
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00 - Write disable
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01 - Write all
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10 - Erase all
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11 - Write enable
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01 - Write
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10 - Read
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11 - Erase
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16KBit EEPROM:
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Bit 0-7 - EEPROM address bit 1-8
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*/
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1KBit EEPROM:
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Bit 0-5 - EEPROM address bit 1-6
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Bit 6-7 - Command
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00 - Extended command address bit 4-5:
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00 - Write disable
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01 - Write all
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10 - Erase all
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11 - Write enable
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01 - Write
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10 - Read
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11 - Erase
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16KBit EEPROM:
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Bit 0-7 - EEPROM address bit 1-8
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*/
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if (ACCESSING_BITS_0_7)
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{
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switch (m_eeprom_mode)
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@ -489,23 +489,23 @@ void ws_rom_eeprom_device::write_io(offs_t offset, u16 data, u16 mem_mask)
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}
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}
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/* EEPROM higher bits/command bits port
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1KBit EEPROM:
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Bit 0 - Start
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Bit 1-7 - Unknown
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16KBit EEPROM:
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Bit 0-1 - EEPROM address bit 9-10
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Bit 2-3 - Command
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00 - Extended command address bit 0-1:
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00 - Write disable
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01 - Write all
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10 - Erase all
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11 - Write enable
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01 - Write
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10 - Read
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11 - Erase
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Bit 4 - Start
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Bit 5-7 - Unknown
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*/
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1KBit EEPROM:
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Bit 0 - Start
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Bit 1-7 - Unknown
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16KBit EEPROM:
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Bit 0-1 - EEPROM address bit 9-10
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Bit 2-3 - Command
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00 - Extended command address bit 0-1:
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00 - Write disable
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01 - Write all
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10 - Erase all
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11 - Write enable
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01 - Write
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10 - Read
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11 - Erase
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Bit 4 - Start
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Bit 5-7 - Unknown
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*/
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if (ACCESSING_BITS_8_15)
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{
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switch (m_eeprom_mode)
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@ -539,14 +539,14 @@ void ws_rom_eeprom_device::write_io(offs_t offset, u16 data, u16 mem_mask)
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case 0x08 / 2:
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/* EEPROM command
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Bit 0 - Read complete (read only)
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Bit 1 - Write complete (read only)
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Bit 2-3 - Unknown
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Bit 4 - Read
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Bit 5 - Write
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Bit 6 - Protect
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Bit 7 - Initialize
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*/
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Bit 0 - Read complete (read only)
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Bit 1 - Write complete (read only)
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Bit 2-3 - Unknown
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Bit 4 - Read
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Bit 5 - Write
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Bit 6 - Protect
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Bit 7 - Initialize
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*/
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if (ACCESSING_BITS_0_7)
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{
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if (data & 0x80) // Initialize
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@ -686,7 +686,7 @@ void ws_wwitch_device::write_ram(offs_t offset, u16 data, u16 mem_mask)
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m_flash_mode = COMMAND_MODE;
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}
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break;
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case 0x80: // Erase (chip or block)
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case 0x80: // Erase (chip or block)
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m_flash_command = data;
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break;
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default: // Unknown command
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@ -49,7 +49,7 @@ TODO:
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#include "logmacro.h"
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#define PRINT_HAPYFSH2 (0)
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#define PRINT_CE_KERNEL (0)
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#define PRINT_CE_KERNEL (0)
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/* prototypes of coprocessor functions */
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void arm7_dt_r_callback(arm_state *arm, uint32_t insn, uint32_t *prn, uint32_t (*read32)(arm_state *arm, uint32_t addr));
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@ -12,10 +12,10 @@
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Todo!
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- Double check cycle timing is 100%.
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- Add penalties when BW, BP, SP, IX, IY etc are changed in the immediately
|
||||
preceding instruction.
|
||||
- wswan mjkiwame (at 0x40141) has rep in al,$b5 (f3 e4 b5). Should this
|
||||
repeat the in instruction or is this a bug made by the programmer?
|
||||
- Add penalties when BW, BP, SP, IX, IY etc are changed in the immediately
|
||||
preceding instruction.
|
||||
- wswan mjkiwame (at 0x40141) has rep in al,$b5 (f3 e4 b5). Should this
|
||||
repeat the in instruction or is this a bug made by the programmer?
|
||||
|
||||
****************************************************************************/
|
||||
|
||||
@ -2382,7 +2382,7 @@ void v30mz_cpu_device::execute_run()
|
||||
case 0x20: and_word(); store_ea_rm_word(m_dst); break;
|
||||
case 0x28: sub_word(); store_ea_rm_word(m_dst); break;
|
||||
case 0x30: xor_word(); store_ea_rm_word(m_dst); break;
|
||||
case 0x38: sub_word(); break; // CMP
|
||||
case 0x38: sub_word(); break; // CMP
|
||||
}
|
||||
break;
|
||||
|
||||
|
@ -4,30 +4,30 @@
|
||||
|
||||
m950x0.cpp
|
||||
|
||||
STmicro M95010/20/40 SPI-bus EEPROM
|
||||
STmicro M95010/20/40 SPI-bus EEPROM
|
||||
|
||||
Common characteristics:
|
||||
- 16-byte page size
|
||||
- Write protection selectable in quarter, half, or full sizes
|
||||
Common characteristics:
|
||||
- 16-byte page size
|
||||
- Write protection selectable in quarter, half, or full sizes
|
||||
|
||||
Part variants with a -DF designation have additional support for an
|
||||
identification page, which is not currently emulated.
|
||||
Part variants with a -DF designation have additional support for an
|
||||
identification page, which is not currently emulated.
|
||||
|
||||
Sizes:
|
||||
M95010 - 1kbit
|
||||
M95020 - 2kbit
|
||||
M95040 - 4kbit, slightly altered instructions for 9th address bit
|
||||
Sizes:
|
||||
M95010 - 1kbit
|
||||
M95020 - 2kbit
|
||||
M95040 - 4kbit, slightly altered instructions for 9th address bit
|
||||
|
||||
Current issues:
|
||||
- Implementation currently operates in a parallel manner, rather than
|
||||
serial.
|
||||
Current issues:
|
||||
- Implementation currently operates in a parallel manner, rather than
|
||||
serial.
|
||||
|
||||
***************************************************************************/
|
||||
|
||||
#include "emu.h"
|
||||
#include "m950x0.h"
|
||||
|
||||
#define VERBOSE (0)
|
||||
#define VERBOSE (0)
|
||||
#include "logmacro.h"
|
||||
|
||||
DEFINE_DEVICE_TYPE(M95010, m95010_device, "m95010", "STmicro M95010 1kbit SPI EEPROM")
|
||||
|
@ -4,7 +4,7 @@
|
||||
|
||||
m950x0.h
|
||||
|
||||
STmicro M95010/20/40 SPI-bus EEPROM
|
||||
STmicro M95010/20/40 SPI-bus EEPROM
|
||||
|
||||
***************************************************************************/
|
||||
|
||||
@ -46,21 +46,21 @@ protected:
|
||||
|
||||
enum : uint8_t
|
||||
{
|
||||
INSN_WRSR0 = 0x01,
|
||||
INSN_WRITE0 = 0x02,
|
||||
INSN_READ0 = 0x03,
|
||||
INSN_WRDI0 = 0x04,
|
||||
INSN_RDSR0 = 0x05,
|
||||
INSN_WREN0 = 0x06,
|
||||
INSN_WRSR0 = 0x01,
|
||||
INSN_WRITE0 = 0x02,
|
||||
INSN_READ0 = 0x03,
|
||||
INSN_WRDI0 = 0x04,
|
||||
INSN_RDSR0 = 0x05,
|
||||
INSN_WREN0 = 0x06,
|
||||
|
||||
INSN_WRSR1 = 0x09,
|
||||
INSN_WRITE1 = 0x0a,
|
||||
INSN_READ1 = 0x0b,
|
||||
INSN_WRDI1 = 0x0c,
|
||||
INSN_RDSR1 = 0x0d,
|
||||
INSN_WREN1 = 0x0e,
|
||||
INSN_WRSR1 = 0x09,
|
||||
INSN_WRITE1 = 0x0a,
|
||||
INSN_READ1 = 0x0b,
|
||||
INSN_WRDI1 = 0x0c,
|
||||
INSN_RDSR1 = 0x0d,
|
||||
INSN_WREN1 = 0x0e,
|
||||
|
||||
STATUS_WEL_BIT = 1
|
||||
STATUS_WEL_BIT = 1
|
||||
};
|
||||
|
||||
const bool m_check_a8;
|
||||
|
@ -10,7 +10,7 @@
|
||||
#include "sa1110.h"
|
||||
|
||||
#define LOG_UNKNOWN (1 << 1)
|
||||
#define LOG_ICP (1 << 2)
|
||||
#define LOG_ICP (1 << 2)
|
||||
#define LOG_UART3 (1 << 3)
|
||||
#define LOG_UART3_HF (1 << 4)
|
||||
#define LOG_MCP (1 << 5)
|
||||
@ -18,16 +18,16 @@
|
||||
#define LOG_OSTIMER (1 << 7)
|
||||
#define LOG_OSTIMER_HF (1 << 8)
|
||||
#define LOG_RTC (1 << 9)
|
||||
#define LOG_RTC_HF (1 << 10)
|
||||
#define LOG_RTC_HF (1 << 10)
|
||||
#define LOG_POWER (1 << 11)
|
||||
#define LOG_POWER_HF (1 << 12)
|
||||
#define LOG_POWER_HF (1 << 12)
|
||||
#define LOG_RESET (1 << 13)
|
||||
#define LOG_GPIO (1 << 14)
|
||||
#define LOG_GPIO_HF (1 << 15)
|
||||
#define LOG_INTC (1 << 16)
|
||||
#define LOG_PPC (1 << 17)
|
||||
#define LOG_DMA (1 << 18)
|
||||
#define LOG_UDC (1 << 19)
|
||||
#define LOG_PPC (1 << 17)
|
||||
#define LOG_DMA (1 << 18)
|
||||
#define LOG_UDC (1 << 19)
|
||||
#define LOG_ALL (LOG_UNKNOWN | LOG_ICP | LOG_UART3 | LOG_MCP | LOG_OSTIMER | LOG_RTC | LOG_POWER | LOG_RESET | LOG_GPIO | LOG_INTC | LOG_PPC | LOG_DMA | LOG_UDC)
|
||||
|
||||
#define VERBOSE (0)
|
||||
@ -297,7 +297,7 @@ void sa1110_periphs_device::icp_w(offs_t offset, uint32_t data, uint32_t mem_mas
|
||||
//parity_t parity = PARITY_NONE;
|
||||
//if (BIT(data, 0))
|
||||
//{
|
||||
// parity = (BIT(data, 1) ? PARITY_EVEN : PARITY_ODD);
|
||||
// parity = (BIT(data, 1) ? PARITY_EVEN : PARITY_ODD);
|
||||
//}
|
||||
|
||||
//set_data_frame(1, BIT(data, 3) ? 8 : 7, parity, stop_bits);
|
||||
@ -314,7 +314,7 @@ void sa1110_periphs_device::icp_w(offs_t offset, uint32_t data, uint32_t mem_mas
|
||||
//const uint8_t old = m_uart_regs.utcr[1] & 0x0f;
|
||||
COMBINE_DATA(&m_icp_regs.uart.utcr[1]);
|
||||
//if ((m_uart_regs.utcr[1] & 0x0f) != old)
|
||||
// icp_uart_recalculate_divisor();
|
||||
// icp_uart_recalculate_divisor();
|
||||
break;
|
||||
}
|
||||
case REG_UTCR2:
|
||||
@ -324,7 +324,7 @@ void sa1110_periphs_device::icp_w(offs_t offset, uint32_t data, uint32_t mem_mas
|
||||
//const uint8_t old = m_uart_regs.utcr[2] & 0xff;
|
||||
COMBINE_DATA(&m_icp_regs.uart.utcr[2]);
|
||||
//if ((m_uart_regs.utcr[2] & 0xff) != old)
|
||||
// icp_uart_recalculate_divisor();
|
||||
// icp_uart_recalculate_divisor();
|
||||
break;
|
||||
}
|
||||
case REG_UTCR3:
|
||||
|
@ -156,26 +156,26 @@ protected:
|
||||
// register offsets
|
||||
enum
|
||||
{
|
||||
UDC_BASE_ADDR = 0x80000000,
|
||||
REG_UDCCR = (0x00000000 >> 2),
|
||||
REG_UDCAR = (0x00000004 >> 2),
|
||||
REG_UDCOMP = (0x00000008 >> 2),
|
||||
REG_UDCIMP = (0x0000000c >> 2),
|
||||
REG_UDCCS0 = (0x00000010 >> 2),
|
||||
REG_UDCCS1 = (0x00000014 >> 2),
|
||||
REG_UDCCS2 = (0x00000018 >> 2),
|
||||
REG_UDCD0 = (0x0000001c >> 2),
|
||||
REG_UDCWC = (0x00000020 >> 2),
|
||||
REG_UDCDR = (0x00000028 >> 2),
|
||||
REG_UDCSR = (0x00000030 >> 2),
|
||||
UDC_BASE_ADDR = 0x80000000,
|
||||
REG_UDCCR = (0x00000000 >> 2),
|
||||
REG_UDCAR = (0x00000004 >> 2),
|
||||
REG_UDCOMP = (0x00000008 >> 2),
|
||||
REG_UDCIMP = (0x0000000c >> 2),
|
||||
REG_UDCCS0 = (0x00000010 >> 2),
|
||||
REG_UDCCS1 = (0x00000014 >> 2),
|
||||
REG_UDCCS2 = (0x00000018 >> 2),
|
||||
REG_UDCD0 = (0x0000001c >> 2),
|
||||
REG_UDCWC = (0x00000020 >> 2),
|
||||
REG_UDCDR = (0x00000028 >> 2),
|
||||
REG_UDCSR = (0x00000030 >> 2),
|
||||
|
||||
ICP_BASE_ADDR = 0x80030000,
|
||||
REG_UTCR4 = (0x00000010 >> 2),
|
||||
REG_HSCR0 = (0x00000060 >> 2),
|
||||
REG_HSCR1 = (0x00000064 >> 2),
|
||||
REG_HSDR = (0x0000006c >> 2),
|
||||
REG_HSSR0 = (0x00000074 >> 2),
|
||||
REG_HSSR1 = (0x00000078 >> 2),
|
||||
ICP_BASE_ADDR = 0x80030000,
|
||||
REG_UTCR4 = (0x00000010 >> 2),
|
||||
REG_HSCR0 = (0x00000060 >> 2),
|
||||
REG_HSCR1 = (0x00000064 >> 2),
|
||||
REG_HSDR = (0x0000006c >> 2),
|
||||
REG_HSSR0 = (0x00000074 >> 2),
|
||||
REG_HSSR1 = (0x00000078 >> 2),
|
||||
|
||||
UART_BASE_ADDR = 0x80050000,
|
||||
REG_UTCR0 = (0x00000000 >> 2),
|
||||
@ -247,73 +247,73 @@ protected:
|
||||
REG_ICFP = (0x00000010 >> 2),
|
||||
REG_ICPR = (0x00000020 >> 2),
|
||||
|
||||
PPC_BASE_ADDR = 0x90060000,
|
||||
REG_PPDR = (0x00000000 >> 2),
|
||||
REG_PPSR = (0x00000004 >> 2),
|
||||
REG_PPAR = (0x00000008 >> 2),
|
||||
REG_PSDR = (0x0000000c >> 2),
|
||||
REG_PPFR = (0x00000010 >> 2),
|
||||
PPC_BASE_ADDR = 0x90060000,
|
||||
REG_PPDR = (0x00000000 >> 2),
|
||||
REG_PPSR = (0x00000004 >> 2),
|
||||
REG_PPAR = (0x00000008 >> 2),
|
||||
REG_PSDR = (0x0000000c >> 2),
|
||||
REG_PPFR = (0x00000010 >> 2),
|
||||
|
||||
DMA_BASE_ADDR = 0xb0000000,
|
||||
REG_DDAR = (0x00000000 >> 2),
|
||||
REG_DSSR = (0x00000004 >> 2),
|
||||
REG_DCSR = (0x00000008 >> 2),
|
||||
REG_DSR = (0x0000000c >> 2),
|
||||
REG_DBSA = (0x00000010 >> 2),
|
||||
REG_DBTA = (0x00000014 >> 2),
|
||||
REG_DBSB = (0x00000018 >> 2),
|
||||
REG_DBTB = (0x0000001c >> 2)
|
||||
DMA_BASE_ADDR = 0xb0000000,
|
||||
REG_DDAR = (0x00000000 >> 2),
|
||||
REG_DSSR = (0x00000004 >> 2),
|
||||
REG_DCSR = (0x00000008 >> 2),
|
||||
REG_DSR = (0x0000000c >> 2),
|
||||
REG_DBSA = (0x00000010 >> 2),
|
||||
REG_DBTA = (0x00000014 >> 2),
|
||||
REG_DBSB = (0x00000018 >> 2),
|
||||
REG_DBTB = (0x0000001c >> 2)
|
||||
};
|
||||
|
||||
// register contents
|
||||
enum : uint32_t
|
||||
{
|
||||
UDCCR_UDD_BIT = 0,
|
||||
UDCCR_UDA_BIT = 1,
|
||||
UDCCR_RESM_BIT = 2,
|
||||
UDCCR_EIM_BIT = 3,
|
||||
UDCCR_RIM_BIT = 4,
|
||||
UDCCR_TIM_BIT = 5,
|
||||
UDCCR_SUSM_BIT = 6,
|
||||
UDCCR_WRITE_MASK = 0x7d,
|
||||
UDCCR_UDD_BIT = 0,
|
||||
UDCCR_UDA_BIT = 1,
|
||||
UDCCR_RESM_BIT = 2,
|
||||
UDCCR_EIM_BIT = 3,
|
||||
UDCCR_RIM_BIT = 4,
|
||||
UDCCR_TIM_BIT = 5,
|
||||
UDCCR_SUSM_BIT = 6,
|
||||
UDCCR_WRITE_MASK = 0x7d,
|
||||
|
||||
UDCAR_WRITE_MASK = 0x7f,
|
||||
UDCAR_WRITE_MASK = 0x7f,
|
||||
|
||||
UDCOMP_WRITE_MASK = 0xff,
|
||||
UDCOMP_WRITE_MASK = 0xff,
|
||||
|
||||
UDCIMP_WRITE_MASK = 0xff,
|
||||
UDCIMP_WRITE_MASK = 0xff,
|
||||
|
||||
UDCCS0_OPR_BIT = 0,
|
||||
UDCCS0_IPR_BIT = 1,
|
||||
UDCCS0_SST_BIT = 2,
|
||||
UDCCS0_FST_BIT = 3,
|
||||
UDCCS0_DE_BIT = 4,
|
||||
UDCCS0_SE_BIT = 5,
|
||||
UDCCS0_SO_BIT = 6,
|
||||
UDCCS0_SSE_BIT = 7,
|
||||
UDCCS0_OPR_BIT = 0,
|
||||
UDCCS0_IPR_BIT = 1,
|
||||
UDCCS0_SST_BIT = 2,
|
||||
UDCCS0_FST_BIT = 3,
|
||||
UDCCS0_DE_BIT = 4,
|
||||
UDCCS0_SE_BIT = 5,
|
||||
UDCCS0_SO_BIT = 6,
|
||||
UDCCS0_SSE_BIT = 7,
|
||||
|
||||
UDCCS1_RFS_BIT = 0,
|
||||
UDCCS1_RPC_BIT = 1,
|
||||
UDCCS1_RPE_BIT = 2,
|
||||
UDCCS1_SST_BIT = 3,
|
||||
UDCCS1_FST_BIT = 4,
|
||||
UDCCS1_RNE_BIT = 5,
|
||||
UDCCS1_RFS_BIT = 0,
|
||||
UDCCS1_RPC_BIT = 1,
|
||||
UDCCS1_RPE_BIT = 2,
|
||||
UDCCS1_SST_BIT = 3,
|
||||
UDCCS1_FST_BIT = 4,
|
||||
UDCCS1_RNE_BIT = 5,
|
||||
|
||||
UDCCS2_TFS_BIT = 0,
|
||||
UDCCS2_TPC_BIT = 1,
|
||||
UDCCS2_TPE_BIT = 2,
|
||||
UDCCS2_TUR_BIT = 3,
|
||||
UDCCS2_SST_BIT = 4,
|
||||
UDCCS2_FST_BIT = 5,
|
||||
UDCCS2_TFS_BIT = 0,
|
||||
UDCCS2_TPC_BIT = 1,
|
||||
UDCCS2_TPE_BIT = 2,
|
||||
UDCCS2_TUR_BIT = 3,
|
||||
UDCCS2_SST_BIT = 4,
|
||||
UDCCS2_FST_BIT = 5,
|
||||
|
||||
UDCWC_WRITE_MASK = 0x0f,
|
||||
UDCWC_WRITE_MASK = 0x0f,
|
||||
|
||||
UDCSR_EIR_BIT = 0,
|
||||
UDCSR_RIR_BIT = 1,
|
||||
UDCSR_TIR_BIT = 2,
|
||||
UDCSR_SUSIR_BIT = 3,
|
||||
UDCSR_RESIR_BIT = 4,
|
||||
UDCSR_RSTIR_BIT = 5,
|
||||
UDCSR_EIR_BIT = 0,
|
||||
UDCSR_RIR_BIT = 1,
|
||||
UDCSR_TIR_BIT = 2,
|
||||
UDCSR_SUSIR_BIT = 3,
|
||||
UDCSR_RESIR_BIT = 4,
|
||||
UDCSR_RSTIR_BIT = 5,
|
||||
|
||||
UART3_FIFO_PRE = 8,
|
||||
UART3_FIFO_FRE = 9,
|
||||
@ -326,8 +326,8 @@ protected:
|
||||
UTCR3_TIE_BIT = 4,
|
||||
UTCR3_LBM_BIT = 5,
|
||||
|
||||
UTCR4_HSE_BIT = 0,
|
||||
UTCR4_LPM_BIT = 1,
|
||||
UTCR4_HSE_BIT = 0,
|
||||
UTCR4_LPM_BIT = 1,
|
||||
|
||||
UTSR0_TFS_BIT = 0,
|
||||
UTSR0_RFS_BIT = 1,
|
||||
@ -343,36 +343,36 @@ protected:
|
||||
UTSR1_FRE_BIT = 4,
|
||||
UTSR1_ROR_BIT = 5,
|
||||
|
||||
HSCR0_ITR_BIT = 0,
|
||||
HSCR0_LBM_BIT = 1,
|
||||
HSCR0_TUS_BIT = 2,
|
||||
HSCR0_TXE_BIT = 3,
|
||||
HSCR0_RXE_BIT = 4,
|
||||
HSCR0_RIE_BIT = 5,
|
||||
HSCR0_TIE_BIT = 6,
|
||||
HSCR0_AME_BIT = 7,
|
||||
HSCR0_ITR_BIT = 0,
|
||||
HSCR0_LBM_BIT = 1,
|
||||
HSCR0_TUS_BIT = 2,
|
||||
HSCR0_TXE_BIT = 3,
|
||||
HSCR0_RXE_BIT = 4,
|
||||
HSCR0_RIE_BIT = 5,
|
||||
HSCR0_TIE_BIT = 6,
|
||||
HSCR0_AME_BIT = 7,
|
||||
|
||||
HSCR2_TXP_BIT = 18,
|
||||
HSCR2_RXP_BIT = 19,
|
||||
HSCR2_TXP_BIT = 18,
|
||||
HSCR2_RXP_BIT = 19,
|
||||
|
||||
HSDR_EOF_BIT = 8,
|
||||
HSDR_CRE_BIT = 9,
|
||||
HSDR_ROR_BIT = 10,
|
||||
HSDR_EOF_BIT = 8,
|
||||
HSDR_CRE_BIT = 9,
|
||||
HSDR_ROR_BIT = 10,
|
||||
|
||||
HSSR0_EIF_BIT = 0,
|
||||
HSSR0_TUR_BIT = 1,
|
||||
HSSR0_RAB_BIT = 2,
|
||||
HSSR0_TFS_BIT = 3,
|
||||
HSSR0_RFS_BIT = 4,
|
||||
HSSR0_FRE_BIT = 5,
|
||||
HSSR0_EIF_BIT = 0,
|
||||
HSSR0_TUR_BIT = 1,
|
||||
HSSR0_RAB_BIT = 2,
|
||||
HSSR0_TFS_BIT = 3,
|
||||
HSSR0_RFS_BIT = 4,
|
||||
HSSR0_FRE_BIT = 5,
|
||||
|
||||
HSSR1_RSY_BIT = 0,
|
||||
HSSR1_TBY_BIT = 1,
|
||||
HSSR1_RNE_BIT = 2,
|
||||
HSSR1_TNF_BIT = 3,
|
||||
HSSR1_EOF_BIT = 4,
|
||||
HSSR1_CRE_BIT = 5,
|
||||
HSSR1_ROR_BIT = 6,
|
||||
HSSR1_RSY_BIT = 0,
|
||||
HSSR1_TBY_BIT = 1,
|
||||
HSSR1_RNE_BIT = 2,
|
||||
HSSR1_TNF_BIT = 3,
|
||||
HSSR1_EOF_BIT = 4,
|
||||
HSSR1_CRE_BIT = 5,
|
||||
HSSR1_ROR_BIT = 6,
|
||||
|
||||
MCCR0_ASD_BIT = 0,
|
||||
MCCR0_ASD_MASK = 0x0000007f,
|
||||
@ -443,25 +443,25 @@ protected:
|
||||
RTSR_HZE_BIT = 3,
|
||||
RTSR_HZE_MASK = (1 << RTSR_HZE_BIT),
|
||||
|
||||
DDAR_RW_BIT = 0,
|
||||
DDAR_E_BIT = 1,
|
||||
DDAR_BS_BIT = 2,
|
||||
DDAR_DW_BIT = 3,
|
||||
DDAR_DA0_BIT = 4,
|
||||
DDAR_DA0_MASK = 0x000000f0,
|
||||
DDAR_DA8_BIT = 8,
|
||||
DDAR_DA8_MASK = 0xffffff00,
|
||||
DDAR_RW_BIT = 0,
|
||||
DDAR_E_BIT = 1,
|
||||
DDAR_BS_BIT = 2,
|
||||
DDAR_DW_BIT = 3,
|
||||
DDAR_DA0_BIT = 4,
|
||||
DDAR_DA0_MASK = 0x000000f0,
|
||||
DDAR_DA8_BIT = 8,
|
||||
DDAR_DA8_MASK = 0xffffff00,
|
||||
|
||||
DSR_RUN_BIT = 0,
|
||||
DSR_IE_BIT = 1,
|
||||
DSR_ERROR_BIT = 2,
|
||||
DSR_DONEA_BIT = 3,
|
||||
DSR_STRTA_BIT = 4,
|
||||
DSR_DONEB_BIT = 5,
|
||||
DSR_STRTB_BIT = 6,
|
||||
DSR_BIU_BIT = 7,
|
||||
DSR_RUN_BIT = 0,
|
||||
DSR_IE_BIT = 1,
|
||||
DSR_ERROR_BIT = 2,
|
||||
DSR_DONEA_BIT = 3,
|
||||
DSR_STRTA_BIT = 4,
|
||||
DSR_DONEB_BIT = 5,
|
||||
DSR_STRTB_BIT = 6,
|
||||
DSR_BIU_BIT = 7,
|
||||
|
||||
DBT_MASK = 0x00001fff
|
||||
DBT_MASK = 0x00001fff
|
||||
};
|
||||
|
||||
// interrupt bits
|
||||
@ -715,9 +715,9 @@ protected:
|
||||
uint32_t dbt[2];
|
||||
};
|
||||
|
||||
udc_regs m_udc_regs;
|
||||
udc_regs m_udc_regs;
|
||||
uart_regs m_uart_regs;
|
||||
icp_regs m_icp_regs;
|
||||
icp_regs m_icp_regs;
|
||||
mcp_regs m_mcp_regs;
|
||||
ssp_regs m_ssp_regs;
|
||||
ostimer_regs m_ostmr_regs;
|
||||
@ -726,9 +726,9 @@ protected:
|
||||
uint32_t m_rcsr;
|
||||
gpio_regs m_gpio_regs;
|
||||
intc_regs m_intc_regs;
|
||||
ppc_regs m_ppc_regs;
|
||||
dma_regs m_dma_regs[6];
|
||||
uint8_t m_dma_active_mask;
|
||||
ppc_regs m_ppc_regs;
|
||||
dma_regs m_dma_regs[6];
|
||||
uint8_t m_dma_active_mask;
|
||||
|
||||
required_device<sa1110_cpu_device> m_maincpu;
|
||||
required_device<input_merger_device> m_uart3_irqs;
|
||||
|
@ -21,7 +21,7 @@
|
||||
#define LOG_GPIO (1 << 10)
|
||||
#define LOG_INTC (1 << 11)
|
||||
#define LOG_CARD (1 << 12)
|
||||
#define LOG_AUDIO_DMA (1 << 13)
|
||||
#define LOG_AUDIO_DMA (1 << 13)
|
||||
#define LOG_ALL (LOG_UNKNOWN | LOG_SBI | LOG_SK | LOG_USB | LOG_AUDIO | LOG_SSP | LOG_TRACK | LOG_MOUSE | LOG_GPIO | LOG_INTC | LOG_CARD)
|
||||
|
||||
#define VERBOSE (0)
|
||||
|
@ -346,19 +346,19 @@ protected:
|
||||
SASCR_RDD_BIT = 17,
|
||||
SASCR_STO_BIT = 18,
|
||||
|
||||
SASR_TNF_BIT = 0,
|
||||
SASR_RNE_BIT = 1,
|
||||
SASR_BSY_BIT = 2,
|
||||
SASR_TFS_BIT = 3,
|
||||
SASR_RFS_BIT = 4,
|
||||
SASR_TUR_BIT = 5,
|
||||
SASR_ROR_BIT = 6,
|
||||
SASR_TFL_BIT = 8,
|
||||
SASR_TNF_BIT = 0,
|
||||
SASR_RNE_BIT = 1,
|
||||
SASR_BSY_BIT = 2,
|
||||
SASR_TFS_BIT = 3,
|
||||
SASR_RFS_BIT = 4,
|
||||
SASR_TUR_BIT = 5,
|
||||
SASR_ROR_BIT = 6,
|
||||
SASR_TFL_BIT = 8,
|
||||
SASR_TFL_MASK = 0x00000f00,
|
||||
SASR_RFL_BIT = 12,
|
||||
SASR_RFL_MASK = 0x0000f000,
|
||||
SASR_SEND_BIT = 16,
|
||||
SASR_RECV_BIT = 17,
|
||||
SASR_SEND_BIT = 16,
|
||||
SASR_RECV_BIT = 17,
|
||||
|
||||
SASR0_L3WD_BIT = 16,
|
||||
SASR0_L3RD_BIT = 17,
|
||||
@ -376,14 +376,14 @@ protected:
|
||||
SADTCS_TDSTA_BIT = 4,
|
||||
SADTCS_TDBDB_BIT = 5,
|
||||
SADTCS_TDSTB_BIT = 6,
|
||||
SADTCS_TBIU_BIT = 7,
|
||||
SADTCS_TBIU_BIT = 7,
|
||||
|
||||
SADRCS_RDEN_BIT = 0,
|
||||
SADRCS_RDBDA_BIT = 3,
|
||||
SADRCS_RDSTA_BIT = 4,
|
||||
SADRCS_RDBDB_BIT = 5,
|
||||
SADRCS_RDSTB_BIT = 6,
|
||||
SADRCS_RBIU_BIT = 7,
|
||||
SADRCS_RBIU_BIT = 7,
|
||||
|
||||
SAITR_TFS_BIT = 0,
|
||||
SAITR_RFS_BIT = 1,
|
||||
@ -480,56 +480,56 @@ protected:
|
||||
// interrupt lines
|
||||
enum : uint32_t
|
||||
{
|
||||
INT_GPA0 = 0,
|
||||
INT_GPA1 = 1,
|
||||
INT_GPA2 = 2,
|
||||
INT_GPA3 = 3,
|
||||
INT_GPB0 = 4,
|
||||
INT_GPB1 = 5,
|
||||
INT_GPB2 = 6,
|
||||
INT_GPB3 = 7,
|
||||
INT_GPB4 = 8,
|
||||
INT_GPB5 = 9,
|
||||
INT_GPC0 = 10,
|
||||
INT_GPC1 = 11,
|
||||
INT_GPC2 = 12,
|
||||
INT_GPC3 = 13,
|
||||
INT_GPC4 = 14,
|
||||
INT_GPC5 = 15,
|
||||
INT_GPC6 = 16,
|
||||
INT_GPC7 = 17,
|
||||
INT_MSTX = 18,
|
||||
INT_MSRX = 19,
|
||||
INT_MSERR = 20,
|
||||
INT_TPTX = 21,
|
||||
INT_TPRX = 22,
|
||||
INT_TPERR = 23,
|
||||
INT_SSPTX = 24,
|
||||
INT_SSPRX = 25,
|
||||
INT_SSPROR = 26,
|
||||
INT_AUDTXA = 32,
|
||||
INT_AUDRXA = 33,
|
||||
INT_AUDTXB = 34,
|
||||
INT_AUDRXB = 35,
|
||||
INT_AUDTFS = 36,
|
||||
INT_AUDRFS = 37,
|
||||
INT_AUDTUR = 38,
|
||||
INT_AUDROR = 39,
|
||||
INT_AUDDTS = 40,
|
||||
INT_AUDRDD = 41,
|
||||
INT_AUDSTO = 42,
|
||||
INT_USBPWR = 43,
|
||||
INT_USBHCIM = 44,
|
||||
INT_USBHCIBUF = 45,
|
||||
INT_USBHCIWAKE = 46,
|
||||
INT_USBHCIMFC = 47,
|
||||
INT_USBRESUME = 48,
|
||||
INT_S0RDY = 49,
|
||||
INT_S1RDY = 50,
|
||||
INT_S0CD = 51,
|
||||
INT_S1CD = 52,
|
||||
INT_S0BVD = 53,
|
||||
INT_S1BVD = 54
|
||||
INT_GPA0 = 0,
|
||||
INT_GPA1 = 1,
|
||||
INT_GPA2 = 2,
|
||||
INT_GPA3 = 3,
|
||||
INT_GPB0 = 4,
|
||||
INT_GPB1 = 5,
|
||||
INT_GPB2 = 6,
|
||||
INT_GPB3 = 7,
|
||||
INT_GPB4 = 8,
|
||||
INT_GPB5 = 9,
|
||||
INT_GPC0 = 10,
|
||||
INT_GPC1 = 11,
|
||||
INT_GPC2 = 12,
|
||||
INT_GPC3 = 13,
|
||||
INT_GPC4 = 14,
|
||||
INT_GPC5 = 15,
|
||||
INT_GPC6 = 16,
|
||||
INT_GPC7 = 17,
|
||||
INT_MSTX = 18,
|
||||
INT_MSRX = 19,
|
||||
INT_MSERR = 20,
|
||||
INT_TPTX = 21,
|
||||
INT_TPRX = 22,
|
||||
INT_TPERR = 23,
|
||||
INT_SSPTX = 24,
|
||||
INT_SSPRX = 25,
|
||||
INT_SSPROR = 26,
|
||||
INT_AUDTXA = 32,
|
||||
INT_AUDRXA = 33,
|
||||
INT_AUDTXB = 34,
|
||||
INT_AUDRXB = 35,
|
||||
INT_AUDTFS = 36,
|
||||
INT_AUDRFS = 37,
|
||||
INT_AUDTUR = 38,
|
||||
INT_AUDROR = 39,
|
||||
INT_AUDDTS = 40,
|
||||
INT_AUDRDD = 41,
|
||||
INT_AUDSTO = 42,
|
||||
INT_USBPWR = 43,
|
||||
INT_USBHCIM = 44,
|
||||
INT_USBHCIBUF = 45,
|
||||
INT_USBHCIWAKE = 46,
|
||||
INT_USBHCIMFC = 47,
|
||||
INT_USBRESUME = 48,
|
||||
INT_S0RDY = 49,
|
||||
INT_S1RDY = 50,
|
||||
INT_S0CD = 51,
|
||||
INT_S1CD = 52,
|
||||
INT_S0BVD = 53,
|
||||
INT_S1BVD = 54
|
||||
};
|
||||
|
||||
struct sbi_regs
|
||||
|
@ -160,7 +160,7 @@ u8 swim1_device::ism_read(offs_t offset)
|
||||
return m_ism_mode;
|
||||
|
||||
default:
|
||||
// logerror("read %s\n", names[offset & 7]);
|
||||
// logerror("read %s\n", names[offset & 7]);
|
||||
break;
|
||||
}
|
||||
return 0xff;
|
||||
|
@ -2,21 +2,21 @@
|
||||
// copyright-holders:Ryan Holtz
|
||||
/***************************************************************************
|
||||
|
||||
Philips UDA1344 Stereo Audio Codec skeleton
|
||||
Philips UDA1344 Stereo Audio Codec skeleton
|
||||
|
||||
****************************************************************************/
|
||||
|
||||
#include "emu.h"
|
||||
#include "sound/uda1344.h"
|
||||
|
||||
#define LOG_ADDR (1 << 1)
|
||||
#define LOG_STATUS_REG (1 << 2)
|
||||
#define LOG_DATA_REG (1 << 3)
|
||||
#define LOG_INPUT (1 << 4)
|
||||
#define LOG_OVERRUNS (1 << 5)
|
||||
#define LOG_ALL (LOG_ADDR | LOG_STATUS_REG | LOG_DATA_REG | LOG_INPUT | LOG_OVERRUNS)
|
||||
#define LOG_ADDR (1 << 1)
|
||||
#define LOG_STATUS_REG (1 << 2)
|
||||
#define LOG_DATA_REG (1 << 3)
|
||||
#define LOG_INPUT (1 << 4)
|
||||
#define LOG_OVERRUNS (1 << 5)
|
||||
#define LOG_ALL (LOG_ADDR | LOG_STATUS_REG | LOG_DATA_REG | LOG_INPUT | LOG_OVERRUNS)
|
||||
|
||||
#define VERBOSE (0)
|
||||
#define VERBOSE (0)
|
||||
#include "logmacro.h"
|
||||
|
||||
|
||||
|
@ -2,7 +2,7 @@
|
||||
// copyright-holders:Ryan Holtz
|
||||
/***************************************************************************
|
||||
|
||||
Philips UDA1344 Stereo Audio Codec skeleton
|
||||
Philips UDA1344 Stereo Audio Codec skeleton
|
||||
|
||||
****************************************************************************/
|
||||
|
||||
@ -41,41 +41,41 @@ protected:
|
||||
|
||||
enum : uint8_t
|
||||
{
|
||||
CHIP_ADDR_MASK = 0xfc,
|
||||
CHIP_ADDR = 0x14,
|
||||
CHIP_ADDR_MASK = 0xfc,
|
||||
CHIP_ADDR = 0x14,
|
||||
|
||||
REG_TYPE_MASK = 0xc0,
|
||||
REG_TYPE_BIT = 6,
|
||||
REG_TYPE_MASK = 0xc0,
|
||||
REG_TYPE_BIT = 6,
|
||||
|
||||
VOLUME_REG = 0x00,
|
||||
VOLUME_REG_MASK = 0x3f,
|
||||
VOLUME_REG = 0x00,
|
||||
VOLUME_REG_MASK = 0x3f,
|
||||
|
||||
EQUALIZER_REG = 0x01,
|
||||
EQUALIZER_REG_MASK = 0x3f,
|
||||
EQUALIZER_BB_MASK = 0x3c,
|
||||
EQUALIZER_BB_BIT = 2,
|
||||
EQUALIZER_TR_MASK = 0x03,
|
||||
EQUALIZER_TR_BIT = 0,
|
||||
EQUALIZER_REG = 0x01,
|
||||
EQUALIZER_REG_MASK = 0x3f,
|
||||
EQUALIZER_BB_MASK = 0x3c,
|
||||
EQUALIZER_BB_BIT = 2,
|
||||
EQUALIZER_TR_MASK = 0x03,
|
||||
EQUALIZER_TR_BIT = 0,
|
||||
|
||||
FILTER_REG = 0x02,
|
||||
FILTER_REG_MASK = 0x1f,
|
||||
FILTER_DE_MASK = 0x18,
|
||||
FILTER_DE_BIT = 3,
|
||||
FILTER_MT_BIT = 2,
|
||||
FILTER_MODE_MASK = 0x03,
|
||||
FILTER_MODE_BIT = 0,
|
||||
FILTER_REG = 0x02,
|
||||
FILTER_REG_MASK = 0x1f,
|
||||
FILTER_DE_MASK = 0x18,
|
||||
FILTER_DE_BIT = 3,
|
||||
FILTER_MT_BIT = 2,
|
||||
FILTER_MODE_MASK = 0x03,
|
||||
FILTER_MODE_BIT = 0,
|
||||
|
||||
POWER_REG = 0x03,
|
||||
POWER_REG_MASK = 0x03,
|
||||
POWER_ADC_BIT = 1,
|
||||
POWER_DAC_BIT = 0,
|
||||
POWER_REG = 0x03,
|
||||
POWER_REG_MASK = 0x03,
|
||||
POWER_ADC_BIT = 1,
|
||||
POWER_DAC_BIT = 0,
|
||||
|
||||
STATUS_REG_MASK = 0x3f,
|
||||
STATUS_SC_MASK = 0x30,
|
||||
STATUS_SC_BIT = 4,
|
||||
STATUS_IF_MASK = 0x0e,
|
||||
STATUS_IF_BIT = 1,
|
||||
STATUS_DC_BIT = 0
|
||||
STATUS_REG_MASK = 0x3f,
|
||||
STATUS_SC_MASK = 0x30,
|
||||
STATUS_SC_BIT = 4,
|
||||
STATUS_IF_MASK = 0x0e,
|
||||
STATUS_IF_BIT = 1,
|
||||
STATUS_DC_BIT = 0
|
||||
};
|
||||
|
||||
sound_stream *m_stream;
|
||||
|
@ -8,9 +8,9 @@
|
||||
- Currently hard-coded for use with the Jornada 720 driver.
|
||||
- Register contents are correctly stored, logged and masked, but
|
||||
register handling is otherwise largely non-present.
|
||||
- There is the potential for endian issues, and it will be
|
||||
dealt with once the Jornada 720 driver makes heavier use of
|
||||
BitBLT operations or other operations relevant to endianness.
|
||||
- There is the potential for endian issues, and it will be
|
||||
dealt with once the Jornada 720 driver makes heavier use of
|
||||
BitBLT operations or other operations relevant to endianness.
|
||||
|
||||
**********************************************************************/
|
||||
|
||||
@ -31,7 +31,7 @@
|
||||
#define LOG_LUT_WR (1 << 11)
|
||||
#define LOG_MPLUG_RD (1 << 12)
|
||||
#define LOG_MPLUG_WR (1 << 13)
|
||||
#define LOG_LCD_RD_HF (1 << 14)
|
||||
#define LOG_LCD_RD_HF (1 << 14)
|
||||
#define LOG_ALL (LOG_MISC_RD | LOG_MISC_WR | LOG_LCD_RD | LOG_LCD_WR | LOG_CRT_RD | LOG_CRT_WR | LOG_BITBLT_RD | LOG_BITBLT_WR | LOG_BITBLT_OP | LOG_LUT_RD \
|
||||
| LOG_LUT_WR | LOG_MPLUG_RD | LOG_MPLUG_WR)
|
||||
|
||||
|
@ -2975,7 +2975,7 @@ std::vector<std::vector<uint8_t>> floppy_image_format_t::extract_sectors_from_tr
|
||||
uint8_t v3 = gcr6bw_tb[h[3]];
|
||||
uint8_t tr = gcr6bw_tb[h[0]] | (v2 & 1 ? 0x40 : 0x00);
|
||||
uint8_t se = gcr6bw_tb[h[1]];
|
||||
// uint8_t si = v2 & 0x20 ? 1 : 0;
|
||||
// uint8_t si = v2 & 0x20 ? 1 : 0;
|
||||
// uint8_t ds = v3 & 0x20 ? 1 : 0;
|
||||
// uint8_t fmt = v3 & 0x1f;
|
||||
uint8_t c1 = (tr^se^v2^v3) & 0x3f;
|
||||
|
@ -372,8 +372,8 @@ protected:
|
||||
|
||||
/*! @brief Test if a variant is present in the variant vector
|
||||
@param variants the variant vector
|
||||
@param variant the variant to test
|
||||
@result true if variant is in variants
|
||||
@param variant the variant to test
|
||||
@result true if variant is in variants
|
||||
*/
|
||||
static bool has_variant(const std::vector<uint32_t> &variants, uint32_t variant);
|
||||
|
||||
|
@ -146,10 +146,10 @@ void cmi01a_device::sound_stream_update(sound_stream &stream, std::vector<read_s
|
||||
{
|
||||
const uint8_t sample8 = wave_ptr[addr++ & 0x3fff];
|
||||
s32 sample = (int32_t)(int8_t)(sample8 ^ 0x80) * m_env * m_vol_latch;
|
||||
// if (m_channel == 5) printf("%08x:%02x:%02x:%02x", (uint32_t)sample, sample8, m_env, m_vol_latch);
|
||||
// if (m_channel == 5) printf("%08x:%02x:%02x:%02x", (uint32_t)sample, sample8, m_env, m_vol_latch);
|
||||
buf.put_int(sampindex, (int16_t)(sample >> 8), 32768);
|
||||
}
|
||||
// if (m_channel == 5) printf("\n");
|
||||
// if (m_channel == 5) printf("\n");
|
||||
|
||||
m_segment_cnt = (m_segment_cnt & ~mask) | addr;
|
||||
}
|
||||
|
@ -263,7 +263,7 @@ u16 wswan_sound_device::port_r(offs_t offset, u16 mem_mask)
|
||||
(m_audio4_noise ? 0x80 : 0x00) |
|
||||
(m_mono ? 0x0100 : 0x00) | (m_output_volume << 9) |
|
||||
(m_external_stereo ? 0x0800 : 0x00) |
|
||||
(m_external_speaker ? 0x00 : 0x00); // TODO 0x80 is set when external speaker is connected
|
||||
(m_external_speaker ? 0x00 : 0x00); // TODO 0x80 is set when external speaker is connected
|
||||
case 0x92 / 2:
|
||||
return m_noise_shift;
|
||||
case 0x94 / 2:
|
||||
|
@ -35,9 +35,9 @@
|
||||
TODO:
|
||||
|
||||
- sas/format/format in abcenix tries to access the SASI card using a memory location mapped for task 0, when the process is run as task 1
|
||||
- MAC task/page/segment addressing failure?
|
||||
- MAC page/segment RAM write strobe decoding failure?
|
||||
- CPU does not enter supervisor mode when needed?
|
||||
- MAC task/page/segment addressing failure?
|
||||
- MAC page/segment RAM write strobe decoding failure?
|
||||
- CPU does not enter supervisor mode when needed?
|
||||
|
||||
[:mac] ':3f' (0009E) ff800:4f TASK 0 SEGMENT 15 PAGE 15 MEM 7f800-7ffff 1ff800
|
||||
[:mac] ':3f' (0009E) ff801:ff TASK 0 SEGMENT 15 PAGE 15 MEM 7f800-7ffff 1ff800
|
||||
|
@ -1834,10 +1834,10 @@ ROM_START( sc4hrolr ) // uses RTC on romcard
|
||||
ROM_REGION( 0x100000, "ymz", 0 )
|
||||
ROM_LOAD( "b3a_highroller.bin", 0x0000, 0x100000, CRC(38ce5435) SHA1(e159420e7929fa048f3b2393f761eeed2e1cf3b7) )
|
||||
|
||||
ROM_REGION( 0x100000, "gals", 0 )
|
||||
ROM_REGION( 0x100000, "gals", 0 )
|
||||
ROM_LOAD( "75585129.ic1.bin", 0x0000, 0x000117, CRC(2454bb33) SHA1(610cde14caef3f2d02f0076b924e015077c3832b) ) /* protected gal16v8 on romcard */
|
||||
|
||||
ROM_END
|
||||
ROM_END
|
||||
|
||||
ROM_START( ad4skill )
|
||||
ROM_REGION( 0x400000, "maincpu", ROMREGION_ERASEFF )
|
||||
|
@ -274,11 +274,11 @@ void design6_state::design6(machine_config &config)
|
||||
NVRAM(config, "nvram", nvram_device::DEFAULT_ALL_0);
|
||||
|
||||
CD4099(config, "outlatch0");
|
||||
// outlatch0.q_out_cb<0>() // enable coin return motor 1
|
||||
// outlatch0.q_out_cb<1>() // enable coin return motor 2
|
||||
// outlatch0.q_out_cb<2>() // enable coin return motor 3
|
||||
// outlatch0.q_out_cb<3>() // master enable coin return motor?
|
||||
// outlatch0.q_out_cb<6>() // ?
|
||||
// outlatch0.q_out_cb<0>() // enable coin return motor 1
|
||||
// outlatch0.q_out_cb<1>() // enable coin return motor 2
|
||||
// outlatch0.q_out_cb<2>() // enable coin return motor 3
|
||||
// outlatch0.q_out_cb<3>() // master enable coin return motor?
|
||||
// outlatch0.q_out_cb<6>() // ?
|
||||
|
||||
cd4099_device &outlatch1(CD4099(config, "outlatch1"));
|
||||
outlatch1.q_out_cb<5>().set("vfd", FUNC(roc10937_device::data));
|
||||
|
@ -27,23 +27,23 @@
|
||||
OUTPUT:
|
||||
all bits = Centronics data
|
||||
|
||||
Colors (from COLORDEM.BAS)
|
||||
0 = black
|
||||
1 = dark blue
|
||||
2 = red
|
||||
3 = magenta
|
||||
4 = brown
|
||||
5 = grey
|
||||
6 = orange
|
||||
7 = pink
|
||||
8 = dark aqua
|
||||
9 = blue
|
||||
A = grey 2
|
||||
B = light blue
|
||||
C = green
|
||||
D = aqua
|
||||
E = yellow
|
||||
F = white
|
||||
Colors (from COLORDEM.BAS)
|
||||
0 = black
|
||||
1 = dark blue
|
||||
2 = red
|
||||
3 = magenta
|
||||
4 = brown
|
||||
5 = grey
|
||||
6 = orange
|
||||
7 = pink
|
||||
8 = dark aqua
|
||||
9 = blue
|
||||
A = grey 2
|
||||
B = light blue
|
||||
C = green
|
||||
D = aqua
|
||||
E = yellow
|
||||
F = white
|
||||
|
||||
****************************************************************************/
|
||||
|
||||
@ -134,7 +134,7 @@ void dim68k_state::dim68k_palette(palette_device &palette)
|
||||
palette.set_pen_color(12, rgb_t(0x19, 0xd7, 0x00)); /* Light Green */
|
||||
palette.set_pen_color(13, rgb_t(0x58, 0xf4, 0xbf)); /* Aquamarine */
|
||||
palette.set_pen_color(14, rgb_t(0xbf, 0xe3, 0x08)); /* Yellow */
|
||||
palette.set_pen_color(15, rgb_t(0xff, 0xff, 0xff)); /* White */
|
||||
palette.set_pen_color(15, rgb_t(0xff, 0xff, 0xff)); /* White */
|
||||
};
|
||||
|
||||
u16 dim68k_state::dim68k_fdc_r()
|
||||
|
@ -701,7 +701,7 @@ GFXDECODE_END
|
||||
|
||||
void fortecrd_state::machine_reset()
|
||||
{
|
||||
// apparently there's a random fill in there (checked thru trojan)
|
||||
// apparently there's a random fill in there (checked thru trojan)
|
||||
for (int i = 0; i < m_vram.bytes(); i++)
|
||||
m_vram[i] = machine().rand();
|
||||
}
|
||||
@ -753,7 +753,7 @@ void fortecrd_state::fortecrd(machine_config &config)
|
||||
|
||||
SPEAKER(config, "mono").front_center();
|
||||
|
||||
ay8910_device &aysnd(AY8910(config, "aysnd", AY_CLOCK)); // 1.5 MHz, measured
|
||||
ay8910_device &aysnd(AY8910(config, "aysnd", AY_CLOCK)); // 1.5 MHz, measured
|
||||
aysnd.port_a_write_callback().set(FUNC(fortecrd_state::ayporta_w));
|
||||
aysnd.port_b_write_callback().set(FUNC(fortecrd_state::ayportb_w));
|
||||
aysnd.add_route(ALL_OUTPUTS, "mono", 0.50);
|
||||
|
@ -618,51 +618,51 @@
|
||||
You'll see the following counters and menu:
|
||||
|
||||
КАРЕ С ЖОКЕР 0 (five of a kind)
|
||||
КЕНТ ФЛЕШ РОЯЛ 0 (royal flush)
|
||||
КЕНТ ФЛЕШ 0 (straight flush)
|
||||
КАРЕ 0 (poker)
|
||||
ФУЛ 0 (full house)
|
||||
ФЛЕШ 0 (flush)
|
||||
КЕНТА 0 (straight)
|
||||
ТРОЙКА 0 (three of a kind)
|
||||
2 ДВОЙКИ 0 (two pairs)
|
||||
ГОЛЯМА ДВОЙКИ 0 (high pair)
|
||||
КЕНТ ФЛЕШ РОЯЛ 0 (royal flush)
|
||||
КЕНТ ФЛЕШ 0 (straight flush)
|
||||
КАРЕ 0 (poker)
|
||||
ФУЛ 0 (full house)
|
||||
ФЛЕШ 0 (flush)
|
||||
КЕНТА 0 (straight)
|
||||
ТРОЙКА 0 (three of a kind)
|
||||
2 ДВОЙКИ 0 (two pairs)
|
||||
ГОЛЯМА ДВОЙКИ 0 (high pair)
|
||||
|
||||
|
||||
ВРЕМЕ: Натиснете бутон Стоп3
|
||||
TIME: Press the Stop3 button
|
||||
ВРЕМЕ: Натиснете бутон Стоп3
|
||||
TIME: Press the Stop3 button
|
||||
|
||||
Изиграно време, мин. : 00
|
||||
Played time, min. : 00
|
||||
Изиграно време, мин. : 00
|
||||
Played time, min. : 00
|
||||
|
||||
Платено време, мин. : 00
|
||||
Paid time, min. : 00
|
||||
Платено време, мин. : 00
|
||||
Paid time, min. : 00
|
||||
|
||||
|
||||
НАСТРОЙКА: Натиснете бутони Стоп2 и Стоп4
|
||||
SETUP: Press the Stop2 and Stop4 buttons
|
||||
НАСТРОЙКА: Натиснете бутони Стоп2 и Стоп4
|
||||
SETUP: Press the Stop2 and Stop4 buttons
|
||||
|
||||
Бутон Стоп1 -- Време за една игра, мин. (1-99, 5 by default)
|
||||
Stop1 Button -- Time for one game, min. (1-99, 5 by default)
|
||||
Бутон Стоп1 -- Време за една игра, мин. (1-99, 5 by default)
|
||||
Stop1 Button -- Time for one game, min. (1-99, 5 by default)
|
||||
|
||||
Бутон Стоп2 -- Залог (1-99, 10 by default)
|
||||
Stop2 button - Bet (1-99, 10 by default)
|
||||
Бутон Стоп2 -- Залог (1-99, 10 by default)
|
||||
Stop2 button - Bet (1-99, 10 by default)
|
||||
|
||||
Бутон Стоп3 -- Ниво на трудност (0-3, 2 by default)
|
||||
Stop3 button -- Level of difficulty (0-3, 2 by default)
|
||||
Бутон Стоп3 -- Ниво на трудност (0-3, 2 by default)
|
||||
Stop3 button -- Level of difficulty (0-3, 2 by default)
|
||||
|
||||
ИЗХОД: Натиснете бутон Старт
|
||||
EXIT: Press the Start button
|
||||
ИЗХОД: Натиснете бутон Старт
|
||||
EXIT: Press the Start button
|
||||
|
||||
|
||||
НУЛИРАНЕ: Стоп1 нулира часовника
|
||||
RESET: Stop1 resets the clock
|
||||
НУЛИРАНЕ: Стоп1 нулира часовника
|
||||
RESET: Stop1 resets the clock
|
||||
|
||||
ИЗЧИСТВАНЕ: Натиснете 2 с. бутон Изчистване
|
||||
CLEAR: Press the Cancel button for 2 seconds
|
||||
ИЗЧИСТВАНЕ: Натиснете 2 с. бутон Изчистване
|
||||
CLEAR: Press the Cancel button for 2 seconds
|
||||
|
||||
ИЗХОД: Натиснете бутон Старт
|
||||
EXIT: Press the Start button
|
||||
ИЗХОД: Натиснете бутон Старт
|
||||
EXIT: Press the Start button
|
||||
|
||||
---------------------------------------------------------------------
|
||||
|
||||
@ -1436,10 +1436,10 @@ static INPUT_PORTS_START( jolycdcy )
|
||||
PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_GAMBLE_KEYIN ) PORT_NAME(u8"Running / Credits (Навъртане)") // НАВЪРТАНЕ
|
||||
PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_POKER_HOLD1 ) PORT_NAME(u8"Stop 1 (Стоп 1)") // СТОП 1
|
||||
PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_POKER_CANCEL ) PORT_NAME(u8"Cancel (Изчистване) / Autostop (Автостоп) / Take (Качване)") // ИЗЧИСТВАНЕ / АВТОСТОП / КАЧВАНЕ
|
||||
PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_START1 ) PORT_NAME(u8"Start (Старт) / Double (Дублиране)") // СТАРТ / ДУБЛИРАНЕ
|
||||
PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_POKER_HOLD5 ) PORT_NAME(u8"Stop 5 (Стоп 5) / Half Gamble (Половин Хазарт)") // СТОП 5 / ПОЛОВИН ХАЗАРТ
|
||||
PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_SERVICE1 ) PORT_NAME(u8"Turnover (Оборот)") // ОБОРОТ (turnover)
|
||||
PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_SERVICE2 ) PORT_NAME(u8"Setup (Настройка)") // НАСТРОЙКА (setup)
|
||||
PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_START1 ) PORT_NAME(u8"Start (Старт) / Double (Дублиране)") // СТАРТ / ДУБЛИРАНЕ
|
||||
PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_POKER_HOLD5 ) PORT_NAME(u8"Stop 5 (Стоп 5) / Half Gamble (Половин Хазарт)") // СТОП 5 / ПОЛОВИН ХАЗАРТ
|
||||
PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_SERVICE1 ) PORT_NAME(u8"Turnover (Оборот)") // ОБОРОТ (turnover)
|
||||
PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_SERVICE2 ) PORT_NAME(u8"Setup (Настройка)") // НАСТРОЙКА (setup)
|
||||
PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_POKER_HOLD4 ) PORT_NAME(u8"Stop 4 (Стоп 4) / Big (Голяма)") // СТОП 4 / ГОЛЯМА
|
||||
|
||||
PORT_START("IN1")
|
||||
@ -1447,13 +1447,13 @@ static INPUT_PORTS_START( jolycdcy )
|
||||
PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_POKER_HOLD3 ) PORT_NAME(u8"Stop 3 (Стоп 3)") // СТОП 3
|
||||
PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_UNKNOWN )
|
||||
PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_UNKNOWN )
|
||||
PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_SERVICE ) PORT_NAME("test 1") PORT_CODE(KEYCODE_A) // present on the test mode, but erased
|
||||
PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_SERVICE ) PORT_NAME("test 2") PORT_CODE(KEYCODE_S) // normally coin2. present on the test mode, but erased.
|
||||
PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_SERVICE ) PORT_NAME("test 1") PORT_CODE(KEYCODE_A) // present on the test mode, but erased
|
||||
PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_SERVICE ) PORT_NAME("test 2") PORT_CODE(KEYCODE_S) // normally coin2. present on the test mode, but erased.
|
||||
PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_UNKNOWN )
|
||||
PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_SERVICE ) PORT_NAME("test 3") PORT_CODE(KEYCODE_D) // normally keyout. present on the test mode as "K'bo?".
|
||||
PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_SERVICE ) PORT_NAME("test 3") PORT_CODE(KEYCODE_D) // normally keyout. present on the test mode as "K'bo?".
|
||||
|
||||
PORT_START("IN2")
|
||||
PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_SERVICE ) PORT_NAME("test 4") PORT_CODE(KEYCODE_F) // normally coin1. present on the test mode, but erased.
|
||||
PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_SERVICE ) PORT_NAME("test 4") PORT_CODE(KEYCODE_F) // normally coin1. present on the test mode, but erased.
|
||||
PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_UNKNOWN )
|
||||
PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_UNKNOWN )
|
||||
PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_UNKNOWN )
|
||||
@ -1463,7 +1463,7 @@ static INPUT_PORTS_START( jolycdcy )
|
||||
PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_UNKNOWN )
|
||||
|
||||
PORT_START("DSW")
|
||||
PORT_DIPNAME( 0x01, 0x01, "State" ) PORT_DIPLOCATION("SW1:8") // only works with credits inserted
|
||||
PORT_DIPNAME( 0x01, 0x01, "State" ) PORT_DIPLOCATION("SW1:8") // only works with credits inserted
|
||||
PORT_DIPSETTING( 0x01, "Normal Play" )
|
||||
PORT_DIPSETTING( 0x00, "Test Mode" )
|
||||
PORT_DIPNAME( 0x02, 0x02, DEF_STR( Unknown ) ) PORT_DIPLOCATION("SW1:7")
|
||||
@ -3083,12 +3083,12 @@ static INPUT_PORTS_START( clubcard )
|
||||
PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_UNKNOWN )
|
||||
PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_UNKNOWN )
|
||||
PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_SERVICE ) PORT_NAME("Hopper SW") PORT_CODE(KEYCODE_H)
|
||||
PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_COIN2 ) PORT_NAME("Coin B")
|
||||
PORT_BIT( 0x20, IP_ACTIVE_LOW, IPT_COIN2 ) PORT_NAME("Coin B")
|
||||
PORT_BIT( 0x40, IP_ACTIVE_LOW, IPT_UNKNOWN )
|
||||
PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_GAMBLE_KEYOUT )
|
||||
|
||||
PORT_START("IN2")
|
||||
PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_COIN1 ) PORT_NAME("Coin A")
|
||||
PORT_BIT( 0x01, IP_ACTIVE_LOW, IPT_COIN1 ) PORT_NAME("Coin A")
|
||||
PORT_BIT( 0x02, IP_ACTIVE_LOW, IPT_UNKNOWN )
|
||||
PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_UNKNOWN )
|
||||
PORT_BIT( 0x08, IP_ACTIVE_LOW, IPT_UNKNOWN )
|
||||
@ -3469,7 +3469,7 @@ void funworld_state::gratispk(machine_config &config)
|
||||
|
||||
void funworld_state::clubcard(machine_config &config)
|
||||
{
|
||||
// fw1stpal(config); // 'alla Royal Card. Card deck wrong colors.
|
||||
// fw1stpal(config); // 'alla Royal Card. Card deck wrong colors.
|
||||
fw2ndpal(config); // proper colors.
|
||||
|
||||
R65C02(config.replace(), m_maincpu, CPU_CLOCK); // 2 MHz.
|
||||
|
@ -20,7 +20,7 @@ TODO:
|
||||
- several unknowns in the video emulation:
|
||||
- score layer is a simplification hack, it is unknown how it should really
|
||||
cope RMW-wise against main layer. It also has wrong colors (different color
|
||||
base or overlay artwork, with extra bit output for taking priority?).
|
||||
base or overlay artwork, with extra bit output for taking priority?).
|
||||
The score background color should change from white(or is it cyan?) to red
|
||||
after Extended Play, the score digits themselves should always be black;
|
||||
- According to flyers, screen sides should have a green background color,
|
||||
@ -201,7 +201,7 @@ void getaway_state::io_w(offs_t offset, u8 data)
|
||||
|
||||
[0x07]
|
||||
???w wwww transfer width, in 8 pixel units
|
||||
Notice that 0xff is set on POST, either full clear or NOP
|
||||
Notice that 0xff is set on POST, either full clear or NOP
|
||||
|
||||
[0x08]
|
||||
hhhh hhhh transfer height, in scanline units
|
||||
|
@ -4,12 +4,12 @@
|
||||
|
||||
HP Jornada PDA skeleton driver
|
||||
|
||||
To boot:
|
||||
- Start MAME with the debugger enabled
|
||||
- Use the following breakpoint command: bp 13E2C,R3==3 && R1==10
|
||||
- Close the debugger and allow the machine to run
|
||||
- When the breakpoint is hit, use the following command: R3=0
|
||||
- Close the debugger, booting will proceed
|
||||
To boot:
|
||||
- Start MAME with the debugger enabled
|
||||
- Use the following breakpoint command: bp 13E2C,R3==3 && R1==10
|
||||
- Close the debugger and allow the machine to run
|
||||
- When the breakpoint is hit, use the following command: R3=0
|
||||
- Close the debugger, booting will proceed
|
||||
|
||||
***************************************************************************/
|
||||
|
||||
@ -59,8 +59,8 @@ public:
|
||||
|
||||
enum : uint8_t
|
||||
{
|
||||
MCU_TXDUMMY = 0x11,
|
||||
MCU_TXDUMMY2 = 0x88
|
||||
MCU_TXDUMMY = 0x11,
|
||||
MCU_TXDUMMY2 = 0x88
|
||||
};
|
||||
|
||||
|
||||
|
@ -1140,7 +1140,7 @@ INPUT_PORTS_START( j6impls )
|
||||
|
||||
PORT_MODIFY("J9_2")
|
||||
PORT_BIT( 0x04, IP_ACTIVE_LOW, IPT_BUTTON9 ) // PORT_NAME("Hopper Dump SW")
|
||||
// PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_BUTTON11 ) // PORT_NAME("Cash / Token Sw")
|
||||
// PORT_BIT( 0x10, IP_ACTIVE_LOW, IPT_BUTTON11 ) // PORT_NAME("Cash / Token Sw")
|
||||
INPUT_PORTS_END
|
||||
|
||||
|
||||
|
@ -434,7 +434,7 @@ void jpmsys5_state::jpm_sys5_common_map(address_map &map)
|
||||
map(0x046080, 0x046083).rw("acia6850_1", FUNC(acia6850_device::read), FUNC(acia6850_device::write)).umask16(0x00ff);
|
||||
|
||||
map(0x046084, 0x046085).r(FUNC(jpmsys5_state::unknown_port_r));
|
||||
// map(0x04608c, 0x04608f).r(FUNC(jpmsys5_state::unk_r));
|
||||
// map(0x04608c, 0x04608f).r(FUNC(jpmsys5_state::unk_r));
|
||||
|
||||
map(0x04608c, 0x04608f).rw("acia6850_2", FUNC(acia6850_device::read), FUNC(acia6850_device::write)).umask16(0x00ff);
|
||||
|
||||
|
@ -1535,8 +1535,8 @@ static INPUT_PORTS_START( shogwarr )
|
||||
PORT_BIT( 0x4000, IP_ACTIVE_LOW, IPT_UNKNOWN )
|
||||
PORT_BIT( 0x8000, IP_ACTIVE_LOW, IPT_UNKNOWN )
|
||||
|
||||
// dip defaults confirmed by manual ("Bolr (sic) face indicate standard setting")
|
||||
// including Demo Sounds
|
||||
// dip defaults confirmed by manual ("Bolr (sic) face indicate standard setting")
|
||||
// including Demo Sounds
|
||||
PORT_START("DSW1") /* from the MCU - 102e15.b <- 200059.b */
|
||||
PORT_DIPNAME( 0x01, 0x01, DEF_STR( Flip_Screen ) ) PORT_DIPLOCATION("SW1:1")
|
||||
PORT_DIPSETTING( 0x01, DEF_STR( Off ) )
|
||||
@ -1555,9 +1555,9 @@ static INPUT_PORTS_START( shogwarr )
|
||||
PORT_DIPSETTING( 0x08, "7" )
|
||||
PORT_DIPSETTING( 0x00, "8 Hard" )
|
||||
PORT_DIPNAME( 0x40, 0x40, "Can Join During Game" ) PORT_DIPLOCATION("SW1:7")
|
||||
// 1p vs 2p is allowed only at title screen with a single credit by pressing 2p start. akin to an "event mode"
|
||||
// 1p vs 2p is allowed only at title screen with a single credit by pressing 2p start. akin to an "event mode"
|
||||
PORT_DIPSETTING( 0x00, DEF_STR( Off ) ) // "impossible", vs.play 1 credit, game over aftewards
|
||||
// "normal mode"
|
||||
// "normal mode"
|
||||
PORT_DIPSETTING( 0x40, DEF_STR( On ) ) // "possible", vs.play 2 credits, winner plays against CPU afterwards
|
||||
PORT_DIPNAME( 0x80, 0x80, "Continue Coin" ) PORT_DIPLOCATION("SW1:8")
|
||||
PORT_DIPSETTING( 0x80, DEF_STR( Off ) )
|
||||
|
@ -145,9 +145,9 @@ void kingpin_state::kingpin_io_map(address_map &map)
|
||||
map(0x20, 0x21).rw("tms9928a", FUNC(tms9928a_device::read), FUNC(tms9928a_device::write));
|
||||
map(0x30, 0x30).w(FUNC(kingpin_state::output1_w));
|
||||
map(0x40, 0x40).w(FUNC(kingpin_state::output2_w));
|
||||
// map(0x50, 0x50)
|
||||
// map(0x50, 0x50)
|
||||
map(0x60, 0x60).w(FUNC(kingpin_state::sound_nmi_w));
|
||||
// map(0x70, 0x70)
|
||||
// map(0x70, 0x70)
|
||||
}
|
||||
|
||||
void kingpin_state::kingpin_sound_map(address_map &map)
|
||||
|
@ -815,7 +815,7 @@ void ksys573_state::gbbchmp_map(address_map& map)
|
||||
|
||||
bool ksys573_state::jvs_is_valid_packet()
|
||||
{
|
||||
if (m_jvs_input_idx_w < 5) {
|
||||
if (m_jvs_input_idx_w < 5) {
|
||||
// A valid packet will have at the very least
|
||||
// - sync (0xe0)
|
||||
// - node number (non-zero)
|
||||
@ -823,35 +823,35 @@ bool ksys573_state::jvs_is_valid_packet()
|
||||
// - at least 1 byte in the request message
|
||||
// - checksum
|
||||
return false;
|
||||
}
|
||||
}
|
||||
|
||||
if (m_jvs_input_buffer[0] != 0xe0 || m_jvs_input_buffer[1] == 0x00) {
|
||||
return false;
|
||||
}
|
||||
|
||||
int command_size = m_jvs_input_buffer[2] + 3;
|
||||
if (m_jvs_input_idx_w < command_size) {
|
||||
int command_size = m_jvs_input_buffer[2] + 3;
|
||||
if (m_jvs_input_idx_w < command_size) {
|
||||
return false;
|
||||
}
|
||||
}
|
||||
|
||||
uint8_t checksum = 0;
|
||||
for (int i = 1; i < command_size - 1; i++) {
|
||||
uint8_t checksum = 0;
|
||||
for (int i = 1; i < command_size - 1; i++) {
|
||||
checksum += m_jvs_input_buffer[i];
|
||||
}
|
||||
}
|
||||
|
||||
return checksum == m_jvs_input_buffer[command_size - 1];
|
||||
return checksum == m_jvs_input_buffer[command_size - 1];
|
||||
}
|
||||
|
||||
void ksys573_state::jvs_input_w(offs_t offset, uint16_t data, uint16_t mem_mask)
|
||||
{
|
||||
m_jvs_input_buffer[m_jvs_input_idx_w++] = data & 0xff;
|
||||
m_jvs_input_buffer[m_jvs_input_idx_w++] = data >> 8;
|
||||
m_jvs_input_buffer[m_jvs_input_idx_w++] = data & 0xff;
|
||||
m_jvs_input_buffer[m_jvs_input_idx_w++] = data >> 8;
|
||||
|
||||
if (m_jvs_input_buffer[0] != 0xe0) {
|
||||
m_jvs_input_idx_w = 0;
|
||||
}
|
||||
|
||||
if (jvs_is_valid_packet()) {
|
||||
if (jvs_is_valid_packet()) {
|
||||
LOGJVS("jvs_input_w( %08x, %08x, %02x %02x )\n", offset, mem_mask, data & 0xff, data >> 8 );
|
||||
for (int i = 0; i < m_jvs_input_idx_w; i++)
|
||||
LOGJVS("%02x ", m_jvs_input_buffer[i]);
|
||||
@ -864,15 +864,15 @@ void ksys573_state::jvs_input_w(offs_t offset, uint16_t data, uint16_t mem_mask)
|
||||
m_jvs_input_idx_r = 0;
|
||||
|
||||
m_jvs_input_buffer[0] = 0;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
uint16_t ksys573_state::jvs_input_r(offs_t offset, uint16_t mem_mask)
|
||||
{
|
||||
uint16_t data = m_jvs_input_buffer[m_jvs_input_idx_r++];
|
||||
data |= m_jvs_input_buffer[m_jvs_input_idx_r++] << 8;
|
||||
uint16_t data = m_jvs_input_buffer[m_jvs_input_idx_r++];
|
||||
data |= m_jvs_input_buffer[m_jvs_input_idx_r++] << 8;
|
||||
|
||||
return data;
|
||||
return data;
|
||||
}
|
||||
|
||||
uint16_t ksys573_state::port_in2_jvs_r(offs_t offset, uint16_t mem_mask)
|
||||
@ -882,21 +882,21 @@ uint16_t ksys573_state::port_in2_jvs_r(offs_t offset, uint16_t mem_mask)
|
||||
return m_in2->read();
|
||||
}
|
||||
|
||||
if (m_jvs_output_len_w <= 0) {
|
||||
if (m_jvs_output_len_w <= 0) {
|
||||
return 0;
|
||||
}
|
||||
}
|
||||
|
||||
uint16_t data = m_jvs_output_buffer[m_jvs_output_idx_w] | (m_jvs_output_buffer[m_jvs_output_idx_w+1] << 8);
|
||||
m_jvs_output_idx_w += 2;
|
||||
uint16_t data = m_jvs_output_buffer[m_jvs_output_idx_w] | (m_jvs_output_buffer[m_jvs_output_idx_w+1] << 8);
|
||||
m_jvs_output_idx_w += 2;
|
||||
|
||||
if (m_jvs_output_idx_w >= m_jvs_output_len_w) {
|
||||
if (m_jvs_output_idx_w >= m_jvs_output_len_w) {
|
||||
m_jvs_output_idx_w = 0;
|
||||
m_jvs_output_len_w = 0;
|
||||
}
|
||||
}
|
||||
|
||||
LOGJVS("m_jvs_output_r %08x %08x | %02x %02x | %02x\n", offset, mem_mask, data & 0xff, data >> 8, m_jvs_output_idx_w);
|
||||
LOGJVS("m_jvs_output_r %08x %08x | %02x %02x | %02x\n", offset, mem_mask, data & 0xff, data >> 8, m_jvs_output_idx_w);
|
||||
|
||||
return data;
|
||||
return data;
|
||||
}
|
||||
|
||||
READ_LINE_MEMBER( ksys573_state::jvs_rx_r )
|
||||
|
@ -6454,12 +6454,12 @@ void model3_state::init_srally2()
|
||||
/*
|
||||
void model3_state::init_srally2pa()
|
||||
{
|
||||
init_model3_20();
|
||||
init_model3_20();
|
||||
|
||||
uint32_t *rom = (uint32_t*)memregion("user1")->base();
|
||||
rom[(0x3ba44^4)/4] = 0x60000000; // Unemulated JTAG stuff, see srally2
|
||||
rom[(0x3ba48^4)/4] = 0x60000000;
|
||||
rom[(0x3ba4c^4)/4] = 0x60000000;
|
||||
uint32_t *rom = (uint32_t*)memregion("user1")->base();
|
||||
rom[(0x3ba44^4)/4] = 0x60000000; // Unemulated JTAG stuff, see srally2
|
||||
rom[(0x3ba48^4)/4] = 0x60000000;
|
||||
rom[(0x3ba4c^4)/4] = 0x60000000;
|
||||
}
|
||||
*/
|
||||
|
||||
|
@ -275,7 +275,7 @@ template <bool SCC> void rtpc_state::iocc_pio_map(address_map &map)
|
||||
|
||||
/*
|
||||
FLOPPY_FORMATS_MEMBER(rtpc_state::floppy_formats)
|
||||
FLOPPY_PC_FORMAT
|
||||
FLOPPY_PC_FORMAT
|
||||
FLOPPY_FORMATS_END
|
||||
*/
|
||||
|
||||
|
@ -8,22 +8,22 @@
|
||||
|
||||
Hardware:
|
||||
- P8085AH
|
||||
- SCN2674B with SCB2675T
|
||||
- SCN2674B with SCB2675T
|
||||
- SCN2681
|
||||
- P8251A
|
||||
- 3x HM6264LP-12 (8k)
|
||||
- 3x HM6116LP-2 (2k)
|
||||
- XTAL: 3.6864 MHz, 10.0000 MHz, 21.7566 MHz, 35.8344 MHz
|
||||
- XTAL: 3.6864 MHz, 10.0000 MHz, 21.7566 MHz, 35.8344 MHz
|
||||
|
||||
TODO:
|
||||
- Dump keyboard controller and emulate it (currently HLE'd)
|
||||
- NVRAM / memory layout
|
||||
- Needs a hack to send out data on the RS232 port:
|
||||
Set $f7a3 = 0 after startup
|
||||
- NVRAM / memory layout
|
||||
- Needs a hack to send out data on the RS232 port:
|
||||
Set $f7a3 = 0 after startup
|
||||
|
||||
Notes:
|
||||
- The hardware has some similarities to cit220.cpp
|
||||
- Everything here is guessed (including the system name), no docs available
|
||||
- The hardware has some similarities to cit220.cpp
|
||||
- Everything here is guessed (including the system name), no docs available
|
||||
|
||||
***************************************************************************/
|
||||
|
||||
@ -257,12 +257,12 @@ void tabe22_state::tabe22(machine_config &config)
|
||||
m_vram_bank->set_data_width(8);
|
||||
m_vram_bank->set_stride(0x1000);
|
||||
|
||||
// NVRAM(config, "nvram", nvram_device::DEFAULT_ALL_0);
|
||||
// NVRAM(config, "nvram", nvram_device::DEFAULT_ALL_0);
|
||||
|
||||
SCREEN(config, m_screen, SCREEN_TYPE_RASTER);
|
||||
m_screen->set_color(rgb_t::amber());
|
||||
m_screen->set_raw(21.7566_MHz_XTAL, 918, 0, 720, 395, 0, 378); // 80 column mode
|
||||
// m_screen->set_raw(35.8344_MHz_XTAL, 1494, 0, 1188, 395, 0, 378); // 132 column mode
|
||||
// m_screen->set_raw(35.8344_MHz_XTAL, 1494, 0, 1188, 395, 0, 378); // 132 column mode
|
||||
m_screen->set_screen_update(m_avdc, FUNC(scn2674_device::screen_update));
|
||||
|
||||
PALETTE(config, m_palette, FUNC(tabe22_state::palette), 4);
|
||||
|
@ -76,7 +76,7 @@ public:
|
||||
void impact_nonvideo_altreels(machine_config &config);
|
||||
|
||||
DECLARE_INPUT_CHANGED_MEMBER(coin_changed);
|
||||
template <unsigned N> DECLARE_READ_LINE_MEMBER( coinsense_r ) { return (m_coinstate >> N) & 1; }
|
||||
template <unsigned N> DECLARE_READ_LINE_MEMBER( coinsense_r ) { return (m_coinstate >> N) & 1; }
|
||||
|
||||
DECLARE_READ_LINE_MEMBER(hopper_b_0_r);
|
||||
DECLARE_READ_LINE_MEMBER(hopper_b_3_r);
|
||||
|
@ -2843,7 +2843,7 @@
|
||||
<element name="vfd0">
|
||||
<!-- if these are really 14 segs, and the hookups are meant to be compaible with the 16segs then the MAME bit order is incorrect -->
|
||||
<!--<led14segsc>
|
||||
<color red="0.0" green="1.0" blue="1.0"/>
|
||||
<color red="0.0" green="1.0" blue="1.0"/>
|
||||
</led14segsc>-->
|
||||
<led16segsc>
|
||||
<color red="0.0" green="1.0" blue="1.0"/>
|
||||
|
@ -3539,7 +3539,7 @@
|
||||
<element name="vfd0">
|
||||
<!-- if these are really 14 segs, and the hookups are meant to be compaible with the 16segs then the MAME bit order is incorrect -->
|
||||
<!--<led14segsc>
|
||||
<color red="0.0" green="1.0" blue="1.0"/>
|
||||
<color red="0.0" green="1.0" blue="1.0"/>
|
||||
</led14segsc>-->
|
||||
<led16segsc>
|
||||
<color red="0.0" green="1.0" blue="1.0"/>
|
||||
|
@ -27,20 +27,20 @@
|
||||
|-------------------------------|
|
||||
|
||||
Notes:
|
||||
DIP8 - 8-position DIP switch
|
||||
CN61 - BS8PSHF1AA 8 pin connector, connects to memory card harness
|
||||
CN62 - BS8PSHF1AA 8 pin connector
|
||||
CN63 - 6P-SHVQ labeled "0", GE885-JB security dongle is connected here
|
||||
CN64 - 6P-SHVQ labeled "1"
|
||||
CN65 - B4PS-VH, 4 pin power connector
|
||||
CN67 - BS15PSHF1AA, 15-pin connector, unpopulated
|
||||
USB-A - USB-A connector
|
||||
USB-B - USB-B connector, connects to USB on System 573 motherboard
|
||||
ADM485JR - Analog Devices ADM485 low power EIA RS-485 transceiver
|
||||
TMPR3904AF - Toshiba TMPR3904AF RISC Microprocessor
|
||||
XCS05/10 - XILINX XCS10XL VQ100AKP9909 A2026631A
|
||||
DRAM4M - Silicon Magic 66 MHz C9742 SM81C256K16CJ-35, 256K x 16 EDO DRAM
|
||||
EP4M16 - ROM labeled "855-A01"
|
||||
DIP8 - 8-position DIP switch
|
||||
CN61 - BS8PSHF1AA 8 pin connector, connects to memory card harness
|
||||
CN62 - BS8PSHF1AA 8 pin connector
|
||||
CN63 - 6P-SHVQ labeled "0", GE885-JB security dongle is connected here
|
||||
CN64 - 6P-SHVQ labeled "1"
|
||||
CN65 - B4PS-VH, 4 pin power connector
|
||||
CN67 - BS15PSHF1AA, 15-pin connector, unpopulated
|
||||
USB-A - USB-A connector
|
||||
USB-B - USB-B connector, connects to USB on System 573 motherboard
|
||||
ADM485JR - Analog Devices ADM485 low power EIA RS-485 transceiver
|
||||
TMPR3904AF - Toshiba TMPR3904AF RISC Microprocessor
|
||||
XCS05/10 - XILINX XCS10XL VQ100AKP9909 A2026631A
|
||||
DRAM4M - Silicon Magic 66 MHz C9742 SM81C256K16CJ-35, 256K x 16 EDO DRAM
|
||||
EP4M16 - ROM labeled "855-A01"
|
||||
*/
|
||||
|
||||
#include "emu.h"
|
||||
|
@ -260,6 +260,7 @@ _count_leading_zeros(uint32_t value)
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
/*-------------------------------------------------
|
||||
count_leading_ones - return the number of
|
||||
leading one bits in a 32-bit value
|
||||
|
Loading…
Reference in New Issue
Block a user