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nes.c: modernized the driver by moving most code into the class, work by Micko. no whatsnew.

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This commit is contained in:
Fabio Priuli 2012-09-21 15:23:07 +00:00
parent 1ef4d3a626
commit 7d021d4d51
7 changed files with 2497 additions and 2416 deletions
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9
src/mess/drivers/nes.c
View File

@ -50,7 +50,7 @@ static ADDRESS_MAP_START( nes_map, AS_PROGRAM, 8, nes_state )
AM_RANGE(0x4016, 0x4016) AM_READWRITE(nes_IN0_r, nes_IN0_w) /* IN0 - input port 1 */
AM_RANGE(0x4017, 0x4017) AM_READ(nes_IN1_r) /* IN1 - input port 2 */
AM_RANGE(0x4017, 0x4017) AM_DEVWRITE_LEGACY("nessound", psg_4017_w) /* PSG second control register */
AM_RANGE(0x4100, 0x5fff) AM_READWRITE_LEGACY(nes_low_mapper_r, nes_low_mapper_w) /* Perform unholy acts on the machine */
AM_RANGE(0x4100, 0x5fff) AM_READWRITE(nes_low_mapper_r, nes_low_mapper_w) /* Perform unholy acts on the machine */
ADDRESS_MAP_END
@ -544,6 +544,9 @@ static MACHINE_CONFIG_DERIVED( famicom, nes )
MCFG_SOFTWARE_LIST_ADD("flop_list","famicom_flop")
MACHINE_CONFIG_END
//static MACHINE_CONFIG_DERIVED( nes_test, nes )
//MACHINE_CONFIG_END
/* rom regions are just place-holders: they get removed and re-allocated when a cart is loaded */
ROM_START( nes )
@ -596,6 +599,8 @@ ROM_START( dendy )
ROM_REGION( 0x800, "ciram", ROMREGION_ERASE00 ) /* CI RAM */
ROM_END
//#define rom_nes_test rom_nes
/***************************************************************************
Game driver(s)
@ -610,3 +615,5 @@ CONS( 1986, famitwin, nes, 0, famicom, famicom, nes_state, famicom, "Sh
CONS( 198?, m82, nes, 0, nes, nes, driver_device, 0, "Nintendo", "M82 Display Unit", GAME_IMPERFECT_GRAPHICS | GAME_NOT_WORKING )
CONS( 1996, drpcjr, nes, 0, famicom, famicom, nes_state, famicom, "Bung", "Doctor PC Jr", GAME_IMPERFECT_GRAPHICS )
CONS( 1992, dendy, nes, 0, dendy, nes, driver_device, 0, "Steepler", "Dendy Classic", GAME_IMPERFECT_GRAPHICS )
//CONS( 1985, nes_test, 0, 0, nes_test, nes, driver_device, 0, "Nintendo", "Nintendo Entertainment System (Testdriver)", GAME_IMPERFECT_GRAPHICS )

300
src/mess/includes/nes.h
View File

@ -108,18 +108,12 @@ public:
int m_last_frame_flip;
/* misc */
write8_space_func m_mmc_write_low;
const char *m_mmc_write_low_name;
write8_space_func m_mmc_write_mid;
const char *m_mmc_write_mid_name;
write8_space_func m_mmc_write;
const char *m_mmc_write_name;
read8_space_func m_mmc_read_low;
const char *m_mmc_read_low_name;
read8_space_func m_mmc_read_mid;
const char *m_mmc_read_mid_name;
read8_space_func m_mmc_read;
const char *m_mmc_read_name;
write8_delegate m_mmc_write_low;
write8_delegate m_mmc_write_mid;
write8_delegate m_mmc_write;
read8_delegate m_mmc_read_low;
read8_delegate m_mmc_read_mid;
read8_delegate m_mmc_read;
emu_timer *m_irq_timer;
nes_prg_callback m_mmc3_prg_cb; // these are used to simplify a lot emulation of some MMC3 pirate clones
@ -260,6 +254,288 @@ public:
virtual void video_start();
virtual void palette_init();
UINT32 screen_update_nes(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect);
DECLARE_WRITE8_MEMBER(mapper6_l_w);
DECLARE_WRITE8_MEMBER(mapper6_w);
DECLARE_WRITE8_MEMBER(mapper8_w);
DECLARE_WRITE8_MEMBER(mapper17_l_w);
DECLARE_WRITE8_MEMBER(nes_chr_w);
DECLARE_READ8_MEMBER(nes_chr_r);
DECLARE_WRITE8_MEMBER(nes_nt_w);
DECLARE_READ8_MEMBER(nes_nt_r);
DECLARE_WRITE8_MEMBER(nes_low_mapper_w);
DECLARE_READ8_MEMBER(nes_low_mapper_r);
DECLARE_WRITE8_MEMBER(uxrom_w);
DECLARE_WRITE8_MEMBER(uxrom_cc_w);
DECLARE_WRITE8_MEMBER(un1rom_w);
DECLARE_WRITE8_MEMBER(cnrom_w);
DECLARE_WRITE8_MEMBER(bandai_pt554_m_w);
DECLARE_WRITE8_MEMBER(cprom_w);
DECLARE_WRITE8_MEMBER(axrom_w);
DECLARE_WRITE8_MEMBER(bxrom_w);
DECLARE_WRITE8_MEMBER(gxrom_w);
DECLARE_WRITE8_MEMBER(sxrom_w);
DECLARE_WRITE8_MEMBER(pxrom_w);
DECLARE_WRITE8_MEMBER(fxrom_w);
DECLARE_WRITE8_MEMBER(txrom_w);
DECLARE_WRITE8_MEMBER(hkrom_m_w);
DECLARE_READ8_MEMBER(hkrom_m_r);
DECLARE_WRITE8_MEMBER(hkrom_w);
DECLARE_WRITE8_MEMBER(txsrom_w);
DECLARE_WRITE8_MEMBER(tqrom_w);
DECLARE_WRITE8_MEMBER(zz_m_w);
DECLARE_WRITE8_MEMBER(qj_m_w);
DECLARE_READ8_MEMBER(exrom_l_r);
DECLARE_WRITE8_MEMBER(exrom_l_w);
DECLARE_WRITE8_MEMBER(ntbrom_w);
DECLARE_WRITE8_MEMBER(jxrom_w);
DECLARE_WRITE8_MEMBER(dxrom_w);
DECLARE_WRITE8_MEMBER(namcot3453_w);
DECLARE_WRITE8_MEMBER(namcot3446_w);
DECLARE_WRITE8_MEMBER(namcot3425_w);
DECLARE_WRITE8_MEMBER(dis_74x377_w);
DECLARE_WRITE8_MEMBER(dis_74x139x74_m_w);
DECLARE_WRITE8_MEMBER(dis_74x161x138_m_w);
DECLARE_WRITE8_MEMBER(dis_74x161x161x32_w);
DECLARE_WRITE8_MEMBER(lz93d50_w);
DECLARE_WRITE8_MEMBER(lz93d50_m_w);
DECLARE_WRITE8_MEMBER(fjump2_w);
DECLARE_WRITE8_MEMBER(bandai_ks_w);
DECLARE_WRITE8_MEMBER(bandai_ok_w);
DECLARE_WRITE8_MEMBER(lrog017_w);
DECLARE_WRITE8_MEMBER(irem_hd_w);
DECLARE_WRITE8_MEMBER(tam_s1_w);
DECLARE_WRITE8_MEMBER(g101_w);
DECLARE_WRITE8_MEMBER(h3001_w);
DECLARE_WRITE8_MEMBER(ss88006_w);
DECLARE_WRITE8_MEMBER(jf11_m_w);
DECLARE_WRITE8_MEMBER(jf13_m_w);
DECLARE_WRITE8_MEMBER(jf16_w);
DECLARE_WRITE8_MEMBER(jf17_w);
DECLARE_WRITE8_MEMBER(jf19_w);
DECLARE_WRITE8_MEMBER(konami_vrc1_w);
DECLARE_WRITE8_MEMBER(konami_vrc2_w);
DECLARE_WRITE8_MEMBER(konami_vrc3_w);
DECLARE_WRITE8_MEMBER(konami_vrc4_w);
DECLARE_WRITE8_MEMBER(konami_vrc6_w);
DECLARE_WRITE8_MEMBER(konami_vrc7_w);
DECLARE_WRITE8_MEMBER(namcot163_l_w);
DECLARE_READ8_MEMBER(namcot163_l_r);
DECLARE_WRITE8_MEMBER(namcot163_w);
DECLARE_WRITE8_MEMBER(sunsoft1_m_w);
DECLARE_WRITE8_MEMBER(sunsoft2_w);
DECLARE_WRITE8_MEMBER(sunsoft3_w);
DECLARE_WRITE8_MEMBER(tc0190fmc_w);
DECLARE_WRITE8_MEMBER(tc0190fmc_p16_w);
DECLARE_WRITE8_MEMBER(x1005_m_w);
DECLARE_READ8_MEMBER(x1005_m_r);
DECLARE_WRITE8_MEMBER(x1005a_m_w);
DECLARE_WRITE8_MEMBER(x1017_m_w);
DECLARE_READ8_MEMBER(x1017_m_r);
DECLARE_WRITE8_MEMBER(agci_50282_w);
DECLARE_WRITE8_MEMBER(nina01_m_w);
DECLARE_WRITE8_MEMBER(nina06_l_w);
DECLARE_WRITE8_MEMBER(ae_act52_w);
DECLARE_WRITE8_MEMBER(cne_decathl_w);
DECLARE_WRITE8_MEMBER(cne_fsb_m_w);
DECLARE_WRITE8_MEMBER(cne_shlz_l_w);
DECLARE_WRITE8_MEMBER(caltron6in1_m_w);
DECLARE_WRITE8_MEMBER(caltron6in1_w);
DECLARE_WRITE8_MEMBER(bf9093_w);
DECLARE_WRITE8_MEMBER(bf9096_w);
DECLARE_WRITE8_MEMBER(golden5_w);
DECLARE_WRITE8_MEMBER(cony_l_w);
DECLARE_READ8_MEMBER(cony_l_r);
DECLARE_WRITE8_MEMBER(cony_w);
DECLARE_WRITE8_MEMBER(yoko_l_w);
DECLARE_READ8_MEMBER(yoko_l_r);
DECLARE_WRITE8_MEMBER(yoko_w);
DECLARE_WRITE8_MEMBER(dreamtech_l_w);
DECLARE_WRITE8_MEMBER(fukutake_l_w);
DECLARE_READ8_MEMBER(fukutake_l_r);
DECLARE_WRITE8_MEMBER(futuremedia_w);
DECLARE_WRITE8_MEMBER(gouder_sf4_l_w);
DECLARE_READ8_MEMBER(gouder_sf4_l_r);
DECLARE_WRITE8_MEMBER(henggedianzi_w);
DECLARE_WRITE8_MEMBER(heng_xjzb_l_w);
DECLARE_WRITE8_MEMBER(heng_xjzb_w);
DECLARE_WRITE8_MEMBER(hes6in1_l_w);
DECLARE_WRITE8_MEMBER(hes_l_w);
DECLARE_WRITE8_MEMBER(hosenkan_w);
DECLARE_WRITE8_MEMBER(ks7058_w);
DECLARE_WRITE8_MEMBER(ks7022_w);
DECLARE_READ8_MEMBER(ks7022_r);
DECLARE_WRITE8_MEMBER(ks7032_w);
DECLARE_WRITE8_MEMBER(ks202_w);
DECLARE_WRITE8_MEMBER(ks7017_l_w);
DECLARE_WRITE8_MEMBER(ks7017_extra_w);
DECLARE_READ8_MEMBER(ks7017_extra_r);
DECLARE_WRITE8_MEMBER(kay_pp_l_w);
DECLARE_READ8_MEMBER(kay_pp_l_r);
DECLARE_WRITE8_MEMBER(kay_pp_w);
DECLARE_WRITE8_MEMBER(kasing_m_w);
DECLARE_WRITE8_MEMBER(magics_md_w);
DECLARE_WRITE8_MEMBER(nanjing_l_w);
DECLARE_READ8_MEMBER(nanjing_l_r);
DECLARE_WRITE8_MEMBER(nitra_w);
DECLARE_WRITE8_MEMBER(ntdec_asder_w);
DECLARE_WRITE8_MEMBER(ntdec_fh_m_w);
DECLARE_WRITE8_MEMBER(daou306_w);
DECLARE_WRITE8_MEMBER(gs2015_w);
DECLARE_WRITE8_MEMBER(rcm_tf_w);
DECLARE_WRITE8_MEMBER(rex_dbz_l_w);
DECLARE_READ8_MEMBER(rex_dbz_l_r);
DECLARE_WRITE8_MEMBER(rex_sl1632_w);
DECLARE_WRITE8_MEMBER(rumblestation_m_w);
DECLARE_WRITE8_MEMBER(rumblestation_w);
DECLARE_WRITE8_MEMBER(sachen_74x374_l_w);
DECLARE_READ8_MEMBER(sachen_74x374_l_r);
DECLARE_WRITE8_MEMBER(sachen_74x374a_l_w);
DECLARE_WRITE8_MEMBER(s8259_l_w);
DECLARE_WRITE8_MEMBER(s8259_m_w);
DECLARE_WRITE8_MEMBER(sa009_l_w);
DECLARE_WRITE8_MEMBER(sa0036_w);
DECLARE_WRITE8_MEMBER(sa0037_w);
DECLARE_WRITE8_MEMBER(sa72007_l_w);
DECLARE_WRITE8_MEMBER(sa72008_l_w);
DECLARE_READ8_MEMBER(tca01_l_r);
DECLARE_WRITE8_MEMBER(tcu01_l_w);
DECLARE_WRITE8_MEMBER(tcu01_m_w);
DECLARE_WRITE8_MEMBER(tcu01_w);
DECLARE_WRITE8_MEMBER(tcu02_l_w);
DECLARE_READ8_MEMBER(tcu02_l_r);
DECLARE_WRITE8_MEMBER(subor0_w);
DECLARE_WRITE8_MEMBER(subor1_w);
DECLARE_WRITE8_MEMBER(sgame_boog_l_w);
DECLARE_WRITE8_MEMBER(sgame_boog_m_w);
DECLARE_WRITE8_MEMBER(sgame_boog_w);
DECLARE_WRITE8_MEMBER(sgame_lion_m_w);
DECLARE_WRITE8_MEMBER(sgame_lion_w);
DECLARE_WRITE8_MEMBER(tengen_800008_w);
DECLARE_WRITE8_MEMBER(tengen_800032_w);
DECLARE_WRITE8_MEMBER(tengen_800037_w);
DECLARE_WRITE8_MEMBER(txc_22211_l_w);
DECLARE_READ8_MEMBER(txc_22211_l_r);
DECLARE_WRITE8_MEMBER(txc_22211_w);
DECLARE_WRITE8_MEMBER(txc_22211b_w);
DECLARE_READ8_MEMBER(txc_22211c_l_r);
DECLARE_WRITE8_MEMBER(txc_tw_l_w);
DECLARE_WRITE8_MEMBER(txc_tw_m_w);
DECLARE_WRITE8_MEMBER(txc_strikewolf_w);
DECLARE_READ8_MEMBER(txc_mxmdhtwo_l_r);
DECLARE_WRITE8_MEMBER(txc_mxmdhtwo_w);
DECLARE_WRITE8_MEMBER(waixing_a_w);
DECLARE_WRITE8_MEMBER(waixing_f_w);
DECLARE_WRITE8_MEMBER(waixing_g_w);
DECLARE_WRITE8_MEMBER(waixing_h_w);
DECLARE_WRITE8_MEMBER(waixing_sgz_w);
DECLARE_WRITE8_MEMBER(waixing_sgzlz_l_w);
DECLARE_WRITE8_MEMBER(waixing_ffv_l_w);
DECLARE_WRITE8_MEMBER(waixing_zs_w);
DECLARE_WRITE8_MEMBER(waixing_dq8_w);
DECLARE_WRITE8_MEMBER(waixing_ps2_w);
DECLARE_WRITE8_MEMBER(waixing_sec_l_w);
DECLARE_READ8_MEMBER(waixing_sh2_chr_r);
DECLARE_WRITE8_MEMBER(unl_8237_l_w);
DECLARE_WRITE8_MEMBER(unl_8237_w);
DECLARE_WRITE8_MEMBER(unl_ax5705_w);
DECLARE_WRITE8_MEMBER(unl_cc21_w);
DECLARE_WRITE8_MEMBER(unl_kof97_w);
DECLARE_WRITE8_MEMBER(ks7057_w);
DECLARE_WRITE8_MEMBER(unl_t230_w);
DECLARE_WRITE8_MEMBER(kof96_l_w);
DECLARE_READ8_MEMBER(kof96_l_r);
DECLARE_WRITE8_MEMBER(kof96_w);
DECLARE_WRITE8_MEMBER(mk2_m_w);
DECLARE_WRITE8_MEMBER(n625092_w);
DECLARE_WRITE8_MEMBER(sc127_w);
DECLARE_WRITE8_MEMBER(smb2j_w);
DECLARE_WRITE8_MEMBER(smb2jb_l_w);
DECLARE_WRITE8_MEMBER(smb2jb_extra_w);
DECLARE_WRITE8_MEMBER(unl_sf3_w);
DECLARE_WRITE8_MEMBER(unl_xzy_l_w);
DECLARE_WRITE8_MEMBER(unl_racmate_w);
DECLARE_WRITE8_MEMBER(unl_fs304_l_w);
DECLARE_WRITE8_MEMBER(btl_smb11_w);
DECLARE_WRITE8_MEMBER(btl_mariobaby_w);
DECLARE_WRITE8_MEMBER(btl_smb2a_w);
DECLARE_WRITE8_MEMBER(whirl2706_w);
DECLARE_WRITE8_MEMBER(btl_tobi_l_w);
DECLARE_WRITE8_MEMBER(btl_smb3_w);
DECLARE_WRITE8_MEMBER(btl_dn_w);
DECLARE_WRITE8_MEMBER(btl_pika_y2k_w);
DECLARE_WRITE8_MEMBER(btl_pika_y2k_m_w);
DECLARE_READ8_MEMBER(btl_pika_y2k_m_r);
DECLARE_WRITE8_MEMBER(fk23c_l_w);
DECLARE_WRITE8_MEMBER(fk23c_w);
DECLARE_WRITE8_MEMBER(bmc_64in1nr_l_w);
DECLARE_WRITE8_MEMBER(bmc_64in1nr_w);
DECLARE_WRITE8_MEMBER(bmc_190in1_w);
DECLARE_WRITE8_MEMBER(bmc_a65as_w);
DECLARE_WRITE8_MEMBER(bmc_gs2004_w);
DECLARE_WRITE8_MEMBER(bmc_gs2013_w);
DECLARE_WRITE8_MEMBER(bmc_s24in1sc03_l_w);
DECLARE_WRITE8_MEMBER(bmc_t262_w);
DECLARE_WRITE8_MEMBER(bmc_ws_m_w);
DECLARE_WRITE8_MEMBER(novel1_w);
DECLARE_WRITE8_MEMBER(novel2_w);
DECLARE_WRITE8_MEMBER(bmc_gka_w);
DECLARE_WRITE8_MEMBER(sng32_w);
DECLARE_WRITE8_MEMBER(bmc_gkb_w);
DECLARE_WRITE8_MEMBER(bmc_super700in1_w);
DECLARE_WRITE8_MEMBER(bmc_36in1_w);
DECLARE_WRITE8_MEMBER(bmc_21in1_w);
DECLARE_WRITE8_MEMBER(bmc_150in1_w);
DECLARE_WRITE8_MEMBER(bmc_35in1_w);
DECLARE_WRITE8_MEMBER(bmc_64in1_w);
DECLARE_WRITE8_MEMBER(bmc_15in1_m_w);
DECLARE_WRITE8_MEMBER(bmc_hik300_w);
DECLARE_WRITE8_MEMBER(supergun20in1_w);
DECLARE_WRITE8_MEMBER(bmc_72in1_w);
DECLARE_WRITE8_MEMBER(bmc_76in1_w);
DECLARE_WRITE8_MEMBER(bmc_1200in1_w);
DECLARE_WRITE8_MEMBER(bmc_31in1_w);
DECLARE_WRITE8_MEMBER(bmc_22g_w);
DECLARE_WRITE8_MEMBER(bmc_20in1_w);
DECLARE_WRITE8_MEMBER(bmc_110in1_w);
DECLARE_WRITE8_MEMBER(bmc_sbig7_w);
DECLARE_WRITE8_MEMBER(bmc_hik8_m_w);
DECLARE_WRITE8_MEMBER(bmc_hik4in1_m_w);
DECLARE_WRITE8_MEMBER(bmc_ball11_m_w);
DECLARE_WRITE8_MEMBER(bmc_ball11_w);
DECLARE_WRITE8_MEMBER(bmc_mario7in1_m_w);
DECLARE_WRITE8_MEMBER(bmc_gold7in1_m_w);
DECLARE_WRITE8_MEMBER(bmc_gc6in1_l_w);
DECLARE_WRITE8_MEMBER(bmc_gc6in1_w);
DECLARE_WRITE8_MEMBER(bmc_family4646_m_w);
DECLARE_WRITE8_MEMBER(bmc_vt5201_w);
DECLARE_READ8_MEMBER(bmc_vt5201_r);
DECLARE_WRITE8_MEMBER(bmc_bs5_w);
DECLARE_WRITE8_MEMBER(bmc_810544_w);
DECLARE_WRITE8_MEMBER(bmc_ntd03_w);
DECLARE_WRITE8_MEMBER(bmc_gb63_w);
DECLARE_READ8_MEMBER(bmc_gb63_r);
DECLARE_WRITE8_MEMBER(edu2k_w);
DECLARE_WRITE8_MEMBER(h2288_l_w);
DECLARE_READ8_MEMBER(h2288_l_r);
DECLARE_WRITE8_MEMBER(h2288_w);
DECLARE_WRITE8_MEMBER(shjy3_w);
DECLARE_WRITE8_MEMBER(unl_6035052_extra_w);
DECLARE_READ8_MEMBER(unl_6035052_extra_r);
DECLARE_WRITE8_MEMBER(pjoy84_m_w);
DECLARE_WRITE8_MEMBER(someri_mmc1_w);
DECLARE_WRITE8_MEMBER(someri_mmc3_w);
DECLARE_WRITE8_MEMBER(someri_vrc2_w);
DECLARE_WRITE8_MEMBER(someri_w);
DECLARE_WRITE8_MEMBER(someri_l_w);
DECLARE_WRITE8_MEMBER(fujiya_m_w);
DECLARE_READ8_MEMBER(fujiya_m_r);
DECLARE_WRITE8_MEMBER(dummy_l_w);
DECLARE_WRITE8_MEMBER(dummy_m_w);
DECLARE_WRITE8_MEMBER(dummy_w);
DECLARE_READ8_MEMBER(dummy_l_r);
DECLARE_READ8_MEMBER(dummy_m_r);
DECLARE_READ8_MEMBER(dummy_r);
void init_nes_core();
};
/*----------- defined in machine/nes.c -----------*/

148
src/mess/machine/nes.c
View File

@ -23,7 +23,6 @@
FUNCTION PROTOTYPES
***************************************************************************/
static void init_nes_core(running_machine &machine);
static void nes_machine_stop(running_machine &machine);
@ -33,55 +32,54 @@ static void fds_irq(device_t *device, int scanline, int vblank, int blanked);
FUNCTIONS
***************************************************************************/
static void init_nes_core( running_machine &machine )
void nes_state::init_nes_core()
{
nes_state *state = machine.driver_data<nes_state>();
address_space &space = machine.device("maincpu")->memory().space(AS_PROGRAM);
address_space &space = machine().device("maincpu")->memory().space(AS_PROGRAM);
static const char *const bank_names[] = { "bank1", "bank2", "bank3", "bank4" };
int prg_banks = (state->m_prg_chunks == 1) ? (2 * 2) : (state->m_prg_chunks * 2);
int prg_banks = (m_prg_chunks == 1) ? (2 * 2) : (m_prg_chunks * 2);
int i;
state->m_rom = machine.root_device().memregion("maincpu")->base();
state->m_ciram = machine.root_device().memregion("ciram")->base();
m_rom = machine().root_device().memregion("maincpu")->base();
m_ciram = machine().root_device().memregion("ciram")->base();
// other pointers got set in the loading routine
/* Brutal hack put in as a consequence of the new memory system; we really need to fix the NES code */
space.install_readwrite_bank(0x0000, 0x07ff, 0, 0x1800, "bank10");
machine.device("ppu")->memory().space(AS_PROGRAM).install_legacy_readwrite_handler(0, 0x1fff, FUNC(nes_chr_r), FUNC(nes_chr_w));
machine.device("ppu")->memory().space(AS_PROGRAM).install_legacy_readwrite_handler(0x2000, 0x3eff, FUNC(nes_nt_r), FUNC(nes_nt_w));
machine().device("ppu")->memory().space(AS_PROGRAM).install_readwrite_handler(0, 0x1fff, read8_delegate(FUNC(nes_state::nes_chr_r),this), write8_delegate(FUNC(nes_state::nes_chr_w),this));
machine().device("ppu")->memory().space(AS_PROGRAM).install_readwrite_handler(0x2000, 0x3eff, read8_delegate(FUNC(nes_state::nes_nt_r),this), write8_delegate(FUNC(nes_state::nes_nt_w),this));
state->membank("bank10")->set_base(state->m_rom);
membank("bank10")->set_base(m_rom);
/* If there is Disk Expansion and no cart has been loaded, setup memory accordingly */
if (state->m_disk_expansion && state->m_pcb_id == NO_BOARD)
if (m_disk_expansion && m_pcb_id == NO_BOARD)
{
/* If we are loading a disk we have already filled state->m_fds_data and we don't want to overwrite it,
/* If we are loading a disk we have already filled m_fds_data and we don't want to overwrite it,
if we are loading a cart image identified as mapper 20 (probably wrong mapper...) we need to alloc
memory for use in nes_fds_r/nes_fds_w. Same goes for allocation of fds_ram (used for bank2) */
if (state->m_fds_data == NULL)
if (m_fds_data == NULL)
{
UINT32 size = (state->m_prg_chunks == 1) ? 2 * 0x4000 : state->m_prg_chunks * 0x4000;
state->m_fds_data = auto_alloc_array_clear(machine, UINT8, size);
memcpy(state->m_fds_data, state->m_prg, size); // copy in fds_data the cart PRG
UINT32 size = (m_prg_chunks == 1) ? 2 * 0x4000 : m_prg_chunks * 0x4000;
m_fds_data = auto_alloc_array_clear(machine(), UINT8, size);
memcpy(m_fds_data, m_prg, size); // copy in fds_data the cart PRG
}
if (state->m_fds_ram == NULL)
state->m_fds_ram = auto_alloc_array(machine, UINT8, 0x8000);
if (m_fds_ram == NULL)
m_fds_ram = auto_alloc_array(machine(), UINT8, 0x8000);
space.install_read_handler(0x4030, 0x403f, read8_delegate(FUNC(nes_state::nes_fds_r),state));
space.install_read_handler(0x4030, 0x403f, read8_delegate(FUNC(nes_state::nes_fds_r),this));
space.install_read_bank(0x6000, 0xdfff, "bank2");
space.install_read_bank(0xe000, 0xffff, "bank1");
space.install_write_handler(0x4020, 0x402f, write8_delegate(FUNC(nes_state::nes_fds_w),state));
space.install_write_handler(0x4020, 0x402f, write8_delegate(FUNC(nes_state::nes_fds_w),this));
space.install_write_bank(0x6000, 0xdfff, "bank2");
state->membank("bank1")->set_base(&state->m_rom[0xe000]);
state->membank("bank2")->set_base(state->m_fds_ram);
membank("bank1")->set_base(&m_rom[0xe000]);
membank("bank2")->set_base(m_fds_ram);
return;
}
/* Set up the mapper callbacks */
pcb_handlers_setup(machine);
pcb_handlers_setup(machine());
/* Set up the memory handlers for the mapper */
space.install_read_bank(0x8000, 0x9fff, "bank1");
@ -93,107 +91,107 @@ static void init_nes_core( running_machine &machine )
/* configure banks 1-4 */
for (i = 0; i < 4; i++)
{
state->membank(bank_names[i])->configure_entries(0, prg_banks, state->m_prg, 0x2000);
membank(bank_names[i])->configure_entries(0, prg_banks, m_prg, 0x2000);
// some mappers (e.g. MMC5) can map PRG RAM in 0x8000-0xffff as well
if (state->m_prg_ram)
state->membank(bank_names[i])->configure_entries(prg_banks, state->m_wram_size / 0x2000, state->m_wram, 0x2000);
if (m_prg_ram)
membank(bank_names[i])->configure_entries(prg_banks, m_wram_size / 0x2000, m_wram, 0x2000);
// however, at start we point to PRG ROM
state->membank(bank_names[i])->set_entry(i);
state->m_prg_bank[i] = i;
membank(bank_names[i])->set_entry(i);
m_prg_bank[i] = i;
}
/* bank 5 configuration is more delicate, since it can have PRG RAM, PRG ROM or SRAM mapped to it */
/* we first map PRG ROM banks, then the battery bank (if a battery is present), and finally PRG RAM (state->m_wram) */
state->membank("bank5")->configure_entries(0, prg_banks, state->m_prg, 0x2000);
state->m_battery_bank5_start = prg_banks;
state->m_prgram_bank5_start = prg_banks;
state->m_empty_bank5_start = prg_banks;
/* we first map PRG ROM banks, then the battery bank (if a battery is present), and finally PRG RAM (m_wram) */
membank("bank5")->configure_entries(0, prg_banks, m_prg, 0x2000);
m_battery_bank5_start = prg_banks;
m_prgram_bank5_start = prg_banks;
m_empty_bank5_start = prg_banks;
/* add battery ram, but only if there's no trainer since they share overlapping memory. */
if (state->m_battery && !state->m_trainer)
if (m_battery && !m_trainer)
{
UINT32 bank_size = (state->m_battery_size > 0x2000) ? 0x2000 : state->m_battery_size;
int bank_num = (state->m_battery_size > 0x2000) ? state->m_battery_size / 0x2000 : 1;
state->membank("bank5")->configure_entries(prg_banks, bank_num, state->m_battery_ram, bank_size);
state->m_prgram_bank5_start += bank_num;
state->m_empty_bank5_start += bank_num;
UINT32 bank_size = (m_battery_size > 0x2000) ? 0x2000 : m_battery_size;
int bank_num = (m_battery_size > 0x2000) ? m_battery_size / 0x2000 : 1;
membank("bank5")->configure_entries(prg_banks, bank_num, m_battery_ram, bank_size);
m_prgram_bank5_start += bank_num;
m_empty_bank5_start += bank_num;
}
/* add prg ram. */
if (state->m_prg_ram)
if (m_prg_ram)
{
state->membank("bank5")->configure_entries(state->m_prgram_bank5_start, state->m_wram_size / 0x2000, state->m_wram, 0x2000);
state->m_empty_bank5_start += state->m_wram_size / 0x2000;
membank("bank5")->configure_entries(m_prgram_bank5_start, m_wram_size / 0x2000, m_wram, 0x2000);
m_empty_bank5_start += m_wram_size / 0x2000;
}
state->membank("bank5")->configure_entry(state->m_empty_bank5_start, state->m_rom + 0x6000);
membank("bank5")->configure_entry(m_empty_bank5_start, m_rom + 0x6000);
/* if we have any additional PRG RAM, point bank5 to its first bank */
if (state->m_battery || state->m_prg_ram)
state->m_prg_bank[4] = state->m_battery_bank5_start;
if (m_battery || m_prg_ram)
m_prg_bank[4] = m_battery_bank5_start;
else
state->m_prg_bank[4] = state->m_empty_bank5_start; // or shall we point to "maincpu" region at 0x6000? point is that we should never access this region if no sram or wram is present!
m_prg_bank[4] = m_empty_bank5_start; // or shall we point to "maincpu" region at 0x6000? point is that we should never access this region if no sram or wram is present!
state->membank("bank5")->set_entry(state->m_prg_bank[4]);
membank("bank5")->set_entry(m_prg_bank[4]);
if (state->m_four_screen_vram)
if (m_four_screen_vram)
{
state->m_extended_ntram = auto_alloc_array_clear(machine, UINT8, 0x2000);
state->save_pointer(NAME(state->m_extended_ntram), 0x2000);
m_extended_ntram = auto_alloc_array_clear(machine(), UINT8, 0x2000);
save_pointer(NAME(m_extended_ntram), 0x2000);
}
if (state->m_four_screen_vram)
set_nt_mirroring(machine, PPU_MIRROR_4SCREEN);
if (m_four_screen_vram)
set_nt_mirroring(machine(), PPU_MIRROR_4SCREEN);
else
{
switch (state->m_hard_mirroring)
switch (m_hard_mirroring)
{
case PPU_MIRROR_HORZ:
case PPU_MIRROR_VERT:
case PPU_MIRROR_HIGH:
case PPU_MIRROR_LOW:
set_nt_mirroring(machine, state->m_hard_mirroring);
set_nt_mirroring(machine(), m_hard_mirroring);
break;
default:
set_nt_mirroring(machine, PPU_MIRROR_NONE);
set_nt_mirroring(machine(), PPU_MIRROR_NONE);
break;
}
}
// there are still some quirk about writes to bank5... I hope to fix them soon. (mappers 34,45,52,246 have both mid_w and WRAM-->check)
if (state->m_mmc_write_mid)
space.install_legacy_write_handler(0x6000, 0x7fff, state->m_mmc_write_mid,state->m_mmc_write_mid_name);
if (state->m_mmc_write)
space.install_legacy_write_handler(0x8000, 0xffff, state->m_mmc_write, state->m_mmc_write_name);
if (!m_mmc_write_mid.isnull())
space.install_write_handler(0x6000, 0x7fff, m_mmc_write_mid);
if (!m_mmc_write.isnull())
space.install_write_handler(0x8000, 0xffff, m_mmc_write);
// In fact, we also allow single pcbs to overwrite the bank read handlers defined above,
// because some pcbs (mainly pirate ones) require protection values to be read instead of
// the expected ROM banks: these handlers, though, must take care of the ROM access as well
if (state->m_mmc_read_mid)
space.install_legacy_read_handler(0x6000, 0x7fff, state->m_mmc_read_mid,state->m_mmc_read_mid_name);
if (state->m_mmc_read)
space.install_legacy_read_handler(0x8000, 0xffff, state->m_mmc_read,state->m_mmc_read_name);
if (!m_mmc_read_mid.isnull())
space.install_read_handler(0x6000, 0x7fff, m_mmc_read_mid);
if (!m_mmc_read.isnull())
space.install_read_handler(0x8000, 0xffff, m_mmc_read);
// install additional handlers
if (state->m_pcb_id == BTL_SMB2B || state->m_mapper == 50)
if (m_pcb_id == BTL_SMB2B || m_mapper == 50)
{
space.install_legacy_write_handler(0x4020, 0x403f, FUNC(smb2jb_extra_w));
space.install_legacy_write_handler(0x40a0, 0x40bf, FUNC(smb2jb_extra_w));
space.install_write_handler(0x4020, 0x403f, write8_delegate(FUNC(nes_state::smb2jb_extra_w),this));
space.install_write_handler(0x40a0, 0x40bf, write8_delegate(FUNC(nes_state::smb2jb_extra_w),this));
}
if (state->m_pcb_id == KAISER_KS7017)
if (m_pcb_id == KAISER_KS7017)
{
space.install_legacy_read_handler(0x4030, 0x4030, FUNC(ks7017_extra_r));
space.install_legacy_write_handler(0x4020, 0x40ff, FUNC(ks7017_extra_w));
space.install_read_handler(0x4030, 0x4030, read8_delegate(FUNC(nes_state::ks7017_extra_r),this));
space.install_write_handler(0x4020, 0x40ff, write8_delegate(FUNC(nes_state::ks7017_extra_w),this));
}
if (state->m_pcb_id == UNL_603_5052)
if (m_pcb_id == UNL_603_5052)
{
space.install_legacy_read_handler(0x4020, 0x40ff, FUNC(unl_6035052_extra_r));
space.install_legacy_write_handler(0x4020, 0x40ff, FUNC(unl_6035052_extra_w));
space.install_read_handler(0x4020, 0x40ff, read8_delegate(FUNC(nes_state::unl_6035052_extra_r),this));
space.install_write_handler(0x4020, 0x40ff, write8_delegate(FUNC(nes_state::unl_6035052_extra_w),this));
}
if (state->m_pcb_id == WAIXING_SH2)
machine.device("ppu")->memory().space(AS_PROGRAM).install_legacy_read_handler(0, 0x1fff, FUNC(waixing_sh2_chr_r));
if (m_pcb_id == WAIXING_SH2)
machine().device("ppu")->memory().space(AS_PROGRAM).install_read_handler(0, 0x1fff, read8_delegate(FUNC(nes_state::waixing_sh2_chr_r),this));
}
// to be probably removed (it does nothing since a long time)
@ -291,7 +289,7 @@ void nes_state::machine_start()
{
m_ppu = machine().device<ppu2c0x_device>("ppu");
init_nes_core(machine());
init_nes_core();
machine().add_notifier(MACHINE_NOTIFY_EXIT, machine_notify_delegate(FUNC(nes_machine_stop),&machine()));
m_maincpu = machine().device<cpu_device>("maincpu");

65
src/mess/machine/nes_ines.c
View File

@ -45,49 +45,47 @@ static void ffe_irq( device_t *device, int scanline, int vblank, int blanked )
}
}
static WRITE8_HANDLER( mapper6_l_w )
WRITE8_MEMBER(nes_state::mapper6_l_w)
{
nes_state *state = space.machine().driver_data<nes_state>();
LOG_MMC(("mapper6_l_w, offset: %04x, data: %02x\n", offset, data));
switch (offset)
{
case 0x1fe:
state->m_mmc_latch1 = data & 0x80;
set_nt_mirroring(space.machine(), BIT(data, 4) ? PPU_MIRROR_HIGH : PPU_MIRROR_LOW);
m_mmc_latch1 = data & 0x80;
set_nt_mirroring(machine(), BIT(data, 4) ? PPU_MIRROR_HIGH : PPU_MIRROR_LOW);
break;
case 0x1ff:
set_nt_mirroring(space.machine(), BIT(data, 4) ? PPU_MIRROR_HORZ : PPU_MIRROR_VERT);
set_nt_mirroring(machine(), BIT(data, 4) ? PPU_MIRROR_HORZ : PPU_MIRROR_VERT);
break;
case 0x401:
state->m_IRQ_enable = data & 0x01;
m_IRQ_enable = data & 0x01;
break;
case 0x402:
state->m_IRQ_count = (state->m_IRQ_count & 0xff00) | data;
m_IRQ_count = (m_IRQ_count & 0xff00) | data;
break;
case 0x403:
state->m_IRQ_enable = 1;
state->m_IRQ_count = (state->m_IRQ_count & 0x00ff) | (data << 8);
m_IRQ_enable = 1;
m_IRQ_count = (m_IRQ_count & 0x00ff) | (data << 8);
break;
}
}
static WRITE8_HANDLER( mapper6_w )
WRITE8_MEMBER(nes_state::mapper6_w)
{
nes_state *state = space.machine().driver_data<nes_state>();
LOG_MMC(("mapper6_w, offset: %04x, data: %02x\n", offset, data));
if (!state->m_mmc_latch1) // when in "FFE mode" we are forced to use CHRRAM/EXRAM bank?
if (!m_mmc_latch1) // when in "FFE mode" we are forced to use CHRRAM/EXRAM bank?
{
prg16_89ab(space.machine(), data >> 2);
// chr8(space.machine(), data & 0x03, ???);
prg16_89ab(machine(), data >> 2);
// chr8(machine(), data & 0x03, ???);
// due to lack of info on the exact behavior, we simply act as if mmc_latch1=1
if (state->m_mmc_chr_source == CHRROM)
chr8(space.machine(), data & 0x03, CHRROM);
if (m_mmc_chr_source == CHRROM)
chr8(machine(), data & 0x03, CHRROM);
}
else if (state->m_mmc_chr_source == CHRROM) // otherwise, we can use CHRROM (when present)
chr8(space.machine(), data, CHRROM);
else if (m_mmc_chr_source == CHRROM) // otherwise, we can use CHRROM (when present)
chr8(machine(), data, CHRROM);
}
/*************************************************************
@ -101,12 +99,12 @@ static WRITE8_HANDLER( mapper6_w )
*************************************************************/
static WRITE8_HANDLER( mapper8_w )
WRITE8_MEMBER(nes_state::mapper8_w)
{
LOG_MMC(("mapper8_w, offset: %04x, data: %02x\n", offset, data));
chr8(space.machine(), data & 0x07, CHRROM);
prg16_89ab(space.machine(), data >> 3);
chr8(machine(), data & 0x07, CHRROM);
prg16_89ab(machine(), data >> 3);
}
/*************************************************************
@ -121,42 +119,41 @@ static WRITE8_HANDLER( mapper8_w )
*************************************************************/
static WRITE8_HANDLER( mapper17_l_w )
WRITE8_MEMBER(nes_state::mapper17_l_w)
{
nes_state *state = space.machine().driver_data<nes_state>();
LOG_MMC(("mapper17_l_w, offset: %04x, data: %02x\n", offset, data));
switch (offset)
{
case 0x1fe:
set_nt_mirroring(space.machine(), BIT(data, 4) ? PPU_MIRROR_HIGH : PPU_MIRROR_LOW);
set_nt_mirroring(machine(), BIT(data, 4) ? PPU_MIRROR_HIGH : PPU_MIRROR_LOW);
break;
case 0x1ff:
set_nt_mirroring(space.machine(), BIT(data, 4) ? PPU_MIRROR_HORZ : PPU_MIRROR_VERT);
set_nt_mirroring(machine(), BIT(data, 4) ? PPU_MIRROR_HORZ : PPU_MIRROR_VERT);
break;
case 0x401:
state->m_IRQ_enable = data & 0x01;
m_IRQ_enable = data & 0x01;
break;
case 0x402:
state->m_IRQ_count = (state->m_IRQ_count & 0xff00) | data;
m_IRQ_count = (m_IRQ_count & 0xff00) | data;
break;
case 0x403:
state->m_IRQ_enable = 1;
state->m_IRQ_count = (state->m_IRQ_count & 0x00ff) | (data << 8);
m_IRQ_enable = 1;
m_IRQ_count = (m_IRQ_count & 0x00ff) | (data << 8);
break;
case 0x404:
prg8_89(space.machine(), data);
prg8_89(machine(), data);
break;
case 0x405:
prg8_ab(space.machine(), data);
prg8_ab(machine(), data);
break;
case 0x406:
prg8_cd(space.machine(), data);
prg8_cd(machine(), data);
break;
case 0x407:
prg8_ef(space.machine(), data);
prg8_ef(machine(), data);
break;
case 0x410:
@ -167,7 +164,7 @@ static WRITE8_HANDLER( mapper17_l_w )
case 0x415:
case 0x416:
case 0x417:
chr1_x(space.machine(), offset & 7, data, CHRROM);
chr1_x(machine(), offset & 7, data, CHRROM);
break;
}
}

50
src/mess/machine/nes_mmc.c
View File

@ -137,10 +137,6 @@
#define LOG_FDS(x) do { if (VERBOSE) logerror x; } while (0)
static void ffe_irq( device_t *device, int scanline, int vblank, int blanked );
static DECLARE_WRITE8_HANDLER( mapper6_l_w );
static DECLARE_WRITE8_HANDLER( mapper6_w );
static DECLARE_WRITE8_HANDLER( mapper8_w );
static DECLARE_WRITE8_HANDLER( mapper17_l_w );
/*************************************************************
@ -165,74 +161,68 @@ static DECLARE_WRITE8_HANDLER( mapper17_l_w );
*************************************************************/
WRITE8_HANDLER( nes_chr_w )
WRITE8_MEMBER(nes_state::nes_chr_w)
{
nes_state *state = space.machine().driver_data<nes_state>();
int bank = offset >> 10;
if (state->m_chr_map[bank].source == CHRRAM)
if (m_chr_map[bank].source == CHRRAM)
{
state->m_chr_map[bank].access[offset & 0x3ff] = data;
m_chr_map[bank].access[offset & 0x3ff] = data;
}
}
READ8_HANDLER( nes_chr_r )
READ8_MEMBER(nes_state::nes_chr_r)
{
nes_state *state = space.machine().driver_data<nes_state>();
int bank = offset >> 10;
// a few CNROM boards contained copy protection schemes through
// suitably configured diodes, so that subsequent CHR reads can
// give actual VROM content or open bus values.
// For most boards, chr_open_bus remains always zero.
if (state->m_chr_open_bus)
if (m_chr_open_bus)
return 0xff;
return state->m_chr_map[bank].access[offset & 0x3ff];
return m_chr_map[bank].access[offset & 0x3ff];
}
WRITE8_HANDLER( nes_nt_w )
WRITE8_MEMBER(nes_state::nes_nt_w)
{
nes_state *state = space.machine().driver_data<nes_state>();
int page = ((offset & 0xc00) >> 10);
if (state->m_nt_page[page].writable == 0)
if (m_nt_page[page].writable == 0)
return;
state->m_nt_page[page].access[offset & 0x3ff] = data;
m_nt_page[page].access[offset & 0x3ff] = data;
}
READ8_HANDLER( nes_nt_r )
READ8_MEMBER(nes_state::nes_nt_r)
{
nes_state *state = space.machine().driver_data<nes_state>();
int page = ((offset & 0xc00) >> 10);
if (state->m_nt_page[page].source == MMC5FILL)
if (m_nt_page[page].source == MMC5FILL)
{
if ((offset & 0x3ff) >= 0x3c0)
return state->m_MMC5_floodattr;
return m_MMC5_floodattr;
return state->m_MMC5_floodtile;
return m_MMC5_floodtile;
}
return state->m_nt_page[page].access[offset & 0x3ff];
return m_nt_page[page].access[offset & 0x3ff];
}
WRITE8_HANDLER( nes_low_mapper_w )
WRITE8_MEMBER(nes_state::nes_low_mapper_w)
{
nes_state *state = space.machine().driver_data<nes_state>();
if (state->m_mmc_write_low)
(*state->m_mmc_write_low)(space, offset, data, mem_mask);
if (!m_mmc_write_low.isnull())
(m_mmc_write_low)(space, offset, data, mem_mask);
else
logerror("Unimplemented LOW mapper write, offset: %04x, data: %02x\n", offset + 0x4100, data);
}
READ8_HANDLER( nes_low_mapper_r )
READ8_MEMBER(nes_state::nes_low_mapper_r)
{
nes_state *state = space.machine().driver_data<nes_state>();
if (state->m_mmc_read_low)
return (*state->m_mmc_read_low)(space, offset, mem_mask);
if (!m_mmc_read_low.isnull())
return (m_mmc_read_low)(space, offset, mem_mask);
else
logerror("Unimplemented LOW mapper read, offset: %04x\n", offset + 0x4100);

15
src/mess/machine/nes_mmc.h
View File

@ -116,21 +116,6 @@ int nes_get_mmc_id(running_machine &machine, int mapper); // for iNES files
void pcb_handlers_setup(running_machine &machine);
int nes_pcb_reset(running_machine &machine);
DECLARE_WRITE8_HANDLER( nes_low_mapper_w );
DECLARE_READ8_HANDLER( nes_low_mapper_r );
DECLARE_WRITE8_HANDLER( nes_chr_w );
DECLARE_READ8_HANDLER( nes_chr_r );
DECLARE_WRITE8_HANDLER( nes_nt_w );
DECLARE_READ8_HANDLER( nes_nt_r );
DECLARE_WRITE8_HANDLER( smb2jb_extra_w );
DECLARE_WRITE8_HANDLER( ks7017_extra_w );
DECLARE_READ8_HANDLER( ks7017_extra_r );
DECLARE_WRITE8_HANDLER( unl_6035052_extra_w );
DECLARE_READ8_HANDLER( unl_6035052_extra_r );
DECLARE_READ8_HANDLER( waixing_sh2_chr_r );
//TEMPORARY PPU STUFF
/* mirroring types */

4326
src/mess/machine/nes_pcb.c
View File

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