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Atmel AIC: implement most of features
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MetalliC
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@ -5,10 +5,13 @@
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ARM AIC (Advanced Interrupt Controller) from Atmel
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typically integrated into the AM91SAM series of chips
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see http://sam7-ex256.narod.ru/include/HTML/AT91SAM7X256_AIC.html
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current implementation only handles basics needed for pgm2 (pgm2.cpp)
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current implementation was tested in pgm2 (pgm2.cpp) only, there might be mistakes if more advanced usage.
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if this peripheral is not available as a standalone chip it could also be moved to
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the CPU folder alongside the ARM instead
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TODO:
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low/high input source types
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check if level/edge input source types logic correct
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FIQ output
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*/
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#include "emu.h"
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@ -22,29 +25,61 @@ DEVICE_ADDRESS_MAP_START( regs_map, 32, arm_aic_device )
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AM_RANGE(0x080, 0x0ff) AM_READWRITE(aic_svr_r, aic_svr_w) // AIC_SVR[32] (AIC_SVR) Source Vector Register
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AM_RANGE(0x100, 0x103) AM_READ(irq_vector_r) // AIC_IVR IRQ Vector Register
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AM_RANGE(0x104, 0x107) AM_READ(firq_vector_r) // AIC_FVR FIQ Vector Register
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// 0x108 AIC_ISR Interrupt Status Register
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// 0x10C AIC_IPR Interrupt Pending Register
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// 0x110 AIC_IMR Interrupt Mask Register
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// 0x114 AIC_CISR Core Interrupt Status Register
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AM_RANGE(0x120, 0x123) AM_WRITE(aic_iecr_w) // 0x120 AIC_IECR Interrupt Enable Command Register
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AM_RANGE(0x124, 0x127) AM_WRITE(aic_idcr_w) // 0x124 AIC_IDCR Interrupt Disable Command Register
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AM_RANGE(0x128, 0x12b) AM_WRITE(aic_iccr_w) // 0x128 AIC_ICCR Interrupt Clear Command Register
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// 0x12C AIC_ISCR Interrupt Set Command Register
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AM_RANGE(0x130, 0x133) AM_WRITE(aic_eoicr_w) // 0x130 AIC_EOICR End of Interrupt Command Register
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// 0x134 AIC_SPU Spurious Vector Register
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// 0x138 AIC_DCR Debug Control Register (Protect)
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// 0x140 AIC_FFER Fast Forcing Enable Register
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// 0x144 AIC_FFDR Fast Forcing Disable Register
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// 0x148 AIC_FFSR Fast Forcing Status Register
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AM_RANGE(0x108, 0x10b) AM_READ(aic_isr_r) // AIC_ISR Interrupt Status Register
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AM_RANGE(0x10c, 0x10f) AM_READ(aic_ipr_r) // AIC_IPR Interrupt Pending Register
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AM_RANGE(0x110, 0x113) AM_READ(aic_imr_r) // AIC_IMR Interrupt Mask Register
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AM_RANGE(0x114, 0x117) AM_READ(aic_cisr_r) // AIC_CISR Core Interrupt Status Register
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AM_RANGE(0x120, 0x123) AM_WRITE(aic_iecr_w) // AIC_IECR Interrupt Enable Command Register
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AM_RANGE(0x124, 0x127) AM_WRITE(aic_idcr_w) // AIC_IDCR Interrupt Disable Command Register
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AM_RANGE(0x128, 0x12b) AM_WRITE(aic_iccr_w) // AIC_ICCR Interrupt Clear Command Register
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AM_RANGE(0x12c, 0x12f) AM_WRITE(aic_iscr_w) // AIC_ISCR Interrupt Set Command Register
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AM_RANGE(0x130, 0x133) AM_WRITE(aic_eoicr_w) // AIC_EOICR End of Interrupt Command Register
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AM_RANGE(0x134, 0x137) AM_WRITE(aic_spu_w) // AIC_SPU Spurious Vector Register
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AM_RANGE(0x138, 0x13b) AM_WRITE(aic_dcr_w) // AIC_DCR Debug Control Register (Protect)
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AM_RANGE(0x140, 0x143) AM_WRITE(aic_ffer_w) // AIC_FFER Fast Forcing Enable Register
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AM_RANGE(0x144, 0x147) AM_WRITE(aic_ffdr_w) // AIC_FFDR Fast Forcing Disable Register
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AM_RANGE(0x144, 0x147) AM_READ(aic_ffsr_r) // AIC_FFSR Fast Forcing Status Register
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ADDRESS_MAP_END
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READ32_MEMBER(arm_aic_device::irq_vector_r)
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{
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uint32_t mask = m_irqs_enabled & m_irqs_pending & ~m_fast_irqs;
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m_current_irq_vector = m_spurious_vector;
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if (mask)
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{
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// looking for highest level pending interrupt, bigger than current
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int pri = get_level();
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int midx = -1;
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do
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{
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uint8_t idx = 31 - count_leading_zeros(mask);
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if ((int)(m_aic_smr[idx] & 7) >= pri)
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{
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midx = idx;
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pri = m_aic_smr[idx] & 7;
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}
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mask ^= 1 << idx;
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} while (mask);
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if (midx > 0)
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{
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m_status = midx;
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m_current_irq_vector = m_aic_svr[midx];
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// note: Debug PROTect mode not implemented (new level pushed on stack and pending line clear only when this register writen after read)
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push_level(m_aic_smr[midx] & 7);
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if (m_aic_smr[midx] & 0x20) // auto clear pending if edge trigger mode
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m_irqs_pending ^= 1 << midx;
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}
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}
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m_core_status &= ~2;
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set_lines();
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return m_current_irq_vector;
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}
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READ32_MEMBER(arm_aic_device::firq_vector_r)
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{
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m_current_firq_vector = (m_irqs_enabled & m_irqs_pending & m_fast_irqs) ? m_aic_svr[0] : m_spurious_vector;
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return m_current_firq_vector;
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}
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@ -56,9 +91,16 @@ void arm_aic_device::device_start()
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save_item(NAME(m_irqs_pending));
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save_item(NAME(m_current_irq_vector));
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save_item(NAME(m_current_firq_vector));
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save_item(NAME(m_status));
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save_item(NAME(m_core_status));
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save_item(NAME(m_spurious_vector));
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save_item(NAME(m_debug));
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save_item(NAME(m_fast_irqs));
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save_item(NAME(m_lvlidx));
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save_item(NAME(m_aic_smr));
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save_item(NAME(m_aic_svr));
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save_item(NAME(m_level_stack));
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}
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void arm_aic_device::device_reset()
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@ -67,43 +109,54 @@ void arm_aic_device::device_reset()
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m_irqs_pending = 0;
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m_current_irq_vector = 0;
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m_current_firq_vector = 0;
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m_status = 0;
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m_core_status = 0;
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m_spurious_vector = 0;
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m_debug = 0;
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m_fast_irqs = 1;
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m_lvlidx = 0;
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for(auto & elem : m_aic_smr) { elem = 0; }
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for(auto & elem : m_aic_svr) { elem = 0; }
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for(auto & elem : m_level_stack) { elem = 0; }
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m_level_stack[0] = -1;
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}
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void arm_aic_device::set_irq(int line, int state)
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{
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// note: configurable edge / level logic is not simulated, TODO
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// note: might be incorrect if edge triggered mode set
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if (state == ASSERT_LINE)
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m_irqs_pending |= 1 << line;
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else
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m_irqs_pending &= ~(1 << line);
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recalc_irqs();
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if (m_aic_smr[line] & 0x40)
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m_irqs_pending &= ~(1 << line);
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check_irqs();
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}
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void arm_aic_device::recalc_irqs()
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void arm_aic_device::check_irqs()
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{
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uint32_t mask = m_irqs_enabled & m_irqs_pending;
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m_core_status = 0;
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uint32_t mask = m_irqs_enabled & m_irqs_pending & ~m_fast_irqs;
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if (mask)
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{
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int pri = -1;
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uint8_t midx = 0;
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// check if we have pending interrupt with level more than current
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int pri = get_level();
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do
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{
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uint8_t idx = 31 - count_leading_zeros(mask);
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if ((int)(m_aic_smr[idx] & 7) > pri)
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{
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midx = idx;
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pri = m_aic_smr[idx] & 7;
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m_core_status |= 2;
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break;
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}
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mask &= ~(1 << idx);
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mask ^= 1 << idx;
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} while (mask);
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// handle FIQ (idx 0) case ??
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m_current_irq_vector = m_aic_svr[midx];
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m_irq_out(ASSERT_LINE);
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}
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else
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m_irq_out(CLEAR_LINE);
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if (m_irqs_enabled & m_irqs_pending & m_fast_irqs)
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m_core_status |= 1;
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set_lines();
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}
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@ -31,17 +31,27 @@ public:
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DECLARE_READ32_MEMBER(irq_vector_r);
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DECLARE_READ32_MEMBER(firq_vector_r);
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DECLARE_READ32_MEMBER(aic_isr_r) { return m_status; };
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DECLARE_READ32_MEMBER(aic_cisr_r) { return m_core_status; };
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DECLARE_READ32_MEMBER(aic_ipr_r) { return m_irqs_pending; };
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DECLARE_READ32_MEMBER(aic_imr_r) { return m_irqs_enabled; };
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DECLARE_READ32_MEMBER(aic_ffsr_r) { return m_fast_irqs; };
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// can't use AM_RAM and AM_SHARE in device submaps
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DECLARE_READ32_MEMBER(aic_smr_r) { return m_aic_smr[offset]; };
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DECLARE_READ32_MEMBER(aic_svr_r) { return m_aic_svr[offset]; };
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DECLARE_WRITE32_MEMBER(aic_smr_w) { COMBINE_DATA(&m_aic_smr[offset]); };
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DECLARE_WRITE32_MEMBER(aic_svr_w) { COMBINE_DATA(&m_aic_svr[offset]); };
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DECLARE_WRITE32_MEMBER(aic_spu_w) { COMBINE_DATA(&m_spurious_vector); };
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DECLARE_WRITE32_MEMBER(aic_dcr_w) { COMBINE_DATA(&m_debug); check_irqs(); };
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DECLARE_WRITE32_MEMBER(aic_ffer_w) { m_fast_irqs |= data & mem_mask; check_irqs(); };
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DECLARE_WRITE32_MEMBER(aic_ffdr_w) { m_fast_irqs &= ~(data & mem_mask) | 1; check_irqs(); };
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DECLARE_WRITE32_MEMBER(aic_iecr_w) { m_irqs_enabled |= data & mem_mask; recalc_irqs(); };
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DECLARE_WRITE32_MEMBER(aic_idcr_w) { m_irqs_enabled &= ~(data & mem_mask); recalc_irqs(); };
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DECLARE_WRITE32_MEMBER(aic_iccr_w) { m_irqs_pending &= ~(data & mem_mask); recalc_irqs(); };
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DECLARE_WRITE32_MEMBER(aic_eoicr_w){ /*logerror("%s: aic_eoicr_w (End of Interrupt Command Register)\n", machine().describe_context().c_str());*/ }; // value doesn't matter
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DECLARE_WRITE32_MEMBER(aic_iecr_w) { m_irqs_enabled |= data & mem_mask; check_irqs(); };
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DECLARE_WRITE32_MEMBER(aic_idcr_w) { m_irqs_enabled &= ~(data & mem_mask); check_irqs(); };
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DECLARE_WRITE32_MEMBER(aic_iccr_w) { m_irqs_pending &= ~(data & mem_mask); check_irqs(); };
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DECLARE_WRITE32_MEMBER(aic_iscr_w) { m_irqs_pending |= data & mem_mask; check_irqs(); };
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DECLARE_WRITE32_MEMBER(aic_eoicr_w) { m_status = 0; pop_level(); check_irqs(); };
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void set_irq(int line, int state);
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@ -54,12 +64,24 @@ private:
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uint32_t m_irqs_pending;
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uint32_t m_current_irq_vector;
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uint32_t m_current_firq_vector;
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uint32_t m_status;
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uint32_t m_core_status;
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uint32_t m_spurious_vector;
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uint32_t m_debug;
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uint32_t m_fast_irqs;
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int m_lvlidx;
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int m_level_stack[9];
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uint32_t m_aic_smr[32];
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uint32_t m_aic_svr[32];
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devcb_write_line m_irq_out;
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void recalc_irqs();
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void check_irqs();
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void set_lines() { m_irq_out((m_core_status & ~m_debug & 2) ? ASSERT_LINE : CLEAR_LINE); }; // TODO FIQ
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void push_level(int lvl) { m_level_stack[++m_lvlidx] = lvl; };
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void pop_level() { if (m_lvlidx) --m_lvlidx; };
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int get_level() { return m_level_stack[m_lvlidx]; };
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};
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#endif
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@ -76,13 +76,13 @@
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08 - fg scroll x
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0a - fg scroll y
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0e - resolution, 0 - low (kof98), 1 - high (rest of games)
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10 - ? orleg2 - 0x13, kov2nl, kof - 0x14 at init (sprite related?)
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10 - ? orleg2 - 0x13, kov2nl, kof98 - 0x14 at init
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14 - sprite enable ? set to 0 before spriteram update, to 1 after
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16 - enable access to vrams/palettes/etc ? (bitmask)
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18 - vblank ack
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1a - ? 0 at init
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1c - ? orleg2 - 5, kov2nl, kof - 7 at init (sprite related?)
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1e - ? 2 at init (sprite related?)
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1c - ? orleg2 - 5, kov2nl, kof - 7 at init
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1e - ? 2 at init
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32 - shared RAM bank
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34, 36 - ? 0 at init, some unused xor feature ?
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38, 3a - sprite mask xor key
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@ -388,11 +388,11 @@ static ADDRESS_MAP_START( pgm2_map, AS_PROGRAM, 32, pgm2_state )
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AM_RANGE(0x40000000, 0x40000003) AM_DEVREADWRITE8("ymz774", ymz774_device, read, write, 0xffffffff)
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// internal to IGS036? - various other writes down here on startup too - could be other standard ATMEL peripherals like the ARM_AIC mixed with custom bits
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AM_RANGE(0xffffec00, 0xffffec5f) AM_RAM
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AM_RANGE(0xffffec00, 0xffffec5f) AM_RAM // SMC controller
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AM_RANGE(0xfffffc00, 0xfffffcff) AM_READWRITE8(encryption_r,encryption_w, 0xffffffff) // confirmed as encryption table for main program rom (see code at 3950)
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AM_RANGE(0xfffff000, 0xfffff14b) AM_DEVICE("arm_aic", arm_aic_device, regs_map)
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// PIOA (gpio)
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AM_RANGE(0xfffff430, 0xfffff433) AM_WRITENOP // often
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AM_RANGE(0xfffff434, 0xfffff437) AM_WRITENOP // often
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