mirror of
https://github.com/holub/mame
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ns32382: new device
This commit is contained in:
Patrick Mackinlay
parent
a733cc701c
commit
89b850c9d9
@ -4934,3 +4934,14 @@ if (MACHINES["BITMAP_PRINTER"]~=null) then
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MAME_DIR .. "src/devices/machine/bitmap_printer.h",
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}
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end
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---------------------------------------------------
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--
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--@src/devices/machine/ns32382.h,MACHINES["NS32382"] = true
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---------------------------------------------------
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if (MACHINES["NS32382"]~=null) then
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files {
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MAME_DIR .. "src/devices/machine/ns32382.cpp",
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MAME_DIR .. "src/devices/machine/ns32382.h",
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}
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end
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@ -831,6 +831,7 @@ MACHINES["NS32081"] = true
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MACHINES["NS32202"] = true
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MACHINES["NS32082"] = true
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MACHINES["BITMAP_PRINTER"] = true
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MACHINES["NS32382"] = true
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--------------------------------------------------
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-- specify available bus cores
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452
src/devices/machine/ns32382.cpp
Normal file
452
src/devices/machine/ns32382.cpp
Normal file
@ -0,0 +1,452 @@
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// license:BSD-3-Clause
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// copyright-holders:Patrick Mackinlay
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/*
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* National Semiconductor 32382 Memory Management Unit.
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*
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* Sources:
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* - http://bitsavers.org/components/national/_dataBooks/1988_National_Series_32000_Microprocessors_Databook.pdf
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*
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* TODO:
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* - tlb
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* - breakpoints
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* - cycles
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* - fast status protocol
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*/
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#include "emu.h"
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#include "ns32382.h"
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#define LOG_GENERAL (1U << 0)
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#define LOG_TRANSLATE (1U << 1)
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//#define VERBOSE (LOG_GENERAL|LOG_TRANSLATE)
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#include "logmacro.h"
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DEFINE_DEVICE_TYPE(NS32382, ns32382_device, "ns32382", "National Semiconductor 32382 Memory Management Unit")
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enum state : unsigned
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{
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IDLE = 0,
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OPERAND = 2, // awaiting operands
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RDVAL = 3, // rdval pending
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WRVAL = 4, // wrval pending
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STATUS = 5, // status word available
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RESULT = 6, // result word available
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};
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enum idbyte : u8
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{
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FORMAT_14 = 0x1e,
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};
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enum reg_mask : unsigned
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{
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BAR = 0x0, // breakpoint address register
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BMR = 0x2, // breakpoint mask register
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BDR = 0x3, // breakpoint data register
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BEAR = 0x6, // bus error address register
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MCR = 0x9, // memory management control register
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MSR = 0xa, // memory management status register
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TEAR = 0xb, // translation exception address register
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PTB0 = 0xc, // page table base register 0
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PTB1 = 0xd, // page table base register 1
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IVAR0 = 0xe, // invalidate virtual address register 0
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IVAR1 = 0xf, // invalidate virtual address register 1
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};
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enum mcr_mask : u32
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{
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MCR_TU = 0x00000001, // translate user-mode
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MCR_TS = 0x00000002, // translate supervisor-mode
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MCR_DS = 0x00000004, // dual-space translation
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MCR_AO = 0x00000008, // access level override
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MCR_BR = 0x00000010, // break on read
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MCR_BW = 0x00000020, // break on write
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MCR_BE = 0x00000040, // break on execution
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MCR_BAS = 0x00000080, // breakpoint address space
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MCR_WM = 0x000000ff,
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};
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enum msr_mask : u32
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{
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MSR_TEX = 0x00000003, // translation exception
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MSR_DDT = 0x00000004, // data direction (translate exception)
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MSR_UST = 0x00000008, // user/supervisor
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MSR_STT = 0x000000f0, // cpu status
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MSR_BP = 0x00000200, // break
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MSR_CE = 0x00000400, // cpu error
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MSR_ME = 0x00000800, // mmu error
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MSR_DDE = 0x00001000, // data direction (bus error)
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MSR_USE = 0x00002000, // user/supervisor
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MSR_STE = 0x0003c000, // cpu status
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MSR_WM = 0x0003feff,
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};
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enum msr_tex_mask : u32
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{
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TEX_IL1 = 0x00000001, // first level pte invalid
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TEX_IL2 = 0x00000002, // second level pte invalid
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TEX_PL = 0x00000003, // protection violation
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};
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enum ptb_mask : u32
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{
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PTB_AB = 0xfffff000, // address bits
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};
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enum pte_mask : u32
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{
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PTE_V = 0x00000001, // valid
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PTE_PL = 0x00000006, // protection level
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PTE_CI = 0x00000040, // (level 2 only) cache inhibit
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PTE_R = 0x00000080, // referenced
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PTE_M = 0x00000100, // modified
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PTE_USR = 0x00000e00, // user
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PTE_PFN = 0xfffff000, // page frame number
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};
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enum pte_pl_mask : u32
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{
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PL_SRO = 0x00000000, // supervisor read only
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PL_SRW = 0x00000002, // supervisor read write
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PL_URO = 0x00000004, // user read only
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PL_URW = 0x00000006, // user read write
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};
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enum va_mask : u32
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{
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VA_INDEX1 = 0xffc00000,
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VA_INDEX2 = 0x003ff000,
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VA_OFFSET = 0x00000fff,
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};
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enum st_mask : unsigned
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{
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ST_ICI = 0x0, // bus idle (CPU busy)
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ST_ICW = 0x1, // bus idle (CPU wait)
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ST_ISE = 0x3, // bus idle (slave execution)
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ST_IAM = 0x4, // interrupt acknowledge, master
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ST_IAC = 0x5, // interrupt acknowledge, cascaded
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ST_EIM = 0x6, // end of interrupt, master
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ST_EIC = 0x7, // end of interrupt, cascaded
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ST_SIF = 0x8, // sequential instruction fetch
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ST_NIF = 0x9, // non-sequential instruction fetch
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ST_ODT = 0xa, // operand data transfer
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ST_RMW = 0xb, // read RMW operand
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ST_EAR = 0xc, // effective address read
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ST_SOP = 0xd, // slave operand
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ST_SST = 0xe, // slave status
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ST_SID = 0xf, // slave ID
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};
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ns32382_device::ns32382_device(machine_config const &mconfig, char const *tag, device_t *owner, u32 clock)
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: device_t(mconfig, NS32382, tag, owner, clock)
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, ns32000_fast_slave_interface(mconfig, *this)
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, ns32000_mmu_interface(mconfig, *this)
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{
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}
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void ns32382_device::device_start()
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{
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save_item(NAME(m_bar));
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save_item(NAME(m_bdr));
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save_item(NAME(m_bear));
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save_item(NAME(m_bmr));
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save_item(NAME(m_mcr));
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save_item(NAME(m_msr));
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save_item(NAME(m_ptb));
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save_item(NAME(m_tear));
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save_item(NAME(m_opword));
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save_item(STRUCT_MEMBER(m_op, expected));
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save_item(STRUCT_MEMBER(m_op, issued));
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save_item(STRUCT_MEMBER(m_op, value));
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save_item(NAME(m_status));
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save_item(NAME(m_state));
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save_item(NAME(m_tcy));
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}
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void ns32382_device::device_reset()
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{
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m_mcr = 0;
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m_msr = 0;
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m_state = IDLE;
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}
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void ns32382_device::state_add(device_state_interface &parent, int &index)
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{
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parent.state_add(index++, "MCR", m_mcr).formatstr("%02X");
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parent.state_add(index++, "MSR", m_msr).formatstr("%08X");
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}
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u32 ns32382_device::read_st(int *icount)
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{
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if (m_state == STATUS)
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{
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m_state = (m_op[2].issued == m_op[2].expected) ? IDLE : RESULT;
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if (icount)
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*icount -= m_tcy;
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LOG("read_st status 0x%04x tcy %d %s (%s)\n", m_status, m_tcy,
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(m_state == RESULT ? "results pending" : "complete"), machine().describe_context());
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return m_status;
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}
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logerror("read_st protocol error reading status (%s)\n", machine().describe_context());
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return 0;
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}
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u32 ns32382_device::read()
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{
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if (m_state == RESULT && m_op[2].issued < m_op[2].expected)
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{
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u32 const data = u32(m_op[2].value >> (m_op[2].issued * 8));
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LOG("read_op dword %d data 0x%08x (%s)\n", m_op[2].issued >> 2, data, machine().describe_context());
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m_op[2].issued += 4;
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if (m_op[2].issued == m_op[2].expected)
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{
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LOG("read_op last result dword issued\n");
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m_state = IDLE;
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}
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return data;
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}
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logerror("read_op protocol error reading result dword (%s)\n", machine().describe_context());
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return 0;
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}
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void ns32382_device::write(u32 data)
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{
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switch (m_state)
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{
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case IDLE:
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if (BIT(data, 24, 8) == FORMAT_14)
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{
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LOG("write_fast match 0x%08x (%s)\n", data, machine().describe_context());
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m_opword = swapendian_int16(data >> 8);
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m_tcy = 0;
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// initialize operands
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for (operand &op : m_op)
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{
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op.expected = 0;
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op.issued = 0;
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op.value = 0;
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}
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// format 14: xxxx xsss s0oo ooii 0001 1110
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unsigned const size = m_opword & 3;
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switch (BIT(m_opword, 2, 4))
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{
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case 0: // rdval
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break;
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case 1: // wrval
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break;
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case 2: // lmr
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m_op[0].expected = size + 1;
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break;
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case 3: // smr
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m_op[2].expected = size + 1;
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break;
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}
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m_state = OPERAND;
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}
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break;
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case OPERAND:
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// check awaiting operand word
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if (m_op[0].issued < m_op[0].expected || m_op[1].issued < m_op[1].expected)
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{
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unsigned const n = (m_op[0].issued < m_op[0].expected) ? 0 : 1;
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operand &op = m_op[n];
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LOG("write_op op%d data 0x%04x (%s)\n", n, data, machine().describe_context());
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// insert dword into operand value
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op.value |= u64(data) << (op.issued * 8);
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op.issued += 4;
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}
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else
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logerror("write_fast protocol error unexpected operand 0x%08x (%s)\n", data, machine().describe_context());
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break;
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}
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// start execution when all operands are available
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if (m_state == OPERAND && m_op[0].issued >= m_op[0].expected && m_op[1].issued >= m_op[1].expected)
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execute();
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}
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void ns32382_device::execute()
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{
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m_status = 0;
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// format 14: xxxx xsss s0oo ooii 0001 1110
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unsigned const quick = BIT(m_opword, 7, 4);
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switch (BIT(m_opword, 2, 4))
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{
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case 0: // rdval
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m_tcy = 21;
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m_state = RDVAL;
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break;
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case 1: // wrval
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m_tcy = 21;
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m_state = WRVAL;
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break;
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case 2: // lmr
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switch (quick)
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{
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case BAR: m_bar = m_op[0].value; break;
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case BMR: m_bmr = m_op[0].value; break;
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case MCR: m_mcr = m_op[0].value; break;
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case MSR: m_msr = m_op[0].value; break;
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case TEAR: m_tear = m_op[0].value; break;
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case PTB0: m_ptb[0] = m_op[0].value & PTB_AB; break;
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case PTB1: m_ptb[1] = m_op[0].value & PTB_AB; break;
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case IVAR0: break; // TODO: invalidate tlb entry
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case IVAR1: break; // TODO: invalidate tlb entry
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default:
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logerror("lmr unknown register %d (%s)\n", quick, machine().describe_context());
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break;
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}
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m_tcy = 30;
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break;
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case 3: // smr
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switch (quick)
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{
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case BAR: m_op[2].value = m_bar; break;
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case BMR: m_op[2].value = m_bmr; break;
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case BDR: m_op[2].value = m_bdr; break;
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case BEAR: m_op[2].value = m_bear; break;
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case MCR: m_op[2].value = m_mcr & MCR_WM; break;
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case MSR: m_op[2].value = m_msr & MSR_WM; break;
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case TEAR: m_op[2].value = m_tear; break;
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case PTB0: m_op[2].value = m_ptb[0]; break;
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case PTB1: m_op[2].value = m_ptb[1]; break;
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default:
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logerror("smr unknown register %d (%s)\n", quick, machine().describe_context());
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break;
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}
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m_tcy = 25;
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break;
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}
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// exceptions suppress result issue
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if (m_status & SLAVE_Q)
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m_op[2].expected = 0;
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if (m_state == OPERAND)
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m_state = STATUS;
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}
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ns32382_device::translate_result ns32382_device::translate(address_space &space, unsigned st, u32 &address, bool user, bool write, bool pfs, bool debug)
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{
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// check translation required
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if ((!(m_mcr & MCR_TU) && user) || (!(m_mcr & MCR_TS) && !user))
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return COMPLETE;
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// treat WRVAL as write
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write |= m_state == WRVAL;
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bool const address_space = (m_mcr & MCR_DS) && user;
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unsigned const access_level = (user && !(m_mcr & MCR_AO))
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? ((write || st == ST_RMW) ? PL_URW : PL_URO) : ((write || st == ST_RMW) ? PL_SRW : PL_SRO);
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if (m_state == IDLE && !debug)
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m_msr &= ~(MSR_STT | MSR_UST | MSR_DDT | MSR_TEX);
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// read level 1 page table entry
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u32 const pte1_address = m_ptb[address_space] | ((address & VA_INDEX1) >> 20);
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u32 const pte1 = space.read_dword(pte1_address);
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LOGMASKED(LOG_TRANSLATE, "translate level 1 page table address 0x%06x entry 0x%08x\n", pte1_address, pte1);
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if (access_level > (pte1 & PTE_PL) || !(pte1 & PTE_V))
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{
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if (m_state == IDLE && !debug)
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{
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m_msr |= ((st & 15) << 4) | (user ? MSR_UST : 0) | (write ? MSR_DDT : 0);
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if (access_level > (pte1 & PTE_PL))
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m_msr |= TEX_PL;
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else if (!(pte1 & PTE_V))
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m_msr |= TEX_IL1;
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m_tear = address;
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}
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if (m_state == RDVAL || m_state == WRVAL)
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{
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if (pte1 & PTE_V)
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{
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m_state = STATUS;
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m_status |= SLAVE_F;
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return CANCEL;
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}
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else
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m_state = IDLE;
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}
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LOGMASKED(LOG_TRANSLATE, "translate level 1 abort address 0x%08x\n", address);
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return ABORT;
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}
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// set referenced
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if (!(pte1 & PTE_R) && !debug)
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space.write_dword(pte1_address, pte1 | PTE_R);
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// read level 2 page table entry
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u32 const pte2_address = (pte1 & PTE_PFN) | ((address & VA_INDEX2) >> 10);
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u32 const pte2 = space.read_dword(pte2_address);
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LOGMASKED(LOG_TRANSLATE, "translate level 2 page table address 0x%06x entry 0x%08x\n", pte2_address, pte2);
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if (access_level > (pte2 & PTE_PL) || !(pte2 & PTE_V))
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{
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if (m_state == IDLE && !debug)
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{
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m_msr |= ((st & 15) << 4) | (user ? MSR_UST : 0) | (write ? MSR_DDT : 0);
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if (access_level > (pte2 & PTE_PL))
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m_msr |= TEX_PL;
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else if (!(pte2 & PTE_V))
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m_msr |= TEX_IL2;
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m_tear = address;
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}
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if (m_state == RDVAL || m_state == WRVAL)
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{
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m_state = STATUS;
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if (pte1 & PTE_V)
|
||||
m_status |= SLAVE_F;
|
||||
|
||||
return CANCEL;
|
||||
}
|
||||
else
|
||||
{
|
||||
LOGMASKED(LOG_TRANSLATE, "translate level 2 abort address 0x%08x\n", address);
|
||||
return ABORT;
|
||||
}
|
||||
}
|
||||
|
||||
// set modified and referenced
|
||||
if ((!(pte2 & PTE_R) || (write && !(pte2 & PTE_M))) && !debug)
|
||||
space.write_dword(pte2_address, pte2 | (write ? PTE_M : 0) | PTE_R);
|
||||
|
||||
address = (pte2 & PTE_PFN) | (address & VA_OFFSET);
|
||||
LOGMASKED(LOG_TRANSLATE, "translate complete 0x%08x\n", address);
|
||||
|
||||
return COMPLETE;
|
||||
}
|
||||
66
src/devices/machine/ns32382.h
Normal file
66
src/devices/machine/ns32382.h
Normal file
@ -0,0 +1,66 @@
|
||||
// license:BSD-3-Clause
|
||||
// copyright-holders:Patrick Mackinlay
|
||||
|
||||
#ifndef MAME_MACHINE_NS32382_H
|
||||
#define MAME_MACHINE_NS32382_H
|
||||
|
||||
#pragma once
|
||||
|
||||
#include "cpu/ns32000/slave.h"
|
||||
|
||||
class ns32382_device
|
||||
: public device_t
|
||||
, public ns32000_fast_slave_interface
|
||||
, public ns32000_mmu_interface
|
||||
{
|
||||
public:
|
||||
ns32382_device(machine_config const &mconfig, char const *tag, device_t *owner, u32 clock);
|
||||
|
||||
// ns32000_slave_interface overrides
|
||||
virtual void state_add(device_state_interface &parent, int &index) override;
|
||||
|
||||
// ns32000_fast_slave_interface overrides
|
||||
virtual u32 read_st(int *icount = nullptr) override;
|
||||
virtual void write(u32 data) override;
|
||||
virtual u32 read() override;
|
||||
|
||||
// ns32000_mmu_interface overrides
|
||||
virtual translate_result translate(address_space &space, unsigned st, u32 &address, bool user, bool write, bool pfs = false, bool debug = false) override;
|
||||
|
||||
protected:
|
||||
// device_t overrides
|
||||
virtual void device_start() override;
|
||||
virtual void device_reset() override;
|
||||
|
||||
void execute();
|
||||
|
||||
private:
|
||||
// registers
|
||||
u32 m_bar; // breakpoint address register
|
||||
u32 m_bdr; // breakpoint data register
|
||||
u32 m_bear; // bus error address register
|
||||
u32 m_bmr; // breakpoint mask register
|
||||
u32 m_mcr; // memory management control register
|
||||
u32 m_msr; // memory management status register
|
||||
u32 m_ptb[2]; // page table base registers
|
||||
u32 m_tear; // translation exception address register
|
||||
|
||||
// operating state
|
||||
u16 m_opword;
|
||||
struct operand
|
||||
{
|
||||
u32 expected;
|
||||
u32 issued;
|
||||
u64 value;
|
||||
}
|
||||
m_op[3];
|
||||
u16 m_status;
|
||||
|
||||
// implementation state
|
||||
u32 m_state;
|
||||
u32 m_tcy;
|
||||
};
|
||||
|
||||
DECLARE_DEVICE_TYPE(NS32382, ns32382_device)
|
||||
|
||||
#endif // MAME_MACHINE_NS32382_H
|
||||
Loading…
Reference in New Issue
Block a user