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New NOT_WORKING software list additions

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---------------------------------------
ibm5170: The ChessMachine (Installer V3.0) [hap]
ibm5170: The ChessMachine (Installer V2.2) [hap]
This commit is contained in:
hap 2019-05-27 19:19:43 +02:00
parent ec8a8deedd
commit 93060c917e
6 changed files with 289 additions and 6 deletions
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53
hash/ibm5170.xml
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@ -8543,6 +8543,56 @@
</part>
</software>
<software name="chessm" supported="no">
<!-- uses ChessMachine ISA card -->
<description>The ChessMachine (Installer V3.0)</description>
<year>1991</year>
<publisher>Tasc</publisher>
<info name="version" value="3.0" />
<info name="serial" value="WR.887.68.354" />
<info name="usage" value="Installer registration number is WR.887.68.354. ChessMachine ISA card required." />
<part name="flop1" interface="floppy_3_5">
<dataarea name="flop" size="737280">
<feature name="part_id" value="Disk 1" />
<rom name="disk1.img" size="737280" crc="6659ab39" sha1="1459c9e2425fd19042d580872cf77d95debaa023"/>
</dataarea>
</part>
<part name="flop2" interface="floppy_3_5">
<dataarea name="flop" size="737280">
<feature name="part_id" value="Disk 2" />
<rom name="disk2.img" size="737280" crc="d7182b95" sha1="bb474de5e0f7a3a5eecbf004ec1038a4a3d0ab9e"/>
</dataarea>
</part>
<part name="flop3" interface="floppy_3_5">
<dataarea name="flop" size="737280">
<feature name="part_id" value="Game 1990" />
<rom name="game1990.img" size="737280" crc="056e572d" sha1="620a44254c1f4e86c01a4d4b407b820f45993a1c"/>
</dataarea>
</part>
</software>
<software name="chessm22" supported="no">
<!-- uses ChessMachine ISA card -->
<description>The ChessMachine (Installer V2.2)</description>
<year>1991</year>
<publisher>Tasc</publisher>
<info name="version" value="2.2" />
<info name="serial" value="50677" />
<info name="usage" value="ChessMachine ISA card required" />
<part name="flop1" interface="floppy_3_5">
<dataarea name="flop" size="737280">
<feature name="part_id" value="Disk 1" />
<rom name="disk1.img" size="737280" crc="a93939a6" sha1="2f3927e50dd82b93ca3fa1436f5b664abc18d061"/>
</dataarea>
</part>
<part name="flop2" interface="floppy_3_5">
<dataarea name="flop" size="737280">
<feature name="part_id" value="Option 1" />
<rom name="option1.img" size="737280" crc="cba1616e" sha1="d773fbf810957c419d63cd4abb8466651ff1a832"/>
</dataarea>
</part>
</software>
<software name="cischeat">
<!-- Dumped via Kryoflux -->
<description>Cisco Heat - All American Police Car Race</description>
@ -9560,10 +9610,11 @@
</software>
<software name="finalchs">
<!-- needs finalchs ISA card to work -->
<!-- uses Final ChessCard ISA card -->
<description>The Final ChessCard</description>
<year>1989</year>
<publisher>Tasc</publisher>
<info name="usage" value="Final ChessCard ISA card required" />
<part name="flop1" interface="floppy_3_5">
<dataarea name="flop" size="1474560">
<rom name="finalchs.img" size="1474560" crc="3428d309" sha1="ea345d6828ffd9ff9be3ac4e037e80491bb7ce74"/>

2
scripts/src/bus.lua
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@ -1231,6 +1231,8 @@ if (BUSES["ISA"]~=null) then
MAME_DIR .. "src/devices/bus/isa/wdxt_gen.h",
MAME_DIR .. "src/devices/bus/isa/adlib.cpp",
MAME_DIR .. "src/devices/bus/isa/adlib.h",
MAME_DIR .. "src/devices/bus/isa/chessm.cpp",
MAME_DIR .. "src/devices/bus/isa/chessm.h",
MAME_DIR .. "src/devices/bus/isa/com.cpp",
MAME_DIR .. "src/devices/bus/isa/com.h",
MAME_DIR .. "src/devices/bus/isa/fdc.cpp",

167
src/devices/bus/isa/chessm.cpp Normal file
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@ -0,0 +1,167 @@
// license:BSD-3-Clause
// copyright-holders:hap
/*
The ChessMachine by Tasc
8-bit ISA card, successor of The Final ChessCard.
No ROM on the card this time, the chess program is sent to RAM instead.
VLSI VY86C010-12QC (ARM2), seen with 30MHz XTAL, but XTAL label usually scratched off.
128KB, 512KB, or 1MB RAM. 512KB version probably the most common.
Also seen with VY86C061PSTC (ARM6) @ 32MHz, very rare or prototype.
TODO:
- It doesn't work. Card detection routine works, comms test works, RAM test works,
program checksum works. But after it's done with tests and needs to start the chess
game, it doesn't acknowledge IRQ and locks up.
- add RAM/CPU configuration
*/
#include "emu.h"
#include "chessm.h"
DEFINE_DEVICE_TYPE(ISA8_CHESSM, isa8_chessm_device, "isa_chessm", "ChessMachine")
//-------------------------------------------------
// constructor
//-------------------------------------------------
isa8_chessm_device::isa8_chessm_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock) :
device_t(mconfig, ISA8_CHESSM, tag, owner, clock),
device_isa8_card_interface(mconfig, *this),
m_maincpu(*this, "maincpu"),
m_mainlatch(*this, "mainlatch"),
m_sublatch(*this, "sublatch")
{ }
//-------------------------------------------------
// device_start - device-specific startup
//-------------------------------------------------
void isa8_chessm_device::device_start()
{
set_isa_device();
m_installed = false;
}
//-------------------------------------------------
// device_reset - device-specific reset
//-------------------------------------------------
void isa8_chessm_device::device_reset()
{
if (!m_installed)
{
// MAME doesn't allow reading ioport at device_start
u16 port = ioport("DSW")->read() * 0x40 + 0x10;
m_isa->install_device(port, port+1, read8_delegate(FUNC(isa8_chessm_device::chessm_r), this), write8_delegate(FUNC(isa8_chessm_device::chessm_w), this));
m_installed = true;
}
}
void isa8_chessm_device::device_reset_after_children()
{
// hold ARM CPU in reset state
chessm_w(machine().dummy_space(), 1, 0);
}
//-------------------------------------------------
// input_ports - device-specific input ports
//-------------------------------------------------
static INPUT_PORTS_START( chessm )
PORT_START("DSW") // DIP switch on the ISA card PCB, installer shows range 0x110-0x390
PORT_DIPNAME( 0x0f, 0x08, "I/O Port Address" ) PORT_DIPLOCATION("CM_SW1:1,2,3,4")
PORT_DIPSETTING( 0x00, "0x010 (Invalid)" )
PORT_DIPSETTING( 0x01, "0x050 (Invalid)" )
PORT_DIPSETTING( 0x02, "0x090 (Invalid)" )
PORT_DIPSETTING( 0x03, "0x0D0 (Invalid)" )
PORT_DIPSETTING( 0x04, "0x110" )
PORT_DIPSETTING( 0x05, "0x150" )
PORT_DIPSETTING( 0x06, "0x190" )
PORT_DIPSETTING( 0x07, "0x1D0" )
PORT_DIPSETTING( 0x08, "0x210" )
PORT_DIPSETTING( 0x09, "0x250" )
PORT_DIPSETTING( 0x0a, "0x290" )
PORT_DIPSETTING( 0x0b, "0x2D0" )
PORT_DIPSETTING( 0x0c, "0x310" )
PORT_DIPSETTING( 0x0d, "0x350" )
PORT_DIPSETTING( 0x0e, "0x390" )
PORT_DIPSETTING( 0x0f, "0x3D0 (Invalid)" )
INPUT_PORTS_END
ioport_constructor isa8_chessm_device::device_input_ports() const
{
return INPUT_PORTS_NAME(chessm);
}
//-------------------------------------------------
// device_add_mconfig - add device configuration
//-------------------------------------------------
void isa8_chessm_device::device_add_mconfig(machine_config &config)
{
ARM(config, m_maincpu, 30_MHz_XTAL/2);
m_maincpu->set_addrmap(AS_PROGRAM, &isa8_chessm_device::chessm_mem);
m_maincpu->set_copro_type(arm_cpu_device::copro_type::VL86C020);
GENERIC_LATCH_8(config, m_mainlatch);
GENERIC_LATCH_8(config, m_sublatch);
m_sublatch->data_pending_callback().set_inputline(m_maincpu, ARM_FIRQ_LINE);
}
/******************************************************************************
I/O
******************************************************************************/
// External handlers
READ8_MEMBER(isa8_chessm_device::chessm_r)
{
if (offset == 0)
return m_mainlatch->read();
else
return m_mainlatch->pending_r() ? 0 : 2;
}
WRITE8_MEMBER(isa8_chessm_device::chessm_w)
{
if (offset == 0)
{
if (m_suspended)
m_maincpu->space(AS_PROGRAM).write_byte(m_ram_offset++, data);
else
m_sublatch->write(data);
}
else
{
// disable CPU, PC side can write to first 256-byte block of RAM when in this state
m_suspended = bool(~data & 1);
m_maincpu->set_input_line(INPUT_LINE_RESET, m_suspended ? ASSERT_LINE : CLEAR_LINE);
m_sublatch->read(); // clear IRQ
m_ram_offset = 0xff;
}
}
// Internal (on-card CPU)
void isa8_chessm_device::chessm_mem(address_map &map)
{
map(0x00000000, 0x0007ffff).ram();
map(0x00380000, 0x00380000).r(m_sublatch, FUNC(generic_latch_8_device::read)).w(m_mainlatch, FUNC(generic_latch_8_device::write));
}

56
src/devices/bus/isa/chessm.h Normal file
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@ -0,0 +1,56 @@
// license:BSD-3-Clause
// copyright-holders:hap
/*
The ChessMachine by Tasc
*/
#ifndef MAME_BUS_ISA_CHESSM_H
#define MAME_BUS_ISA_CHESSM_H
#pragma once
#include "isa.h"
#include "cpu/arm/arm.h"
#include "machine/gen_latch.h"
class isa8_chessm_device :
public device_t,
public device_isa8_card_interface
{
public:
// construction/destruction
isa8_chessm_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock);
protected:
// device-level overrides
virtual void device_start() override;
virtual void device_reset() override;
virtual void device_reset_after_children() override;
// optional information overrides
virtual void device_add_mconfig(machine_config &config) override;
virtual ioport_constructor device_input_ports() const override;
private:
required_device<arm_cpu_device> m_maincpu;
required_device<generic_latch_8_device> m_mainlatch;
required_device<generic_latch_8_device> m_sublatch;
u8 m_ram_offset;
bool m_suspended;
bool m_installed;
DECLARE_READ8_MEMBER(chessm_r);
DECLARE_WRITE8_MEMBER(chessm_w);
void chessm_mem(address_map &map);
};
DECLARE_DEVICE_TYPE(ISA8_CHESSM, isa8_chessm_device)
#endif // MAME_BUS_ISA_CHESSM_H

12
src/devices/bus/isa/finalchs.cpp
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@ -8,7 +8,11 @@ The Final ChessCard by Tasc
It is similar to the C64 version, actually not as impressive since a PC from around 1989
should be able to run a good chess game by itself.
Tasc later released The ChessMachine ISA card, not emulated yet.
Tasc later released The ChessMachine ISA card, see chessm.cpp.
TODO:
- ChessMachine software(which claims to support this card too) does not detect it,
maybe it expects a newer ROM revision?
*/
@ -84,7 +88,7 @@ const tiny_rom_entry *isa8_finalchs_device::device_rom_region() const
static INPUT_PORTS_START( finalchs )
PORT_START("DSW") // DIP switch on the ISA card PCB
PORT_DIPNAME( 0x0f, 0x07, "I/O Port Address" ) PORT_DIPLOCATION("SW1:!1,!2,!3,!4")
PORT_DIPNAME( 0x0f, 0x08, "I/O Port Address" ) PORT_DIPLOCATION("FCC_SW1:1,2,3,4")
PORT_DIPSETTING( 0x00, "0x100" )
PORT_DIPSETTING( 0x01, "0x110" )
PORT_DIPSETTING( 0x02, "0x120" )
@ -137,7 +141,7 @@ READ8_MEMBER(isa8_finalchs_device::finalchs_r)
if (offset == 0)
return m_mainlatch->read();
else
return !m_mainlatch->pending_r();
return m_mainlatch->pending_r() ? 0 : 1;
}
WRITE8_MEMBER(isa8_finalchs_device::finalchs_w)
@ -147,7 +151,7 @@ WRITE8_MEMBER(isa8_finalchs_device::finalchs_w)
}
// internal (on-card CPU)
// Internal (on-card CPU)
void isa8_finalchs_device::finalchs_mem(address_map &map)
{

5
src/devices/bus/isa/isa_cards.cpp
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@ -73,6 +73,7 @@
#include "pds.h"
// other
#include "chessm.h"
#include "finalchs.h"
@ -101,7 +102,6 @@ void pc_isa8_cards(device_slot_interface &device)
device.option_add("fdc344", ISA8_FDC344);
device.option_add("fdcmag", ISA8_FDCMAG);
device.option_add("wdxt_gen", ISA8_WDXT_GEN);
device.option_add("finalchs", ISA8_FINALCHS);
device.option_add("xtide", ISA8_XTIDE);
device.option_add("side116", ISA8_SIDE116);
device.option_add("hdc", ISA8_HDC);
@ -122,6 +122,8 @@ void pc_isa8_cards(device_slot_interface &device)
device.option_add("pds", ISA8_PDS);
device.option_add("lba_enhancer", ISA8_LBA_ENHANCER);
device.option_add("asc88", ASC88);
device.option_add("chessm", ISA8_CHESSM);
device.option_add("finalchs", ISA8_FINALCHS);
}
void pc_isa16_cards(device_slot_interface &device)
@ -159,6 +161,7 @@ void pc_isa16_cards(device_slot_interface &device)
device.option_add("dectalk", ISA8_DECTALK);
device.option_add("pds", ISA8_PDS);
device.option_add("lba_enhancer", ISA8_LBA_ENHANCER);
device.option_add("chessm", ISA8_CHESSM);
device.option_add("finalchs", ISA8_FINALCHS);
// 16-bit
device.option_add("ide", ISA16_IDE);