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bus/vme: De-skeletonized vme_hcpu30.cpp. (#7467)
This commit is contained in:
shattered
GitHub
parent
171604d40a
commit
96773054a1
@ -2,22 +2,31 @@
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// copyright-holders:Sergey Svishchev
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/*
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* Besta HCPU30 board, skeleton driver.
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* Besta HCPU30 board.
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*
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* Supported by SysV R3 "Bestix" port and also by Linux port,
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* see https://github.com/shattered/linux-m68k
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*
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* 68030 @ 33 MHz - primary CPU
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* 68882 @ ?? Mhz - FPU
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* 68020 @ ?? MHz - I/O CPU (using shared memory region)
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* 68882 @ 33 Mhz - FPU
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* 68020 @ 16 MHz - I/O CPU (using shared memory region)
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*
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* 4 or 16 MB of DRAM
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* 8 or 32 KB of NVRAM
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*
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* WD33C93 - SCSI
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* 33C93A - SCSI
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* DP8473 - Floppy
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* i82586? - Ethernet
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* 62421 - Real-time clock
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* i82590 - Ethernet
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* 62421A - Real-time clock
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*
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* To do:
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*
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* - pass functional test
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* - boot to multiuser (SysV and Linux)
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* - add LAN and Centronics
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* - floppy: how is TC signal generated? (m_fdcdrq_hack); ready signal routing; dp8493 hacks
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* - dump PALs (should help with irq routing)
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*
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*/
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#include "emu.h"
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@ -55,48 +64,87 @@ DEFINE_DEVICE_TYPE(VME_HCPU30, vme_hcpu30_card_device, "hcpu30", "Besta HCPU30 C
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void vme_hcpu30_card_device::hcpu30_mem(address_map &map)
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{
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map(0x00000000, 0x00000007).ram().w(FUNC(vme_hcpu30_card_device::bootvect_w)); /* After first write we act as RAM */
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map(0x00000000, 0x00000007).rom().r(FUNC(vme_hcpu30_card_device::bootvect_r)); /* ROM mirror just during reset */
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map(0x00000008, 0x001fffff).ram(); // local bus DRAM, 4MB
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map(0x00200000, 0x00201fff).ram(); // .share("iocpu");
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map(0xff000000, 0xff007fff).rom().mirror(0x8000).region("user1", 0);
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map(0xff020000, 0xff027fff).ram().mirror(0x8000); // SRAM 32KB
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map(0xffff8000, 0xffff8fff).unmaprw(); // shared memory with iocpu
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map(0xffff9000, 0xffff9fff).ram(); // SRAM, optional: battery-backed
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map(0xfffff100, 0xfffff11f).unmaprw(); // VME bus configuration (accessed after DIP switch read)
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map(0xfffff120, 0xfffff123).portr("SA1");
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map(0xfffff200, 0xfffff2ff).unmaprw();
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map.unmap_value_high();
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map(0x00000000, 0x003fffff).ram().share("dram"); // local bus DRAM, 4 MB
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map(0x00400000, 0x00ffffff).ram().share("hldram"); // optional HLDRAM
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map(0xff000000, 0xff007fff).rom().region("user1", 0).mirror(0x8000);
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map(0xfff1f400, 0xfff1f4ff).unmaprw(); // LAN DMA
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map(0xff020000, 0xff021fff).ram().share("mailbox").mirror(0x8000); // SRAM 32KB -- shared with iocpu
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map(0xff022000, 0xff027fff).ram().mirror(0x8000);
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map(0xffff8000, 0xffff9fff).ram().share("mailbox");
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map(0xfffff000, 0xfffff0ff).rw(FUNC(vme_hcpu30_card_device::dma_r), FUNC(vme_hcpu30_card_device::dma_w));
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map(0xfffff100, 0xfffff11f).rw(FUNC(vme_hcpu30_card_device::irq_state_r), FUNC(vme_hcpu30_card_device::irq_mask_w));
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map(0xfffff120, 0xfffff13f).rw(FUNC(vme_hcpu30_card_device::rtc_r), FUNC(vme_hcpu30_card_device::rtc_w));
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map(0xfffff200, 0xfffff2ff).rw("scsi:7:wd33c93", FUNC(wd33c93_device::indir_r), FUNC(wd33c93_device::indir_w)).umask32(0xffff0000);
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map(0xfffff300, 0xfffff3ff).rw("duscc", FUNC(duscc68562_device::read), FUNC(duscc68562_device::write));
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map(0xfffff600, 0xfffff6ff).unmaprw();
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map(0xfffff700, 0xfffff7ff).unmaprw();
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map(0xfffff580, 0xfffff583).rw("scsi:7:wd33c93", FUNC(wd33c93_device::dma_r), FUNC(wd33c93_device::dma_w)).umask32(0xff000000);
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map(0xfffff600, 0xfffff6ff).unmaprw(); // LAN
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map(0xfffff700, 0xfffff7ff).m("floppy", FUNC(dp8473_device::map));
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}
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void vme_hcpu30_card_device::hcpu30_os_mem(address_map &map)
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{
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// bus error handler
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map(0x00000000, 0xffffffff).rw(FUNC(vme_hcpu30_card_device::trap_r), FUNC(vme_hcpu30_card_device::trap_w));
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// shared memory with iocpu
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map(0x00000000, 0x003fffff).ram().share("dram");
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map(0x00400000, 0x00ffffff).ram().share("hldram");
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map(0xffff8000, 0xffff9fff).ram().share("mailbox");
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}
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void vme_hcpu30_card_device::cpu_space_map(address_map &map)
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{
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map(0xfffffff0, 0xffffffff).lr16(NAME([](offs_t offset) -> u16 { return 0x18 + offset; }));
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}
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void vme_hcpu30_card_device::oscpu_space_map(address_map &map)
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{
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map(0xfffffff0, 0xffffffff).lr16(NAME([this](offs_t offset) -> u16 {
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u16 vec = (offset & 1) ? (m_mailbox[offset >> 1] >> 8) : (m_mailbox[offset >> 1] >> 24);
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logerror("68030 iack %d = %02x\n", offset, vec);
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if (1 || BIT(m_irq_state, 6)) // FIXME: irq routing is not fully understood
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{
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m_irq_state &= ~(1 << 6); // raise IRQ30*
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update_030_irq(offset, CLEAR_LINE);
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return vec;
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}
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else
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{
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return 0;
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}
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}));
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}
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static INPUT_PORTS_START(hcpu30)
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PORT_START("SA1")
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PORT_DIPNAME(0x03000000, 0x00000000, "Console port speed")
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PORT_DIPSETTING(0x00000000, "9600")
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PORT_DIPSETTING(0x01000000, "19200")
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PORT_DIPSETTING(0x02000000, "38400")
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PORT_DIPSETTING(0x03000000, "4800")
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PORT_DIPNAME(0x04000000, 0x04000000, "Boot into...")
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PORT_DIPSETTING(0x00000000, "UNIX")
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PORT_DIPSETTING(0x04000000, "Monitor")
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PORT_DIPNAME(0x10000000, 0x00000000, "VME bus width")
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PORT_DIPSETTING(0x00000000, "32 bits")
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PORT_DIPSETTING(0x10000000, "16 bits")
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PORT_DIPNAME(0x20000000, 0x00000000, "VME bus free")
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PORT_DIPSETTING(0x00000000, "ROR")
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PORT_DIPSETTING(0x20000000, "not ROR")
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PORT_DIPNAME(0x40000000, 0x00000000, "Cache burst mode")
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PORT_DIPSETTING(0x00000000, "Off")
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PORT_DIPSETTING(0x40000000, "On")
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PORT_DIPNAME(0x80000000, 0x00000000, "Undefined")
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PORT_DIPSETTING(0x00000000, "Off")
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PORT_DIPSETTING(0x80000000, "On")
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PORT_DIPNAME(0x03, 0x00, "Console port speed")
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PORT_DIPSETTING(0x00, "9600")
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PORT_DIPSETTING(0x01, "19200")
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PORT_DIPSETTING(0x02, "38400")
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PORT_DIPSETTING(0x03, "4800")
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PORT_DIPNAME(0x04, 0x04, "Boot into...")
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PORT_DIPSETTING(0x00, "UNIX")
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PORT_DIPSETTING(0x04, "Monitor")
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PORT_DIPNAME(0x08, 0x00, "Undefined 1")
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PORT_DIPSETTING(0x00, "Off")
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PORT_DIPSETTING(0x08, "On")
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PORT_DIPNAME(0x10, 0x00, "VME bus width")
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PORT_DIPSETTING(0x00, "32 bits")
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PORT_DIPSETTING(0x10, "16 bits")
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PORT_DIPNAME(0x20, 0x00, "VME bus free")
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PORT_DIPSETTING(0x00, "ROR")
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PORT_DIPSETTING(0x20, "REC")
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PORT_DIPNAME(0x40, 0x00, "Cache burst mode")
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PORT_DIPSETTING(0x00, "Off")
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PORT_DIPSETTING(0x40, "On")
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PORT_DIPNAME(0x80, 0x00, "Undefined 2")
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PORT_DIPSETTING(0x00, "Off")
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PORT_DIPSETTING(0x80, "On")
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INPUT_PORTS_END
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ROM_START(hcpu30)
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ROM_REGION32_BE(0x8000, "user1", ROMREGION_ERASEFF)
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// Rev 1.E of 09-NOV-1993
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ROM_LOAD("hcpu30.27c256.dat", 0x0000, 0x8000, CRC(d24da66e) SHA1(5431b0559b168a995e725b35e1465a0b8ee8aa72))
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ROM_END
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@ -118,24 +166,38 @@ ioport_constructor vme_hcpu30_card_device::device_input_ports() const
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return INPUT_PORTS_NAME(hcpu30);
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}
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static void hcpu_floppies(device_slot_interface &device)
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{
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device.option_add("525qd", FLOPPY_525_QD);
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}
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//-------------------------------------------------
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// device_add_mconfig - add device configuration
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//-------------------------------------------------
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void vme_hcpu30_card_device::device_add_mconfig(machine_config &config)
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{
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M68030(config, m_maincpu, 2*16670000);
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// I/O CPU
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M68020(config, m_maincpu, 16670000);
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m_maincpu->set_addrmap(AS_PROGRAM, &vme_hcpu30_card_device::hcpu30_mem);
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m_maincpu->set_addrmap(m68000_base_device::AS_CPU_SPACE, &vme_hcpu30_card_device::cpu_space_map);
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m_maincpu->disable_interrupt_mixer();
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// FIXME: functional test expects dtr->dcd, rts->cts connections on both ports and tx->rx connection on port B
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DUSCC68562(config, m_dusccterm, DUSCC_CLOCK);
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m_dusccterm->configure_channels(0, 0, 0, 0);
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m_dusccterm->out_txda_callback().set(RS232P1_TAG, FUNC(rs232_port_device::write_txd));
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m_dusccterm->out_dtra_callback().set(RS232P1_TAG, FUNC(rs232_port_device::write_dtr));
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m_dusccterm->out_rtsa_callback().set(RS232P1_TAG, FUNC(rs232_port_device::write_rts));
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// m_dusccterm->out_dtra_callback().set(m_dusccterm, FUNC(duscc68562_device::dcda_w));
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// m_dusccterm->out_rtsa_callback().set(m_dusccterm, FUNC(duscc68562_device::ctsa_w));
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m_dusccterm->out_txdb_callback().set(RS232P2_TAG, FUNC(rs232_port_device::write_txd));
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m_dusccterm->out_dtrb_callback().set(RS232P2_TAG, FUNC(rs232_port_device::write_dtr));
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m_dusccterm->out_rtsb_callback().set(RS232P2_TAG, FUNC(rs232_port_device::write_rts));
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// m_dusccterm->out_int_callback(),set(FUNC());
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// m_dusccterm->out_txdb_callback().set(m_dusccterm, FUNC(duscc68562_device::rxb_w));
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// m_dusccterm->out_dtrb_callback().set(m_dusccterm, FUNC(duscc68562_device::dcdb_w));
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// m_dusccterm->out_rtsb_callback().set(m_dusccterm, FUNC(duscc68562_device::ctsb_w));
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m_dusccterm->out_int_callback().set(FUNC(vme_hcpu30_card_device::dusirq_callback));
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rs232_port_device &rs232p1(RS232_PORT(config, RS232P1_TAG, default_rs232_devices, "terminal"));
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rs232p1.rxd_handler().set(m_dusccterm, FUNC(duscc68562_device::rxa_w));
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@ -144,21 +206,332 @@ void vme_hcpu30_card_device::device_add_mconfig(machine_config &config)
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rs232_port_device &rs232p2(RS232_PORT(config, RS232P2_TAG, default_rs232_devices, nullptr));
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rs232p2.rxd_handler().set(m_dusccterm, FUNC(duscc68562_device::rxb_w));
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rs232p2.cts_handler().set(m_dusccterm, FUNC(duscc68562_device::ctsb_w));
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NSCSI_BUS(config, "scsi");
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NSCSI_CONNECTOR(config, "scsi:0").option_set("hd", NSCSI_HARDDISK);
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NSCSI_CONNECTOR(config, "scsi:1").option_set("hd", NSCSI_HARDDISK);
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NSCSI_CONNECTOR(config, "scsi:2").option_set("hd", NSCSI_HARDDISK);
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NSCSI_CONNECTOR(config, "scsi:7").option_set("wd33c93", WD33C93A).machine_config(
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[this](device_t *device)
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{
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wd33c9x_base_device &wd33c93(downcast<wd33c9x_base_device &>(*device));
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wd33c93.set_clock(16670000/4); // default internal divisor is 2
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wd33c93.irq_cb().set(*this, FUNC(vme_hcpu30_card_device::scsiirq_callback)).invert();
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wd33c93.drq_cb().set(*this, FUNC(vme_hcpu30_card_device::scsidrq_callback));
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});
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// schematics connect INT to IPL1, not DRQ; could be outdated
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DP8473(config, m_fdc, 24_MHz_XTAL);
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m_fdc->drq_wr_callback().set_inputline(m_maincpu, M68K_IRQ_IPL1);
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m_fdc->intrq_wr_callback().set(*this, FUNC(vme_hcpu30_card_device::fdcirq_callback)).invert();
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// FIXME: drive select signals are swapped, handle this
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FLOPPY_CONNECTOR(config, "floppy:0", hcpu_floppies, "525qd", floppy_image_device::default_pc_floppy_formats);
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FLOPPY_CONNECTOR(config, "floppy:1", hcpu_floppies, "525qd", floppy_image_device::default_pc_floppy_formats);
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RTC62421(config, m_rtc, 32.768_kHz_XTAL);
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// FIXME: functional test expects A26-C24 A27-C28 A28-C26 A29-C30 A30-C32
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// i.e. ACKNOWL-CENTDS BUSY-CENTD3 PE-CENTD1 SLCT-CENTD5 ERROR-CENTD7
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CENTRONICS(config, m_centronics, centronics_devices, "printer");
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INPUT_BUFFER(config, m_cent_status_in);
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OUTPUT_LATCH(config, m_cent_data_out);
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// OS CPU
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M68030(config, m_oscpu, 2*16670000);
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m_oscpu->set_addrmap(AS_PROGRAM, &vme_hcpu30_card_device::hcpu30_os_mem);
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m_oscpu->set_addrmap(m68000_base_device::AS_CPU_SPACE, &vme_hcpu30_card_device::oscpu_space_map);
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m_oscpu->set_disable();
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}
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/* Boot vector handler, the PCB hardwires the first 8 bytes from 0xff800000 to 0x0 at reset */
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uint32_t vme_hcpu30_card_device::bootvect_r(offs_t offset)
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uint32_t vme_hcpu30_card_device::rtc_r(offs_t offset)
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{
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LOG("%s\n", FUNCNAME);
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return m_sysrom[offset];
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uint32_t data;
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if (m_rtc_hack)
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{
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data = (m_rtc_reg[offset << 1] << 28) | (m_rtc_reg[(offset << 1) + 1] << 12);
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data |= (m_rtc_reg[offset << 1] << 20) | (m_rtc_reg[(offset << 1) + 1] << 4);
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}
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else
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{
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data = (m_rtc->read(offset << 1) << 28) | (m_rtc->read((offset << 1) + 1) << 12);
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data |= (m_rtc->read(offset << 1) << 20) | (m_rtc->read((offset << 1) + 1) << 4);
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}
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if (offset == 0)
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{
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data &= 0xffffff;
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data |= ioport("SA1")->read() << 24;
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}
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if (offset == 7)
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{
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data &= 0xff00ffff;
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data |= (m_cent_status_in->read() ^ 0xff) << 16;
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}
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LOG("%s(%02x)==%08x%s\n", FUNCNAME, offset, data, m_rtc_hack ? " hacked" : "");
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return data;
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}
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void vme_hcpu30_card_device::bootvect_w(offs_t offset, uint32_t data, uint32_t mem_mask)
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void vme_hcpu30_card_device::rtc_w(offs_t offset, uint32_t data, uint32_t mem_mask)
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{
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LOG("%s\n", FUNCNAME);
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m_sysram[offset % std::size(m_sysram)] &= ~mem_mask;
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m_sysram[offset % std::size(m_sysram)] |= (data & mem_mask);
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m_sysrom = &m_sysram[0]; // redirect all upcoming accesses to masking RAM until reset.
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LOG("%s(%02x,%08x)<-%08x\n", FUNCNAME, offset, mem_mask, data);
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if (mem_mask == 0xffff0000)
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{
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m_rtc->write(offset << 1, (data >> 4) & 15);
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m_rtc_reg[offset << 1] = (data >> 4) & 15;
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if (offset == 7)
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{
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m_cent_data_out->write(data >> 8);
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}
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}
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else
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{
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m_rtc->write((offset << 1) + 1, (data >> 20) & 15);
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m_rtc_reg[(offset << 1) + 1] = (data >> 20) & 15;
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}
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if (offset < 6 || (offset == 6 && mem_mask == 0xffff0000)) m_rtc_hack = true; else m_rtc_hack = false;
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}
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uint32_t vme_hcpu30_card_device::dma_r(offs_t offset)
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{
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if (m_fdcdrq_hack++ == 1023)
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{
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m_fdc->tc_w(1);
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m_fdcdrq_hack = 0;
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}
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else
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{
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m_fdc->tc_w(0);
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}
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return m_fdc->dma_r() << 24;
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}
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void vme_hcpu30_card_device::dma_w(offs_t offset, uint32_t data, uint32_t mem_mask)
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{
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if (m_fdcdrq_hack++ == 1023)
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{
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m_fdc->tc_w(1);
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m_fdcdrq_hack = 0;
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}
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else
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{
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m_fdc->tc_w(0);
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}
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m_fdc->dma_w(data);
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}
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uint32_t vme_hcpu30_card_device::trap_r(offs_t offset, uint32_t mem_mask)
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{
|
||||
if (!machine().side_effects_disabled()) set_bus_error((offset << 2), true, mem_mask);
|
||||
|
||||
return 0xffffffff;
|
||||
}
|
||||
|
||||
void vme_hcpu30_card_device::trap_w(offs_t offset, uint32_t data, uint32_t mem_mask)
|
||||
{
|
||||
LOG("%s(%08x,%08X)\n", FUNCNAME, offset << 2, data);
|
||||
if (!machine().side_effects_disabled()) set_bus_error((offset << 2), false, mem_mask);
|
||||
}
|
||||
|
||||
// AH?
|
||||
WRITE_LINE_MEMBER(vme_hcpu30_card_device::dusirq_callback)
|
||||
{
|
||||
LOGINT("%s(%02x)\n", FUNCNAME, state);
|
||||
m_irq_state &= ~(1 << (8+4));
|
||||
m_irq_state |= (state << (8+4));
|
||||
}
|
||||
|
||||
// AL?
|
||||
WRITE_LINE_MEMBER(vme_hcpu30_card_device::scsiirq_callback)
|
||||
{
|
||||
LOGINT("%s(%02x)\n", FUNCNAME, state);
|
||||
m_irq_state &= ~(1 << 8);
|
||||
m_irq_state |= (state << 8);
|
||||
}
|
||||
|
||||
// AL?
|
||||
WRITE_LINE_MEMBER(vme_hcpu30_card_device::scsidrq_callback)
|
||||
{
|
||||
LOGINT("%s(%02x)\n", FUNCNAME, state);
|
||||
m_irq_state &= ~(1 << 7);
|
||||
m_irq_state |= (state << 7);
|
||||
}
|
||||
|
||||
// AL?
|
||||
WRITE_LINE_MEMBER(vme_hcpu30_card_device::fdcirq_callback)
|
||||
{
|
||||
LOGINT("%s(%02x)\n", FUNCNAME, state);
|
||||
m_irq_state &= ~(1 << (8+2));
|
||||
m_irq_state |= (state << (8+2));
|
||||
}
|
||||
|
||||
// AL?
|
||||
WRITE_LINE_MEMBER(vme_hcpu30_card_device::fdcdrq_callback)
|
||||
{
|
||||
LOGINT("%s(%02x)\n", FUNCNAME, state);
|
||||
#if 0
|
||||
if (state)
|
||||
{
|
||||
if (m_fdcdrq_hack++ == 1022)
|
||||
{
|
||||
m_fdc->tc_w(1);
|
||||
m_fdcdrq_hack = 0;
|
||||
}
|
||||
else
|
||||
{
|
||||
m_fdc->tc_w(0);
|
||||
}
|
||||
}
|
||||
#endif
|
||||
}
|
||||
|
||||
// FF0003F2: move.w #$1d40, D7
|
||||
// i.e. DUSIRQ, ABORT, FDCIRQ, SCSIIRQ, IRQ30
|
||||
// FF00074C: eori.w #$2540, D0
|
||||
// i.e. bits 6, 8, 10, 13 are active low
|
||||
// D70 translates to DL16-23
|
||||
// D69 translates to DI0-7, D67 to DL24-31
|
||||
//
|
||||
// == f101.w ==
|
||||
// 0 - SYSFAIL*
|
||||
// 1 - ACFAIL*
|
||||
// 2 - TERMRES*
|
||||
// 3 - nc
|
||||
// 4 - FPSENSE*
|
||||
// 5 - RST*
|
||||
// 6 - IRQ30* D119 PLM output (CLRINT* and VECT20 inputs)
|
||||
// 7 - SDMRQ*
|
||||
// == f100.w ==
|
||||
// 8 - SCSIIRQ
|
||||
// 9 - CENTIRQ*
|
||||
// 10 - FDCIRQ*
|
||||
// 11 - ABORT*
|
||||
// 12 - DUSIRQ*
|
||||
// 13 - LANIRQ
|
||||
// 14 - IPEND* from 030
|
||||
// 15 - LDMARQ*
|
||||
uint32_t vme_hcpu30_card_device::irq_state_r(offs_t offset)
|
||||
{
|
||||
return m_irq_state << 16;
|
||||
}
|
||||
|
||||
void vme_hcpu30_card_device::update_030_irq(int irq, line_state state)
|
||||
{
|
||||
if (irq != 0)
|
||||
{
|
||||
if (state == ASSERT_LINE)
|
||||
{
|
||||
LOG("triggering 68030 irq %d\n", irq);
|
||||
m_oscpu->set_input_line(M68K_IRQ_NONE + irq, ASSERT_LINE);
|
||||
}
|
||||
else
|
||||
{
|
||||
LOG("clearing 68030 irq %d\n", irq);
|
||||
m_oscpu->set_input_line(M68K_IRQ_NONE + irq, CLEAR_LINE);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
// D60 translates from DI0-7 (DL24-31)
|
||||
// D61 translates from DL16-21
|
||||
// 0 - INTL0
|
||||
// 1 - INTL1
|
||||
// 2 - INTL2
|
||||
// 3 - VME16
|
||||
// 4 - CLRINT* D119 PLM input
|
||||
// 5 - LPBK* (loopback?)
|
||||
// 6-7 - nc
|
||||
// 8 - SCSIRES*
|
||||
// 9 - ROR
|
||||
// 10 - CENTDS (strobe)
|
||||
// 11 - RESET*
|
||||
// 12 - HALT*
|
||||
// 13 - SRLOCL*
|
||||
// 14 - PWRDOWN
|
||||
// 15 - INTENA* "enable input" pin of LS148 priority encoder
|
||||
void vme_hcpu30_card_device::irq_mask_w(offs_t offset, uint32_t data, uint32_t mem_mask)
|
||||
{
|
||||
uint16_t diff;
|
||||
|
||||
data >>= 16;
|
||||
diff = data ^ m_irq_mask;
|
||||
|
||||
LOG("%s(%04x,%04x)\n", FUNCNAME, data, diff);
|
||||
|
||||
if (BIT(diff, 15))
|
||||
{
|
||||
update_030_irq((BIT(data, 15) ? m_irq_mask : data) & 7, BIT(data, 15) ? CLEAR_LINE : ASSERT_LINE);
|
||||
}
|
||||
// CLRINT* affects IRQ30*
|
||||
if (BIT(diff, 4))
|
||||
{
|
||||
m_irq_state &= ~(1 << 6);
|
||||
m_irq_state |= (BIT(data, 4) << 6);
|
||||
}
|
||||
if (BIT(diff, 8))
|
||||
{
|
||||
m_scsi->reset_w(BIT(data, 8));
|
||||
m_irq_state &= ~(1 << 5);
|
||||
m_irq_state |= (!BIT(data, 8) << 5);
|
||||
}
|
||||
if (BIT(diff, 10))
|
||||
{
|
||||
m_centronics->write_strobe(BIT(data, 10));
|
||||
}
|
||||
if (BIT(diff, 11))
|
||||
{
|
||||
if (BIT(m_irq_mask, 11))
|
||||
{
|
||||
m_oscpu->set_input_line(INPUT_LINE_RESET, ASSERT_LINE);
|
||||
LOG("68030 halted by reset\n");
|
||||
}
|
||||
else
|
||||
{
|
||||
if (m_oscpu->suspended(SUSPEND_REASON_RESET))
|
||||
{
|
||||
m_oscpu->set_input_line(INPUT_LINE_RESET, CLEAR_LINE);
|
||||
LOG("68030 started after reset\n");
|
||||
}
|
||||
}
|
||||
}
|
||||
if (BIT(diff, 12))
|
||||
{
|
||||
if (BIT(m_irq_mask, 12))
|
||||
{
|
||||
m_oscpu->suspend(SUSPEND_REASON_DISABLE, 1);
|
||||
LOG("68030 halted\n");
|
||||
}
|
||||
else
|
||||
{
|
||||
if (m_oscpu->suspended(SUSPEND_REASON_DISABLE))
|
||||
{
|
||||
m_oscpu->resume(SUSPEND_REASON_DISABLE);
|
||||
LOG("68030 started\n");
|
||||
}
|
||||
}
|
||||
}
|
||||
m_irq_mask = data;
|
||||
}
|
||||
|
||||
void vme_hcpu30_card_device::set_bus_error(uint32_t address, bool rw, uint32_t mem_mask)
|
||||
{
|
||||
if (m_bus_error)
|
||||
{
|
||||
return;
|
||||
}
|
||||
LOG("bus error at %08x & %08x (%s)\n", address, mem_mask, rw ? "read" : "write");
|
||||
if (!ACCESSING_BITS_16_31)
|
||||
{
|
||||
address++;
|
||||
}
|
||||
m_bus_error = true;
|
||||
m_oscpu->set_buserror_details(address, rw, m_oscpu->get_fc());
|
||||
m_oscpu->set_input_line(M68K_LINE_BUSERROR, ASSERT_LINE);
|
||||
m_bus_error_timer->adjust(m_oscpu->cycles_to_attotime(16)); // let rmw cycles complete
|
||||
}
|
||||
|
||||
vme_hcpu30_card_device::vme_hcpu30_card_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, uint32_t clock)
|
||||
@ -166,11 +539,25 @@ vme_hcpu30_card_device::vme_hcpu30_card_device(const machine_config &mconfig, de
|
||||
, device_vme_card_interface(mconfig, *this)
|
||||
, m_maincpu(*this, "maincpu")
|
||||
, m_dusccterm(*this, "duscc")
|
||||
, m_scsi(*this, "scsi:7:wd33c93")
|
||||
, m_fdc(*this, "floppy")
|
||||
, m_floppy0(*this, "floppy:0")
|
||||
, m_floppy1(*this, "floppy:1")
|
||||
, m_rtc(*this, "rtc")
|
||||
, m_centronics(*this, "centronics")
|
||||
, m_cent_data_out(*this, "cent_data_out")
|
||||
, m_cent_status_in(*this, "cent_status_in")
|
||||
, m_oscpu(*this, "oscpu")
|
||||
, m_mailbox(*this, "mailbox")
|
||||
, m_p_ram(*this, "dram")
|
||||
, m_sysrom(*this, "user1")
|
||||
{
|
||||
LOG("%s %s\n", tag, FUNCNAME);
|
||||
m_slot = 1;
|
||||
}
|
||||
|
||||
//
|
||||
|
||||
vme_hcpu30_card_device::vme_hcpu30_card_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock)
|
||||
: vme_hcpu30_card_device(mconfig, VME_HCPU30, tag, owner, clock)
|
||||
{
|
||||
@ -180,14 +567,38 @@ void vme_hcpu30_card_device::device_start()
|
||||
{
|
||||
LOG("%s %s\n", tag(), FUNCNAME);
|
||||
|
||||
save_pointer (NAME (m_sysrom), sizeof(m_sysrom));
|
||||
save_pointer (NAME (m_sysram), sizeof(m_sysram));
|
||||
|
||||
/* Setup pointer to bootvector in ROM for bootvector handler bootvect_r */
|
||||
m_sysrom = (uint32_t*)(memregion ("user1")->base());
|
||||
m_bus_error_timer = timer_alloc(0);
|
||||
}
|
||||
|
||||
void vme_hcpu30_card_device::device_reset()
|
||||
{
|
||||
address_space &program = m_maincpu->space(AS_PROGRAM);
|
||||
|
||||
LOG("%s %s\n", tag(), FUNCNAME);
|
||||
m_irq_state = (1 << 10) | (1 << 6); // fdcirq | irq30*
|
||||
m_irq_mask = 0;
|
||||
m_rtc_hack = false;
|
||||
m_fdcdrq_hack = 0;
|
||||
m_fdc->ready_w(false);
|
||||
|
||||
program.install_rom(0x00000000, 0x00000007, m_sysrom); // do it here for F3
|
||||
m_rom_shadow_tap = program.install_read_tap(0xff000000, 0xff007fff, "rom_shadow_r", [this](offs_t offset, u32 &data, u32 mem_mask)
|
||||
{
|
||||
if (!machine().side_effects_disabled())
|
||||
{
|
||||
// delete this tap
|
||||
m_rom_shadow_tap->remove();
|
||||
|
||||
// reinstall ram over the rom shadow
|
||||
m_maincpu->space(AS_PROGRAM).install_ram(0x00000000, 0x00000007, m_p_ram);
|
||||
}
|
||||
|
||||
// return the original data
|
||||
return data;
|
||||
});
|
||||
}
|
||||
|
||||
void vme_hcpu30_card_device::device_timer(emu_timer &timer, device_timer_id id, int param, void *ptr)
|
||||
{
|
||||
m_bus_error = false;
|
||||
}
|
||||
|
||||
@ -5,12 +5,17 @@
|
||||
|
||||
#pragma once
|
||||
|
||||
#include "bus/vme/vme.h"
|
||||
#include "bus/centronics/ctronics.h"
|
||||
#include "bus/nscsi/hd.h"
|
||||
#include "bus/rs232/rs232.h"
|
||||
#include "bus/vme/vme.h"
|
||||
#include "cpu/m68000/m68000.h"
|
||||
#include "machine/68230pit.h"
|
||||
#include "imagedev/floppy.h"
|
||||
#include "machine/clock.h"
|
||||
#include "machine/msm6242.h"
|
||||
#include "machine/scnxx562.h"
|
||||
#include "machine/terminal.h"
|
||||
#include "machine/upd765.h"
|
||||
#include "machine/wd33c9x.h"
|
||||
|
||||
DECLARE_DEVICE_TYPE(VME_HCPU30, vme_hcpu30_card_device)
|
||||
@ -30,19 +35,56 @@ protected:
|
||||
virtual void device_add_mconfig(machine_config &config) override;
|
||||
virtual const tiny_rom_entry *device_rom_region() const override;
|
||||
virtual ioport_constructor device_input_ports() const override;
|
||||
virtual void device_timer(emu_timer &timer, device_timer_id id, int param, void *ptr) override;
|
||||
|
||||
private:
|
||||
required_device<cpu_device> m_maincpu;
|
||||
required_device<m68000_base_device> m_maincpu;
|
||||
required_device<duscc68562_device> m_dusccterm;
|
||||
required_device<wd33c93a_device> m_scsi;
|
||||
required_device<upd765_family_device> m_fdc;
|
||||
required_device<floppy_connector> m_floppy0;
|
||||
required_device<floppy_connector> m_floppy1;
|
||||
required_device<rtc62421_device> m_rtc;
|
||||
required_device<centronics_device> m_centronics;
|
||||
required_device<output_latch_device> m_cent_data_out;
|
||||
required_device<input_buffer_device> m_cent_status_in;
|
||||
required_device<m68000_base_device> m_oscpu;
|
||||
required_shared_ptr<uint32_t> m_mailbox;
|
||||
required_shared_ptr<uint32_t> m_p_ram;
|
||||
required_region_ptr<uint32_t> m_sysrom;
|
||||
|
||||
DECLARE_WRITE_LINE_MEMBER(dusirq_callback);
|
||||
DECLARE_WRITE_LINE_MEMBER(scsiirq_callback);
|
||||
DECLARE_WRITE_LINE_MEMBER(scsidrq_callback);
|
||||
DECLARE_WRITE_LINE_MEMBER(fdcirq_callback);
|
||||
DECLARE_WRITE_LINE_MEMBER(fdcdrq_callback);
|
||||
|
||||
// Pointer to System ROMs needed by bootvect_r and masking RAM buffer for post reset accesses
|
||||
uint32_t *m_sysrom;
|
||||
uint32_t m_sysram[2];
|
||||
memory_passthrough_handler *m_rom_shadow_tap;
|
||||
uint16_t m_irq_state;
|
||||
uint16_t m_irq_mask;
|
||||
uint8_t m_rtc_reg[16];
|
||||
bool m_rtc_hack;
|
||||
int m_fdcdrq_hack;
|
||||
bool m_bus_error;
|
||||
emu_timer *m_bus_error_timer;
|
||||
|
||||
uint32_t bootvect_r(offs_t offset);
|
||||
void bootvect_w(offs_t offset, uint32_t data, uint32_t mem_mask = ~0);
|
||||
uint32_t irq_state_r(offs_t offset);
|
||||
void irq_mask_w(offs_t offset, uint32_t data, uint32_t mem_mask = ~0);
|
||||
uint32_t rtc_r(offs_t offset);
|
||||
void rtc_w(offs_t offset, uint32_t data, uint32_t mem_mask = ~0);
|
||||
uint32_t dma_r(offs_t offset);
|
||||
void dma_w(offs_t offset, uint32_t data, uint32_t mem_mask = ~0);
|
||||
uint32_t trap_r(offs_t offset, uint32_t mem_mask);
|
||||
void trap_w(offs_t offset, uint32_t data, uint32_t mem_mask = ~0);
|
||||
|
||||
void set_bus_error(uint32_t address, bool write, uint32_t mem_mask);
|
||||
void update_030_irq(int irq, line_state state);
|
||||
|
||||
void hcpu30_mem(address_map &map);
|
||||
void hcpu30_os_mem(address_map &map);
|
||||
void cpu_space_map(address_map &map);
|
||||
void oscpu_space_map(address_map &map);
|
||||
};
|
||||
|
||||
#endif // MAME_BUS_VME_VME_HCPU30_H
|
||||
|
||||
Loading…
Reference in New Issue
Block a user