Pointer-ified the M377xx.
This commit is contained in:
R. Belmont
parent
2b5f8f5f0e
commit
987696750a
File diff suppressed because it is too large
Load Diff
@ -85,12 +85,6 @@ enum
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M37710_SER0_XMIT, M37710_SER1_REC, M37710_SER1_XMIT
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};
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/* ======================================================================== */
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/* ============================== PROTOTYPES ============================== */
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/* ======================================================================== */
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extern int m37710_ICount; /* cycle count */
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/* ======================================================================== */
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/* ================================= MAME ================================= */
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/* ======================================================================== */
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@ -106,13 +100,13 @@ void m37710_state_load(void *file);
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#undef M37710_CALL_DEBUGGER
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#define M37710_CALL_DEBUGGER(x) debugger_instruction_hook(m37710i_cpu.device, x)
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#define m37710_read_8(addr) memory_read_byte_16le(m37710i_cpu.program, addr)
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#define m37710_write_8(addr,data) memory_write_byte_16le(m37710i_cpu.program, addr,data)
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#define m37710_read_8_immediate(A) memory_read_byte_16le(m37710i_cpu.program, A)
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#define m37710_read_16(addr) memory_read_word_16le(m37710i_cpu.program, addr)
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#define m37710_write_16(addr,data) memory_write_word_16le(m37710i_cpu.program, addr,data)
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#define m37710_jumping(A) change_pc(A)
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#define M37710_CALL_DEBUGGER(x) debugger_instruction_hook(m37710i_cpu->device, x)
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#define m37710_read_8(addr) memory_read_byte_16le(m37710i_cpu->program, addr)
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#define m37710_write_8(addr,data) memory_write_byte_16le(m37710i_cpu->program, addr,data)
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#define m37710_read_8_immediate(A) memory_read_byte_16le(m37710i_cpu->program, A)
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#define m37710_read_16(addr) memory_read_word_16le(m37710i_cpu->program, addr)
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#define m37710_write_16(addr,data) memory_write_word_16le(m37710i_cpu->program, addr,data)
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#define m37710_jumping(A) change_pc(A)
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#define m37710_branching(A)
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@ -96,18 +96,21 @@ struct _m37710i_cpu_struct
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uint im4; /* Immediate load target */
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uint irq_delay; /* delay 1 instruction before checking irq */
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uint irq_level; /* irq level */
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int ICount; /* cycle count */
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uint source; /* temp register */
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uint destination; /* temp register */
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cpu_irq_callback int_ack;
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const device_config *device;
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const address_space *program;
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const address_space *io;
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uint stopped; /* Sets how the CPU is stopped */
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void (*const *opcodes)(void); /* opcodes with no prefix */
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void (*const *opcodes42)(void); /* opcodes with 0x42 prefix */
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void (*const *opcodes89)(void); /* opcodes with 0x89 prefix */
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uint (*get_reg)(int regnum);
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void (*set_reg)(int regnum, uint val);
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void (*set_line)(int line, int state);
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int (*execute)(int cycles);
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void (*const *opcodes)(m37710i_cpu_struct *m37710i_cpu); /* opcodes with no prefix */
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void (*const *opcodes42)(m37710i_cpu_struct *m37710i_cpu); /* opcodes with 0x42 prefix */
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void (*const *opcodes89)(m37710i_cpu_struct *m37710i_cpu); /* opcodes with 0x89 prefix */
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uint (*get_reg)(m37710i_cpu_struct *m37710i_cpu, int regnum);
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void (*set_reg)(m37710i_cpu_struct *m37710i_cpu, int regnum, uint val);
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void (*set_line)(m37710i_cpu_struct *m37710i_cpu, int line, int state);
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int (*execute)(m37710i_cpu_struct *m37710i_cpu, int cycles);
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// on-board peripheral stuff
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UINT8 m37710_regs[128];
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@ -116,62 +119,54 @@ struct _m37710i_cpu_struct
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};
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extern m37710i_cpu_struct m37710i_cpu;
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extern int m37710_ICount;
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extern uint m37710i_source;
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extern uint m37710i_destination;
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extern uint m37710i_adc_tbl[];
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extern uint m37710i_sbc_tbl[];
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extern void (*const *const m37710i_opcodes[])(void);
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extern void (*const *const m37710i_opcodes2[])(void);
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extern void (*const *const m37710i_opcodes3[])(void);
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extern uint (*const m37710i_get_reg[])(int regnum);
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extern void (*const m37710i_set_reg[])(int regnum, uint val);
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extern void (*const m37710i_set_line[])(int line, int state);
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extern int (*const m37710i_execute[])(int cycles);
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extern void (*const *const m37710i_opcodes[])(m37710i_cpu_struct *m37710i_cpu);
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extern void (*const *const m37710i_opcodes2[])(m37710i_cpu_struct *m37710i_cpu);
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extern void (*const *const m37710i_opcodes3[])(m37710i_cpu_struct *m37710i_cpu);
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extern uint (*const m37710i_get_reg[])(m37710i_cpu_struct *m37710i_cpu,int regnum);
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extern void (*const m37710i_set_reg[])(m37710i_cpu_struct *m37710i_cpu,int regnum, uint val);
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extern void (*const m37710i_set_line[])(m37710i_cpu_struct *m37710i_cpu,int line, int state);
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extern int (*const m37710i_execute[])(m37710i_cpu_struct *m37710i_cpu, int cycles);
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#define REG_A m37710i_cpu.a /* Accumulator */
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#define REG_B m37710i_cpu.b /* Accumulator hi byte */
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#define REG_BA m37710i_cpu.ba /* Secondary Accumulator */
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#define REG_BB m37710i_cpu.bb /* Secondary Accumulator hi byte */
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#define REG_X m37710i_cpu.x /* Index X Register */
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#define REG_Y m37710i_cpu.y /* Index Y Register */
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#define REG_S m37710i_cpu.s /* Stack Pointer */
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#define REG_PC m37710i_cpu.pc /* Program Counter */
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#define REG_PPC m37710i_cpu.ppc /* Previous Program Counter */
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#define REG_PB m37710i_cpu.pb /* Program Bank */
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#define REG_DB m37710i_cpu.db /* Data Bank */
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#define REG_D m37710i_cpu.d /* Direct Register */
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#define FLAG_M m37710i_cpu.flag_m /* Memory/Accumulator Select Flag */
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#define FLAG_X m37710i_cpu.flag_x /* Index Select Flag */
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#define FLAG_N m37710i_cpu.flag_n /* Negative Flag */
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#define FLAG_V m37710i_cpu.flag_v /* Overflow Flag */
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#define FLAG_D m37710i_cpu.flag_d /* Decimal Mode Flag */
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#define FLAG_I m37710i_cpu.flag_i /* Interrupt Mask Flag */
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#define FLAG_Z m37710i_cpu.flag_z /* Zero Flag (inverted) */
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#define FLAG_C m37710i_cpu.flag_c /* Carry Flag */
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#define LINE_IRQ m37710i_cpu.line_irq /* Status of the IRQ line */
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#define REG_IR m37710i_cpu.ir /* Instruction Register */
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#define REG_IM m37710i_cpu.im /* Immediate load value */
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#define REG_IM2 m37710i_cpu.im2 /* Immediate load target */
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#define REG_IM3 m37710i_cpu.im3 /* Immediate load target */
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#define REG_IM4 m37710i_cpu.im4 /* Immediate load target */
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#define INT_ACK m37710i_cpu.int_ack /* Interrupt Acknowledge function pointer */
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#define CLOCKS m37710_ICount /* Clock cycles remaining */
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#define IRQ_DELAY m37710i_cpu.irq_delay /* Delay 1 instruction before checking IRQ */
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#define CPU_STOPPED m37710i_cpu.stopped /* Stopped status of the CPU */
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#define REG_A m37710i_cpu->a /* Accumulator */
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#define REG_B m37710i_cpu->b /* Accumulator hi byte */
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#define REG_BA m37710i_cpu->ba /* Secondary Accumulator */
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#define REG_BB m37710i_cpu->bb /* Secondary Accumulator hi byte */
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#define REG_X m37710i_cpu->x /* Index X Register */
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#define REG_Y m37710i_cpu->y /* Index Y Register */
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#define REG_S m37710i_cpu->s /* Stack Pointer */
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#define REG_PC m37710i_cpu->pc /* Program Counter */
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#define REG_PPC m37710i_cpu->ppc /* Previous Program Counter */
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#define REG_PB m37710i_cpu->pb /* Program Bank */
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#define REG_DB m37710i_cpu->db /* Data Bank */
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#define REG_D m37710i_cpu->d /* Direct Register */
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#define FLAG_M m37710i_cpu->flag_m /* Memory/Accumulator Select Flag */
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#define FLAG_X m37710i_cpu->flag_x /* Index Select Flag */
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#define FLAG_N m37710i_cpu->flag_n /* Negative Flag */
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#define FLAG_V m37710i_cpu->flag_v /* Overflow Flag */
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#define FLAG_D m37710i_cpu->flag_d /* Decimal Mode Flag */
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#define FLAG_I m37710i_cpu->flag_i /* Interrupt Mask Flag */
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#define FLAG_Z m37710i_cpu->flag_z /* Zero Flag (inverted) */
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#define FLAG_C m37710i_cpu->flag_c /* Carry Flag */
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#define LINE_IRQ m37710i_cpu->line_irq /* Status of the IRQ line */
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#define REG_IR m37710i_cpu->ir /* Instruction Register */
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#define REG_IM m37710i_cpu->im /* Immediate load value */
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#define REG_IM2 m37710i_cpu->im2 /* Immediate load target */
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#define REG_IM3 m37710i_cpu->im3 /* Immediate load target */
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#define REG_IM4 m37710i_cpu->im4 /* Immediate load target */
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#define INT_ACK m37710i_cpu->int_ack /* Interrupt Acknowledge function pointer */
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#define CLOCKS m37710i_cpu->ICount /* Clock cycles remaining */
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#define IRQ_DELAY m37710i_cpu->irq_delay /* Delay 1 instruction before checking IRQ */
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#define CPU_STOPPED m37710i_cpu->stopped /* Stopped status of the CPU */
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#define FTABLE_OPCODES m37710i_cpu.opcodes
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#define FTABLE_OPCODES2 m37710i_cpu.opcodes42
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#define FTABLE_OPCODES3 m37710i_cpu.opcodes89
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#define FTABLE_GET_REG m37710i_cpu.get_reg
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#define FTABLE_SET_REG m37710i_cpu.set_reg
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#define FTABLE_SET_LINE m37710i_cpu.set_line
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#define FTABLE_EXECUTE m37710i_cpu.execute
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#define FTABLE_GET_REG m37710i_cpu->get_reg
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#define FTABLE_SET_REG m37710i_cpu->set_reg
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#define FTABLE_SET_LINE m37710i_cpu->set_line
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#define SRC m37710i_source /* Source Operand */
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#define DST m37710i_destination /* Destination Operand */
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#define SRC m37710i_cpu->source /* Source Operand */
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#define DST m37710i_cpu->destination /* Destination Operand */
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#define STOP_LEVEL_WAI 1
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#define STOP_LEVEL_STOP 2
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@ -181,15 +176,15 @@ extern int (*const m37710i_execute[])(int cycles);
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#define EXECUTION_MODE_M1X0 2
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#define EXECUTION_MODE_M1X1 3
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INLINE void m37710i_set_execution_mode(uint mode)
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INLINE void m37710i_set_execution_mode(m37710i_cpu_struct *m37710i_cpu, uint mode)
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{
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FTABLE_OPCODES = m37710i_opcodes[mode];
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FTABLE_OPCODES2 = m37710i_opcodes2[mode];
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FTABLE_OPCODES3 = m37710i_opcodes3[mode];
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m37710i_cpu->opcodes = m37710i_opcodes[mode];
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m37710i_cpu->opcodes42 = m37710i_opcodes2[mode];
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m37710i_cpu->opcodes89 = m37710i_opcodes3[mode];
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FTABLE_GET_REG = m37710i_get_reg[mode];
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FTABLE_SET_REG = m37710i_set_reg[mode];
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FTABLE_SET_LINE = m37710i_set_line[mode];
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FTABLE_EXECUTE = m37710i_execute[mode];
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m37710i_cpu->execute = m37710i_execute[mode];
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}
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/* ======================================================================== */
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@ -317,7 +312,7 @@ INLINE void m37710i_set_execution_mode(uint mode)
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#define CFLAG_AS_1() ((FLAG_C>>8)&1)
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/* update IRQ state (internal use only) */
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void m37710i_update_irqs(void);
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void m37710i_update_irqs(m37710i_cpu_struct *m37710i_cpu);
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/* ======================================================================== */
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/* ================================== CPU ================================= */
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File diff suppressed because it is too large
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