-netlist: Added 82S126 4kbit (512x8) TTL bipolar PROM. [Ryan Holtz]

This commit is contained in:
therealmogminer@gmail.com 2016-12-23 20:01:32 +01:00
parent 0768d0b4fd
commit 9c4c4d0a5b
13 changed files with 386 additions and 39 deletions

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@ -149,6 +149,8 @@ project "netlist"
MAME_DIR .. "src/lib/netlist/devices/nld_74ls629.h",
MAME_DIR .. "src/lib/netlist/devices/nld_82S16.cpp",
MAME_DIR .. "src/lib/netlist/devices/nld_82S16.h",
MAME_DIR .. "src/lib/netlist/devices/nld_82S115.cpp",
MAME_DIR .. "src/lib/netlist/devices/nld_82S115.h",
MAME_DIR .. "src/lib/netlist/devices/nld_82S126.cpp",
MAME_DIR .. "src/lib/netlist/devices/nld_82S126.h",
MAME_DIR .. "src/lib/netlist/devices/nld_9310.cpp",

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@ -95,6 +95,7 @@ NLOBJS := \
$(NLOBJ)/devices/nld_74365.o \
$(NLOBJ)/devices/nld_74ls629.o \
$(NLOBJ)/devices/nld_82S16.o \
$(NLOBJ)/devices/nld_82S115.o \
$(NLOBJ)/devices/nld_82S126.o \
$(NLOBJ)/devices/nld_9310.o \
$(NLOBJ)/devices/nld_9312.o \

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@ -136,7 +136,8 @@ static void initialize_factory(factory_list_t &factory)
//ENTRY(74279, TTL_74279, "-") // only dip available
ENTRYX(SN74LS629, SN74LS629, "CAP")
ENTRYX(82S16, TTL_82S16, "-")
ENTRYX(82S126, TTL_82S126, "-")
ENTRYX(82S115, PROM_82S115, "-")
ENTRYX(82S126, PROM_82S126, "-")
ENTRYX(9310, TTL_9310, "-")
ENTRYX(9312, TTL_9312, "-")
ENTRYX(9316, TTL_9316, "+CLK,ENP,ENT,CLRQ,LOADQ,A,B,C,D")

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@ -42,6 +42,7 @@
#include "nld_74365.h"
#include "nld_74ls629.h"
#include "nld_82S16.h"
#include "nld_82S115.h"
#include "nld_82S126.h"
#include "nld_9310.h"
#include "nld_9312.h"

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@ -64,18 +64,77 @@ namespace netlist
};
NETLIB_OBJECT_DERIVED(74107, 74107A)
NETLIB_OBJECT(74107)
{
public:
NETLIB_CONSTRUCTOR_DERIVED(74107, 74107A) { }
NETLIB_CONSTRUCTOR(74107)
, m_CLK(*this, "CLK")
, m_J(*this, "J")
, m_K(*this, "K")
, m_CLRQ(*this, "CLRQ")
, m_last_CLK(*this, "m_last_CLK", 0)
, m_q(*this, "m_q", 0)
, m_latched_JK(*this, "m_latched_JK", 0)
, m_Q(*this, "Q")
, m_QQ(*this, "QQ")
{
}
NETLIB_RESETI();
NETLIB_UPDATEI();
public:
logic_input_t m_CLK;
logic_input_t m_J;
logic_input_t m_K;
logic_input_t m_CLRQ;
state_var<unsigned> m_last_CLK;
state_var<unsigned> m_q;
state_var<unsigned> m_latched_JK;
logic_output_t m_Q;
logic_output_t m_QQ;
};
NETLIB_RESET(74107)
{
m_last_CLK = 0;
m_latched_JK = 0;
}
NETLIB_OBJECT(74107_dip)
{
NETLIB_CONSTRUCTOR(74107_dip)
, m_1(*this, "1")
, m_2(*this, "2")
{
register_subalias("1", m_1.m_CLK);
register_subalias("2", m_1.m_CLRQ);
register_subalias("3", m_1.m_K);
//register_subalias("4", ); ==> VCC
register_subalias("5", m_2.m_CLK);
register_subalias("6", m_2.m_CLRQ);
register_subalias("7", m_2.m_J);
register_subalias("8", m_2.m_QQ);
register_subalias("9", m_2.m_Q);
register_subalias("10", m_2.m_K);
//register_subalias("11", ); ==> VCC
register_subalias("12", m_2.m_Q);
register_subalias("13", m_1.m_QQ);
register_subalias("14", m_1.m_J);
}
private:
NETLIB_SUB(74107) m_1;
NETLIB_SUB(74107) m_2;
};
NETLIB_OBJECT(74107A_dip)
{
NETLIB_CONSTRUCTOR(74107A_dip)
, m_1(*this, "1")
, m_2(*this, "2")
{
register_subalias("1", m_1.m_J);
register_subalias("2", m_1.m_sub.m_QQ);
@ -102,8 +161,8 @@ namespace netlist
//NETLIB_UPDATEI();
private:
NETLIB_SUB(74107) m_1;
NETLIB_SUB(74107) m_2;
NETLIB_SUB(74107A) m_1;
NETLIB_SUB(74107A) m_2;
};
NETLIB_RESET(74107Asub)
@ -173,9 +232,44 @@ namespace netlist
m_sub.m_clk.activate_hl();
}
NETLIB_UPDATE(74107)
{
if (m_CLRQ())
{
if (m_CLK() && !m_last_CLK)
{
m_latched_JK = (m_J() << 1) | m_K();
}
else if (!m_CLK() && m_last_CLK)
{
switch (m_latched_JK)
{
case 1: // (!m_J) & m_K))
m_q = 0;
break;
case 2: // (m_J) & !m_K))
m_q = 1;
break;
case 3: // (m_J) & m_K))
m_q ^= 1;
break;
default:
case 0:
break;
}
}
}
m_last_CLK = m_CLK();
m_Q.push(m_q, NLTIME_FROM_NS(20)); // FIXME: timing
m_QQ.push(m_q ^ 1, NLTIME_FROM_NS(20)); // FIXME: timing
}
NETLIB_DEVICE_IMPL(74107)
NETLIB_DEVICE_IMPL(74107A)
NETLIB_DEVICE_IMPL(74107_dip)
NETLIB_DEVICE_IMPL(74107A_dip)
} //namespace devices
} // namespace netlist

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@ -61,17 +61,24 @@
#include "nl_setup.h"
#define TTL_74107A(name, cCLK, cJ, cK, cCLRQ) \
NET_REGISTER_DEV(TTL_74107A, name) \
NET_CONNECT(name, CLK, cCLK) \
NET_CONNECT(name, J, cJ) \
NET_CONNECT(name, K, cK) \
#define PARAMS_74107_74107A(name, cCLK, cJ, cK, cCLRQ) \
NET_CONNECT(name, CLK, cCLK) \
NET_CONNECT(name, J, cJ) \
NET_CONNECT(name, K, cK) \
NET_CONNECT(name, CLRQ, cCLRQ)
#define TTL_74107(name, cCLK, cJ, cK, cCLRQ) \
TTL_74107A(name, cCLK, cJ, cK, cCLRQ)
#define TTL_74107(name, cCLK, cJ, cK, cCLRQ) \
NET_REGISTER_DEV(TTL_74107, name) \
PARAMS_74107_74107A(name, cCLK, cJ, cK, cCLRQ)
#define TTL_74107_DIP(name) \
#define TTL_74107A(name, cCLK, cJ, cK, cCLRQ) \
NET_REGISTER_DEV(TTL_74107A, name) \
PARAMS_74107_74107A(name, cCLK, cJ, cK, cCLRQ)
#define TTL_74107_DIP(name) \
NET_REGISTER_DEV(TTL_74107_DIP, name)
#define TTL_74107A_DIP(name) \
NET_REGISTER_DEV(TTL_74107A_DIP, name)
#endif /* NLD_74107_H_ */

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@ -20,6 +20,7 @@ namespace netlist
, m_CLRQ(*this, "CLRQ")
, m_last_CLK(*this, "m_last_CLK", 0)
, m_q(*this, "m_q", 0)
, m_latched_JK(*this, "m_latched_JK", 0)
, m_Q(*this, "Q")
, m_QQ(*this, "QQ")
{
@ -36,6 +37,7 @@ namespace netlist
state_var<unsigned> m_last_CLK;
state_var<unsigned> m_q;
state_var<unsigned> m_latched_JK;
logic_output_t m_Q;
logic_output_t m_QQ;
@ -107,17 +109,20 @@ namespace netlist
NETLIB_RESET(7473)
{
m_last_CLK = 0;
m_latched_JK = 0;
}
NETLIB_UPDATE(7473)
{
const auto JK = (m_J() << 1) | m_K();
if (m_CLRQ())
{
if (!m_CLK() && m_last_CLK)
if (m_CLK() && !m_last_CLK)
{
m_latched_JK = (m_J() << 1) | m_K();
}
else if (!m_CLK() && m_last_CLK)
{
switch (JK)
switch (m_latched_JK)
{
case 1: // (!m_J) & m_K))
m_q = 0;

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@ -0,0 +1,113 @@
// license:BSD-3-Clause
// copyright-holders:Ryan Holtz
/*
* nld_82S115.cpp
*
*/
#include "nld_82S115.h"
namespace netlist
{
namespace devices
{
NETLIB_OBJECT(82S115)
{
NETLIB_CONSTRUCTOR(82S115)
, m_A(*this, {{"A0", "A1", "A2", "A3", "A4", "A5", "A6", "A7", "A8"}})
, m_CE1(*this, "CE1")
, m_CE2Q(*this, "CE2Q")
, m_STROBE(*this, "STROBE")
, m_O(*this, {{"O1", "O2", "O3", "O4", "O5", "O6", "O7", "O8"}})
, m_last_O(*this, "m_last_O", 0)
, m_ROM(*this, "m_ROM", nullptr)
{
}
NETLIB_RESETI();
NETLIB_UPDATEI();
protected:
object_array_t<logic_input_t, 9> m_A;
logic_input_t m_CE1;
logic_input_t m_CE2Q;
logic_input_t m_STROBE;
object_array_t<logic_output_t, 8> m_O;
state_var<unsigned> m_last_O;
param_ptr_t m_ROM; // 4096 bits, 512x8
};
NETLIB_OBJECT_DERIVED(82S115_dip, 82S115)
{
NETLIB_CONSTRUCTOR_DERIVED(82S115_dip, 82S115)
{
register_subalias("21", m_A[0]);
register_subalias("22", m_A[1]);
register_subalias("23", m_A[2]);
register_subalias("1", m_A[3]);
register_subalias("2", m_A[4]);
register_subalias("3", m_A[5]);
register_subalias("4", m_A[6]);
register_subalias("5", m_A[7]);
register_subalias("6", m_A[8]);
register_subalias("20", m_CE1);
register_subalias("19", m_CE2Q);
// register_subalias("13", m_FE1);
// register_subalias("11", m_FE2);
register_subalias("18", m_STROBE);
register_subalias("7", m_O[0]);
register_subalias("8", m_O[1]);
register_subalias("9", m_O[2]);
register_subalias("10", m_O[3]);
register_subalias("14", m_O[4]);
register_subalias("15", m_O[5]);
register_subalias("16", m_O[6]);
register_subalias("17", m_O[7]);
}
};
NETLIB_RESET(82S115)
{
m_last_O = 0;
}
// FIXME: timing!
NETLIB_UPDATE(82S115)
{
unsigned o = 0;
if (m_CE1() && !m_CE2Q())
{
if (m_STROBE())
{
unsigned a = 0;
for (std::size_t i=0; i<9; i++)
a |= (m_A[i]() << i);
if (m_ROM() != nullptr)
o = ((std::uint_fast8_t*)(m_ROM()))[a];
}
else
{
o = m_last_O;
}
}
m_last_O = o;
// FIXME: Outputs are tristate. This needs to be properly implemented
for (std::size_t i=0; i<8; i++)
m_O[i].push((o >> i) & 1, NLTIME_FROM_NS(40)); // FIXME: Timing
}
NETLIB_DEVICE_IMPL(82S115)
NETLIB_DEVICE_IMPL(82S115_dip)
} //namespace devices
} // namespace netlist

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@ -0,0 +1,51 @@
// license:BSD-3-Clause
// copyright-holders:Ryan Holtz
/*
* nld_82S115.h
*
* 82S115: 4K-bit TTL bipolar PROM (512 x 8)
*
* +--------------+
* A3 |1 ++ 24| VCC
* A4 |2 23| A2
* A5 |3 22| A1
* A6 |4 82S115 21| A0
* A7 |5 20| CE1Q
* A8 |6 19| CE2
* O1 |7 18| STROBE
* O2 |8 17| O8
* O3 |9 16| O7
* O4 |10 15| O6
* FE2 |11 14| O5
* GND |12 13| FE1
* +--------------+
*
*
* Naming conventions follow Signetics datasheet
*
*/
#ifndef NLD_82S115_H_
#define NLD_82S115_H_
#include "nl_setup.h"
#define PROM_82S115(name, cCE1, cCE2Q, cA0, cA1, cA2, cA3, cA4, cA5, cA6, cA7, cA8, cSTROBE) \
NET_REGISTER_DEV(PROM_82S115, name) \
NET_CONNECT(name, CE1Q, cCE1Q) \
NET_CONNECT(name, CE2Q, cCE2Q) \
NET_CONNECT(name, A0, cA0) \
NET_CONNECT(name, A1, cA1) \
NET_CONNECT(name, A2, cA2) \
NET_CONNECT(name, A3, cA3) \
NET_CONNECT(name, A4, cA4) \
NET_CONNECT(name, A5, cA5) \
NET_CONNECT(name, A6, cA6) \
NET_CONNECT(name, A7, cA7) \
NET_CONNECT(name, A8, cA8) \
NET_CONNECT(name, STROBE, cSTROBE)
#define PROM_82S115_DIP(name) \
NET_REGISTER_DEV(PROM_82S115_DIP, name)
#endif /* NLD_82S115_H_ */

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@ -1,7 +1,7 @@
// license:BSD-3-Clause
// copyright-holders:Ryan Holtz
/*
* nld_82s126.cpp
* nld_82S126.cpp
*
*/
@ -62,7 +62,7 @@ namespace netlist
unsigned o = 0xf;
netlist_time delay = NLTIME_FROM_NS(25);
if (m_CE1Q() && m_CE1Q())
if (!m_CE1Q() && !m_CE2Q())
{
unsigned a = 0;
for (std::size_t i=0; i<8; i++)
@ -73,20 +73,7 @@ namespace netlist
delay = NLTIME_FROM_NS(50);
}
#if 0
printf("CE1Q%d CE2Q%d %d%d%d%d%d%d%d%d %x\n",
m_CE1Q() ? 1 : 0,
m_CE2Q() ? 1 : 0,
m_A[0]() ? 1 : 0,
m_A[1]() ? 1 : 0,
m_A[2]() ? 1 : 0,
m_A[3]() ? 1 : 0,
m_A[4]() ? 1 : 0,
m_A[5]() ? 1 : 0,
m_A[6]() ? 1 : 0,
m_A[7]() ? 1 : 0,
o);
#endif
// FIXME: Outputs are tristate. This needs to be properly implemented
for (std::size_t i=0; i<4; i++)
m_O[i].push((o >> i) & 1, delay);

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@ -26,8 +26,8 @@
#include "nl_setup.h"
#define TTL_82S126(name, cCE1Q, cCE2Q, cA0, cA1, cA2, cA3, cA4, cA5, cA6, cA7) \
NET_REGISTER_DEV(TTL_82S126, name) \
#define PROM_82S126(name, cCE1Q, cCE2Q, cA0, cA1, cA2, cA3, cA4, cA5, cA6, cA7) \
NET_REGISTER_DEV(PROM_82S126, name) \
NET_CONNECT(name, CE1Q, cCE1Q) \
NET_CONNECT(name, CE2Q, cCE2Q) \
NET_CONNECT(name, A0, cA0) \
@ -39,7 +39,7 @@
NET_CONNECT(name, A6, cA6) \
NET_CONNECT(name, A7, cA7)
#define TTL_82S126_DIP(name) \
NET_REGISTER_DEV(TTL_82S126_DIP, name)
#define PROM_82S126_DIP(name) \
NET_REGISTER_DEV(PROM_82S126_DIP, name)
#endif /* NLD_82S126_H_ */

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@ -48,7 +48,7 @@ NETLIST_START(hazelvid)
/* Horizontal/Vertical timing signals */
/* signal lookup PROM */
TTL_82S126(u71, high, high, u70.QA, u70.QB, u70.QC, u70.QD, u69.QA, u69.QB, u69.QC, low)
PROM_82S126(u71, low, low, u70.QA, u70.QB, u70.QC, u70.QD, u69.QA, u69.QB, u69.QC, low)
/* signal decoding */
TTL_DM9334(u72, high, u81.Q1Q, u71.O4, u71.O1, u71.O2, u71.O3)

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@ -24,4 +24,89 @@ NETLIST_START(stuntcyc)
MAINCLOCK(main_clk, 14318181.8)
ALIAS(Y1, main_clk)
#if 0
TTL_7404_INVERT(N3_6, main_clk)
ALIAS(HF_CLOCK, N3_6.Q)
ALIAS(P, high)
ALIAS(GND, low)
TTL_7474(N4_2, N3_6.Q, N4_2.QQ, P, P)
ALIAS(CLOCKQ, N4_2.QQ)
TTL_9316(M4, N4_2.Q, P, P, P, J6_1.Q, GND, GND, GND, GND)
TTL_9316(L4, N4_2.Q, M4.RC, P, P, J6_1.Q, GND, GND, GND, GND)
ALIAS( 1H, M4.QA)
ALIAS( 2H, M4.QB)
ALIAS( 4H, M4.QC)
ALIAS( 8H, M4.QD)
ALIAS( 16H, L4.QA)
ALIAS( 32H, L4.QB)
ALIAS( 64H, L4.QC)
ALIAS(128H, L4.QD)
TTL_74107(K4_1, 128H, P, P, P)
ALIAS(256H, K4_1.Q)
ALIAS(256HQ, K4_1.QQ)
TTL_7420_NAND(J6_1, 8H, 64H, 128H, 256H)
ALIAS(HRESETQ, J6_1.Q)
TTL_7404_INVERT(H6_3, HRESETQ)
ALIAS(HRESET, H6_3.Q)
TTL_7493(L3, HRESET, L3.QA, VRESET, VRESET)
TTL_7493(K3, L3.QD, K3.QA, VRESET, VRESET)
ALIAS( 1V, L3.QA)
ALIAS( 2V, L3.QB)
ALIAS( 4V, L3.QC)
ALIAS( 8V, L3.QD)
ALIAS( 16V, K3.QA)
ALIAS( 32V, K3.QB)
ALIAS( 64V, K3.QC)
ALIAS(128V, K3.QD)
TTL_74107(K4_2, 128V, P, P, VRESETQ)
ALIAS(256V, K4_2.Q)
ALIAS(256VQ, K4_2.QQ)
TTL_7410_NAND(M5_3, 256V, 2V, 1V)
TTL_7474(M3_2, HRESET, M5_3.Q, P, P)
ALIAS(VRESET, M3_2.QQ)
ALIAS(VRESETQ, M3_2.Q)
TTL_7402_NOR(J5_2, H6_3.Q, J5_1.Q)
TTL_7402_NOR(J5_1, 32H, J5_2.Q)
TTL_7402_NOR(J5_3, 8V, J5_4.Q)
TTL_7402_NOR(J5_4, VRESET, J5_3.Q)
ALIAS(HSYNC, J5_1.Q)
ALIAS(HSYNCQ, J5_2.Q)
ALIAS(VSYNC, J5_3.Q)
ALIAS(VSYNCQ, J5_4.Q)
TTL_7486_XOR(J4_1, HSYNC, VSYNCQ)
ALIAS(COMPSYNCQ, J4_1.Q)
TTL_7474(N4_1, HWINDOW, HSYNC, RAMP_WINDOW_HITQ, N4_1.QQ)
TTL_7474(M3_1, N4_1.Q, M3_1.QQ, CYCLE_RESETQ, P)
ALIAS(DIRECTION, M3_1.Q)
ALIAS(DIRECTIONQ, M3_1.QQ)
TTL_7404_INVERT(N3_3, 32V)
TTL_7474(J2_2, N3_3.Q, J2_1.Q, P, P)
TTL_7474(J2_1, N4_1.Q, P, J2_2.QQ, P)
TTL_7408_AND(H5_2, 256VQ, VSYNCQ)
TTL_9316(K1, HSYNC, P, H5_2.Q, V_COUNTER_RESETQ, L2_3.Q, Av, Bv, Cv, Dv)
TTL_9316(K2, HSYNC, K1.RC, J2_2.QQ, V_COUNTER_RESETQ, L2_3.Q, GND, GND, GND, GND)
TTL_7400_NAND(L2_3, K1.RC, K2.RC)
TTL_7402_NOR(D4_3, DIRECTION, H6)
TTL_7408_AND(B5_1, DIRECTION, H5H6)
TTL_7402_NOR(D4_4, D4_3.Q, B5_1.Q)
TTL_7400_NAND(H2_1, HSYNCQ, D4_4.Q)
TTL_7400_NAND(H2_2, HSYNCQ, H5)
TTL_9322(J1, HSYNC, V4, P, V3, 4V, V1, 1V, V2, 2V, GND)
#endif
NETLIST_END()