mirror of
https://github.com/holub/mame
synced 2025-04-22 16:31:49 +03:00
-netlist: Added 82S126 4kbit (512x8) TTL bipolar PROM. [Ryan Holtz]
This commit is contained in:
parent
0768d0b4fd
commit
9c4c4d0a5b
@ -149,6 +149,8 @@ project "netlist"
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MAME_DIR .. "src/lib/netlist/devices/nld_74ls629.h",
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MAME_DIR .. "src/lib/netlist/devices/nld_82S16.cpp",
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MAME_DIR .. "src/lib/netlist/devices/nld_82S16.h",
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MAME_DIR .. "src/lib/netlist/devices/nld_82S115.cpp",
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MAME_DIR .. "src/lib/netlist/devices/nld_82S115.h",
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MAME_DIR .. "src/lib/netlist/devices/nld_82S126.cpp",
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MAME_DIR .. "src/lib/netlist/devices/nld_82S126.h",
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MAME_DIR .. "src/lib/netlist/devices/nld_9310.cpp",
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@ -95,6 +95,7 @@ NLOBJS := \
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$(NLOBJ)/devices/nld_74365.o \
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$(NLOBJ)/devices/nld_74ls629.o \
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$(NLOBJ)/devices/nld_82S16.o \
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$(NLOBJ)/devices/nld_82S115.o \
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$(NLOBJ)/devices/nld_82S126.o \
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$(NLOBJ)/devices/nld_9310.o \
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$(NLOBJ)/devices/nld_9312.o \
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@ -136,7 +136,8 @@ static void initialize_factory(factory_list_t &factory)
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//ENTRY(74279, TTL_74279, "-") // only dip available
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ENTRYX(SN74LS629, SN74LS629, "CAP")
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ENTRYX(82S16, TTL_82S16, "-")
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ENTRYX(82S126, TTL_82S126, "-")
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ENTRYX(82S115, PROM_82S115, "-")
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ENTRYX(82S126, PROM_82S126, "-")
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ENTRYX(9310, TTL_9310, "-")
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ENTRYX(9312, TTL_9312, "-")
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ENTRYX(9316, TTL_9316, "+CLK,ENP,ENT,CLRQ,LOADQ,A,B,C,D")
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@ -42,6 +42,7 @@
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#include "nld_74365.h"
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#include "nld_74ls629.h"
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#include "nld_82S16.h"
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#include "nld_82S115.h"
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#include "nld_82S126.h"
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#include "nld_9310.h"
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#include "nld_9312.h"
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@ -64,18 +64,77 @@ namespace netlist
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};
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NETLIB_OBJECT_DERIVED(74107, 74107A)
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NETLIB_OBJECT(74107)
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{
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public:
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NETLIB_CONSTRUCTOR_DERIVED(74107, 74107A) { }
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NETLIB_CONSTRUCTOR(74107)
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, m_CLK(*this, "CLK")
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, m_J(*this, "J")
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, m_K(*this, "K")
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, m_CLRQ(*this, "CLRQ")
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, m_last_CLK(*this, "m_last_CLK", 0)
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, m_q(*this, "m_q", 0)
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, m_latched_JK(*this, "m_latched_JK", 0)
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, m_Q(*this, "Q")
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, m_QQ(*this, "QQ")
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{
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}
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NETLIB_RESETI();
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NETLIB_UPDATEI();
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public:
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logic_input_t m_CLK;
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logic_input_t m_J;
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logic_input_t m_K;
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logic_input_t m_CLRQ;
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state_var<unsigned> m_last_CLK;
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state_var<unsigned> m_q;
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state_var<unsigned> m_latched_JK;
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logic_output_t m_Q;
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logic_output_t m_QQ;
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};
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NETLIB_RESET(74107)
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{
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m_last_CLK = 0;
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m_latched_JK = 0;
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}
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NETLIB_OBJECT(74107_dip)
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{
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NETLIB_CONSTRUCTOR(74107_dip)
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, m_1(*this, "1")
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, m_2(*this, "2")
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{
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register_subalias("1", m_1.m_CLK);
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register_subalias("2", m_1.m_CLRQ);
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register_subalias("3", m_1.m_K);
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//register_subalias("4", ); ==> VCC
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register_subalias("5", m_2.m_CLK);
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register_subalias("6", m_2.m_CLRQ);
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register_subalias("7", m_2.m_J);
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register_subalias("8", m_2.m_QQ);
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register_subalias("9", m_2.m_Q);
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register_subalias("10", m_2.m_K);
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//register_subalias("11", ); ==> VCC
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register_subalias("12", m_2.m_Q);
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register_subalias("13", m_1.m_QQ);
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register_subalias("14", m_1.m_J);
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}
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private:
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NETLIB_SUB(74107) m_1;
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NETLIB_SUB(74107) m_2;
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};
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NETLIB_OBJECT(74107A_dip)
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{
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NETLIB_CONSTRUCTOR(74107A_dip)
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, m_1(*this, "1")
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, m_2(*this, "2")
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{
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register_subalias("1", m_1.m_J);
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register_subalias("2", m_1.m_sub.m_QQ);
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@ -102,8 +161,8 @@ namespace netlist
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//NETLIB_UPDATEI();
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private:
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NETLIB_SUB(74107) m_1;
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NETLIB_SUB(74107) m_2;
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NETLIB_SUB(74107A) m_1;
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NETLIB_SUB(74107A) m_2;
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};
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NETLIB_RESET(74107Asub)
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@ -173,9 +232,44 @@ namespace netlist
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m_sub.m_clk.activate_hl();
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}
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NETLIB_UPDATE(74107)
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{
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if (m_CLRQ())
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{
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if (m_CLK() && !m_last_CLK)
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{
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m_latched_JK = (m_J() << 1) | m_K();
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}
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else if (!m_CLK() && m_last_CLK)
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{
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switch (m_latched_JK)
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{
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case 1: // (!m_J) & m_K))
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m_q = 0;
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break;
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case 2: // (m_J) & !m_K))
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m_q = 1;
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break;
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case 3: // (m_J) & m_K))
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m_q ^= 1;
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break;
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default:
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case 0:
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break;
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}
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}
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}
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m_last_CLK = m_CLK();
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m_Q.push(m_q, NLTIME_FROM_NS(20)); // FIXME: timing
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m_QQ.push(m_q ^ 1, NLTIME_FROM_NS(20)); // FIXME: timing
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}
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NETLIB_DEVICE_IMPL(74107)
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NETLIB_DEVICE_IMPL(74107A)
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NETLIB_DEVICE_IMPL(74107_dip)
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NETLIB_DEVICE_IMPL(74107A_dip)
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} //namespace devices
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} // namespace netlist
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@ -61,17 +61,24 @@
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#include "nl_setup.h"
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#define TTL_74107A(name, cCLK, cJ, cK, cCLRQ) \
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NET_REGISTER_DEV(TTL_74107A, name) \
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NET_CONNECT(name, CLK, cCLK) \
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NET_CONNECT(name, J, cJ) \
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NET_CONNECT(name, K, cK) \
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#define PARAMS_74107_74107A(name, cCLK, cJ, cK, cCLRQ) \
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NET_CONNECT(name, CLK, cCLK) \
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NET_CONNECT(name, J, cJ) \
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NET_CONNECT(name, K, cK) \
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NET_CONNECT(name, CLRQ, cCLRQ)
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#define TTL_74107(name, cCLK, cJ, cK, cCLRQ) \
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TTL_74107A(name, cCLK, cJ, cK, cCLRQ)
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#define TTL_74107(name, cCLK, cJ, cK, cCLRQ) \
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NET_REGISTER_DEV(TTL_74107, name) \
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PARAMS_74107_74107A(name, cCLK, cJ, cK, cCLRQ)
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#define TTL_74107_DIP(name) \
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#define TTL_74107A(name, cCLK, cJ, cK, cCLRQ) \
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NET_REGISTER_DEV(TTL_74107A, name) \
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PARAMS_74107_74107A(name, cCLK, cJ, cK, cCLRQ)
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#define TTL_74107_DIP(name) \
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NET_REGISTER_DEV(TTL_74107_DIP, name)
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#define TTL_74107A_DIP(name) \
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NET_REGISTER_DEV(TTL_74107A_DIP, name)
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#endif /* NLD_74107_H_ */
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@ -20,6 +20,7 @@ namespace netlist
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, m_CLRQ(*this, "CLRQ")
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, m_last_CLK(*this, "m_last_CLK", 0)
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, m_q(*this, "m_q", 0)
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, m_latched_JK(*this, "m_latched_JK", 0)
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, m_Q(*this, "Q")
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, m_QQ(*this, "QQ")
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{
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@ -36,6 +37,7 @@ namespace netlist
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state_var<unsigned> m_last_CLK;
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state_var<unsigned> m_q;
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state_var<unsigned> m_latched_JK;
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logic_output_t m_Q;
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logic_output_t m_QQ;
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@ -107,17 +109,20 @@ namespace netlist
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NETLIB_RESET(7473)
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{
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m_last_CLK = 0;
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m_latched_JK = 0;
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}
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NETLIB_UPDATE(7473)
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{
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const auto JK = (m_J() << 1) | m_K();
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if (m_CLRQ())
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{
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if (!m_CLK() && m_last_CLK)
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if (m_CLK() && !m_last_CLK)
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{
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m_latched_JK = (m_J() << 1) | m_K();
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}
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else if (!m_CLK() && m_last_CLK)
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{
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switch (JK)
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switch (m_latched_JK)
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{
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case 1: // (!m_J) & m_K))
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m_q = 0;
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113
src/lib/netlist/devices/nld_82S115.cpp
Normal file
113
src/lib/netlist/devices/nld_82S115.cpp
Normal file
@ -0,0 +1,113 @@
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// license:BSD-3-Clause
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// copyright-holders:Ryan Holtz
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/*
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* nld_82S115.cpp
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*
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*/
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#include "nld_82S115.h"
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namespace netlist
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{
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namespace devices
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{
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NETLIB_OBJECT(82S115)
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{
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NETLIB_CONSTRUCTOR(82S115)
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, m_A(*this, {{"A0", "A1", "A2", "A3", "A4", "A5", "A6", "A7", "A8"}})
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, m_CE1(*this, "CE1")
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, m_CE2Q(*this, "CE2Q")
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, m_STROBE(*this, "STROBE")
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, m_O(*this, {{"O1", "O2", "O3", "O4", "O5", "O6", "O7", "O8"}})
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, m_last_O(*this, "m_last_O", 0)
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, m_ROM(*this, "m_ROM", nullptr)
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{
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}
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NETLIB_RESETI();
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NETLIB_UPDATEI();
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protected:
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object_array_t<logic_input_t, 9> m_A;
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logic_input_t m_CE1;
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logic_input_t m_CE2Q;
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logic_input_t m_STROBE;
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object_array_t<logic_output_t, 8> m_O;
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state_var<unsigned> m_last_O;
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param_ptr_t m_ROM; // 4096 bits, 512x8
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};
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NETLIB_OBJECT_DERIVED(82S115_dip, 82S115)
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{
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NETLIB_CONSTRUCTOR_DERIVED(82S115_dip, 82S115)
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{
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register_subalias("21", m_A[0]);
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register_subalias("22", m_A[1]);
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register_subalias("23", m_A[2]);
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register_subalias("1", m_A[3]);
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register_subalias("2", m_A[4]);
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register_subalias("3", m_A[5]);
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register_subalias("4", m_A[6]);
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register_subalias("5", m_A[7]);
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register_subalias("6", m_A[8]);
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register_subalias("20", m_CE1);
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register_subalias("19", m_CE2Q);
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// register_subalias("13", m_FE1);
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// register_subalias("11", m_FE2);
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register_subalias("18", m_STROBE);
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register_subalias("7", m_O[0]);
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register_subalias("8", m_O[1]);
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register_subalias("9", m_O[2]);
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register_subalias("10", m_O[3]);
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register_subalias("14", m_O[4]);
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register_subalias("15", m_O[5]);
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register_subalias("16", m_O[6]);
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register_subalias("17", m_O[7]);
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}
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};
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NETLIB_RESET(82S115)
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{
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m_last_O = 0;
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}
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// FIXME: timing!
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NETLIB_UPDATE(82S115)
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{
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unsigned o = 0;
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if (m_CE1() && !m_CE2Q())
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{
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if (m_STROBE())
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{
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unsigned a = 0;
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for (std::size_t i=0; i<9; i++)
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a |= (m_A[i]() << i);
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if (m_ROM() != nullptr)
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o = ((std::uint_fast8_t*)(m_ROM()))[a];
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}
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else
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{
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o = m_last_O;
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}
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}
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m_last_O = o;
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// FIXME: Outputs are tristate. This needs to be properly implemented
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for (std::size_t i=0; i<8; i++)
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m_O[i].push((o >> i) & 1, NLTIME_FROM_NS(40)); // FIXME: Timing
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}
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NETLIB_DEVICE_IMPL(82S115)
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NETLIB_DEVICE_IMPL(82S115_dip)
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} //namespace devices
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} // namespace netlist
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51
src/lib/netlist/devices/nld_82S115.h
Normal file
51
src/lib/netlist/devices/nld_82S115.h
Normal file
@ -0,0 +1,51 @@
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// license:BSD-3-Clause
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// copyright-holders:Ryan Holtz
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/*
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* nld_82S115.h
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*
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* 82S115: 4K-bit TTL bipolar PROM (512 x 8)
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*
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* +--------------+
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* A3 |1 ++ 24| VCC
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* A4 |2 23| A2
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* A5 |3 22| A1
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* A6 |4 82S115 21| A0
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* A7 |5 20| CE1Q
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* A8 |6 19| CE2
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* O1 |7 18| STROBE
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* O2 |8 17| O8
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* O3 |9 16| O7
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* O4 |10 15| O6
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* FE2 |11 14| O5
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* GND |12 13| FE1
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* +--------------+
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*
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*
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* Naming conventions follow Signetics datasheet
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*
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*/
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#ifndef NLD_82S115_H_
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#define NLD_82S115_H_
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#include "nl_setup.h"
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#define PROM_82S115(name, cCE1, cCE2Q, cA0, cA1, cA2, cA3, cA4, cA5, cA6, cA7, cA8, cSTROBE) \
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NET_REGISTER_DEV(PROM_82S115, name) \
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NET_CONNECT(name, CE1Q, cCE1Q) \
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NET_CONNECT(name, CE2Q, cCE2Q) \
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NET_CONNECT(name, A0, cA0) \
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NET_CONNECT(name, A1, cA1) \
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NET_CONNECT(name, A2, cA2) \
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NET_CONNECT(name, A3, cA3) \
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NET_CONNECT(name, A4, cA4) \
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NET_CONNECT(name, A5, cA5) \
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NET_CONNECT(name, A6, cA6) \
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NET_CONNECT(name, A7, cA7) \
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NET_CONNECT(name, A8, cA8) \
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NET_CONNECT(name, STROBE, cSTROBE)
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#define PROM_82S115_DIP(name) \
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NET_REGISTER_DEV(PROM_82S115_DIP, name)
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#endif /* NLD_82S115_H_ */
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@ -1,7 +1,7 @@
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// license:BSD-3-Clause
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// copyright-holders:Ryan Holtz
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/*
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* nld_82s126.cpp
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* nld_82S126.cpp
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*
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*/
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@ -62,7 +62,7 @@ namespace netlist
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unsigned o = 0xf;
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netlist_time delay = NLTIME_FROM_NS(25);
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if (m_CE1Q() && m_CE1Q())
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if (!m_CE1Q() && !m_CE2Q())
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{
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unsigned a = 0;
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for (std::size_t i=0; i<8; i++)
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@ -73,20 +73,7 @@ namespace netlist
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delay = NLTIME_FROM_NS(50);
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}
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#if 0
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printf("CE1Q%d CE2Q%d %d%d%d%d%d%d%d%d %x\n",
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m_CE1Q() ? 1 : 0,
|
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m_CE2Q() ? 1 : 0,
|
||||
m_A[0]() ? 1 : 0,
|
||||
m_A[1]() ? 1 : 0,
|
||||
m_A[2]() ? 1 : 0,
|
||||
m_A[3]() ? 1 : 0,
|
||||
m_A[4]() ? 1 : 0,
|
||||
m_A[5]() ? 1 : 0,
|
||||
m_A[6]() ? 1 : 0,
|
||||
m_A[7]() ? 1 : 0,
|
||||
o);
|
||||
#endif
|
||||
|
||||
// FIXME: Outputs are tristate. This needs to be properly implemented
|
||||
for (std::size_t i=0; i<4; i++)
|
||||
m_O[i].push((o >> i) & 1, delay);
|
||||
|
@ -26,8 +26,8 @@
|
||||
|
||||
#include "nl_setup.h"
|
||||
|
||||
#define TTL_82S126(name, cCE1Q, cCE2Q, cA0, cA1, cA2, cA3, cA4, cA5, cA6, cA7) \
|
||||
NET_REGISTER_DEV(TTL_82S126, name) \
|
||||
#define PROM_82S126(name, cCE1Q, cCE2Q, cA0, cA1, cA2, cA3, cA4, cA5, cA6, cA7) \
|
||||
NET_REGISTER_DEV(PROM_82S126, name) \
|
||||
NET_CONNECT(name, CE1Q, cCE1Q) \
|
||||
NET_CONNECT(name, CE2Q, cCE2Q) \
|
||||
NET_CONNECT(name, A0, cA0) \
|
||||
@ -39,7 +39,7 @@
|
||||
NET_CONNECT(name, A6, cA6) \
|
||||
NET_CONNECT(name, A7, cA7)
|
||||
|
||||
#define TTL_82S126_DIP(name) \
|
||||
NET_REGISTER_DEV(TTL_82S126_DIP, name)
|
||||
#define PROM_82S126_DIP(name) \
|
||||
NET_REGISTER_DEV(PROM_82S126_DIP, name)
|
||||
|
||||
#endif /* NLD_82S126_H_ */
|
||||
|
@ -48,7 +48,7 @@ NETLIST_START(hazelvid)
|
||||
/* Horizontal/Vertical timing signals */
|
||||
|
||||
/* signal lookup PROM */
|
||||
TTL_82S126(u71, high, high, u70.QA, u70.QB, u70.QC, u70.QD, u69.QA, u69.QB, u69.QC, low)
|
||||
PROM_82S126(u71, low, low, u70.QA, u70.QB, u70.QC, u70.QD, u69.QA, u69.QB, u69.QC, low)
|
||||
|
||||
/* signal decoding */
|
||||
TTL_DM9334(u72, high, u81.Q1Q, u71.O4, u71.O1, u71.O2, u71.O3)
|
||||
|
@ -24,4 +24,89 @@ NETLIST_START(stuntcyc)
|
||||
MAINCLOCK(main_clk, 14318181.8)
|
||||
ALIAS(Y1, main_clk)
|
||||
|
||||
#if 0
|
||||
TTL_7404_INVERT(N3_6, main_clk)
|
||||
ALIAS(HF_CLOCK, N3_6.Q)
|
||||
|
||||
ALIAS(P, high)
|
||||
ALIAS(GND, low)
|
||||
|
||||
TTL_7474(N4_2, N3_6.Q, N4_2.QQ, P, P)
|
||||
ALIAS(CLOCKQ, N4_2.QQ)
|
||||
|
||||
TTL_9316(M4, N4_2.Q, P, P, P, J6_1.Q, GND, GND, GND, GND)
|
||||
TTL_9316(L4, N4_2.Q, M4.RC, P, P, J6_1.Q, GND, GND, GND, GND)
|
||||
ALIAS( 1H, M4.QA)
|
||||
ALIAS( 2H, M4.QB)
|
||||
ALIAS( 4H, M4.QC)
|
||||
ALIAS( 8H, M4.QD)
|
||||
ALIAS( 16H, L4.QA)
|
||||
ALIAS( 32H, L4.QB)
|
||||
ALIAS( 64H, L4.QC)
|
||||
ALIAS(128H, L4.QD)
|
||||
|
||||
TTL_74107(K4_1, 128H, P, P, P)
|
||||
ALIAS(256H, K4_1.Q)
|
||||
ALIAS(256HQ, K4_1.QQ)
|
||||
|
||||
TTL_7420_NAND(J6_1, 8H, 64H, 128H, 256H)
|
||||
ALIAS(HRESETQ, J6_1.Q)
|
||||
|
||||
TTL_7404_INVERT(H6_3, HRESETQ)
|
||||
ALIAS(HRESET, H6_3.Q)
|
||||
|
||||
TTL_7493(L3, HRESET, L3.QA, VRESET, VRESET)
|
||||
TTL_7493(K3, L3.QD, K3.QA, VRESET, VRESET)
|
||||
ALIAS( 1V, L3.QA)
|
||||
ALIAS( 2V, L3.QB)
|
||||
ALIAS( 4V, L3.QC)
|
||||
ALIAS( 8V, L3.QD)
|
||||
ALIAS( 16V, K3.QA)
|
||||
ALIAS( 32V, K3.QB)
|
||||
ALIAS( 64V, K3.QC)
|
||||
ALIAS(128V, K3.QD)
|
||||
|
||||
TTL_74107(K4_2, 128V, P, P, VRESETQ)
|
||||
ALIAS(256V, K4_2.Q)
|
||||
ALIAS(256VQ, K4_2.QQ)
|
||||
|
||||
TTL_7410_NAND(M5_3, 256V, 2V, 1V)
|
||||
TTL_7474(M3_2, HRESET, M5_3.Q, P, P)
|
||||
ALIAS(VRESET, M3_2.QQ)
|
||||
ALIAS(VRESETQ, M3_2.Q)
|
||||
|
||||
TTL_7402_NOR(J5_2, H6_3.Q, J5_1.Q)
|
||||
TTL_7402_NOR(J5_1, 32H, J5_2.Q)
|
||||
TTL_7402_NOR(J5_3, 8V, J5_4.Q)
|
||||
TTL_7402_NOR(J5_4, VRESET, J5_3.Q)
|
||||
ALIAS(HSYNC, J5_1.Q)
|
||||
ALIAS(HSYNCQ, J5_2.Q)
|
||||
ALIAS(VSYNC, J5_3.Q)
|
||||
ALIAS(VSYNCQ, J5_4.Q)
|
||||
|
||||
TTL_7486_XOR(J4_1, HSYNC, VSYNCQ)
|
||||
ALIAS(COMPSYNCQ, J4_1.Q)
|
||||
|
||||
TTL_7474(N4_1, HWINDOW, HSYNC, RAMP_WINDOW_HITQ, N4_1.QQ)
|
||||
TTL_7474(M3_1, N4_1.Q, M3_1.QQ, CYCLE_RESETQ, P)
|
||||
ALIAS(DIRECTION, M3_1.Q)
|
||||
ALIAS(DIRECTIONQ, M3_1.QQ)
|
||||
|
||||
TTL_7404_INVERT(N3_3, 32V)
|
||||
TTL_7474(J2_2, N3_3.Q, J2_1.Q, P, P)
|
||||
TTL_7474(J2_1, N4_1.Q, P, J2_2.QQ, P)
|
||||
|
||||
TTL_7408_AND(H5_2, 256VQ, VSYNCQ)
|
||||
TTL_9316(K1, HSYNC, P, H5_2.Q, V_COUNTER_RESETQ, L2_3.Q, Av, Bv, Cv, Dv)
|
||||
TTL_9316(K2, HSYNC, K1.RC, J2_2.QQ, V_COUNTER_RESETQ, L2_3.Q, GND, GND, GND, GND)
|
||||
TTL_7400_NAND(L2_3, K1.RC, K2.RC)
|
||||
|
||||
TTL_7402_NOR(D4_3, DIRECTION, H6)
|
||||
TTL_7408_AND(B5_1, DIRECTION, H5H6)
|
||||
TTL_7402_NOR(D4_4, D4_3.Q, B5_1.Q)
|
||||
TTL_7400_NAND(H2_1, HSYNCQ, D4_4.Q)
|
||||
TTL_7400_NAND(H2_2, HSYNCQ, H5)
|
||||
|
||||
TTL_9322(J1, HSYNC, V4, P, V3, 4V, V1, 1V, V2, 2V, GND)
|
||||
#endif
|
||||
NETLIST_END()
|
||||
|
Loading…
Reference in New Issue
Block a user