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i386.cpp: add more msrs releted to smm to athlon xp (nw)

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This commit is contained in:
yz70s 2019-04-24 19:58:42 +02:00
parent a712bb9fd2
commit 9e850ffe14
3 changed files with 38 additions and 1 deletions
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33
src/devices/cpu/i386/cpuidmsrs.hxx
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@ -236,7 +236,7 @@ void athlonxp_device::opcode_cpuid()
case 0x80000007:
{
REG32(EDX) = 1;
REG32(EDX) = 1; // Advanced power management information, temperature sensor present
CYCLES(CYCLES_CPUID);
break;
}
@ -368,7 +368,21 @@ uint64_t athlonxp_device::opcode_rdmsr(bool &valid_msr)
break;
case 0xC001001D: // TOP_MEM2
break;
case 0xC0010111: // SMM_BASE
// address of system management mode area
ret = (uint64_t)m_msr_smm_base;
break;
case 0xC0010113: // SMM_MASK
// 1 TValid - Enable TSeg SMRAM Range
// 0 AValid - Enable ASeg SMRAM Range
/* Access to the ASeg (a0000-bffff) depends on bit 0 of smm_mask
if the bit is 0 use the associated fixed mtrr
if the bit is 1
if smm is active
access goes to dram (wrmem 1 rdmem 1)
if smm not active
access goes to mmio (wrmem 0 rdmem 0) */
ret = m_msr_smm_mask;
break;
}
valid_msr = true;
@ -414,6 +428,11 @@ void athlonxp_device::opcode_wrmsr(uint64_t data, bool &valid_msr)
break;
case 0x259: // MTRRfix16K_A0000
m_msr_mtrrfix[2] = data;
if (m_msr_smm_mask & 1)
{
// data = 0x1818181818181818; // when smm is implemented
data = 0; // when smm is not active
}
parse_mtrrfix(data, 0xa0000, 16);
break;
case 0x268: // MTRRfix4K_C0000-F8000
@ -448,7 +467,19 @@ void athlonxp_device::opcode_wrmsr(uint64_t data, bool &valid_msr)
case 0xC001001A: // TOP_MEM
m_msr_top_mem = (offs_t)data;
break;
case 0xC0010111: // SMM_BASE
m_msr_smm_base = (offs_t)data;
break;
case 0xC0010113: // SMM_MASK
m_msr_smm_mask = data;
if (m_msr_smm_mask & 1)
{
// data = 0x1818181818181818; // when smm is implemented
data = 0; // when smm is not active
}
else
data = m_msr_mtrrfix[2];
parse_mtrrfix(data, 0xa0000, 16);
break;
}
valid_msr = true;

4
src/devices/cpu/i386/i386.cpp
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@ -4708,6 +4708,8 @@ void athlonxp_device::device_start()
save_item(NAME(m_processor_name_string));
save_item(NAME(m_msr_top_mem));
save_item(NAME(m_msr_sys_cfg));
save_item(NAME(m_msr_smm_base));
save_item(NAME(m_msr_smm_mask));
save_item(NAME(m_msr_mtrrfix));
save_item(NAME(m_memory_ranges_1m));
}
@ -4761,6 +4763,8 @@ void athlonxp_device::device_reset()
m_memory_ranges_1m[n] = 0;
m_msr_top_mem = 1024 * 1024;
m_msr_sys_cfg = 0;
m_msr_smm_base = 0x30000;
m_msr_smm_mask = 0;
m_cpuid_max_input_value_eax = 0x01;
m_cpu_version = REG32(EDX);

2
src/devices/cpu/i386/i386.h
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@ -1677,6 +1677,8 @@ private:
uint8_t m_processor_name_string[48];
offs_t m_msr_top_mem;
uint64_t m_msr_sys_cfg;
offs_t m_msr_smm_base;
uint64_t m_msr_smm_mask;
uint64_t m_msr_mtrrfix[11];
uint8_t m_memory_ranges_1m[1024 / 4];
cpucache<17, 9, Cache2Way, CacheLineBytes64> cache; // 512 sets, 2 ways (cachelines per set), 64 bytes per cacheline