mirror of
https://github.com/holub/mame
synced 2025-05-22 21:58:57 +03:00
SH2: fix PC relative MOV in delay slot
This commit is contained in:
R. Belmont
parent
2fa7094eab
commit
9ea6e5de56
@ -574,7 +574,7 @@ static UINT32 op1111(char *buffer, UINT32 pc, UINT16 opcode)
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return 0;
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}
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static unsigned DasmSH2(char *buffer, unsigned pc, UINT16 opcode)
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unsigned DasmSH2(char *buffer, unsigned pc, UINT16 opcode)
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{
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UINT32 flags;
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@ -22,6 +22,7 @@
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#include "profiler.h"
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CPU_DISASSEMBLE( sh2 );
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extern unsigned DasmSH2(char *buffer, unsigned pc, UINT16 opcode);
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#ifdef USE_SH2DRC
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@ -106,17 +107,17 @@ static void static_generate_memory_accessor(sh2_state *sh2, int size, int iswrit
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static void generate_update_cycles(sh2_state *sh2, drcuml_block *block, compiler_state *compiler, drcuml_ptype ptype, UINT64 pvalue, int allow_exception);
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static void generate_checksum_block(sh2_state *sh2, drcuml_block *block, compiler_state *compiler, const opcode_desc *seqhead, const opcode_desc *seqlast);
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static void generate_sequence_instruction(sh2_state *sh2, drcuml_block *block, compiler_state *compiler, const opcode_desc *desc);
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static void generate_delay_slot(sh2_state *sh2, drcuml_block *block, compiler_state *compiler, const opcode_desc *desc);
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static void generate_sequence_instruction(sh2_state *sh2, drcuml_block *block, compiler_state *compiler, const opcode_desc *desc, UINT32 ovrpc);
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static void generate_delay_slot(sh2_state *sh2, drcuml_block *block, compiler_state *compiler, const opcode_desc *desc, UINT32 ovrpc);
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static int generate_opcode(sh2_state *sh2, drcuml_block *block, compiler_state *compiler, const opcode_desc *desc);
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static int generate_group_0(sh2_state *sh2, drcuml_block *block, compiler_state *compiler, const opcode_desc *desc, UINT16 opcode, int in_delay_slot);
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static int generate_group_2(sh2_state *sh2, drcuml_block *block, compiler_state *compiler, const opcode_desc *desc, UINT16 opcode, int in_delay_slot);
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static int generate_group_3(sh2_state *sh2, drcuml_block *block, compiler_state *compiler, const opcode_desc *desc, UINT16 opcode);
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static int generate_group_4(sh2_state *sh2, drcuml_block *block, compiler_state *compiler, const opcode_desc *desc, UINT16 opcode, int in_delay_slot);
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static int generate_group_6(sh2_state *sh2, drcuml_block *block, compiler_state *compiler, const opcode_desc *desc, UINT16 opcode, int in_delay_slot);
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static int generate_group_8(sh2_state *sh2, drcuml_block *block, compiler_state *compiler, const opcode_desc *desc, UINT16 opcode, int in_delay_slot);
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static int generate_group_12(sh2_state *sh2, drcuml_block *block, compiler_state *compiler, const opcode_desc *desc, UINT16 opcode, int in_delay_slot);
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static int generate_opcode(sh2_state *sh2, drcuml_block *block, compiler_state *compiler, const opcode_desc *desc, UINT32 ovrpc);
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static int generate_group_0(sh2_state *sh2, drcuml_block *block, compiler_state *compiler, const opcode_desc *desc, UINT16 opcode, int in_delay_slot, UINT32 ovrpc);
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static int generate_group_2(sh2_state *sh2, drcuml_block *block, compiler_state *compiler, const opcode_desc *desc, UINT16 opcode, int in_delay_slot, UINT32 ovrpc);
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static int generate_group_3(sh2_state *sh2, drcuml_block *block, compiler_state *compiler, const opcode_desc *desc, UINT16 opcode, UINT32 ovrpc);
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static int generate_group_4(sh2_state *sh2, drcuml_block *block, compiler_state *compiler, const opcode_desc *desc, UINT16 opcode, int in_delay_slot, UINT32 ovrpc);
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static int generate_group_6(sh2_state *sh2, drcuml_block *block, compiler_state *compiler, const opcode_desc *desc, UINT16 opcode, int in_delay_slot, UINT32 ovrpc);
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static int generate_group_8(sh2_state *sh2, drcuml_block *block, compiler_state *compiler, const opcode_desc *desc, UINT16 opcode, int in_delay_slot, UINT32 ovrpc);
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static int generate_group_12(sh2_state *sh2, drcuml_block *block, compiler_state *compiler, const opcode_desc *desc, UINT16 opcode, int in_delay_slot, UINT32 ovrpc);
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static void code_compile_block(sh2_state *sh2, UINT8 mode, offs_t pc);
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@ -1001,7 +1002,7 @@ static void code_compile_block(sh2_state *sh2, UINT8 mode, offs_t pc)
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/* iterate over instructions in the sequence and compile them */
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for (curdesc = seqhead; curdesc != seqlast->next; curdesc = curdesc->next)
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{
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generate_sequence_instruction(sh2, block, &compiler, curdesc);
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generate_sequence_instruction(sh2, block, &compiler, curdesc, 0xffffffff);
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}
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/* if we need to return to the start, do it */
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@ -1571,7 +1572,7 @@ static void generate_checksum_block(sh2_state *sh2, drcuml_block *block, compile
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for a single instruction in a sequence
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-------------------------------------------------*/
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static void generate_sequence_instruction(sh2_state *sh2, drcuml_block *block, compiler_state *compiler, const opcode_desc *desc)
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static void generate_sequence_instruction(sh2_state *sh2, drcuml_block *block, compiler_state *compiler, const opcode_desc *desc, UINT32 ovrpc)
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{
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offs_t expc;
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@ -1642,7 +1643,7 @@ static void generate_sequence_instruction(sh2_state *sh2, drcuml_block *block, c
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else if (!(desc->flags & OPFLAG_VIRTUAL_NOOP))
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{
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/* compile the instruction */
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if (!generate_opcode(sh2, block, compiler, desc))
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if (!generate_opcode(sh2, block, compiler, desc, ovrpc))
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{
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UML_MOV(block, MEM(&sh2->pc), IMM(desc->pc)); // mov [pc],desc->pc
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UML_MOV(block, MEM(&sh2->arg0), IMM(desc->opptr.w[0])); // mov [arg0],opcode
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@ -1655,13 +1656,13 @@ static void generate_sequence_instruction(sh2_state *sh2, drcuml_block *block, c
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generate_delay_slot
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------------------------------------------------------------------*/
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static void generate_delay_slot(sh2_state *sh2, drcuml_block *block, compiler_state *compiler, const opcode_desc *desc)
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static void generate_delay_slot(sh2_state *sh2, drcuml_block *block, compiler_state *compiler, const opcode_desc *desc, UINT32 ovrpc)
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{
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compiler_state compiler_temp = *compiler;
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/* compile the delay slot using temporary compiler state */
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assert(desc->delay != NULL);
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generate_sequence_instruction(sh2, block, &compiler_temp, desc->delay); // <next instruction>
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generate_sequence_instruction(sh2, block, &compiler_temp, desc->delay, ovrpc); // <next instruction>
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/* update the label */
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compiler->labelnum = compiler_temp.labelnum;
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@ -1672,7 +1673,7 @@ static void generate_delay_slot(sh2_state *sh2, drcuml_block *block, compiler_st
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opcode
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-------------------------------------------------*/
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static int generate_opcode(sh2_state *sh2, drcuml_block *block, compiler_state *compiler, const opcode_desc *desc)
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static int generate_opcode(sh2_state *sh2, drcuml_block *block, compiler_state *compiler, const opcode_desc *desc, UINT32 ovrpc)
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{
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UINT32 scratch, scratch2;
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INT32 disp;
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@ -1683,7 +1684,7 @@ static int generate_opcode(sh2_state *sh2, drcuml_block *block, compiler_state *
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switch (opswitch)
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{
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case 0:
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return generate_group_0(sh2, block, compiler, desc, opcode, in_delay_slot);
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return generate_group_0(sh2, block, compiler, desc, opcode, in_delay_slot, ovrpc);
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case 1: // MOVLS4
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scratch = (opcode & 0x0f) * 4;
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@ -1697,11 +1698,11 @@ static int generate_opcode(sh2_state *sh2, drcuml_block *block, compiler_state *
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return TRUE;
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case 2:
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return generate_group_2(sh2, block, compiler, desc, opcode, in_delay_slot);
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return generate_group_2(sh2, block, compiler, desc, opcode, in_delay_slot, ovrpc);
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case 3:
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return generate_group_3(sh2, block, compiler, desc, opcode);
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return generate_group_3(sh2, block, compiler, desc, opcode, ovrpc);
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case 4:
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return generate_group_4(sh2, block, compiler, desc, opcode, in_delay_slot);
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return generate_group_4(sh2, block, compiler, desc, opcode, in_delay_slot, ovrpc);
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case 5: // MOVLL4
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scratch = (opcode & 0x0f) * 4;
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@ -1715,7 +1716,7 @@ static int generate_opcode(sh2_state *sh2, drcuml_block *block, compiler_state *
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return TRUE;
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case 6:
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return generate_group_6(sh2, block, compiler, desc, opcode, in_delay_slot);
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return generate_group_6(sh2, block, compiler, desc, opcode, in_delay_slot, ovrpc);
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case 7: // ADDI
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scratch = opcode & 0xff;
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@ -1724,10 +1725,17 @@ static int generate_opcode(sh2_state *sh2, drcuml_block *block, compiler_state *
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return TRUE;
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case 8:
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return generate_group_8(sh2, block, compiler, desc, opcode, in_delay_slot);
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return generate_group_8(sh2, block, compiler, desc, opcode, in_delay_slot, ovrpc);
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case 9: // MOVWI
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scratch = (desc->pc + 2) + ((opcode & 0xff) * 2) + 2;
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if (ovrpc == 0xffffffff)
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{
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scratch = (desc->pc + 2) + ((opcode & 0xff) * 2) + 2;
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}
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else
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{
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scratch = (ovrpc + 2) + ((opcode & 0xff) * 2) + 2;
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}
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if (sh2->drcoptions & SH2DRC_STRICT_PCREL)
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{
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@ -1747,12 +1755,11 @@ static int generate_opcode(sh2_state *sh2, drcuml_block *block, compiler_state *
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return TRUE;
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case 10: // BRA
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generate_delay_slot(sh2, block, compiler, desc);
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disp = ((INT32)opcode << 20) >> 20;
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sh2->ea = (desc->pc + 2) + disp * 2 + 2; // sh2->ea = pc+4 + disp*2 + 2
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generate_delay_slot(sh2, block, compiler, desc, sh2->ea);
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generate_update_cycles(sh2, block, compiler, IMM(sh2->ea), TRUE); // <subtract cycles>
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UML_HASHJMP(block, IMM(0), IMM(sh2->ea), sh2->nocode); // hashjmp sh2->ea
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return TRUE;
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@ -1762,20 +1769,27 @@ static int generate_opcode(sh2_state *sh2, drcuml_block *block, compiler_state *
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// do this before running the delay slot
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UML_ADD(block, MEM(&sh2->pr), IMM(desc->pc), IMM(4)); // add sh2->pr, desc->pc, #4 (skip the current insn & delay slot)
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generate_delay_slot(sh2, block, compiler, desc);
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disp = ((INT32)opcode << 20) >> 20;
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sh2->ea = (desc->pc + 2) + disp * 2 + 2; // sh2->ea = pc+4 + disp*2 + 2
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generate_delay_slot(sh2, block, compiler, desc, sh2->ea);
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generate_update_cycles(sh2, block, compiler, IMM(sh2->ea), TRUE); // <subtract cycles>
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UML_HASHJMP(block, IMM(0), IMM(sh2->ea), sh2->nocode); // hashjmp sh2->ea
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return TRUE;
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case 12:
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return generate_group_12(sh2, block, compiler, desc, opcode, in_delay_slot);
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return generate_group_12(sh2, block, compiler, desc, opcode, in_delay_slot, ovrpc);
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case 13: // MOVLI
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scratch = ((desc->pc + 4) & ~3) + ((opcode & 0xff) * 4);
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if (ovrpc == 0xffffffff)
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{
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scratch = ((desc->pc + 4) & ~3) + ((opcode & 0xff) * 4);
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}
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else
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{
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scratch = ((ovrpc + 4) & ~3) + ((opcode & 0xff) * 4);
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}
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if (sh2->drcoptions & SH2DRC_STRICT_PCREL)
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{
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@ -1806,7 +1820,7 @@ static int generate_opcode(sh2_state *sh2, drcuml_block *block, compiler_state *
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return FALSE;
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}
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static int generate_group_0(sh2_state *sh2, drcuml_block *block, compiler_state *compiler, const opcode_desc *desc, UINT16 opcode, int in_delay_slot)
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static int generate_group_0(sh2_state *sh2, drcuml_block *block, compiler_state *compiler, const opcode_desc *desc, UINT16 opcode, int in_delay_slot, UINT32 ovrpc)
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{
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switch (opcode & 0x3F)
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{
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@ -1842,7 +1856,7 @@ static int generate_group_0(sh2_state *sh2, drcuml_block *block, compiler_state
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// clobbering the calculated PR, so do it first
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UML_ADD(block, MEM(&sh2->pr), IMM(desc->pc), IMM(4)); // add sh2->pr, desc->pc, #4 (skip the current insn & delay slot)
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generate_delay_slot(sh2, block, compiler, desc);
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generate_delay_slot(sh2, block, compiler, desc, sh2->target);
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generate_update_cycles(sh2, block, compiler, MEM(&sh2->target), TRUE); // <subtract cycles>
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UML_HASHJMP(block, IMM(0), MEM(&sh2->target), sh2->nocode); // jmp target
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@ -1908,7 +1922,7 @@ static int generate_group_0(sh2_state *sh2, drcuml_block *block, compiler_state
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case 0x0b: // RTS();
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UML_MOV(block, MEM(&sh2->target), MEM(&sh2->pr)); // mov target, pr (in case of d-slot shenanigans)
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generate_delay_slot(sh2, block, compiler, desc);
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generate_delay_slot(sh2, block, compiler, desc, sh2->target);
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generate_update_cycles(sh2, block, compiler, MEM(&sh2->target), TRUE); // <subtract cycles>
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UML_HASHJMP(block, IMM(0), MEM(&sh2->target), sh2->nocode);
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@ -2026,7 +2040,7 @@ static int generate_group_0(sh2_state *sh2, drcuml_block *block, compiler_state
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{
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UML_ADD(block, MEM(&sh2->target), R32(Rn), IMM(desc->pc+4)); // add target, Rn, pc+4
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generate_delay_slot(sh2, block, compiler, desc);
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generate_delay_slot(sh2, block, compiler, desc, sh2->target);
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generate_update_cycles(sh2, block, compiler, MEM(&sh2->target), TRUE); // <subtract cycles>
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UML_HASHJMP(block, IMM(0), MEM(&sh2->target), sh2->nocode); // jmp target
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@ -2048,7 +2062,7 @@ static int generate_group_0(sh2_state *sh2, drcuml_block *block, compiler_state
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return TRUE;
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case 0x2b: // RTE();
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generate_delay_slot(sh2, block, compiler, desc);
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generate_delay_slot(sh2, block, compiler, desc, 0xffffffff);
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UML_MOV(block, IREG(0), R32(15)); // mov r0, R15
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UML_CALLH(block, sh2->read32); // call read32
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@ -2071,7 +2085,7 @@ static int generate_group_0(sh2_state *sh2, drcuml_block *block, compiler_state
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return FALSE;
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}
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static int generate_group_2(sh2_state *sh2, drcuml_block *block, compiler_state *compiler, const opcode_desc *desc, UINT16 opcode, int in_delay_slot)
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static int generate_group_2(sh2_state *sh2, drcuml_block *block, compiler_state *compiler, const opcode_desc *desc, UINT16 opcode, int in_delay_slot, UINT32 ovrpc)
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{
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switch (opcode & 15)
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{
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@ -2240,7 +2254,7 @@ static int generate_group_2(sh2_state *sh2, drcuml_block *block, compiler_state
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return FALSE;
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}
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static int generate_group_3(sh2_state *sh2, drcuml_block *block, compiler_state *compiler, const opcode_desc *desc, UINT16 opcode)
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static int generate_group_3(sh2_state *sh2, drcuml_block *block, compiler_state *compiler, const opcode_desc *desc, UINT16 opcode, UINT32 ovrpc)
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{
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switch (opcode & 15)
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{
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@ -2352,7 +2366,7 @@ static int generate_group_3(sh2_state *sh2, drcuml_block *block, compiler_state
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return FALSE;
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}
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static int generate_group_4(sh2_state *sh2, drcuml_block *block, compiler_state *compiler, const opcode_desc *desc, UINT16 opcode, int in_delay_slot)
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static int generate_group_4(sh2_state *sh2, drcuml_block *block, compiler_state *compiler, const opcode_desc *desc, UINT16 opcode, int in_delay_slot, UINT32 ovrpc)
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{
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switch (opcode & 0x3F)
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{
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@ -2459,7 +2473,7 @@ static int generate_group_4(sh2_state *sh2, drcuml_block *block, compiler_state
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UML_ADD(block, MEM(&sh2->pr), IMM(desc->pc), IMM(4)); // add sh2->pr, desc->pc, #4 (skip the current insn & delay slot)
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generate_delay_slot(sh2, block, compiler, desc);
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generate_delay_slot(sh2, block, compiler, desc, sh2->target);
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generate_update_cycles(sh2, block, compiler, MEM(&sh2->target), TRUE); // <subtract cycles>
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UML_HASHJMP(block, IMM(0), MEM(&sh2->target), sh2->nocode); // and do the jump
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@ -2679,7 +2693,7 @@ static int generate_group_4(sh2_state *sh2, drcuml_block *block, compiler_state
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case 0x2b: // JMP(Rn);
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UML_MOV(block, MEM(&sh2->target), R32(Rn)); // mov target, Rn
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generate_delay_slot(sh2, block, compiler, desc);
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generate_delay_slot(sh2, block, compiler, desc, sh2->target);
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generate_update_cycles(sh2, block, compiler, MEM(&sh2->target), TRUE); // <subtract cycles>
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UML_HASHJMP(block, IMM(0), MEM(&sh2->target), sh2->nocode); // jmp (target)
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@ -2717,7 +2731,7 @@ static int generate_group_4(sh2_state *sh2, drcuml_block *block, compiler_state
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return FALSE;
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}
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static int generate_group_6(sh2_state *sh2, drcuml_block *block, compiler_state *compiler, const opcode_desc *desc, UINT16 opcode, int in_delay_slot)
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static int generate_group_6(sh2_state *sh2, drcuml_block *block, compiler_state *compiler, const opcode_desc *desc, UINT16 opcode, int in_delay_slot, UINT32 ovrpc)
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{
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switch (opcode & 15)
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{
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@ -2847,7 +2861,7 @@ static int generate_group_6(sh2_state *sh2, drcuml_block *block, compiler_state
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return FALSE;
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}
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static int generate_group_8(sh2_state *sh2, drcuml_block *block, compiler_state *compiler, const opcode_desc *desc, UINT16 opcode, int in_delay_slot)
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static int generate_group_8(sh2_state *sh2, drcuml_block *block, compiler_state *compiler, const opcode_desc *desc, UINT16 opcode, int in_delay_slot, UINT32 ovrpc)
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{
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INT32 disp;
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UINT32 udisp;
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@ -2951,13 +2965,13 @@ static int generate_group_8(sh2_state *sh2, drcuml_block *block, compiler_state
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UML_TEST(block, MEM(&sh2->sr), IMM(T)); // test sh2->sr, T
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UML_JMPc(block, IF_Z, compiler->labelnum); // jz compiler->labelnum
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templabel = compiler->labelnum; // save our label
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compiler->labelnum++; // make sure the delay slot doesn't use it
|
||||
generate_delay_slot(sh2, block, compiler, desc);
|
||||
|
||||
disp = ((INT32)opcode << 24) >> 24;
|
||||
sh2->ea = (desc->pc + 2) + disp * 2 + 2; // sh2->ea = destination
|
||||
|
||||
templabel = compiler->labelnum; // save our label
|
||||
compiler->labelnum++; // make sure the delay slot doesn't use it
|
||||
generate_delay_slot(sh2, block, compiler, desc, sh2->ea);
|
||||
|
||||
generate_update_cycles(sh2, block, compiler, IMM(sh2->ea), TRUE); // <subtract cycles>
|
||||
UML_HASHJMP(block, IMM(0), IMM(sh2->ea), sh2->nocode); // jmp sh2->ea
|
||||
|
||||
@ -2972,13 +2986,13 @@ static int generate_group_8(sh2_state *sh2, drcuml_block *block, compiler_state
|
||||
UML_TEST(block, MEM(&sh2->sr), IMM(T)); // test sh2->sr, T
|
||||
UML_JMPc(block, IF_NZ, compiler->labelnum); // jnz compiler->labelnum
|
||||
|
||||
templabel = compiler->labelnum; // save our label
|
||||
compiler->labelnum++; // make sure the delay slot doesn't use it
|
||||
generate_delay_slot(sh2, block, compiler, desc); // delay slot only if the branch is taken
|
||||
|
||||
disp = ((INT32)opcode << 24) >> 24;
|
||||
sh2->ea = (desc->pc + 2) + disp * 2 + 2; // sh2->ea = destination
|
||||
|
||||
templabel = compiler->labelnum; // save our label
|
||||
compiler->labelnum++; // make sure the delay slot doesn't use it
|
||||
generate_delay_slot(sh2, block, compiler, desc, sh2->ea); // delay slot only if the branch is taken
|
||||
|
||||
generate_update_cycles(sh2, block, compiler, IMM(sh2->ea), TRUE); // <subtract cycles>
|
||||
UML_HASHJMP(block, IMM(0), IMM(sh2->ea), sh2->nocode); // jmp sh2->ea
|
||||
|
||||
@ -2991,7 +3005,7 @@ static int generate_group_8(sh2_state *sh2, drcuml_block *block, compiler_state
|
||||
return FALSE;
|
||||
}
|
||||
|
||||
static int generate_group_12(sh2_state *sh2, drcuml_block *block, compiler_state *compiler, const opcode_desc *desc, UINT16 opcode, int in_delay_slot)
|
||||
static int generate_group_12(sh2_state *sh2, drcuml_block *block, compiler_state *compiler, const opcode_desc *desc, UINT16 opcode, int in_delay_slot, UINT32 ovrpc)
|
||||
{
|
||||
UINT32 scratch;
|
||||
|
||||
|
||||
Loading…
Reference in New Issue
Block a user