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Refactor 680x0 so that member variables aren't public. [smf]

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This commit is contained in:
smf- 2017-12-13 11:26:25 +00:00
parent 4e3de8d3ac
commit a63f658108
25 changed files with 6323 additions and 6560 deletions
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297
src/devices/cpu/m68000/m68000.h
View File

@ -10,43 +10,30 @@
#define softfloat_h 1
#include "softfloat/milieu.h"
#include "softfloat/softfloat.h"
extern flag floatx80_is_nan(floatx80 a);
#endif
/* MMU constants */
#define MMU_ATC_ENTRIES (22) // 68851 has 64, 030 has 22
constexpr int MMU_ATC_ENTRIES = (22); // 68851 has 64, 030 has 22
/* instruction cache constants */
#define M68K_IC_SIZE 128
#define m68ki_check_address_error(m68k, ADDR, WRITE_MODE, FC) \
if((ADDR)&1) \
{ \
m68k->aerr_address = ADDR; \
m68k->aerr_write_mode = WRITE_MODE; \
m68k->aerr_fc = FC; \
throw 10; \
}
constexpr int M68K_IC_SIZE = 128;
/* There are 7 levels of interrupt to the 68K.
* A transition from < 7 to 7 will cause a non-maskable interrupt (NMI).
*/
#define M68K_IRQ_NONE 0
#define M68K_IRQ_1 1
#define M68K_IRQ_2 2
#define M68K_IRQ_3 3
#define M68K_IRQ_4 4
#define M68K_IRQ_5 5
#define M68K_IRQ_6 6
#define M68K_IRQ_7 7
constexpr int M68K_IRQ_NONE = 0;
constexpr int M68K_IRQ_1 = 1;
constexpr int M68K_IRQ_2 = 2;
constexpr int M68K_IRQ_3 = 3;
constexpr int M68K_IRQ_4 = 4;
constexpr int M68K_IRQ_5 = 5;
constexpr int M68K_IRQ_6 = 6;
constexpr int M68K_IRQ_7 = 7;
// special input lines
#define M68K_LINE_BUSERROR 16
constexpr int M68K_LINE_BUSERROR = 16;
/* CPU types for use in m68k_set_cpu_type() */
enum
@ -78,9 +65,9 @@ enum
};
/* HMMU enable types for use with m68k_set_hmmu_enable() */
#define M68K_HMMU_DISABLE 0 /* no translation */
#define M68K_HMMU_ENABLE_II 1 /* Mac II style fixed translation */
#define M68K_HMMU_ENABLE_LC 2 /* Mac LC style fixed translation */
constexpr int M68K_HMMU_DISABLE = 0; /* no translation */
constexpr int M68K_HMMU_ENABLE_II = 1; /* Mac II style fixed translation */
constexpr int M68K_HMMU_ENABLE_LC = 2; /* Mac LC style fixed translation */
/* Special interrupt acknowledge values.
* Use these as special returns from the interrupt acknowledge callback
@ -91,30 +78,25 @@ enum
* This happens in a real 68K if VPA or AVEC is asserted during an interrupt
* acknowledge cycle instead of DTACK.
*/
#define M68K_INT_ACK_AUTOVECTOR 0xffffffff
constexpr uint32_t M68K_INT_ACK_AUTOVECTOR = 0xffffffff;
/* Causes the spurious interrupt vector (0x18) to be taken
* This happens in a real 68K if BERR is asserted during the interrupt
* acknowledge cycle (i.e. no devices responded to the acknowledge).
*/
#define M68K_INT_ACK_SPURIOUS 0xfffffffe
constexpr uint32_t M68K_INT_ACK_SPURIOUS = 0xfffffffe;
enum
{
/* NOTE: M68K_SP fetches the current SP, be it USP, ISP, or MSP */
M68K_PC = STATE_GENPC, M68K_SP = 1, M68K_ISP, M68K_USP, M68K_MSP, M68K_SR, M68K_VBR,
M68K_SFC, M68K_DFC, M68K_CACR, M68K_CAAR, M68K_PREF_ADDR, M68K_PREF_DATA,
M68K_SFC, M68K_DFC, M68K_CACR, M68K_CAAR, M68K_IR, M68K_PREF_ADDR, M68K_PREF_DATA,
M68K_D0, M68K_D1, M68K_D2, M68K_D3, M68K_D4, M68K_D5, M68K_D6, M68K_D7,
M68K_A0, M68K_A1, M68K_A2, M68K_A3, M68K_A4, M68K_A5, M68K_A6, M68K_A7,
M68K_FP0, M68K_FP1, M68K_FP2, M68K_FP3, M68K_FP4, M68K_FP5, M68K_FP6, M68K_FP7,
M68K_FPSR, M68K_FPCR
};
class m68000_base_device;
extern const device_type M68K;
class m68000_base_device : public cpu_device
{
public:
@ -122,6 +104,7 @@ public:
// construction/destruction
m68000_base_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock);
protected:
void presave();
void postload();
@ -150,6 +133,7 @@ public:
void define_state(void);
public:
void set_reset_callback(write_line_delegate callback);
void set_cmpild_callback(write32_delegate callback);
void set_rte_callback(write_line_delegate callback);
@ -157,8 +141,6 @@ public:
uint16_t get_fc();
void set_hmmu_enable(int enable);
void set_fpu_enable(int enable);
int get_fpu_enable();
void set_instruction_hook(read32_delegate ihook);
void set_buserror_details(uint32_t fault_addr, uint8_t rw, uint8_t fc);
protected:
@ -168,91 +150,89 @@ protected:
m68000_base_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock,
const device_type type, uint32_t prg_data_width, uint32_t prg_address_bits, address_map_constructor internal_map);
private:
int has_fpu; /* Indicates if a FPU is available (yes on 030, 040, may be on 020) */
public:
int m_has_fpu; /* Indicates if a FPU is available (yes on 030, 040, may be on 020) */
uint32_t cpu_type; /* CPU Type: 68000, 68008, 68010, 68EC020, 68020, 68EC030, 68030, 68EC040, or 68040 */
// uint32_t dasm_type; /* disassembly type */
uint32_t dar[16]; /* Data and Address Registers */
uint32_t ppc; /* Previous program counter */
uint32_t pc; /* Program Counter */
uint32_t sp[7]; /* User, Interrupt, and Master Stack Pointers */
uint32_t vbr; /* Vector Base Register (m68010+) */
uint32_t sfc; /* Source Function Code Register (m68010+) */
uint32_t dfc; /* Destination Function Code Register (m68010+) */
uint32_t cacr; /* Cache Control Register (m68020, unemulated) */
uint32_t caar; /* Cache Address Register (m68020, unemulated) */
uint32_t ir; /* Instruction Register */
floatx80 fpr[8]; /* FPU Data Register (m68030/040) */
uint32_t fpiar; /* FPU Instruction Address Register (m68040) */
uint32_t fpsr; /* FPU Status Register (m68040) */
uint32_t fpcr; /* FPU Control Register (m68040) */
uint32_t t1_flag; /* Trace 1 */
uint32_t t0_flag; /* Trace 0 */
uint32_t s_flag; /* Supervisor */
uint32_t m_flag; /* Master/Interrupt state */
uint32_t x_flag; /* Extend */
uint32_t n_flag; /* Negative */
uint32_t not_z_flag; /* Zero, inverted for speedups */
uint32_t v_flag; /* Overflow */
uint32_t c_flag; /* Carry */
uint32_t int_mask; /* I0-I2 */
uint32_t int_level; /* State of interrupt pins IPL0-IPL2 -- ASG: changed from ints_pending */
uint32_t stopped; /* Stopped state */
uint32_t pref_addr; /* Last prefetch address */
uint32_t pref_data; /* Data in the prefetch queue */
uint32_t sr_mask; /* Implemented status register bits */
uint32_t instr_mode; /* Stores whether we are in instruction mode or group 0/1 exception mode */
uint32_t run_mode; /* Stores whether we are processing a reset, bus error, address error, or something else */
int has_pmmu; /* Indicates if a PMMU available (yes on 030, 040, no on EC030) */
int has_hmmu; /* Indicates if an Apple HMMU is available in place of the 68851 (020 only) */
int pmmu_enabled; /* Indicates if the PMMU is enabled */
int hmmu_enabled; /* Indicates if the HMMU is enabled */
int fpu_just_reset; /* Indicates the FPU was just reset */
uint32_t m_cpu_type; /* CPU Type: 68000, 68008, 68010, 68EC020, 68020, 68EC030, 68030, 68EC040, or 68040 */
//
uint32_t m_dar[16]; /* Data and Address Registers */
uint32_t m_ppc; /* Previous program counter */
uint32_t m_pc; /* Program Counter */
uint32_t m_sp[7]; /* User, Interrupt, and Master Stack Pointers */
uint32_t m_vbr; /* Vector Base Register (m68010+) */
uint32_t m_sfc; /* Source Function Code Register (m68010+) */
uint32_t m_dfc; /* Destination Function Code Register (m68010+) */
uint32_t m_cacr; /* Cache Control Register (m68020, unemulated) */
uint32_t m_caar; /* Cache Address Register (m68020, unemulated) */
uint32_t m_ir; /* Instruction Register */
floatx80 m_fpr[8]; /* FPU Data Register (m68030/040) */
uint32_t m_fpiar; /* FPU Instruction Address Register (m68040) */
uint32_t m_fpsr; /* FPU Status Register (m68040) */
uint32_t m_fpcr; /* FPU Control Register (m68040) */
uint32_t m_t1_flag; /* Trace 1 */
uint32_t m_t0_flag; /* Trace 0 */
uint32_t m_s_flag; /* Supervisor */
uint32_t m_m_flag; /* Master/Interrupt state */
uint32_t m_x_flag; /* Extend */
uint32_t m_n_flag; /* Negative */
uint32_t m_not_z_flag; /* Zero, inverted for speedups */
uint32_t m_v_flag; /* Overflow */
uint32_t m_c_flag; /* Carry */
uint32_t m_int_mask; /* I0-I2 */
uint32_t m_int_level; /* State of interrupt pins IPL0-IPL2 -- ASG: changed from ints_pending */
uint32_t m_stopped; /* Stopped state */
uint32_t m_pref_addr; /* Last prefetch address */
uint32_t m_pref_data; /* Data in the prefetch queue */
uint32_t m_sr_mask; /* Implemented status register bits */
uint32_t m_instr_mode; /* Stores whether we are in instruction mode or group 0/1 exception mode */
uint32_t m_run_mode; /* Stores whether we are processing a reset, bus error, address error, or something else */
int m_has_pmmu; /* Indicates if a PMMU available (yes on 030, 040, no on EC030) */
int m_has_hmmu; /* Indicates if an Apple HMMU is available in place of the 68851 (020 only) */
int m_pmmu_enabled; /* Indicates if the PMMU is enabled */
int m_hmmu_enabled; /* Indicates if the HMMU is enabled */
int m_fpu_just_reset; /* Indicates the FPU was just reset */
/* Clocks required for instructions / exceptions */
uint32_t cyc_bcc_notake_b;
uint32_t cyc_bcc_notake_w;
uint32_t cyc_dbcc_f_noexp;
uint32_t cyc_dbcc_f_exp;
uint32_t cyc_scc_r_true;
uint32_t cyc_movem_w;
uint32_t cyc_movem_l;
uint32_t cyc_shift;
uint32_t cyc_reset;
uint32_t m_cyc_bcc_notake_b;
uint32_t m_cyc_bcc_notake_w;
uint32_t m_cyc_dbcc_f_noexp;
uint32_t m_cyc_dbcc_f_exp;
uint32_t m_cyc_scc_r_true;
uint32_t m_cyc_movem_w;
uint32_t m_cyc_movem_l;
uint32_t m_cyc_shift;
uint32_t m_cyc_reset;
int initial_cycles;
int remaining_cycles; /* Number of clocks remaining */
int reset_cycles;
uint32_t tracing;
int m_initial_cycles;
int m_remaining_cycles; /* Number of clocks remaining */
int m_reset_cycles;
uint32_t m_tracing;
int m_address_error;
uint32_t aerr_address;
uint32_t aerr_write_mode;
uint32_t aerr_fc;
uint32_t m_aerr_address;
uint32_t m_aerr_write_mode;
uint32_t m_aerr_fc;
/* Virtual IRQ lines state */
uint32_t virq_state;
uint32_t nmi_pending;
uint32_t m_virq_state;
uint32_t m_nmi_pending;
void (**jump_table)(m68000_base_device *m68k);
const uint8_t* cyc_instruction;
const uint8_t* cyc_exception;
void (m68000_base_device::**m_jump_table)();
const uint8_t* m_cyc_instruction;
const uint8_t* m_cyc_exception;
/* Callbacks to host */
device_irq_acknowledge_delegate int_ack_callback; /* Interrupt Acknowledge */
write32_delegate bkpt_ack_callback; /* Breakpoint Acknowledge */
write_line_delegate reset_instr_callback; /* Called when a RESET instruction is encountered */
write32_delegate cmpild_instr_callback; /* Called when a CMPI.L #v, Dn instruction is encountered */
write_line_delegate rte_instr_callback; /* Called when a RTE instruction is encountered */
write8_delegate tas_write_callback; /* Called instead of normal write8 by the TAS instruction,
device_irq_acknowledge_delegate m_int_ack_callback; /* Interrupt Acknowledge */
write32_delegate m_bkpt_ack_callback; /* Breakpoint Acknowledge */
write_line_delegate m_reset_instr_callback; /* Called when a RESET instruction is encountered */
write32_delegate m_cmpild_instr_callback; /* Called when a CMPI.L #v, Dn instruction is encountered */
write_line_delegate m_rte_instr_callback; /* Called when a RTE instruction is encountered */
write8_delegate m_tas_write_callback; /* Called instead of normal write8 by the TAS instruction,
allowing writeback to be disabled globally or selectively
or other side effects to be implemented */
address_space *program, *oprogram;
address_space *m_program, *m_oprogram;
/* Redirect memory calls */
@ -264,25 +244,21 @@ public:
typedef delegate<void (offs_t, uint16_t)> m68k_write16_delegate;
typedef delegate<void (offs_t, uint32_t)> m68k_write32_delegate;
// class m68k_memory_interface
// {
public:
void init8(address_space &space, address_space &ospace);
void init16(address_space &space, address_space &ospace);
void init32(address_space &space, address_space &ospace);
void init32mmu(address_space &space, address_space &ospace);
void init32hmmu(address_space &space, address_space &ospace);
offs_t opcode_xor; // Address Calculation
m68k_readimm16_delegate readimm16; // Immediate read 16 bit
m68k_read8_delegate read8;
m68k_read16_delegate read16;
m68k_read32_delegate read32;
m68k_write8_delegate write8;
m68k_write16_delegate write16;
m68k_write32_delegate write32;
offs_t m_opcode_xor; // Address Calculation
m68k_readimm16_delegate m_readimm16; // Immediate read 16 bit
m68k_read8_delegate m_read8;
m68k_read16_delegate m_read16;
m68k_read32_delegate m_read32;
m68k_write8_delegate m_write8;
m68k_write16_delegate m_write16;
m68k_write32_delegate m_write32;
private:
uint16_t m68008_read_immediate_16(offs_t address);
uint16_t read_immediate_16(offs_t address);
uint16_t simple_read_immediate_16(offs_t address);
@ -305,57 +281,47 @@ public:
uint32_t readlong_d32_hmmu(offs_t address);
void writelong_d32_hmmu(offs_t address, uint32_t data);
// m68000_base_device *m_cpustate;
// };
public:
// m68k_memory_interface memory;
address_space *m_space, *m_ospace;
direct_read_data<0> *m_direct, *m_odirect;
uint32_t iotemp;
uint32_t m_iotemp;
/* save state data */
uint16_t save_sr;
uint8_t save_stopped;
uint8_t save_halted;
uint16_t m_save_sr;
uint8_t m_save_stopped;
uint8_t m_save_halted;
/* PMMU registers */
uint32_t mmu_crp_aptr, mmu_crp_limit;
uint32_t mmu_srp_aptr, mmu_srp_limit;
uint32_t mmu_urp_aptr; /* 040 only */
uint32_t mmu_tc;
uint16_t mmu_sr;
uint32_t mmu_sr_040;
uint32_t mmu_atc_tag[MMU_ATC_ENTRIES], mmu_atc_data[MMU_ATC_ENTRIES];
uint32_t mmu_atc_rr;
uint32_t mmu_tt0, mmu_tt1;
uint32_t mmu_itt0, mmu_itt1, mmu_dtt0, mmu_dtt1;
uint32_t mmu_acr0, mmu_acr1, mmu_acr2, mmu_acr3;
uint32_t mmu_last_page_entry, mmu_last_page_entry_addr;
uint32_t m_mmu_crp_aptr, m_mmu_crp_limit;
uint32_t m_mmu_srp_aptr, m_mmu_srp_limit;
uint32_t m_mmu_urp_aptr; /* 040 only */
uint32_t m_mmu_tc;
uint16_t m_mmu_sr;
uint32_t m_mmu_sr_040;
uint32_t m_mmu_atc_tag[MMU_ATC_ENTRIES], m_mmu_atc_data[MMU_ATC_ENTRIES];
uint32_t m_mmu_atc_rr;
uint32_t m_mmu_tt0, m_mmu_tt1;
uint32_t m_mmu_itt0, m_mmu_itt1, m_mmu_dtt0, m_mmu_dtt1;
uint32_t m_mmu_acr0, m_mmu_acr1, m_mmu_acr2, m_mmu_acr3;
uint32_t m_mmu_last_page_entry, m_mmu_last_page_entry_addr;
uint16_t mmu_tmp_sr; /* temporary hack: status code for ptest and to handle write protection */
uint16_t mmu_tmp_fc; /* temporary hack: function code for the mmu (moves) */
uint16_t mmu_tmp_rw; /* temporary hack: read/write (1/0) for the mmu */
uint32_t mmu_tmp_buserror_address; /* temporary hack: (first) bus error address */
uint16_t mmu_tmp_buserror_occurred; /* temporary hack: flag that bus error has occurred from mmu */
uint16_t mmu_tmp_buserror_fc; /* temporary hack: (first) bus error fc */
uint16_t mmu_tmp_buserror_rw; /* temporary hack: (first) bus error rw */
uint16_t m_mmu_tmp_sr; /* temporary hack: status code for ptest and to handle write protection */
uint16_t m_mmu_tmp_fc; /* temporary hack: function code for the mmu (moves) */
uint16_t m_mmu_tmp_rw; /* temporary hack: read/write (1/0) for the mmu */
uint32_t m_mmu_tmp_buserror_address; /* temporary hack: (first) bus error address */
uint16_t m_mmu_tmp_buserror_occurred; /* temporary hack: flag that bus error has occurred from mmu */
uint16_t m_mmu_tmp_buserror_fc; /* temporary hack: (first) bus error fc */
uint16_t m_mmu_tmp_buserror_rw; /* temporary hack: (first) bus error rw */
uint32_t ic_address[M68K_IC_SIZE]; /* instruction cache address data */
uint32_t ic_data[M68K_IC_SIZE]; /* instruction cache content data */
bool ic_valid[M68K_IC_SIZE]; /* instruction cache valid flags */
uint32_t m_ic_address[M68K_IC_SIZE]; /* instruction cache address data */
uint32_t m_ic_data[M68K_IC_SIZE]; /* instruction cache content data */
bool m_ic_valid[M68K_IC_SIZE]; /* instruction cache valid flags */
/* 68307 / 68340 internal address map */
address_space *internal;
/* external instruction hook (does not depend on debug mode) */
read32_delegate instruction_hook;
address_space *m_internal;
@ -378,10 +344,18 @@ public:
void init_cpu_coldfire(void);
void m68ki_exception_interrupt(m68000_base_device *m68k, uint32_t int_level);
void m68ki_exception_interrupt(uint32_t int_level);
void reset_cpu(void);
inline void cpu_execute(void);
inline void m68ki_check_address_error(uint32_t ADDR, uint32_t WRITE_MODE, uint32_t FC)
{
if((ADDR)&1)
{
m_aerr_address = ADDR;
m_aerr_write_mode = WRITE_MODE;
m_aerr_fc = FC;
throw 10;
}
}
// device_state_interface overrides
virtual void state_import(const device_state_entry &entry) override;
@ -390,6 +364,11 @@ public:
// device_memory_interface overrides
virtual bool memory_translate(int space, int intention, offs_t &address) override;
#include "m68kcpu.h"
#include "m68kops.h"
#include "m68kfpu.hxx"
#include "m68kmmu.h"
};

7563
src/devices/cpu/m68000/m68k_in.cpp
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File diff suppressed because it is too large Load Diff

1360
src/devices/cpu/m68000/m68kcpu.cpp
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File diff suppressed because it is too large Load Diff

1560
src/devices/cpu/m68000/m68kcpu.h
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File diff suppressed because it is too large Load Diff

1073
src/devices/cpu/m68000/m68kfpu.hxx
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File diff suppressed because it is too large Load Diff

25
src/devices/cpu/m68000/m68kmake.cpp
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@ -789,8 +789,8 @@ static void get_base_name(char* base_name, opcode_struct* op)
/* Write the name of an opcode handler function */
static void write_function_name(FILE* filep, char* base_name)
{
fprintf(filep, "void m68000_base_device_ops::%s(m68000_base_device* mc68kcpu)\n", base_name);
fprintf(g_prototype_file, "static void %s(m68000_base_device* mc68kcpu);\n", base_name);
fprintf(filep, "void m68000_base_device::%s()\n", base_name);
fprintf(g_prototype_file, "void %s();\n", base_name);
}
static void add_opcode_output_table_entry(opcode_struct* op, char* name)
@ -803,7 +803,7 @@ static void add_opcode_output_table_entry(opcode_struct* op, char* name)
*ptr = *op;
sprintf( ptr->name, "m68000_base_device_ops::%s", name);
sprintf( ptr->name, "&m68000_base_device::%s", name);
ptr->bits = num_bits(ptr->op_mask);
}
@ -880,17 +880,17 @@ static void generate_opcode_handler(FILE* filep, body_struct* body, replace_stru
/* Add any replace strings needed */
if(ea_mode != EA_MODE_NONE)
{
sprintf(str, "EA_%s_8(mc68kcpu)", g_ea_info_table[ea_mode].ea_add);
sprintf(str, "EA_%s_8()", g_ea_info_table[ea_mode].ea_add);
add_replace_string(replace, ID_OPHANDLER_EA_AY_8, str);
sprintf(str, "EA_%s_16(mc68kcpu)", g_ea_info_table[ea_mode].ea_add);
sprintf(str, "EA_%s_16()", g_ea_info_table[ea_mode].ea_add);
add_replace_string(replace, ID_OPHANDLER_EA_AY_16, str);
sprintf(str, "EA_%s_32(mc68kcpu)", g_ea_info_table[ea_mode].ea_add);
sprintf(str, "EA_%s_32()", g_ea_info_table[ea_mode].ea_add);
add_replace_string(replace, ID_OPHANDLER_EA_AY_32, str);
sprintf(str, "OPER_%s_8(mc68kcpu)", g_ea_info_table[ea_mode].ea_add);
sprintf(str, "OPER_%s_8()", g_ea_info_table[ea_mode].ea_add);
add_replace_string(replace, ID_OPHANDLER_OPER_AY_8, str);
sprintf(str, "OPER_%s_16(mc68kcpu)", g_ea_info_table[ea_mode].ea_add);
sprintf(str, "OPER_%s_16()", g_ea_info_table[ea_mode].ea_add);
add_replace_string(replace, ID_OPHANDLER_OPER_AY_16, str);
sprintf(str, "OPER_%s_32(mc68kcpu)", g_ea_info_table[ea_mode].ea_add);
sprintf(str, "OPER_%s_32()", g_ea_info_table[ea_mode].ea_add);
add_replace_string(replace, ID_OPHANDLER_OPER_AY_32, str);
}
@ -972,8 +972,8 @@ static void generate_opcode_cc_variants(FILE* filep, body_struct* body, replace_
for(i=2;i<16;i++)
{
/* Add replace strings for this condition code */
sprintf(repl, "COND_%s(mc68kcpu)", g_cc_table[i][1]);
sprintf(replnot, "COND_NOT_%s(mc68kcpu)", g_cc_table[i][1]);
sprintf(repl, "COND_%s()", g_cc_table[i][1]);
sprintf(replnot, "COND_NOT_%s()", g_cc_table[i][1]);
add_replace_string(replace, ID_OPHANDLER_CC, repl);
add_replace_string(replace, ID_OPHANDLER_NOT_CC, replnot);
@ -1358,9 +1358,7 @@ int main(int argc, char *argv[])
error_exit("Duplicate opcode handler section");
fprintf(g_table_file, "%s\n\n", ophandler_header_insert);
fprintf(g_prototype_file, "#ifdef OPCODE_PROTOTYPES\n\n");
process_opcode_handlers(g_table_file);
fprintf(g_prototype_file, "#else\n");
fprintf(g_table_file, "%s\n\n", ophandler_footer_insert);
ophandler_body_read = 1;
@ -1390,7 +1388,6 @@ int main(int argc, char *argv[])
fprintf(g_table_file, "%s\n\n", table_footer_insert);
fprintf(g_prototype_file, "%s\n\n", prototype_footer_insert);
fprintf(g_prototype_file, "#endif\n");
break;
}

534
src/devices/cpu/m68000/m68kmmu.h
View File

File diff suppressed because it is too large Load Diff

178
src/devices/machine/68307.cpp
View File

@ -23,17 +23,13 @@ DEFINE_DEVICE_TYPE(M68307, m68307_cpu_device, "mc68307", "MC68307")
*/
READ8_MEMBER( m68307_cpu_device::m68307_internal_serial_r )
{
m68307_cpu_device *m68k = this;
if (offset&1) return m_duart->read(*m68k->program, offset>>1);
if (offset&1) return m_duart->read(*m_program, offset>>1);
return 0x0000;
}
WRITE8_MEMBER(m68307_cpu_device::m68307_internal_serial_w)
{
m68307_cpu_device *m68k = this;
if (offset & 1) m_duart->write(*m68k->program, offset >> 1, data);
if (offset & 1) m_duart->write(*m_program, offset >> 1, data);
}
@ -55,20 +51,20 @@ MACHINE_CONFIG_END
m68307_cpu_device::m68307_cpu_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock)
: m68000_device(mconfig, tag, owner, clock, M68307, 16, 24, ADDRESS_MAP_NAME(m68307_internal_map)),
write_irq(*this),
write_a_tx(*this),
write_b_tx(*this),
read_inport(*this),
write_outport(*this),
m_write_irq(*this),
m_write_a_tx(*this),
m_write_b_tx(*this),
m_read_inport(*this),
m_write_outport(*this),
m_duart(*this, "internal68681")
{
m68307SIM = nullptr;
m68307MBUS = nullptr;
m68307TIMER = nullptr;
m68307_base = 0;
m68307_scrhigh = 0;
m68307_scrlow = 0;
m68307_currentcs = 0;
m_m68307SIM = nullptr;
m_m68307MBUS = nullptr;
m_m68307TIMER = nullptr;
m_m68307_base = 0;
m_m68307_scrhigh = 0;
m_m68307_scrlow = 0;
m_m68307_currentcs = 0;
}
@ -80,13 +76,13 @@ void m68307_cpu_device::device_reset()
{
m68000_device::device_reset();
if (m68307SIM) m68307SIM->reset();
if (m68307MBUS) m68307MBUS->reset();
if (m68307TIMER) m68307TIMER->reset();
if (m_m68307SIM) m_m68307SIM->reset();
if (m_m68307MBUS) m_m68307MBUS->reset();
if (m_m68307TIMER) m_m68307TIMER->reset();
m68307_base = 0xbfff;
m68307_scrhigh = 0x0007;
m68307_scrlow = 0xf010;
m_m68307_base = 0xbfff;
m_m68307_scrhigh = 0x0007;
m_m68307_scrlow = 0xf010;
}
@ -97,7 +93,7 @@ void m68307_cpu_device::device_reset()
inline int m68307_cpu_device::calc_cs(offs_t address) const
{
m68307_sim const &sim = *m68307SIM;
m68307_sim const &sim = *m_m68307SIM;
for (int i=0; i < 4; i++)
{
int const br = sim.m_br[i] & 1;
@ -112,43 +108,43 @@ inline int m68307_cpu_device::calc_cs(offs_t address) const
uint16_t m68307_cpu_device::simple_read_immediate_16_m68307(offs_t address)
{
// m68307_currentcs = calc_cs(address);
// m_m68307_currentcs = calc_cs(address);
return m_direct->read_word(address);
}
uint8_t m68307_cpu_device::read_byte_m68307(offs_t address)
{
// m68307_currentcs = calc_cs(address);
// m_m68307_currentcs = calc_cs(address);
return m_space->read_byte(address);
}
uint16_t m68307_cpu_device::read_word_m68307(offs_t address)
{
// m68307_currentcs = calc_cs(address);
// m_m68307_currentcs = calc_cs(address);
return m_space->read_word(address);
}
uint32_t m68307_cpu_device::read_dword_m68307(offs_t address)
{
// m68307_currentcs = calc_cs(address);
// m_m68307_currentcs = calc_cs(address);
return m_space->read_dword(address);
}
void m68307_cpu_device::write_byte_m68307(offs_t address, uint8_t data)
{
// m68307_currentcs = calc_cs(address);
// m_m68307_currentcs = calc_cs(address);
m_space->write_byte(address, data);
}
void m68307_cpu_device::write_word_m68307(offs_t address, uint16_t data)
{
// m68307_currentcs = calc_cs(address);
// m_m68307_currentcs = calc_cs(address);
m_space->write_word(address, data);
}
void m68307_cpu_device::write_dword_m68307(offs_t address, uint32_t data)
{
// m68307_currentcs = calc_cs(address);
// m_m68307_currentcs = calc_cs(address);
m_space->write_dword(address, data);
}
@ -159,15 +155,15 @@ void m68307_cpu_device::init16_m68307(address_space &space)
{
m_space = &space;
m_direct = space.direct<0>();
opcode_xor = 0;
m_opcode_xor = 0;
readimm16 = m68k_readimm16_delegate(&m68307_cpu_device::simple_read_immediate_16_m68307, this);
read8 = m68k_read8_delegate(&m68307_cpu_device::read_byte_m68307, this);
read16 = m68k_read16_delegate(&m68307_cpu_device::read_word_m68307, this);
read32 = m68k_read32_delegate(&m68307_cpu_device::read_dword_m68307, this);
write8 = m68k_write8_delegate(&m68307_cpu_device::write_byte_m68307, this);
write16 = m68k_write16_delegate(&m68307_cpu_device::write_word_m68307, this);
write32 = m68k_write32_delegate(&m68307_cpu_device::write_dword_m68307, this);
m_readimm16 = m68k_readimm16_delegate(&m68307_cpu_device::simple_read_immediate_16_m68307, this);
m_read8 = m68k_read8_delegate(&m68307_cpu_device::read_byte_m68307, this);
m_read16 = m68k_read16_delegate(&m68307_cpu_device::read_word_m68307, this);
m_read32 = m68k_read32_delegate(&m68307_cpu_device::read_dword_m68307, this);
m_write8 = m68k_write8_delegate(&m68307_cpu_device::write_byte_m68307, this);
m_write16 = m68k_write16_delegate(&m68307_cpu_device::write_word_m68307, this);
m_write32 = m68k_write32_delegate(&m68307_cpu_device::write_dword_m68307, this);
}
@ -190,9 +186,9 @@ void m68307_cpu_device::set_port_callbacks(
uint16_t m68307_cpu_device::get_cs(offs_t address)
{
m68307_currentcs = calc_cs(address);
m_m68307_currentcs = calc_cs(address);
return m68307_currentcs;
return m_m68307_currentcs;
}
@ -205,22 +201,22 @@ void m68307_cpu_device::set_interrupt(int level, int vector)
void m68307_cpu_device::timer0_interrupt()
{
int prioritylevel = (m68307SIM->m_picr & 0x7000)>>12;
int vector = (m68307SIM->m_pivr & 0x00f0) | 0xa;
int prioritylevel = (m_m68307SIM->m_picr & 0x7000)>>12;
int vector = (m_m68307SIM->m_pivr & 0x00f0) | 0xa;
set_interrupt(prioritylevel, vector);
}
void m68307_cpu_device::timer1_interrupt()
{
int prioritylevel = (m68307SIM->m_picr & 0x0700)>>8;
int vector = (m68307SIM->m_pivr & 0x00f0) | 0xb;
int prioritylevel = (m_m68307SIM->m_picr & 0x0700)>>8;
int vector = (m_m68307SIM->m_pivr & 0x00f0) | 0xb;
set_interrupt(prioritylevel, vector);
}
void m68307_cpu_device::serial_interrupt(int vector)
{
int prioritylevel = (m68307SIM->m_picr & 0x0070)>>4;
int prioritylevel = (m_m68307SIM->m_picr & 0x0070)>>4;
set_interrupt(prioritylevel, vector);
}
@ -234,16 +230,16 @@ WRITE_LINE_MEMBER(m68307_cpu_device::m68307_duart_irq_handler)
void m68307_cpu_device::mbus_interrupt()
{
int prioritylevel = (m68307SIM->m_picr & 0x0007)>>0;
int vector = (m68307SIM->m_pivr & 0x00f0) | 0xd;
int prioritylevel = (m_m68307SIM->m_picr & 0x0007)>>0;
int vector = (m_m68307SIM->m_pivr & 0x00f0) | 0xd;
set_interrupt(prioritylevel, vector);
}
void m68307_cpu_device::licr2_interrupt()
{
int prioritylevel = (m68307SIM->m_licr2 & 0x0007)>>0;
int vector = (m68307SIM->m_pivr & 0x00f0) | 0x9;
m68307SIM->m_licr2 |= 0x8;
int prioritylevel = (m_m68307SIM->m_licr2 & 0x0007)>>0;
int vector = (m_m68307SIM->m_pivr & 0x00f0) | 0x9;
m_m68307SIM->m_licr2 |= 0x8;
set_interrupt(prioritylevel, vector);
@ -257,28 +253,28 @@ void m68307_cpu_device::device_start()
set via remappable register
*/
init16_m68307(*program);
init16_m68307(*m_program);
m68307SIM = new m68307_sim();
m68307MBUS = new m68307_mbus();
m68307TIMER = new m68307_timer();
m_m68307SIM = new m68307_sim();
m_m68307MBUS = new m68307_mbus();
m_m68307TIMER = new m68307_timer();
m68307TIMER->init(this);
m_m68307TIMER->init(this);
m68307SIM->reset();
m68307MBUS->reset();
m68307TIMER->reset();
m_m68307SIM->reset();
m_m68307MBUS->reset();
m_m68307TIMER->reset();
internal = &this->space(AS_PROGRAM);
m68307_base = 0xbfff;
m68307_scrhigh = 0x0007;
m68307_scrlow = 0xf010;
m_internal = &space(AS_PROGRAM);
m_m68307_base = 0xbfff;
m_m68307_scrhigh = 0x0007;
m_m68307_scrlow = 0xf010;
write_irq.resolve_safe();
write_a_tx.resolve_safe();
write_b_tx.resolve_safe();
read_inport.resolve();
write_outport.resolve_safe();
m_write_irq.resolve_safe();
m_write_a_tx.resolve_safe();
m_write_b_tx.resolve_safe();
m_read_inport.resolve();
m_write_outport.resolve_safe();
set_port_callbacks(porta_read_delegate(), porta_write_delegate(), portb_read_delegate(), portb_write_delegate());
}
@ -287,16 +283,14 @@ void m68307_cpu_device::device_start()
READ16_MEMBER( m68307_cpu_device::m68307_internal_base_r )
{
m68307_cpu_device *m68k = this;
int pc = space.device().safe_pc();
logerror("%08x m68307_internal_base_r %08x, (%04x)\n", pc, offset*2,mem_mask);
switch (offset<<1)
{
case 0x2: return m68k->m68307_base;
case 0x4: return m68k->m68307_scrhigh;
case 0x6: return m68k->m68307_scrlow;
case 0x2: return m_m68307_base;
case 0x4: return m_m68307_scrhigh;
case 0x6: return m_m68307_scrlow;
}
logerror("(read was illegal?)\n");
@ -306,8 +300,6 @@ READ16_MEMBER( m68307_cpu_device::m68307_internal_base_r )
WRITE16_MEMBER( m68307_cpu_device::m68307_internal_base_w )
{
m68307_cpu_device *m68k = this;
int pc = space.device().safe_pc();
logerror("%08x m68307_internal_base_w %08x, %04x (%04x)\n", pc, offset*2,data,mem_mask);
int base;
@ -317,35 +309,35 @@ WRITE16_MEMBER( m68307_cpu_device::m68307_internal_base_w )
{
case 0x2:
/* remove old internal handler */
base = (m68k->m68307_base & 0x0fff) << 12;
//mask = (m68k->m68307_base & 0xe000) >> 13;
//if ( m68k->m68307_base & 0x1000 ) mask |= 7;
m68k->internal->unmap_readwrite(base+0x000, base+0x04f);
m68k->internal->unmap_readwrite(base+0x100, base+0x11f);
m68k->internal->unmap_readwrite(base+0x120, base+0x13f);
m68k->internal->unmap_readwrite(base+0x140, base+0x149);
base = (m_m68307_base & 0x0fff) << 12;
//mask = (m_m68307_base & 0xe000) >> 13;
//if ( m_m68307_base & 0x1000 ) mask |= 7;
m_internal->unmap_readwrite(base+0x000, base+0x04f);
m_internal->unmap_readwrite(base+0x100, base+0x11f);
m_internal->unmap_readwrite(base+0x120, base+0x13f);
m_internal->unmap_readwrite(base+0x140, base+0x149);
/* store new base address */
COMBINE_DATA(&m68k->m68307_base);
COMBINE_DATA(&m_m68307_base);
/* install new internal handler */
base = (m68k->m68307_base & 0x0fff) << 12;
//mask = (m68k->m68307_base & 0xe000) >> 13;
//if ( m68k->m68307_base & 0x1000 ) mask |= 7;
m68k->internal->install_readwrite_handler(base + 0x000, base + 0x04f, read16_delegate(FUNC(m68307_cpu_device::m68307_internal_sim_r),this), write16_delegate(FUNC(m68307_cpu_device::m68307_internal_sim_w),this));
m68k->internal->install_readwrite_handler(base + 0x100, base + 0x11f, read8_delegate(FUNC(m68307_cpu_device::m68307_internal_serial_r),this), write8_delegate(FUNC(m68307_cpu_device::m68307_internal_serial_w),this), 0xffff);
m68k->internal->install_readwrite_handler(base + 0x120, base + 0x13f, read16_delegate(FUNC(m68307_cpu_device::m68307_internal_timer_r),this), write16_delegate(FUNC(m68307_cpu_device::m68307_internal_timer_w),this));
m68k->internal->install_readwrite_handler(base + 0x140, base + 0x149, read8_delegate(FUNC(m68307_cpu_device::m68307_internal_mbus_r),this), write8_delegate(FUNC(m68307_cpu_device::m68307_internal_mbus_w),this), 0xffff);
base = (m_m68307_base & 0x0fff) << 12;
//mask = (m_m68307_base & 0xe000) >> 13;
//if ( m_m68307_base & 0x1000 ) mask |= 7;
m_internal->install_readwrite_handler(base + 0x000, base + 0x04f, read16_delegate(FUNC(m68307_cpu_device::m68307_internal_sim_r),this), write16_delegate(FUNC(m68307_cpu_device::m68307_internal_sim_w),this));
m_internal->install_readwrite_handler(base + 0x100, base + 0x11f, read8_delegate(FUNC(m68307_cpu_device::m68307_internal_serial_r),this), write8_delegate(FUNC(m68307_cpu_device::m68307_internal_serial_w),this), 0xffff);
m_internal->install_readwrite_handler(base + 0x120, base + 0x13f, read16_delegate(FUNC(m68307_cpu_device::m68307_internal_timer_r),this), write16_delegate(FUNC(m68307_cpu_device::m68307_internal_timer_w),this));
m_internal->install_readwrite_handler(base + 0x140, base + 0x149, read8_delegate(FUNC(m68307_cpu_device::m68307_internal_mbus_r),this), write8_delegate(FUNC(m68307_cpu_device::m68307_internal_mbus_w),this), 0xffff);
break;
case 0x4:
COMBINE_DATA(&m68k->m68307_scrhigh);
COMBINE_DATA(&m_m68307_scrhigh);
break;
case 0x6:
COMBINE_DATA(&m68k->m68307_scrlow);
COMBINE_DATA(&m_m68307_scrlow);
break;
default:

40
src/devices/machine/68307.h
View File

@ -36,11 +36,11 @@ public:
m68307_cpu_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock);
/* trampolines so we can specify the 68681 serial configuration when adding the CPU */
template <class Object> static devcb_base &set_irq_cb(device_t &device, Object &&cb) { return downcast<m68307_cpu_device &>(device).write_irq.set_callback(std::forward<Object>(cb)); }
template <class Object> static devcb_base &set_a_tx_cb(device_t &device, Object &&cb) { return downcast<m68307_cpu_device &>(device).write_a_tx.set_callback(std::forward<Object>(cb)); }
template <class Object> static devcb_base &set_b_tx_cb(device_t &device, Object &&cb) { return downcast<m68307_cpu_device &>(device).write_b_tx.set_callback(std::forward<Object>(cb)); }
template <class Object> static devcb_base &set_inport_cb(device_t &device, Object &&cb) { return downcast<m68307_cpu_device &>(device).read_inport.set_callback(std::forward<Object>(cb)); }
template <class Object> static devcb_base &set_outport_cb(device_t &device, Object &&cb) { return downcast<m68307_cpu_device &>(device).write_outport.set_callback(std::forward<Object>(cb)); }
template <class Object> static devcb_base &set_irq_cb(device_t &device, Object &&cb) { return downcast<m68307_cpu_device &>(device).m_write_irq.set_callback(std::forward<Object>(cb)); }
template <class Object> static devcb_base &set_a_tx_cb(device_t &device, Object &&cb) { return downcast<m68307_cpu_device &>(device).m_write_a_tx.set_callback(std::forward<Object>(cb)); }
template <class Object> static devcb_base &set_b_tx_cb(device_t &device, Object &&cb) { return downcast<m68307_cpu_device &>(device).m_write_b_tx.set_callback(std::forward<Object>(cb)); }
template <class Object> static devcb_base &set_inport_cb(device_t &device, Object &&cb) { return downcast<m68307_cpu_device &>(device).m_read_inport.set_callback(std::forward<Object>(cb)); }
template <class Object> static devcb_base &set_outport_cb(device_t &device, Object &&cb) { return downcast<m68307_cpu_device &>(device).m_write_outport.set_callback(std::forward<Object>(cb)); }
uint16_t simple_read_immediate_16_m68307(offs_t address);
@ -87,30 +87,30 @@ protected:
void mbus_interrupt();
DECLARE_WRITE_LINE_MEMBER(m68307_duart_irq_handler);
DECLARE_WRITE_LINE_MEMBER(m68307_duart_txa) { write_a_tx(state); }
DECLARE_WRITE_LINE_MEMBER(m68307_duart_txb) { write_b_tx(state); }
DECLARE_READ8_MEMBER(m68307_duart_input_r) { return read_inport(); }
DECLARE_WRITE8_MEMBER(m68307_duart_output_w) { write_outport(data); }
DECLARE_WRITE_LINE_MEMBER(m68307_duart_txa) { m_write_a_tx(state); }
DECLARE_WRITE_LINE_MEMBER(m68307_duart_txb) { m_write_b_tx(state); }
DECLARE_READ8_MEMBER(m68307_duart_input_r) { return m_read_inport(); }
DECLARE_WRITE8_MEMBER(m68307_duart_output_w) { m_write_outport(data); }
void init16_m68307(address_space &space);
int calc_cs(offs_t address) const;
devcb_write_line write_irq, write_a_tx, write_b_tx;
devcb_read8 read_inport;
devcb_write8 write_outport;
devcb_write_line m_write_irq, m_write_a_tx, m_write_b_tx;
devcb_read8 m_read_inport;
devcb_write8 m_write_outport;
/* 68307 peripheral modules */
m68307_sim* m68307SIM;
m68307_mbus* m68307MBUS;
// m68307_serial* m68307SERIAL;
m68307_timer* m68307TIMER;
m68307_sim* m_m68307SIM;
m68307_mbus* m_m68307MBUS;
// m68307_serial* m_m68307SERIAL;
m68307_timer* m_m68307TIMER;
uint16_t m68307_base;
uint16_t m68307_scrhigh;
uint16_t m68307_scrlow;
uint16_t m_m68307_base;
uint16_t m_m68307_scrhigh;
uint16_t m_m68307_scrlow;
int m68307_currentcs;
int m_m68307_currentcs;
porta_read_delegate m_porta_r;
porta_write_delegate m_porta_w;

8
src/devices/machine/68307bus.cpp
View File

@ -15,8 +15,8 @@
READ8_MEMBER( m68307_cpu_device::m68307_internal_mbus_r )
{
assert(m68307MBUS);
m68307_mbus &mbus = *m68307MBUS;
assert(m_m68307MBUS);
m68307_mbus &mbus = *m_m68307MBUS;
uint8_t retval;
int pc = space.device().safe_pc();
@ -59,8 +59,8 @@ READ8_MEMBER( m68307_cpu_device::m68307_internal_mbus_r )
WRITE8_MEMBER( m68307_cpu_device::m68307_internal_mbus_w )
{
assert(m68307MBUS);
m68307_mbus &mbus = *m68307MBUS;
assert(m_m68307MBUS);
m68307_mbus &mbus = *m_m68307MBUS;
int pc = space.device().safe_pc();

8
src/devices/machine/68307sim.cpp
View File

@ -32,8 +32,8 @@
READ16_MEMBER( m68307_cpu_device::m68307_internal_sim_r )
{
assert(m68307SIM);
m68307_sim &sim = *m68307SIM;
assert(m_m68307SIM);
m68307_sim &sim = *m_m68307SIM;
int pc = space.device().safe_pc();
@ -64,8 +64,8 @@ READ16_MEMBER( m68307_cpu_device::m68307_internal_sim_r )
WRITE16_MEMBER( m68307_cpu_device::m68307_internal_sim_w )
{
assert(m68307SIM);
m68307_sim &sim = *m68307SIM;
assert(m_m68307SIM);
m68307_sim &sim = *m_m68307SIM;
int pc = space.device().safe_pc();

12
src/devices/machine/68307tmu.cpp
View File

@ -17,8 +17,8 @@
READ16_MEMBER( m68307_cpu_device::m68307_internal_timer_r )
{
assert(m68307TIMER);
m68307_timer &timer = *m68307TIMER;
assert(m_m68307TIMER);
m68307_timer &timer = *m_m68307TIMER;
int pc = space.device().safe_pc();
int which = offset & 0x8;
@ -39,8 +39,8 @@ READ16_MEMBER( m68307_cpu_device::m68307_internal_timer_r )
WRITE16_MEMBER( m68307_cpu_device::m68307_internal_timer_w )
{
assert(m68307TIMER);
m68307_timer &timer = *m68307TIMER;
assert(m_m68307TIMER);
m68307_timer &timer = *m_m68307TIMER;
int pc = space.device().safe_pc();
int which = offset & 0x8;
@ -102,7 +102,7 @@ WRITE16_MEMBER( m68307_cpu_device::m68307_internal_timer_w )
TIMER_CALLBACK_MEMBER(m68307_cpu_device::m68307_timer::timer0_callback )
{
m68307_cpu_device* m68k = (m68307_cpu_device *)ptr;
single_timer* tptr = &m68k->m68307TIMER->singletimer[0];
single_timer* tptr = &m68k->m_m68307TIMER->singletimer[0];
tptr->regs[m68307TIMER_TMR] |= 0x2;
m68k->timer0_interrupt();
@ -113,7 +113,7 @@ TIMER_CALLBACK_MEMBER(m68307_cpu_device::m68307_timer::timer0_callback )
TIMER_CALLBACK_MEMBER(m68307_cpu_device::m68307_timer::timer1_callback )
{
m68307_cpu_device* m68k = (m68307_cpu_device *)ptr;
single_timer* tptr = &m68k->m68307TIMER->singletimer[1];
single_timer* tptr = &m68k->m_m68307TIMER->singletimer[1];
tptr->regs[m68307TIMER_TMR] |= 0x2;
m68k->timer1_interrupt();

76
src/devices/machine/68340.cpp
View File

@ -11,17 +11,17 @@ DEFINE_DEVICE_TYPE(M68340, m68340_cpu_device, "mc68340", "MC68340")
int m68340_cpu_device::calc_cs(offs_t address) const
{
if ( !(m68340SIM->m_ba[0] & 1) ) return 1;
if ( !(m_m68340SIM->m_ba[0] & 1) ) return 1;
for (int i=0;i<4;i++)
{
if (m68340SIM->m_ba[i] & 1)
if (m_m68340SIM->m_ba[i] & 1)
{
int mask = ((m68340SIM->m_am[i]&0xffffff00) | 0xff);
int base = m68340SIM->m_ba[i] & 0xffffff00;
int fcmask = (m68340SIM->m_am[i] & 0xf0);
int fcbase = (m68340SIM->m_ba[i] & 0xf0) & ~(m68340SIM->m_am[i] & 0xf0);
int fc = mmu_tmp_fc;
int mask = ((m_m68340SIM->m_am[i]&0xffffff00) | 0xff);
int base = m_m68340SIM->m_ba[i] & 0xffffff00;
int fcmask = (m_m68340SIM->m_am[i] & 0xf0);
int fcbase = (m_m68340SIM->m_ba[i] & 0xf0) & ~(m_m68340SIM->m_am[i] & 0xf0);
int fc = m_mmu_tmp_fc;
if ((address & ~mask) == base && ((fc << 4) & ~fcmask ) == fcbase ) return i+1;
}
@ -45,58 +45,56 @@ uint16_t m68340_cpu_device::get_cs(offs_t address)
READ32_MEMBER( m68340_cpu_device::m68340_internal_base_r )
{
int pc = space.device().safe_pc();
logerror("%08x m68340_internal_base_r %08x, (%08x)\n", pc, offset*4,mem_mask);
return m68340_base;
logerror("%08x m68340_internal_base_r %08x, (%08x)\n", m_ppc, offset*4,mem_mask);
return m_m68340_base;
}
WRITE32_MEMBER( m68340_cpu_device::m68340_internal_base_w )
{
int pc = space.device().safe_pc();
logerror("%08x m68340_internal_base_w %08x, %08x (%08x)\n", pc, offset*4,data,mem_mask);
logerror("%08x m68340_internal_base_w %08x, %08x (%08x)\n", m_ppc, offset*4,data,mem_mask);
// other conditions?
if (dfc==0x7)
if (m_dfc==0x7)
{
// unmap old modules
if (m68340_base&1)
if (m_m68340_base&1)
{
int base = m68340_base & 0xfffff000;
int base = m_m68340_base & 0xfffff000;
internal->unmap_readwrite(base + 0x000, base + 0x05f);
internal->unmap_readwrite(base + 0x600, base + 0x67f);
internal->unmap_readwrite(base + 0x700, base + 0x723);
internal->unmap_readwrite(base + 0x780, base + 0x7bf);
m_internal->unmap_readwrite(base + 0x000, base + 0x05f);
m_internal->unmap_readwrite(base + 0x600, base + 0x67f);
m_internal->unmap_readwrite(base + 0x700, base + 0x723);
m_internal->unmap_readwrite(base + 0x780, base + 0x7bf);
}
COMBINE_DATA(&m68340_base);
logerror("%08x m68340_internal_base_w %08x, %08x (%08x) (m68340_base write)\n", pc, offset*4,data,mem_mask);
COMBINE_DATA(&m_m68340_base);
logerror("%08x m68340_internal_base_w %08x, %08x (%08x) (m_m68340_base write)\n", pc, offset*4,data,mem_mask);
// map new modules
if (m68340_base&1)
if (m_m68340_base&1)
{
int base = m68340_base & 0xfffff000;
int base = m_m68340_base & 0xfffff000;
internal->install_readwrite_handler(base + 0x000, base + 0x03f,
m_internal->install_readwrite_handler(base + 0x000, base + 0x03f,
read16_delegate(FUNC(m68340_cpu_device::m68340_internal_sim_r),this),
write16_delegate(FUNC(m68340_cpu_device::m68340_internal_sim_w),this),0xffffffff);
internal->install_readwrite_handler(base + 0x010, base + 0x01f, // Intentionally punches a hole in previous address mapping
m_internal->install_readwrite_handler(base + 0x010, base + 0x01f, // Intentionally punches a hole in previous address mapping
read8_delegate(FUNC(m68340_cpu_device::m68340_internal_sim_ports_r),this),
write8_delegate(FUNC(m68340_cpu_device::m68340_internal_sim_ports_w),this),0xffffffff);
internal->install_readwrite_handler(base + 0x040, base + 0x05f,
m_internal->install_readwrite_handler(base + 0x040, base + 0x05f,
read32_delegate(FUNC(m68340_cpu_device::m68340_internal_sim_cs_r),this),
write32_delegate(FUNC(m68340_cpu_device::m68340_internal_sim_cs_w),this));
internal->install_readwrite_handler(base + 0x600, base + 0x63f,
m_internal->install_readwrite_handler(base + 0x600, base + 0x63f,
READ16_DEVICE_DELEGATE(m_timer1, mc68340_timer_module_device, read),
WRITE16_DEVICE_DELEGATE(m_timer1, mc68340_timer_module_device, write),0xffffffff);
internal->install_readwrite_handler(base + 0x640, base + 0x67f,
m_internal->install_readwrite_handler(base + 0x640, base + 0x67f,
READ16_DEVICE_DELEGATE(m_timer2, mc68340_timer_module_device, read),
WRITE16_DEVICE_DELEGATE(m_timer2, mc68340_timer_module_device, write),0xffffffff);
internal->install_readwrite_handler(base + 0x700, base + 0x723,
m_internal->install_readwrite_handler(base + 0x700, base + 0x723,
READ8_DEVICE_DELEGATE(m_serial, mc68340_serial_module_device, read),
WRITE8_DEVICE_DELEGATE(m_serial, mc68340_serial_module_device, write),0xffffffff);
internal->install_readwrite_handler(base + 0x780, base + 0x7bf,
m_internal->install_readwrite_handler(base + 0x780, base + 0x7bf,
read32_delegate(FUNC(m68340_cpu_device::m68340_internal_dma_r),this),
write32_delegate(FUNC(m68340_cpu_device::m68340_internal_dma_w),this));
@ -145,9 +143,9 @@ m68340_cpu_device::m68340_cpu_device(const machine_config &mconfig, const char *
, m_pb_out_cb(*this)
, m_pb_in_cb(*this)
{
m68340SIM = nullptr;
m68340DMA = nullptr;
m68340_base = 0;
m_m68340SIM = nullptr;
m_m68340DMA = nullptr;
m_m68340_base = 0;
}
void m68340_cpu_device::device_reset()
@ -168,15 +166,15 @@ void m68340_cpu_device::device_start()
{
fscpu32_device::device_start();
m68340SIM = new m68340_sim();
m68340DMA = new m68340_dma();
m_m68340SIM = new m68340_sim();
m_m68340DMA = new m68340_dma();
m68340SIM->reset();
m68340DMA->reset();
m_m68340SIM->reset();
m_m68340DMA->reset();
start_68340_sim();
m68340_base = 0x00000000;
m_m68340_base = 0x00000000;
internal = &this->space(AS_PROGRAM);
m_internal = &space(AS_PROGRAM);
}

6
src/devices/machine/68340.h
View File

@ -125,10 +125,10 @@ protected:
uint32_t m_extal;
/* 68340 peripheral modules */
m68340_sim* m68340SIM;
m68340_dma* m68340DMA;
m68340_sim* m_m68340SIM;
m68340_dma* m_m68340DMA;
uint32_t m68340_base;
uint32_t m_m68340_base;
emu_timer *m_irq_timer;

2
src/devices/machine/68340ser.cpp
View File

@ -150,7 +150,7 @@ WRITE_LINE_MEMBER( mc68340_serial_module_device::irq_w )
LOGINT("IRQ!\n%s\n", FUNCNAME);
if (m_ilr > 0)
{
if (((m_cpu->m68340SIM->m_avr_rsr >> (8 + m_ilr)) & 1) != 0) // use autovector ?
if (((m_cpu->m_m68340SIM->m_avr_rsr >> (8 + m_ilr)) & 1) != 0) // use autovector ?
{
LOGINT("- Autovector level %d\n", m_ilr);
m_cpu->set_input_line(m_ilr, HOLD_LINE);

40
src/devices/machine/68340sim.cpp
View File

@ -45,8 +45,8 @@
READ16_MEMBER( m68340_cpu_device::m68340_internal_sim_r )
{
LOGR("%s\n", FUNCNAME);
assert(m68340SIM);
m68340_sim &sim = *m68340SIM;
assert(m_m68340SIM);
m68340_sim &sim = *m_m68340SIM;
int val = 0;
int pc = space.device().safe_pc();
@ -106,8 +106,8 @@ WRITE16_MEMBER( m68340_cpu_device::m68340_internal_sim_w )
((offset * 2) >= 0x10 && (offset * 2) < 0x20) || (offset * 2) >= 0x60 ? "Error - should not happen" :
std::array<char const *, 8> {{"MCR", "reserved", "SYNCR", "AVR/RSR", "SWIV/SYPCR", "PICR", "PITR", "SWSR"}}[(offset * 2) <= m68340_sim::REG_AVR_RSR ? offset : offset - 0x10 + 0x04]);
assert(m68340SIM);
m68340_sim &sim = *m68340SIM;
assert(m_m68340SIM);
m68340_sim &sim = *m_m68340SIM;
int pc = space.device().safe_pc();
@ -200,8 +200,8 @@ READ8_MEMBER( m68340_cpu_device::m68340_internal_sim_ports_r )
{
LOGR("%s\n", FUNCNAME);
offset += 0x10;
assert(m68340SIM);
m68340_sim &sim = *m68340SIM;
assert(m_m68340SIM);
m68340_sim &sim = *m_m68340SIM;
int pc = space.device().safe_pc();
int val = space.machine().rand();
@ -287,8 +287,8 @@ WRITE8_MEMBER( m68340_cpu_device::m68340_internal_sim_ports_w )
{
LOG("%s", FUNCNAME);
offset += 0x10;
assert(m68340SIM);
m68340_sim &sim = *m68340SIM;
assert(m_m68340SIM);
m68340_sim &sim = *m_m68340SIM;
int pc = space.device().safe_pc();
@ -352,8 +352,8 @@ READ32_MEMBER( m68340_cpu_device::m68340_internal_sim_cs_r )
LOGR("%s\n", FUNCNAME);
offset += m68340_sim::REG_AM_CS0>>2;
assert(m68340SIM);
m68340_sim &sim = *m68340SIM;
assert(m_m68340SIM);
m68340_sim &sim = *m_m68340SIM;
int pc = space.device().safe_pc();
@ -382,17 +382,17 @@ WRITE32_MEMBER( m68340_cpu_device::m68340_internal_sim_cs_w )
if (offset & 1)
{
LOGCS("%08x Base address CS%d %08x, %08x (%08x) ", pc, (offset - 0x10) / 2, offset * 4, data, mem_mask);
LOGCS("%08x Base address CS%d %08x, %08x (%08x) ", m_ppc, (offset - 0x10) / 2, offset * 4, data, mem_mask);
LOGCS("- Base: %08x BFC:%02x WP:%d FTE:%d NCS:%d Valid: %s\n", data & 0xffffff00, (data & 0xf0) >> 4, data & 0x08 ? 1 : 0, data & 0x04 ? 1 : 0, data & 0x02 ? 1 : 0, data & 0x01 ? "Yes" : "No");
}
else
{
LOGCS("%08x Address mask CS%d %08x, %08x (%08x) ", pc, (offset - 0x10) / 2, offset * 4, data, mem_mask);
LOGCS("%08x Address mask CS%d %08x, %08x (%08x) ", m_ppc, (offset - 0x10) / 2, offset * 4, data, mem_mask);
LOGCS("- Mask: %08x FCM:%02x DD:%d PS: %s\n", data & 0xffffff00, (data & 0xf0) >> 4, (data >> 2) & 0x03, std::array<char const *, 4>{{"Reserved", "16-Bit", "8-bit", "External DSACK response"}}[data & 0x03]);
}
assert(m68340SIM);
m68340_sim &sim = *m68340SIM;
assert(m_m68340SIM);
m68340_sim &sim = *m_m68340SIM;
int pc = space.device().safe_pc();
@ -438,8 +438,8 @@ WRITE32_MEMBER( m68340_cpu_device::m68340_internal_sim_cs_w )
void m68340_cpu_device::do_pit_irq()
{
assert(m68340SIM);
m68340_sim &sim = *m68340SIM;
assert(m_m68340SIM);
m68340_sim &sim = *m_m68340SIM;
//logerror("do_pit_irq\n");
int timer_irq_level = (sim.m_picr & 0x0700) >> 8;
@ -485,8 +485,8 @@ void m68340_cpu_device::start_68340_sim()
m_pb_in_cb.resolve();
// Setup correct VCO/clock speed based on reset values and crystal
assert(m68340SIM);
m68340_sim &sim = *m68340SIM;
assert(m_m68340SIM);
m68340_sim &sim = *m_m68340SIM;
switch (m_clock_mode)
{
case m68340_sim::CLOCK_MODE_EXT:
@ -534,8 +534,8 @@ void m68340_sim::reset()
/* do_tick_pit works on whole clock cycles, no flank support */
void m68340_cpu_device::do_tick_pit()
{
assert(m68340SIM);
m68340_sim &sim = *m68340SIM;
assert(m_m68340SIM);
m68340_sim &sim = *m_m68340SIM;
sim.m_pit_counter--;
if ( ( (sim.m_mcr & m68340_sim::REG_MCR_FRZ1) == 0) &&

4
src/devices/machine/68340tmu.cpp
View File

@ -310,8 +310,8 @@ void mc68340_timer_module_device::device_start()
void mc68340_timer_module_device::do_timer_irq()
{
assert(m_cpu->m68340SIM);
m68340_sim &sim = *m_cpu->m68340SIM;
assert(m_cpu->m_m68340SIM);
m68340_sim &sim = *m_cpu->m_m68340SIM;
int timer_irq_level = (m_ir & 0x0700) >> 8;
int timer_irq_vector = (m_ir & 0x00ff) >> 0;

9
src/mame/drivers/apollo.cpp
View File

@ -29,7 +29,7 @@
#include "includes/apollo.h"
#include "cpu/m68000/m68kcpu.h"
#include "cpu/m68000/m68000.h"
#include "sound/beep.h"
// we use set_verbose
@ -212,6 +212,7 @@ uint8_t apollo_get_ram_config_byte(void) {
return ram_config_byte;
}
#if 0
/***************************************************************************
apollo_instruction_hook
must be called by the CPU core before executing each instruction
@ -264,6 +265,8 @@ READ32_MEMBER(apollo_state::apollo_instruction_hook)
return apollo_debug_instruction_hook(m_maincpu, offset);
}
#endif
/***************************************************************************
apollo bus error
***************************************************************************/
@ -495,7 +498,7 @@ READ32_MEMBER(apollo_state::apollo_unmapped_r)
} else if (address == 0x0000ac00 && VERBOSE < 2) {
// omit logging for Bus error test address in DN3000 boot prom
} else {
SLOG1(("unmapped memory dword read from %08x with mask %08x (ir=%04x)", address , mem_mask, m68k->ir));
SLOG1(("unmapped memory dword read from %08x with mask %08x (ir=%04x)", address , mem_mask, m68k->state_int(M68K_IR)));
}
/* unmapped; access causes a bus error */
@ -920,7 +923,9 @@ void apollo_state::machine_reset()
m_node_id->set_node_id_from_disk();
}
#if 0
m_maincpu->set_instruction_hook(read32_delegate(FUNC(apollo_state::apollo_instruction_hook),this));
#endif
}
WRITE_LINE_MEMBER(apollo_state::apollo_reset_instr_callback)

14
src/mame/drivers/cubo.cpp
View File

@ -1193,7 +1193,7 @@ void cubo_state::chip_ram_w8_hack(offs_t byteoffs, uint8_t data)
void cubo_state::cndypuzl_input_hack()
{
if (m_maincpu->pc < m_chip_ram.bytes())
if (m_maincpu->pc() < m_chip_ram.bytes())
{
uint32_t r_A5 = m_maincpu->state_int(M68K_A5);
chip_ram_w(r_A5 - 0x7ebe, 0x0000);
@ -1208,7 +1208,7 @@ DRIVER_INIT_MEMBER( cubo_state, cndypuzl )
void cubo_state::haremchl_input_hack()
{
if (m_maincpu->pc < m_chip_ram.bytes())
if (m_maincpu->pc() < m_chip_ram.bytes())
{
uint32_t r_A5 = m_maincpu->state_int(M68K_A5);
uint32_t r_A2 = (chip_ram_r(r_A5 - 0x7f00 + 0) << 16) | (chip_ram_r(r_A5 - 0x7f00 + 2));
@ -1224,7 +1224,7 @@ DRIVER_INIT_MEMBER( cubo_state, haremchl )
void cubo_state::lsrquiz_input_hack()
{
if (m_maincpu->pc < m_chip_ram.bytes())
if (m_maincpu->pc() < m_chip_ram.bytes())
{
uint32_t r_A5 = m_maincpu->state_int(M68K_A5);
uint32_t r_A2 = (chip_ram_r(r_A5 - 0x7fe0 + 0) << 16) | (chip_ram_r(r_A5 - 0x7fe0 + 2));
@ -1241,7 +1241,7 @@ DRIVER_INIT_MEMBER( cubo_state, lsrquiz )
/* The hack isn't working if you exit the test mode with P1 button 2 ! */
void cubo_state::lsrquiz2_input_hack()
{
if (m_maincpu->pc < m_chip_ram.bytes())
if (m_maincpu->pc() < m_chip_ram.bytes())
{
uint32_t r_A5 = m_maincpu->state_int(M68K_A5);
uint32_t r_A2 = (chip_ram_r(r_A5 - 0x7fdc + 0) << 16) | (chip_ram_r(r_A5 - 0x7fdc + 2));
@ -1257,7 +1257,7 @@ DRIVER_INIT_MEMBER( cubo_state, lsrquiz2 )
void cubo_state::lasstixx_input_hack()
{
if (m_maincpu->pc < m_chip_ram.bytes())
if (m_maincpu->pc() < m_chip_ram.bytes())
{
uint32_t r_A5 = m_maincpu->state_int(M68K_A5);
uint32_t r_A2 = (chip_ram_r(r_A5 - 0x7fa2 + 0) << 16) | (chip_ram_r(r_A5 - 0x7fa2 + 2));
@ -1273,7 +1273,7 @@ DRIVER_INIT_MEMBER(cubo_state, lasstixx)
void cubo_state::mgnumber_input_hack()
{
if (m_maincpu->pc < m_chip_ram.bytes())
if (m_maincpu->pc() < m_chip_ram.bytes())
{
uint32_t r_A5 = m_maincpu->state_int(M68K_A5);
chip_ram_w(r_A5 - 0x7ed8, 0x0000);
@ -1288,7 +1288,7 @@ DRIVER_INIT_MEMBER( cubo_state, mgnumber )
void cubo_state::mgprem11_input_hack()
{
if (m_maincpu->pc < m_chip_ram.bytes())
if (m_maincpu->pc() < m_chip_ram.bytes())
{
uint32_t r_A5 = m_maincpu->state_int(M68K_A5);
chip_ram_w8_hack(r_A5 - 0x7eca, 0x00);

8
src/mame/drivers/r9751.cpp
View File

@ -152,17 +152,17 @@ uint32_t r9751_state::swap_uint32( uint32_t val )
uint32_t r9751_state::debug_a6()
{
return m_maincpu->space(AS_PROGRAM).read_dword(ptr_m68000->dar[14] + 4);
return m_maincpu->space(AS_PROGRAM).read_dword(ptr_m68000->state_int(M68K_A6) + 4);
}
uint32_t r9751_state::debug_a5()
{
return m_maincpu->space(AS_PROGRAM).read_dword(ptr_m68000->dar[13]);
return m_maincpu->space(AS_PROGRAM).read_dword(ptr_m68000->state_int(M68K_A5));
}
uint32_t r9751_state::debug_a5_20()
{
return m_maincpu->space(AS_PROGRAM).read_dword(ptr_m68000->dar[13] + 0x20);
return m_maincpu->space(AS_PROGRAM).read_dword(ptr_m68000->state_int(M68K_A5) + 0x20);
}
READ8_MEMBER(r9751_state::pdc_dma_r)
@ -396,7 +396,7 @@ WRITE32_MEMBER( r9751_state::r9751_mmio_5ff_w )
m_pdc->reg_p5 = 0;
/* Send FDD SCSI command location address to PDC 0x2, 0x3 */
if(TRACE_FDC) logerror("--- FDD command address: %08X PC: %08X Register: %08X (A6+4): %08X A4: %08X (A5): %08X (A5+20): %08X\n", (fdd_dma_bank & 0x7FFFF800) + ((data << 1)&0x3FFFF), space.machine().firstcpu->pc(), offset << 2 | 0x5FF00000, debug_a6(), ptr_m68000->dar[12], debug_a5(), debug_a5_20());
if(TRACE_FDC) logerror("--- FDD command address: %08X PC: %08X Register: %08X (A6+4): %08X A4: %08X (A5): %08X (A5+20): %08X\n", (fdd_dma_bank & 0x7FFFF800) + ((data << 1)&0x3FFFF), space.machine().firstcpu->pc(), offset << 2 | 0x5FF00000, debug_a6(), ptr_m68000->state_int(M68K_A4), debug_a5(), debug_a5_20());
data_b0 = data & 0xFF;
data_b1 = (data & 0xFF00) >> 8;
m_pdc->reg_p2 = data_b0;

16
src/mame/drivers/sun2.cpp
View File

@ -207,7 +207,7 @@ READ16_MEMBER( sun2_state::tl_mmu_r )
switch (offset & 7)
{
case 4:
//printf("sun2: Read IDPROM @ %x (PC=%x)\n", offset<<1, m_maincpu->pc);
//printf("sun2: Read IDPROM @ %x (PC=%x)\n", offset<<1, m_maincpu->pc());
return m_idprom_ptr[(offset>>10) & 0x1f]<<8;
case 5:
@ -215,7 +215,7 @@ READ16_MEMBER( sun2_state::tl_mmu_r )
return m_diagreg;
case 6:
//printf("sun2: Read bus error @ PC %x\n", m_maincpu->pc);
//printf("sun2: Read bus error @ PC %x\n", m_maincpu->pc());
return m_buserror;
case 7:
@ -325,7 +325,7 @@ READ16_MEMBER( sun2_state::tl_mmu_r )
if (!machine().side_effect_disabled()) printf("sun2: pagemap entry not valid!\n");
}
if (!machine().side_effect_disabled()) printf("sun2: Unmapped read @ %08x (FC %d, mask %04x, PC=%x, seg %x)\n", offset<<1, fc, mem_mask, m_maincpu->pc, offset>>15);
if (!machine().side_effect_disabled()) printf("sun2: Unmapped read @ %08x (FC %d, mask %04x, PC=%x, seg %x)\n", offset<<1, fc, mem_mask, m_maincpu->pc(), offset>>15);
return 0xffff;
}
@ -334,7 +334,7 @@ WRITE16_MEMBER( sun2_state::tl_mmu_w )
{
uint8_t fc = m_maincpu->get_fc();
//printf("sun2: Write %04x (FC %d, mask %04x, PC=%x) to %08x\n", data, fc, mem_mask, m_maincpu->pc, offset<<1);
//printf("sun2: Write %04x (FC %d, mask %04x, PC=%x) to %08x\n", data, fc, mem_mask, m_maincpu->pc(), offset<<1);
if (fc == 3)
{
@ -348,7 +348,7 @@ WRITE16_MEMBER( sun2_state::tl_mmu_w )
case 5:
// XOR to match Table 2-1 in the 2/50 Field Service Manual
printf("sun2: CPU LEDs to %02x (PC=%x) => ", (data & 0xff) ^ 0xff, m_maincpu->pc);
printf("sun2: CPU LEDs to %02x (PC=%x) => ", (data & 0xff) ^ 0xff, m_maincpu->pc());
m_diagreg = data & 0xff;
for (int i = 0; i < 8; i++)
{
@ -396,11 +396,11 @@ WRITE16_MEMBER( sun2_state::tl_mmu_w )
m_pagemap[page] &= 0x0000ffff;
m_pagemap[page] |= (data<<16);
}
//printf("entry now %08x (adr %08x PC=%x)\n", m_pagemap[page], (m_pagemap[page] & 0xfffff) << 11, m_maincpu->pc);
//printf("entry now %08x (adr %08x PC=%x)\n", m_pagemap[page], (m_pagemap[page] & 0xfffff) << 11, m_maincpu->pc());
return;
case 2: // segment map
//printf("sun2: Write %02x to segment map at %x (entry %d, user ctx %d PC=%x)\n", data & 0xff, offset<<1, offset>>14, m_context & 7, m_maincpu->pc);
//printf("sun2: Write %02x to segment map at %x (entry %d, user ctx %d PC=%x)\n", data & 0xff, offset<<1, offset>>14, m_context & 7, m_maincpu->pc());
m_segmap[m_context & 7][offset >> 14] = data & 0xff;
return;
@ -452,7 +452,7 @@ WRITE16_MEMBER( sun2_state::tl_mmu_w )
if (!machine().side_effect_disabled()) printf("sun2: pagemap entry not valid!\n");
}
printf("sun2: Unmapped write %04x (FC %d, mask %04x, PC=%x) to %08x\n", data, fc, mem_mask, m_maincpu->pc, offset<<1);
printf("sun2: Unmapped write %04x (FC %d, mask %04x, PC=%x) to %08x\n", data, fc, mem_mask, m_maincpu->pc(), offset<<1);
}
// BW2 video control

42
src/mame/drivers/sun3.cpp
View File

@ -308,7 +308,7 @@ READ32_MEMBER( sun3_state::ram_r )
if (!m_bInBusErr)
{
//printf("ram_r: bus error on timeout, access to invalid addr %08x, PC=%x\n", offset<<2, m_maincpu->pc);
//printf("ram_r: bus error on timeout, access to invalid addr %08x, PC=%x\n", offset<<2, m_maincpu->pc());
//fflush(stdout);
m_buserr = BE_TIMEOUT;
m_maincpu->set_input_line(M68K_LINE_BUSERROR, ASSERT_LINE);
@ -381,7 +381,7 @@ WRITE32_MEMBER( sun3_state::ram_w )
if (!m_bInBusErr)
{
//printf("ram_w: bus error on timeout, access to invalid addr %08x, PC=%x\n", offset<<2, m_maincpu->pc);
//printf("ram_w: bus error on timeout, access to invalid addr %08x, PC=%x\n", offset<<2, m_maincpu->pc());
fflush(stdout);
m_buserr = BE_TIMEOUT;
m_maincpu->set_input_line(M68K_LINE_BUSERROR, ASSERT_LINE);
@ -432,22 +432,22 @@ READ32_MEMBER( sun3_state::tl_mmu_r )
return 0;
case 8: // cache tags
//printf("sun3: read cache tags @ %x, PC = %x\n", offset, m_maincpu->pc);
//printf("sun3: read cache tags @ %x, PC = %x\n", offset, m_maincpu->pc());
return m_cache_tags[(offset & 0x3fff) >> 2];
case 9: // cache data
//printf("sun3: read cache data @ %x, PC = %x\n", offset, m_maincpu->pc);
//printf("sun3: read cache data @ %x, PC = %x\n", offset, m_maincpu->pc());
return m_cache_data[(offset & 0x3fff)];
case 10: // flush cache
return 0xffffffff;
case 11: // block copy
printf("sun3: read block copy @ %x, PC = %x\n", offset, m_maincpu->pc);
printf("sun3: read block copy @ %x, PC = %x\n", offset, m_maincpu->pc());
return 0xffffffff;
case 15: // UART bypass
//printf("sun3: read UART bypass @ %x, PC = %x, mask = %08x\n", offset, m_maincpu->pc, mem_mask);
//printf("sun3: read UART bypass @ %x, PC = %x, mask = %08x\n", offset, m_maincpu->pc(), mem_mask);
return 0xffffffff;
}
}
@ -513,7 +513,7 @@ READ32_MEMBER( sun3_state::tl_mmu_r )
}
else
{
// if (!machine().side_effect_disabled()) printf("sun3: pagemap entry not valid! (PC=%x)\n", m_maincpu->pc);
// if (!machine().side_effect_disabled()) printf("sun3: pagemap entry not valid! (PC=%x)\n", m_maincpu->pc());
m_maincpu->set_input_line(M68K_LINE_BUSERROR, ASSERT_LINE);
m_maincpu->set_input_line(M68K_LINE_BUSERROR, CLEAR_LINE);
m_buserr = BE_INVALID;
@ -521,7 +521,7 @@ READ32_MEMBER( sun3_state::tl_mmu_r )
return 0xffffffff;
}
if (!machine().side_effect_disabled()) logerror("sun3: Unmapped read @ %08x (FC %d, mask %08x, PC=%x, seg %x)\n", offset<<2, fc, mem_mask, m_maincpu->pc, offset>>15);
if (!machine().side_effect_disabled()) logerror("sun3: Unmapped read @ %08x (FC %d, mask %08x, PC=%x, seg %x)\n", offset<<2, fc, mem_mask, m_maincpu->pc(), offset>>15);
return 0xffffffff;
}
@ -530,7 +530,7 @@ WRITE32_MEMBER( sun3_state::tl_mmu_w )
{
uint8_t fc = m_maincpu->get_fc();
//printf("sun3: Write %08x (FC %d, mask %08x, PC=%x) to %08x\n", data, fc, mem_mask, m_maincpu->pc, offset<<1);
//printf("sun3: Write %08x (FC %d, mask %08x, PC=%x) to %08x\n", data, fc, mem_mask, m_maincpu->pc(), offset<<1);
if (fc == 3) // control space
{
@ -549,11 +549,11 @@ WRITE32_MEMBER( sun3_state::tl_mmu_w )
//printf("sun3: Write %04x to page map at %x (entry %d), ", data, offset<<2, page);
COMBINE_DATA(&m_pagemap[page]);
//printf("entry now %08x (adr %08x PC=%x mask %x)\n", m_pagemap[page], (m_pagemap[page] & 0xfffff) << 13, m_maincpu->pc, mem_mask);
//printf("entry now %08x (adr %08x PC=%x mask %x)\n", m_pagemap[page], (m_pagemap[page] & 0xfffff) << 13, m_maincpu->pc(), mem_mask);
return;
case 2: // segment map
//printf("sun3: Write %02x to segment map at %x (entry %d, user ctx %d PC=%x mask %x)\n", (data>>24) & 0xff, offset<<2, (offset & ~0x3c000000)>>15, m_context & 7, m_maincpu->pc, mem_mask);
//printf("sun3: Write %02x to segment map at %x (entry %d, user ctx %d PC=%x mask %x)\n", (data>>24) & 0xff, offset<<2, (offset & ~0x3c000000)>>15, m_context & 7, m_maincpu->pc(), mem_mask);
m_segmap[m_context & 7][(offset >> 15) & 0x7ff] = (data>>24) & 0xff;
//printf("segment map[%d][%d] now %x\n", m_context & 7, (offset & ~0x3c000000) >> 15, m_segmap[m_context & 7][(offset & ~0x3c000000) >> 15] = (data>>24) & 0xff);
return;
@ -564,7 +564,7 @@ WRITE32_MEMBER( sun3_state::tl_mmu_w )
return;
case 4: // enable reg
//printf("sun3: Write %x to enable, PC=%x\n", data, m_maincpu->pc);
//printf("sun3: Write %x to enable, PC=%x\n", data, m_maincpu->pc());
COMBINE_DATA(&m_enable);
return;
@ -578,7 +578,7 @@ WRITE32_MEMBER( sun3_state::tl_mmu_w )
case 7: // diagnostic reg
m_diag = data >> 24;
#if 0
printf("sun3: CPU LEDs to %02x (PC=%x) => ", ((data>>24) & 0xff) ^ 0xff, m_maincpu->pc);
printf("sun3: CPU LEDs to %02x (PC=%x) => ", ((data>>24) & 0xff) ^ 0xff, m_maincpu->pc());
for (int i = 0; i < 8; i++)
{
if (m_diag & (1<<i))
@ -595,12 +595,12 @@ WRITE32_MEMBER( sun3_state::tl_mmu_w )
return;
case 8: // cache tags
//printf("sun3: %08x to cache tags @ %x, PC = %x, mask = %08x\n", data, offset, m_maincpu->pc, mem_mask);
//printf("sun3: %08x to cache tags @ %x, PC = %x, mask = %08x\n", data, offset, m_maincpu->pc(), mem_mask);
m_cache_tags[(offset & 0x3fff) >> 2] = data;
return;
case 9: // cache data
//printf("sun3: %08x to cache data @ %x, PC = %x, mask = %08x\n", data, offset, m_maincpu->pc, mem_mask);
//printf("sun3: %08x to cache data @ %x, PC = %x, mask = %08x\n", data, offset, m_maincpu->pc(), mem_mask);
m_cache_data[(offset & 0x3fff)] = data;
return;
@ -608,11 +608,11 @@ WRITE32_MEMBER( sun3_state::tl_mmu_w )
return;
case 11: // block copy
printf("sun3: %08x to block copy @ %x, PC = %x\n", data, offset, m_maincpu->pc);
printf("sun3: %08x to block copy @ %x, PC = %x\n", data, offset, m_maincpu->pc());
return;
case 15: // UART bypass
//printf("sun3: %08x to UART bypass @ %x, PC = %x\n", data, offset, m_maincpu->pc);
//printf("sun3: %08x to UART bypass @ %x, PC = %x\n", data, offset, m_maincpu->pc());
return;
}
}
@ -626,7 +626,7 @@ WRITE32_MEMBER( sun3_state::tl_mmu_w )
if ((!(m_pagemap[entry] & PM_WRITEMASK)) ||
((m_pagemap[entry] & PM_SYSMASK) && (fc < M68K_FC_SUPERVISOR_DATA)))
{
//printf("sun3: write protect MMU error (PC=%x)\n", m_maincpu->pc);
//printf("sun3: write protect MMU error (PC=%x)\n", m_maincpu->pc());
m_buserr = BE_PROTERR;
m_maincpu->set_input_line(M68K_LINE_BUSERROR, ASSERT_LINE);
m_maincpu->set_input_line(M68K_LINE_BUSERROR, CLEAR_LINE);
@ -671,7 +671,7 @@ WRITE32_MEMBER( sun3_state::tl_mmu_w )
return;
}
logerror("sun3: Unmapped write %04x (FC %d, mask %04x, PC=%x) to %08x\n", data, fc, mem_mask, m_maincpu->pc, offset<<2);
logerror("sun3: Unmapped write %04x (FC %d, mask %04x, PC=%x) to %08x\n", data, fc, mem_mask, m_maincpu->pc(), offset<<2);
}
READ32_MEMBER(sun3_state::parity_r)
@ -783,7 +783,7 @@ WRITE32_MEMBER(sun3_state::irqctrl_w)
READ8_MEMBER(sun3_state::rtc7170_r)
{
//printf("read 7170 @ %x, PC=%x\n", offset, m_maincpu->pc);
//printf("read 7170 @ %x, PC=%x\n", offset, m_maincpu->pc());
return 0xff;
}
@ -803,7 +803,7 @@ WRITE8_MEMBER(sun3_state::rtc7170_w)
READ32_MEMBER(sun3_state::ecc_r)
{
//printf("read ECC @ %x, PC=%x\n", offset, m_maincpu->pc);
//printf("read ECC @ %x, PC=%x\n", offset, m_maincpu->pc());
// fefc34a
int mbram = (m_ram_size / (1024*1024));
int beoff = (mbram / 32) * 0x10;

1
src/mame/drivers/x68k.cpp
View File

@ -968,7 +968,6 @@ void x68k_state::set_bus_error(uint32_t address, bool write, uint16_t mem_mask)
address++;
m_bus_error = true;
m_maincpu->set_buserror_details(address, write, m_maincpu->get_fc());
m_maincpu->mmu_tmp_buserror_address = address; // Hack for x68030
m_maincpu->set_input_line(M68K_LINE_BUSERROR, ASSERT_LINE);
m_maincpu->set_input_line(M68K_LINE_BUSERROR, CLEAR_LINE);
m_bus_error_timer->adjust(m_maincpu->cycles_to_attotime(16)); // let rmw cycles complete

2
src/mame/includes/apollo.h
View File

@ -87,8 +87,10 @@ uint8_t apollo_get_ram_config_byte(void);
//apollo_get_node_id - get the node id
uint32_t apollo_get_node_id(void);
#if 0
// should be called by the CPU core before executing each instruction
int apollo_instruction_hook(m68000_base_device *device, offs_t curpc);
#endif
void apollo_set_cache_status_register(device_t *device,uint8_t mask, uint8_t data);

5
src/mame/machine/apollo_dbg.cpp
View File

@ -13,7 +13,9 @@
#include "emu.h"
#include "debug/debugbuf.h"
#include "includes/apollo.h"
#include "cpu/m68000/m68kcpu.h"
#include "cpu/m68000/m68000.h"
#if 0
//------------------------------------------------------
// TRAP 0
@ -1168,3 +1170,4 @@ int apollo_debug_instruction_hook(m68000_base_device *device, offs_t curpc)
}
return 0;
}
#endif