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i860.c: Modernized cpu core. (nw)

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This commit is contained in:
Wilbert Pol 2013-08-03 19:51:36 +00:00
parent 68ab455560
commit a70f95ea21
4 changed files with 1223 additions and 1278 deletions
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541
src/emu/cpu/i860/i860.c
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@ -22,349 +22,220 @@ TODO: Separate out i860XR and i860XP (make different types, etc).
#include "debugger.h" #include "debugger.h"
#include "i860.h" #include "i860.h"
/**************************************************************************
* Functions specified by GET_INFO
**************************************************************************/
static CPU_INIT( i860 ) /* Control register numbers. */
enum {
CR_FIR = 0,
CR_PSR = 1,
CR_DIRBASE = 2,
CR_DB = 3,
CR_FSR = 4,
CR_EPSR = 5
};
const device_type I860 = &device_creator<i860_cpu_device>;
i860_cpu_device::i860_cpu_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
: cpu_device(mconfig, I860, "i860XR", tag, owner, clock, "i860xr", __FILE__)
, m_program_config("program", ENDIANNESS_LITTLE, 64, 32, 0)
{ {
i860_state_t *cpustate = get_safe_token(device);
cpustate->device = device;
cpustate->program = &device->space(AS_PROGRAM);
reset_i860(cpustate);
i860_set_pin(device, DEC_PIN_BUS_HOLD, 0);
i860_set_pin(device, DEC_PIN_RESET, 0);
cpustate->single_stepping = 0;
device->save_item(NAME(cpustate->iregs));
device->save_item(NAME(cpustate->cregs));
device->save_item(NAME(cpustate->frg));
device->save_item(NAME(cpustate->pc));
}
static CPU_RESET( i860 )
{
i860_state_t *cpustate = get_safe_token(device);
reset_i860(cpustate);
} }
extern CPU_DISASSEMBLE( i860 ); void i860_cpu_device::device_start()
{
m_program = &space(AS_PROGRAM);
reset_i860();
i860_set_pin(DEC_PIN_BUS_HOLD, 0);
i860_set_pin(DEC_PIN_RESET, 0);
m_single_stepping = 0;
save_item(NAME(m_iregs));
save_item(NAME(m_cregs));
save_item(NAME(m_frg));
save_item(NAME(m_pc));
state_add( I860_PC, "PC", m_pc).formatstr("%08X");
state_add( I860_FIR, "FIR", m_cregs[CR_FIR]).formatstr("%08X");
state_add( I860_PSR, "PSR", m_cregs[CR_PSR]).formatstr("%08X");
state_add( I860_DIRBASE, "DIRBASE", m_cregs[CR_DIRBASE]).formatstr("%08X");
state_add( I860_DB, "DB", m_cregs[CR_DB]).formatstr("%08X");
state_add( I860_FSR, "FSR", m_cregs[CR_FSR]).formatstr("%08X");
state_add( I860_EPSR, "EPSR", m_cregs[CR_EPSR]).formatstr("%08X");
state_add( I860_R0, "R0", m_iregs[0]).formatstr("%08X");
state_add( I860_R1, "R1", m_iregs[1]).formatstr("%08X");
state_add( I860_R2, "R2", m_iregs[2]).formatstr("%08X");
state_add( I860_R3, "R3", m_iregs[3]).formatstr("%08X");
state_add( I860_R4, "R4", m_iregs[4]).formatstr("%08X");
state_add( I860_R5, "R5", m_iregs[5]).formatstr("%08X");
state_add( I860_R6, "R6", m_iregs[6]).formatstr("%08X");
state_add( I860_R7, "R7", m_iregs[7]).formatstr("%08X");
state_add( I860_R8, "R8", m_iregs[8]).formatstr("%08X");
state_add( I860_R9, "R9", m_iregs[9]).formatstr("%08X");
state_add( I860_R10, "R10", m_iregs[10]).formatstr("%08X");
state_add( I860_R11, "R11", m_iregs[11]).formatstr("%08X");
state_add( I860_R12, "R12", m_iregs[12]).formatstr("%08X");
state_add( I860_R13, "R13", m_iregs[13]).formatstr("%08X");
state_add( I860_R14, "R14", m_iregs[14]).formatstr("%08X");
state_add( I860_R15, "R15", m_iregs[15]).formatstr("%08X");
state_add( I860_R16, "R16", m_iregs[16]).formatstr("%08X");
state_add( I860_R17, "R17", m_iregs[17]).formatstr("%08X");
state_add( I860_R18, "R18", m_iregs[18]).formatstr("%08X");
state_add( I860_R19, "R19", m_iregs[19]).formatstr("%08X");
state_add( I860_R20, "R20", m_iregs[20]).formatstr("%08X");
state_add( I860_R21, "R21", m_iregs[21]).formatstr("%08X");
state_add( I860_R22, "R22", m_iregs[22]).formatstr("%08X");
state_add( I860_R23, "R23", m_iregs[23]).formatstr("%08X");
state_add( I860_R24, "R24", m_iregs[24]).formatstr("%08X");
state_add( I860_R25, "R25", m_iregs[25]).formatstr("%08X");
state_add( I860_R26, "R26", m_iregs[26]).formatstr("%08X");
state_add( I860_R27, "R27", m_iregs[27]).formatstr("%08X");
state_add( I860_R28, "R28", m_iregs[28]).formatstr("%08X");
state_add( I860_R29, "R29", m_iregs[29]).formatstr("%08X");
state_add( I860_R30, "R30", m_iregs[30]).formatstr("%08X");
state_add( I860_R31, "R31", m_iregs[31]).formatstr("%08X");
state_add( I860_F0, "F0", m_freg[0]).callimport().callexport().formatstr("%08X");
state_add( I860_F1, "F1", m_freg[1]).callimport().callexport().formatstr("%08X");
state_add( I860_F2, "F2", m_freg[2]).callimport().callexport().formatstr("%08X");
state_add( I860_F3, "F3", m_freg[3]).callimport().callexport().formatstr("%08X");
state_add( I860_F4, "F4", m_freg[4]).callimport().callexport().formatstr("%08X");
state_add( I860_F5, "F5", m_freg[5]).callimport().callexport().formatstr("%08X");
state_add( I860_F6, "F6", m_freg[6]).callimport().callexport().formatstr("%08X");
state_add( I860_F7, "F7", m_freg[7]).callimport().callexport().formatstr("%08X");
state_add( I860_F8, "F8", m_freg[8]).callimport().callexport().formatstr("%08X");
state_add( I860_F9, "F9", m_freg[9]).callimport().callexport().formatstr("%08X");
state_add( I860_F10, "F10", m_freg[10]).callimport().callexport().formatstr("%08X");
state_add( I860_F11, "F11", m_freg[11]).callimport().callexport().formatstr("%08X");
state_add( I860_F12, "F12", m_freg[12]).callimport().callexport().formatstr("%08X");
state_add( I860_F13, "F13", m_freg[13]).callimport().callexport().formatstr("%08X");
state_add( I860_F14, "F14", m_freg[14]).callimport().callexport().formatstr("%08X");
state_add( I860_F15, "F15", m_freg[15]).callimport().callexport().formatstr("%08X");
state_add( I860_F16, "F16", m_freg[16]).callimport().callexport().formatstr("%08X");
state_add( I860_F17, "F17", m_freg[17]).callimport().callexport().formatstr("%08X");
state_add( I860_F18, "F18", m_freg[18]).callimport().callexport().formatstr("%08X");
state_add( I860_F19, "F19", m_freg[19]).callimport().callexport().formatstr("%08X");
state_add( I860_F20, "F20", m_freg[20]).callimport().callexport().formatstr("%08X");
state_add( I860_F21, "F21", m_freg[21]).callimport().callexport().formatstr("%08X");
state_add( I860_F22, "F22", m_freg[22]).callimport().callexport().formatstr("%08X");
state_add( I860_F23, "F23", m_freg[23]).callimport().callexport().formatstr("%08X");
state_add( I860_F24, "F24", m_freg[24]).callimport().callexport().formatstr("%08X");
state_add( I860_F25, "F25", m_freg[25]).callimport().callexport().formatstr("%08X");
state_add( I860_F26, "F26", m_freg[26]).callimport().callexport().formatstr("%08X");
state_add( I860_F27, "F27", m_freg[27]).callimport().callexport().formatstr("%08X");
state_add( I860_F28, "F28", m_freg[28]).callimport().callexport().formatstr("%08X");
state_add( I860_F29, "F29", m_freg[29]).callimport().callexport().formatstr("%08X");
state_add( I860_F30, "F30", m_freg[30]).callimport().callexport().formatstr("%08X");
state_add( I860_F31, "F31", m_freg[31]).callimport().callexport().formatstr("%08X");
state_add(STATE_GENPC, "curpc", m_pc).noshow();
m_icountptr = &m_icount;
}
void i860_cpu_device::state_import(const device_state_entry &entry)
{
#define I860_SET_INFO_F(fnum) m_frg[0+(4*fnum)] = (m_freg[fnum] & 0x000000ff); \
m_frg[1+(4*fnum)] = (m_freg[fnum] & 0x0000ff00) >> 8; \
m_frg[2+(4*fnum)] = (m_freg[fnum] & 0x00ff0000) >> 16; \
m_frg[3+(4*fnum)] = (m_freg[fnum] & 0xff000000) >> 24;
switch (entry.index())
{
case I860_F0: I860_SET_INFO_F(0); break;
case I860_F1: I860_SET_INFO_F(1); break;
case I860_F2: I860_SET_INFO_F(2); break;
case I860_F3: I860_SET_INFO_F(3); break;
case I860_F4: I860_SET_INFO_F(4); break;
case I860_F5: I860_SET_INFO_F(5); break;
case I860_F6: I860_SET_INFO_F(6); break;
case I860_F7: I860_SET_INFO_F(7); break;
case I860_F8: I860_SET_INFO_F(8); break;
case I860_F9: I860_SET_INFO_F(9); break;
case I860_F10: I860_SET_INFO_F(10); break;
case I860_F11: I860_SET_INFO_F(11); break;
case I860_F12: I860_SET_INFO_F(12); break;
case I860_F13: I860_SET_INFO_F(13); break;
case I860_F14: I860_SET_INFO_F(14); break;
case I860_F15: I860_SET_INFO_F(15); break;
case I860_F16: I860_SET_INFO_F(16); break;
case I860_F17: I860_SET_INFO_F(17); break;
case I860_F18: I860_SET_INFO_F(18); break;
case I860_F19: I860_SET_INFO_F(19); break;
case I860_F20: I860_SET_INFO_F(20); break;
case I860_F21: I860_SET_INFO_F(21); break;
case I860_F22: I860_SET_INFO_F(22); break;
case I860_F23: I860_SET_INFO_F(23); break;
case I860_F24: I860_SET_INFO_F(24); break;
case I860_F25: I860_SET_INFO_F(25); break;
case I860_F26: I860_SET_INFO_F(26); break;
case I860_F27: I860_SET_INFO_F(27); break;
case I860_F28: I860_SET_INFO_F(28); break;
case I860_F29: I860_SET_INFO_F(29); break;
case I860_F30: I860_SET_INFO_F(30); break;
case I860_F31: I860_SET_INFO_F(31); break;
}
}
void i860_cpu_device::state_export(const device_state_entry &entry)
{
#define I860_GET_INFO_F(fnum) m_freg[fnum] = m_frg[0+(4*fnum)] | ( m_frg[1+(4*fnum)] << 8 ) | ( m_frg[2+(4*fnum)] << 16 ) | ( m_frg[3+(4*fnum)] << 24)
switch (entry.index())
{
case I860_F0: I860_GET_INFO_F(0); break;
case I860_F1: I860_GET_INFO_F(1); break;
case I860_F2: I860_GET_INFO_F(2); break;
case I860_F3: I860_GET_INFO_F(3); break;
case I860_F4: I860_GET_INFO_F(4); break;
case I860_F5: I860_GET_INFO_F(5); break;
case I860_F6: I860_GET_INFO_F(6); break;
case I860_F7: I860_GET_INFO_F(7); break;
case I860_F8: I860_GET_INFO_F(8); break;
case I860_F9: I860_GET_INFO_F(9); break;
case I860_F10: I860_GET_INFO_F(10); break;
case I860_F11: I860_GET_INFO_F(11); break;
case I860_F12: I860_GET_INFO_F(12); break;
case I860_F13: I860_GET_INFO_F(13); break;
case I860_F14: I860_GET_INFO_F(14); break;
case I860_F15: I860_GET_INFO_F(15); break;
case I860_F16: I860_GET_INFO_F(16); break;
case I860_F17: I860_GET_INFO_F(17); break;
case I860_F18: I860_GET_INFO_F(18); break;
case I860_F19: I860_GET_INFO_F(19); break;
case I860_F20: I860_GET_INFO_F(20); break;
case I860_F21: I860_GET_INFO_F(21); break;
case I860_F22: I860_GET_INFO_F(22); break;
case I860_F23: I860_GET_INFO_F(23); break;
case I860_F24: I860_GET_INFO_F(24); break;
case I860_F25: I860_GET_INFO_F(25); break;
case I860_F26: I860_GET_INFO_F(26); break;
case I860_F27: I860_GET_INFO_F(27); break;
case I860_F28: I860_GET_INFO_F(28); break;
case I860_F29: I860_GET_INFO_F(29); break;
case I860_F30: I860_GET_INFO_F(30); break;
case I860_F31: I860_GET_INFO_F(31); break;
}
}
void i860_cpu_device::device_reset()
{
reset_i860();
}
offs_t i860_cpu_device::disasm_disassemble(char *buffer, offs_t pc, const UINT8 *oprom, const UINT8 *opram, UINT32 options)
{
extern CPU_DISASSEMBLE( i860 );
return CPU_DISASSEMBLE_NAME(i860)(this, buffer, pc, oprom, opram, options);
}
/************************************************************************** /**************************************************************************
* The actual decode and execute code. * The actual decode and execute code.
**************************************************************************/ **************************************************************************/
#include "i860dec.c" #include "i860dec.c"
/**************************************************************************
* Generic set_info/get_info
**************************************************************************/
#define CPU_SET_INFO_F(fnum) cpustate->frg[0+(4*fnum)] = (info->i & 0x000000ff); \
cpustate->frg[1+(4*fnum)] = (info->i & 0x0000ff00) >> 8; \
cpustate->frg[2+(4*fnum)] = (info->i & 0x00ff0000) >> 16; \
cpustate->frg[3+(4*fnum)] = (info->i & 0xff000000) >> 24;
static CPU_SET_INFO( i860 )
{
i860_state_t *cpustate = get_safe_token(device);
switch(state)
{
case CPUINFO_INT_PC:
case CPUINFO_INT_REGISTER + I860_PC: cpustate->pc = info->i & 0xffffffff; break;
case CPUINFO_INT_REGISTER + I860_FIR: cpustate->cregs[CR_FIR] = info->i & 0xffffffff; break;
case CPUINFO_INT_REGISTER + I860_PSR: cpustate->cregs[CR_PSR] = info->i & 0xffffffff; break;
case CPUINFO_INT_REGISTER + I860_DIRBASE: cpustate->cregs[CR_DIRBASE] = info->i & 0xffffffff; break;
case CPUINFO_INT_REGISTER + I860_DB: cpustate->cregs[CR_DB] = info->i & 0xffffffff; break;
case CPUINFO_INT_REGISTER + I860_FSR: cpustate->cregs[CR_FSR] = info->i & 0xffffffff; break;
case CPUINFO_INT_REGISTER + I860_EPSR: cpustate->cregs[CR_EPSR] = info->i & 0xffffffff; break;
case CPUINFO_INT_REGISTER + I860_R0: cpustate->iregs[0] = info->i & 0xffffffff; break;
case CPUINFO_INT_REGISTER + I860_R1: cpustate->iregs[1] = info->i & 0xffffffff; break;
case CPUINFO_INT_REGISTER + I860_R2: cpustate->iregs[2] = info->i & 0xffffffff; break;
case CPUINFO_INT_REGISTER + I860_R3: cpustate->iregs[3] = info->i & 0xffffffff; break;
case CPUINFO_INT_REGISTER + I860_R4: cpustate->iregs[4] = info->i & 0xffffffff; break;
case CPUINFO_INT_REGISTER + I860_R5: cpustate->iregs[5] = info->i & 0xffffffff; break;
case CPUINFO_INT_REGISTER + I860_R6: cpustate->iregs[6] = info->i & 0xffffffff; break;
case CPUINFO_INT_REGISTER + I860_R7: cpustate->iregs[7] = info->i & 0xffffffff; break;
case CPUINFO_INT_REGISTER + I860_R8: cpustate->iregs[8] = info->i & 0xffffffff; break;
case CPUINFO_INT_REGISTER + I860_R9: cpustate->iregs[9] = info->i & 0xffffffff; break;
case CPUINFO_INT_REGISTER + I860_R10: cpustate->iregs[10] = info->i & 0xffffffff; break;
case CPUINFO_INT_REGISTER + I860_R11: cpustate->iregs[11] = info->i & 0xffffffff; break;
case CPUINFO_INT_REGISTER + I860_R12: cpustate->iregs[12] = info->i & 0xffffffff; break;
case CPUINFO_INT_REGISTER + I860_R13: cpustate->iregs[13] = info->i & 0xffffffff; break;
case CPUINFO_INT_REGISTER + I860_R14: cpustate->iregs[14] = info->i & 0xffffffff; break;
case CPUINFO_INT_REGISTER + I860_R15: cpustate->iregs[15] = info->i & 0xffffffff; break;
case CPUINFO_INT_REGISTER + I860_R16: cpustate->iregs[16] = info->i & 0xffffffff; break;
case CPUINFO_INT_REGISTER + I860_R17: cpustate->iregs[17] = info->i & 0xffffffff; break;
case CPUINFO_INT_REGISTER + I860_R18: cpustate->iregs[18] = info->i & 0xffffffff; break;
case CPUINFO_INT_REGISTER + I860_R19: cpustate->iregs[19] = info->i & 0xffffffff; break;
case CPUINFO_INT_REGISTER + I860_R20: cpustate->iregs[20] = info->i & 0xffffffff; break;
case CPUINFO_INT_REGISTER + I860_R21: cpustate->iregs[21] = info->i & 0xffffffff; break;
case CPUINFO_INT_REGISTER + I860_R22: cpustate->iregs[22] = info->i & 0xffffffff; break;
case CPUINFO_INT_REGISTER + I860_R23: cpustate->iregs[23] = info->i & 0xffffffff; break;
case CPUINFO_INT_REGISTER + I860_R24: cpustate->iregs[24] = info->i & 0xffffffff; break;
case CPUINFO_INT_REGISTER + I860_R25: cpustate->iregs[25] = info->i & 0xffffffff; break;
case CPUINFO_INT_REGISTER + I860_R26: cpustate->iregs[26] = info->i & 0xffffffff; break;
case CPUINFO_INT_REGISTER + I860_R27: cpustate->iregs[27] = info->i & 0xffffffff; break;
case CPUINFO_INT_REGISTER + I860_R28: cpustate->iregs[28] = info->i & 0xffffffff; break;
case CPUINFO_INT_REGISTER + I860_R29: cpustate->iregs[29] = info->i & 0xffffffff; break;
case CPUINFO_INT_REGISTER + I860_R30: cpustate->iregs[30] = info->i & 0xffffffff; break;
case CPUINFO_INT_REGISTER + I860_R31: cpustate->iregs[31] = info->i & 0xffffffff; break;
case CPUINFO_INT_REGISTER + I860_F0: CPU_SET_INFO_F(0); break;
case CPUINFO_INT_REGISTER + I860_F1: CPU_SET_INFO_F(1); break;
case CPUINFO_INT_REGISTER + I860_F2: CPU_SET_INFO_F(2); break;
case CPUINFO_INT_REGISTER + I860_F3: CPU_SET_INFO_F(3); break;
case CPUINFO_INT_REGISTER + I860_F4: CPU_SET_INFO_F(4); break;
case CPUINFO_INT_REGISTER + I860_F5: CPU_SET_INFO_F(5); break;
case CPUINFO_INT_REGISTER + I860_F6: CPU_SET_INFO_F(6); break;
case CPUINFO_INT_REGISTER + I860_F7: CPU_SET_INFO_F(7); break;
case CPUINFO_INT_REGISTER + I860_F8: CPU_SET_INFO_F(8); break;
case CPUINFO_INT_REGISTER + I860_F9: CPU_SET_INFO_F(9); break;
case CPUINFO_INT_REGISTER + I860_F10: CPU_SET_INFO_F(10); break;
case CPUINFO_INT_REGISTER + I860_F11: CPU_SET_INFO_F(11); break;
case CPUINFO_INT_REGISTER + I860_F12: CPU_SET_INFO_F(12); break;
case CPUINFO_INT_REGISTER + I860_F13: CPU_SET_INFO_F(13); break;
case CPUINFO_INT_REGISTER + I860_F14: CPU_SET_INFO_F(14); break;
case CPUINFO_INT_REGISTER + I860_F15: CPU_SET_INFO_F(15); break;
case CPUINFO_INT_REGISTER + I860_F16: CPU_SET_INFO_F(16); break;
case CPUINFO_INT_REGISTER + I860_F17: CPU_SET_INFO_F(17); break;
case CPUINFO_INT_REGISTER + I860_F18: CPU_SET_INFO_F(18); break;
case CPUINFO_INT_REGISTER + I860_F19: CPU_SET_INFO_F(19); break;
case CPUINFO_INT_REGISTER + I860_F20: CPU_SET_INFO_F(20); break;
case CPUINFO_INT_REGISTER + I860_F21: CPU_SET_INFO_F(21); break;
case CPUINFO_INT_REGISTER + I860_F22: CPU_SET_INFO_F(22); break;
case CPUINFO_INT_REGISTER + I860_F23: CPU_SET_INFO_F(23); break;
case CPUINFO_INT_REGISTER + I860_F24: CPU_SET_INFO_F(24); break;
case CPUINFO_INT_REGISTER + I860_F25: CPU_SET_INFO_F(25); break;
case CPUINFO_INT_REGISTER + I860_F26: CPU_SET_INFO_F(26); break;
case CPUINFO_INT_REGISTER + I860_F27: CPU_SET_INFO_F(27); break;
case CPUINFO_INT_REGISTER + I860_F28: CPU_SET_INFO_F(28); break;
case CPUINFO_INT_REGISTER + I860_F29: CPU_SET_INFO_F(29); break;
case CPUINFO_INT_REGISTER + I860_F30: CPU_SET_INFO_F(30); break;
case CPUINFO_INT_REGISTER + I860_F31: CPU_SET_INFO_F(31); break;
}
}
#define CPU_GET_INFO_INT_F(fnum) (info->i = cpustate->frg[0+(4*fnum)] | \
cpustate->frg[1+(4*fnum)] << 8 | \
cpustate->frg[2+(4*fnum)] << 16 | \
cpustate->frg[3+(4*fnum)] << 24)
#define CPU_GET_INFO_STR_F(fnum) (sprintf(info->s, "F%d : %08x", fnum, cpustate->frg[0+(4*fnum)] | \
cpustate->frg[1+(4*fnum)] << 8 | \
cpustate->frg[2+(4*fnum)] << 16 | \
cpustate->frg[3+(4*fnum)] << 24))
CPU_GET_INFO( i860 )
{
i860_state_t *cpustate = (device != NULL && device->token() != NULL) ? get_safe_token(device) : NULL;
switch (state)
{
/* --- the following bits of info are returned as 64-bit signed integers --- */
case CPUINFO_INT_CONTEXT_SIZE: info->i = sizeof(i860_state_t); break;
case CPUINFO_INT_INPUT_LINES: info->i = 0; break;
case CPUINFO_INT_DEFAULT_IRQ_VECTOR: info->i = 0x00000000; break;
case CPUINFO_INT_ENDIANNESS: info->i = ENDIANNESS_LITTLE; break;
case CPUINFO_INT_CLOCK_MULTIPLIER: info->i = 1; break;
case CPUINFO_INT_CLOCK_DIVIDER: info->i = 1; break;
case CPUINFO_INT_MIN_INSTRUCTION_BYTES: info->i = 4; break;
case CPUINFO_INT_MAX_INSTRUCTION_BYTES: info->i = 4; break;
case CPUINFO_INT_MIN_CYCLES: info->i = 1; break;
case CPUINFO_INT_MAX_CYCLES: info->i = 8; break;
case CPUINFO_INT_DATABUS_WIDTH + AS_PROGRAM: info->i = 64; break;
case CPUINFO_INT_ADDRBUS_WIDTH + AS_PROGRAM: info->i = 32; break;
case CPUINFO_INT_ADDRBUS_SHIFT + AS_PROGRAM: info->i = 0; break;
case CPUINFO_INT_DATABUS_WIDTH + AS_DATA: info->i = 0; break;
case CPUINFO_INT_ADDRBUS_WIDTH + AS_DATA: info->i = 0; break;
case CPUINFO_INT_ADDRBUS_SHIFT + AS_DATA: info->i = 0; break;
case CPUINFO_INT_DATABUS_WIDTH + AS_IO: info->i = 0; break;
case CPUINFO_INT_ADDRBUS_WIDTH + AS_IO: info->i = 0; break;
case CPUINFO_INT_ADDRBUS_SHIFT + AS_IO: info->i = 0; break;
case CPUINFO_INT_PC:
case CPUINFO_INT_REGISTER + I860_PC: info->i = cpustate->pc; break;
case CPUINFO_INT_PREVIOUSPC: info->i = cpustate->ppc; break;
case CPUINFO_INT_REGISTER + I860_FIR: info->i = cpustate->cregs[CR_FIR]; break;
case CPUINFO_INT_REGISTER + I860_PSR: info->i = cpustate->cregs[CR_PSR]; break;
case CPUINFO_INT_REGISTER + I860_DIRBASE: info->i = cpustate->cregs[CR_DIRBASE]; break;
case CPUINFO_INT_REGISTER + I860_DB: info->i = cpustate->cregs[CR_DB]; break;
case CPUINFO_INT_REGISTER + I860_FSR: info->i = cpustate->cregs[CR_FSR]; break;
case CPUINFO_INT_REGISTER + I860_EPSR: info->i = cpustate->cregs[CR_EPSR]; break;
case CPUINFO_INT_REGISTER + I860_R0: info->i = cpustate->iregs[0]; break;
case CPUINFO_INT_REGISTER + I860_R1: info->i = cpustate->iregs[1]; break;
case CPUINFO_INT_REGISTER + I860_R2: info->i = cpustate->iregs[2]; break;
case CPUINFO_INT_REGISTER + I860_R3: info->i = cpustate->iregs[3]; break;
case CPUINFO_INT_REGISTER + I860_R4: info->i = cpustate->iregs[4]; break;
case CPUINFO_INT_REGISTER + I860_R5: info->i = cpustate->iregs[5]; break;
case CPUINFO_INT_REGISTER + I860_R6: info->i = cpustate->iregs[6]; break;
case CPUINFO_INT_REGISTER + I860_R7: info->i = cpustate->iregs[7]; break;
case CPUINFO_INT_REGISTER + I860_R8: info->i = cpustate->iregs[8]; break;
case CPUINFO_INT_REGISTER + I860_R9: info->i = cpustate->iregs[9]; break;
case CPUINFO_INT_REGISTER + I860_R10: info->i = cpustate->iregs[10]; break;
case CPUINFO_INT_REGISTER + I860_R11: info->i = cpustate->iregs[11]; break;
case CPUINFO_INT_REGISTER + I860_R12: info->i = cpustate->iregs[12]; break;
case CPUINFO_INT_REGISTER + I860_R13: info->i = cpustate->iregs[13]; break;
case CPUINFO_INT_REGISTER + I860_R14: info->i = cpustate->iregs[14]; break;
case CPUINFO_INT_REGISTER + I860_R15: info->i = cpustate->iregs[15]; break;
case CPUINFO_INT_REGISTER + I860_R16: info->i = cpustate->iregs[16]; break;
case CPUINFO_INT_REGISTER + I860_R17: info->i = cpustate->iregs[17]; break;
case CPUINFO_INT_REGISTER + I860_R18: info->i = cpustate->iregs[18]; break;
case CPUINFO_INT_REGISTER + I860_R19: info->i = cpustate->iregs[19]; break;
case CPUINFO_INT_REGISTER + I860_R20: info->i = cpustate->iregs[20]; break;
case CPUINFO_INT_REGISTER + I860_R21: info->i = cpustate->iregs[21]; break;
case CPUINFO_INT_REGISTER + I860_R22: info->i = cpustate->iregs[22]; break;
case CPUINFO_INT_REGISTER + I860_R23: info->i = cpustate->iregs[23]; break;
case CPUINFO_INT_REGISTER + I860_R24: info->i = cpustate->iregs[24]; break;
case CPUINFO_INT_REGISTER + I860_R25: info->i = cpustate->iregs[25]; break;
case CPUINFO_INT_REGISTER + I860_R26: info->i = cpustate->iregs[26]; break;
case CPUINFO_INT_REGISTER + I860_R27: info->i = cpustate->iregs[27]; break;
case CPUINFO_INT_REGISTER + I860_R28: info->i = cpustate->iregs[28]; break;
case CPUINFO_INT_REGISTER + I860_R29: info->i = cpustate->iregs[29]; break;
case CPUINFO_INT_REGISTER + I860_R30: info->i = cpustate->iregs[30]; break;
case CPUINFO_INT_REGISTER + I860_R31: info->i = cpustate->iregs[31]; break;
case CPUINFO_INT_REGISTER + I860_F0: CPU_GET_INFO_INT_F(0); break;
case CPUINFO_INT_REGISTER + I860_F1: CPU_GET_INFO_INT_F(1); break;
case CPUINFO_INT_REGISTER + I860_F2: CPU_GET_INFO_INT_F(2); break;
case CPUINFO_INT_REGISTER + I860_F3: CPU_GET_INFO_INT_F(3); break;
case CPUINFO_INT_REGISTER + I860_F4: CPU_GET_INFO_INT_F(4); break;
case CPUINFO_INT_REGISTER + I860_F5: CPU_GET_INFO_INT_F(5); break;
case CPUINFO_INT_REGISTER + I860_F6: CPU_GET_INFO_INT_F(6); break;
case CPUINFO_INT_REGISTER + I860_F7: CPU_GET_INFO_INT_F(7); break;
case CPUINFO_INT_REGISTER + I860_F8: CPU_GET_INFO_INT_F(8); break;
case CPUINFO_INT_REGISTER + I860_F9: CPU_GET_INFO_INT_F(9); break;
case CPUINFO_INT_REGISTER + I860_F10: CPU_GET_INFO_INT_F(10); break;
case CPUINFO_INT_REGISTER + I860_F11: CPU_GET_INFO_INT_F(11); break;
case CPUINFO_INT_REGISTER + I860_F12: CPU_GET_INFO_INT_F(12); break;
case CPUINFO_INT_REGISTER + I860_F13: CPU_GET_INFO_INT_F(13); break;
case CPUINFO_INT_REGISTER + I860_F14: CPU_GET_INFO_INT_F(14); break;
case CPUINFO_INT_REGISTER + I860_F15: CPU_GET_INFO_INT_F(15); break;
case CPUINFO_INT_REGISTER + I860_F16: CPU_GET_INFO_INT_F(16); break;
case CPUINFO_INT_REGISTER + I860_F17: CPU_GET_INFO_INT_F(17); break;
case CPUINFO_INT_REGISTER + I860_F18: CPU_GET_INFO_INT_F(18); break;
case CPUINFO_INT_REGISTER + I860_F19: CPU_GET_INFO_INT_F(19); break;
case CPUINFO_INT_REGISTER + I860_F20: CPU_GET_INFO_INT_F(20); break;
case CPUINFO_INT_REGISTER + I860_F21: CPU_GET_INFO_INT_F(21); break;
case CPUINFO_INT_REGISTER + I860_F22: CPU_GET_INFO_INT_F(22); break;
case CPUINFO_INT_REGISTER + I860_F23: CPU_GET_INFO_INT_F(23); break;
case CPUINFO_INT_REGISTER + I860_F24: CPU_GET_INFO_INT_F(24); break;
case CPUINFO_INT_REGISTER + I860_F25: CPU_GET_INFO_INT_F(25); break;
case CPUINFO_INT_REGISTER + I860_F26: CPU_GET_INFO_INT_F(26); break;
case CPUINFO_INT_REGISTER + I860_F27: CPU_GET_INFO_INT_F(27); break;
case CPUINFO_INT_REGISTER + I860_F28: CPU_GET_INFO_INT_F(28); break;
case CPUINFO_INT_REGISTER + I860_F29: CPU_GET_INFO_INT_F(29); break;
case CPUINFO_INT_REGISTER + I860_F30: CPU_GET_INFO_INT_F(30); break;
case CPUINFO_INT_REGISTER + I860_F31: CPU_GET_INFO_INT_F(31); break;
/* --- the following bits of info are returned as pointers to data or functions --- */
case CPUINFO_FCT_SET_INFO: info->setinfo = CPU_SET_INFO_NAME(i860); break;
case CPUINFO_FCT_INIT: info->init = CPU_INIT_NAME(i860); break;
case CPUINFO_FCT_RESET: info->reset = CPU_RESET_NAME(i860); break;
case CPUINFO_FCT_EXIT: info->exit = NULL; break;
case CPUINFO_FCT_EXECUTE: info->execute = CPU_EXECUTE_NAME(i860); break;
case CPUINFO_FCT_BURN: info->burn = NULL; break;
case CPUINFO_FCT_DISASSEMBLE: info->disassemble = CPU_DISASSEMBLE_NAME(i860); break;
case CPUINFO_FCT_DEBUG_INIT: info->debug_init = NULL; break;
case CPUINFO_FCT_TRANSLATE: info->translate = NULL; break;
case CPUINFO_FCT_READ: info->read = NULL; break;
case CPUINFO_FCT_WRITE: info->write = NULL; break;
case CPUINFO_FCT_READOP: info->readop = NULL; break;
case CPUINFO_PTR_INSTRUCTION_COUNTER: info->icount = &cpustate->icount; break;
/* --- the following bits of info are returned as NULL-terminated strings --- */
case CPUINFO_STR_NAME: strcpy(info->s, "i860XR"); break;
case CPUINFO_STR_FAMILY: strcpy(info->s, "Intel i860"); break;
case CPUINFO_STR_VERSION: strcpy(info->s, "0.1"); break;
case CPUINFO_STR_SOURCE_FILE: strcpy(info->s, __FILE__); break;
case CPUINFO_STR_CREDITS: strcpy(info->s, "Jason Eckhardt"); break;
case CPUINFO_STR_FLAGS:
strcpy(info->s, ""); break;
case CPUINFO_STR_REGISTER + I860_PC: sprintf(info->s, "PC : %08x", cpustate->pc); break;
case CPUINFO_STR_REGISTER + I860_FIR: sprintf(info->s, "FIR : %08x", cpustate->cregs[CR_FIR]); break;
case CPUINFO_STR_REGISTER + I860_PSR: sprintf(info->s, "PSR : %08x", cpustate->cregs[CR_PSR]); break;
case CPUINFO_STR_REGISTER + I860_DIRBASE: sprintf(info->s, "DIRBASE : %08x", cpustate->cregs[CR_DIRBASE]);break;
case CPUINFO_STR_REGISTER + I860_DB: sprintf(info->s, "DB : %08x", cpustate->cregs[CR_DB]); break;
case CPUINFO_STR_REGISTER + I860_FSR: sprintf(info->s, "FSR : %08x", cpustate->cregs[CR_FSR]); break;
case CPUINFO_STR_REGISTER + I860_EPSR: sprintf(info->s, "EPSR : %08x", cpustate->cregs[CR_EPSR]); break;
case CPUINFO_STR_REGISTER + I860_R0: sprintf(info->s, "R0 : %08x", cpustate->iregs[0]); break;
case CPUINFO_STR_REGISTER + I860_R1: sprintf(info->s, "R1 : %08x", cpustate->iregs[1]); break;
case CPUINFO_STR_REGISTER + I860_R2: sprintf(info->s, "R2 : %08x", cpustate->iregs[2]); break;
case CPUINFO_STR_REGISTER + I860_R3: sprintf(info->s, "R3 : %08x", cpustate->iregs[3]); break;
case CPUINFO_STR_REGISTER + I860_R4: sprintf(info->s, "R4 : %08x", cpustate->iregs[4]); break;
case CPUINFO_STR_REGISTER + I860_R5: sprintf(info->s, "R5 : %08x", cpustate->iregs[5]); break;
case CPUINFO_STR_REGISTER + I860_R6: sprintf(info->s, "R6 : %08x", cpustate->iregs[6]); break;
case CPUINFO_STR_REGISTER + I860_R7: sprintf(info->s, "R7 : %08x", cpustate->iregs[7]); break;
case CPUINFO_STR_REGISTER + I860_R8: sprintf(info->s, "R8 : %08x", cpustate->iregs[8]); break;
case CPUINFO_STR_REGISTER + I860_R9: sprintf(info->s, "R9 : %08x", cpustate->iregs[9]); break;
case CPUINFO_STR_REGISTER + I860_R10: sprintf(info->s, "R10 : %08x", cpustate->iregs[10]); break;
case CPUINFO_STR_REGISTER + I860_R11: sprintf(info->s, "R11 : %08x", cpustate->iregs[11]); break;
case CPUINFO_STR_REGISTER + I860_R12: sprintf(info->s, "R12 : %08x", cpustate->iregs[12]); break;
case CPUINFO_STR_REGISTER + I860_R13: sprintf(info->s, "R13 : %08x", cpustate->iregs[13]); break;
case CPUINFO_STR_REGISTER + I860_R14: sprintf(info->s, "R14 : %08x", cpustate->iregs[14]); break;
case CPUINFO_STR_REGISTER + I860_R15: sprintf(info->s, "R15 : %08x", cpustate->iregs[15]); break;
case CPUINFO_STR_REGISTER + I860_R16: sprintf(info->s, "R16 : %08x", cpustate->iregs[16]); break;
case CPUINFO_STR_REGISTER + I860_R17: sprintf(info->s, "R17 : %08x", cpustate->iregs[17]); break;
case CPUINFO_STR_REGISTER + I860_R18: sprintf(info->s, "R18 : %08x", cpustate->iregs[18]); break;
case CPUINFO_STR_REGISTER + I860_R19: sprintf(info->s, "R19 : %08x", cpustate->iregs[19]); break;
case CPUINFO_STR_REGISTER + I860_R20: sprintf(info->s, "R20 : %08x", cpustate->iregs[20]); break;
case CPUINFO_STR_REGISTER + I860_R21: sprintf(info->s, "R21 : %08x", cpustate->iregs[21]); break;
case CPUINFO_STR_REGISTER + I860_R22: sprintf(info->s, "R22 : %08x", cpustate->iregs[22]); break;
case CPUINFO_STR_REGISTER + I860_R23: sprintf(info->s, "R23 : %08x", cpustate->iregs[23]); break;
case CPUINFO_STR_REGISTER + I860_R24: sprintf(info->s, "R24 : %08x", cpustate->iregs[24]); break;
case CPUINFO_STR_REGISTER + I860_R25: sprintf(info->s, "R25 : %08x", cpustate->iregs[25]); break;
case CPUINFO_STR_REGISTER + I860_R26: sprintf(info->s, "R26 : %08x", cpustate->iregs[26]); break;
case CPUINFO_STR_REGISTER + I860_R27: sprintf(info->s, "R27 : %08x", cpustate->iregs[27]); break;
case CPUINFO_STR_REGISTER + I860_R28: sprintf(info->s, "R28 : %08x", cpustate->iregs[28]); break;
case CPUINFO_STR_REGISTER + I860_R29: sprintf(info->s, "R29 : %08x", cpustate->iregs[29]); break;
case CPUINFO_STR_REGISTER + I860_R30: sprintf(info->s, "R30 : %08x", cpustate->iregs[30]); break;
case CPUINFO_STR_REGISTER + I860_R31: sprintf(info->s, "R31 : %08x", cpustate->iregs[31]); break;
case CPUINFO_STR_REGISTER + I860_F0: CPU_GET_INFO_STR_F(0); break;
case CPUINFO_STR_REGISTER + I860_F1: CPU_GET_INFO_STR_F(1); break;
case CPUINFO_STR_REGISTER + I860_F2: CPU_GET_INFO_STR_F(2); break;
case CPUINFO_STR_REGISTER + I860_F3: CPU_GET_INFO_STR_F(3); break;
case CPUINFO_STR_REGISTER + I860_F4: CPU_GET_INFO_STR_F(4); break;
case CPUINFO_STR_REGISTER + I860_F5: CPU_GET_INFO_STR_F(5); break;
case CPUINFO_STR_REGISTER + I860_F6: CPU_GET_INFO_STR_F(6); break;
case CPUINFO_STR_REGISTER + I860_F7: CPU_GET_INFO_STR_F(7); break;
case CPUINFO_STR_REGISTER + I860_F8: CPU_GET_INFO_STR_F(8); break;
case CPUINFO_STR_REGISTER + I860_F9: CPU_GET_INFO_STR_F(9); break;
case CPUINFO_STR_REGISTER + I860_F10: CPU_GET_INFO_STR_F(10); break;
case CPUINFO_STR_REGISTER + I860_F11: CPU_GET_INFO_STR_F(11); break;
case CPUINFO_STR_REGISTER + I860_F12: CPU_GET_INFO_STR_F(12); break;
case CPUINFO_STR_REGISTER + I860_F13: CPU_GET_INFO_STR_F(13); break;
case CPUINFO_STR_REGISTER + I860_F14: CPU_GET_INFO_STR_F(14); break;
case CPUINFO_STR_REGISTER + I860_F15: CPU_GET_INFO_STR_F(15); break;
case CPUINFO_STR_REGISTER + I860_F16: CPU_GET_INFO_STR_F(16); break;
case CPUINFO_STR_REGISTER + I860_F17: CPU_GET_INFO_STR_F(17); break;
case CPUINFO_STR_REGISTER + I860_F18: CPU_GET_INFO_STR_F(18); break;
case CPUINFO_STR_REGISTER + I860_F19: CPU_GET_INFO_STR_F(19); break;
case CPUINFO_STR_REGISTER + I860_F20: CPU_GET_INFO_STR_F(20); break;
case CPUINFO_STR_REGISTER + I860_F21: CPU_GET_INFO_STR_F(21); break;
case CPUINFO_STR_REGISTER + I860_F22: CPU_GET_INFO_STR_F(22); break;
case CPUINFO_STR_REGISTER + I860_F23: CPU_GET_INFO_STR_F(23); break;
case CPUINFO_STR_REGISTER + I860_F24: CPU_GET_INFO_STR_F(24); break;
case CPUINFO_STR_REGISTER + I860_F25: CPU_GET_INFO_STR_F(25); break;
case CPUINFO_STR_REGISTER + I860_F26: CPU_GET_INFO_STR_F(26); break;
case CPUINFO_STR_REGISTER + I860_F27: CPU_GET_INFO_STR_F(27); break;
case CPUINFO_STR_REGISTER + I860_F28: CPU_GET_INFO_STR_F(28); break;
case CPUINFO_STR_REGISTER + I860_F29: CPU_GET_INFO_STR_F(29); break;
case CPUINFO_STR_REGISTER + I860_F30: CPU_GET_INFO_STR_F(30); break;
case CPUINFO_STR_REGISTER + I860_F31: CPU_GET_INFO_STR_F(31); break;
}
}
DEFINE_LEGACY_CPU_DEVICE(I860, i860);

225
src/emu/cpu/i860/i860.h
View File

@ -46,37 +46,71 @@ enum
}; };
/* Needed for MAME */
DECLARE_LEGACY_CPU_DEVICE(I860, i860);
class i860_cpu_device : public cpu_device
{
public:
// construction/destruction
i860_cpu_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
/*************************************************************************** /* This is the external interface for asserting an external interrupt
STRUCTURES & TYPEDEFS to the i860. */
***************************************************************************/ void i860_gen_interrupt();
/* This is the external interface for asserting/deasserting a pin on
the i860. */
void i860_set_pin(int, int);
/* Hard or soft reset. */
void reset_i860();
protected:
// device-level overrides
virtual void device_start();
virtual void device_reset();
// device_execute_interface overrides
virtual UINT32 execute_min_cycles() const { return 1; }
virtual UINT32 execute_max_cycles() const { return 8; }
virtual UINT32 execute_input_lines() const { return 0; }
virtual void execute_run();
// device_memory_interface overrides
virtual const address_space_config *memory_space_config(address_spacenum spacenum = AS_0) const { return (spacenum == AS_PROGRAM) ? &m_program_config : NULL; }
// device_state_interface overrides
void state_export(const device_state_entry &entry);
void state_import(const device_state_entry &entry);
// device_disasm_interface overrides
virtual UINT32 disasm_min_opcode_bytes() const { return 4; }
virtual UINT32 disasm_max_opcode_bytes() const { return 4; }
virtual offs_t disasm_disassemble(char *buffer, offs_t pc, const UINT8 *oprom, const UINT8 *opram, UINT32 options);
private:
address_space_config m_program_config;
/* i860 state. */
struct i860_state_t {
/* Integer registers (32 x 32-bits). */ /* Integer registers (32 x 32-bits). */
UINT32 iregs[32]; UINT32 m_iregs[32];
/* Floating point registers (32 x 32-bits, 16 x 64 bits, or 8 x 128 bits). /* Floating point registers (32 x 32-bits, 16 x 64 bits, or 8 x 128 bits).
When referenced as pairs or quads, the higher numbered registers When referenced as pairs or quads, the higher numbered registers
are the upper bits. E.g., double precision f0 is f1:f0. */ are the upper bits. E.g., double precision f0 is f1:f0. */
UINT8 frg[32 * 4]; UINT8 m_frg[32 * 4];
/* Control registers (6 x 32-bits). */ /* Control registers (6 x 32-bits). */
UINT32 cregs[6]; UINT32 m_cregs[6];
/* Program counter (1 x 32-bits). Reset starts at pc=0xffffff00. */ /* Program counter (1 x 32-bits). Reset starts at pc=0xffffff00. */
UINT32 pc; UINT32 m_pc;
/* Special registers (4 x 64-bits). */ /* Special registers (4 x 64-bits). */
union union
{ {
float s; float s;
double d; double d;
} KR, KI, T; } m_KR, m_KI, m_T;
UINT64 merge; UINT64 m_merge;
/* The adder pipeline, always 3 stages. */ /* The adder pipeline, always 3 stages. */
struct struct
@ -92,7 +126,7 @@ struct i860_state_t {
/* Adder result precision (1 = dbl, 0 = sgl). */ /* Adder result precision (1 = dbl, 0 = sgl). */
char arp; char arp;
} stat; } stat;
} A[3]; } m_A[3];
/* The multiplier pipeline. 3 stages for single precision, 2 stages /* The multiplier pipeline. 3 stages for single precision, 2 stages
for double precision, and confusing for mixed precision. */ for double precision, and confusing for mixed precision. */
@ -108,7 +142,7 @@ struct i860_state_t {
/* Multiplier result precision (1 = dbl, 0 = sgl). */ /* Multiplier result precision (1 = dbl, 0 = sgl). */
char mrp; char mrp;
} stat; } stat;
} M[3]; } m_M[3];
/* The load pipeline, always 3 stages. */ /* The load pipeline, always 3 stages. */
struct { struct {
@ -123,7 +157,7 @@ struct i860_state_t {
/* Load result precision (1 = dbl, 0 = sgl). */ /* Load result precision (1 = dbl, 0 = sgl). */
char lrp; char lrp;
} stat; } stat;
} L[3]; } m_L[3];
/* The graphics/integer pipeline, always 1 stage. */ /* The graphics/integer pipeline, always 1 stage. */
struct { struct {
@ -138,65 +172,141 @@ struct i860_state_t {
/* Integer/graphics result precision (1 = dbl, 0 = sgl). */ /* Integer/graphics result precision (1 = dbl, 0 = sgl). */
char irp; char irp;
} stat; } stat;
} G; } m_G;
/* Pins. */ /* Pins. */
int pin_bus_hold; int m_pin_bus_hold;
int pin_reset; int m_pin_reset;
/* /*
* Other emulator state. * Other emulator state.
*/ */
int exiting_readmem; int m_exiting_readmem;
int exiting_ifetch; int m_exiting_ifetch;
/* Indicate a control-flow instruction, so we know the PC is updated. */ /* Indicate a control-flow instruction, so we know the PC is updated. */
int pc_updated; int m_pc_updated;
/* Indicate an instruction just generated a trap, so we know the PC /* Indicate an instruction just generated a trap, so we know the PC
needs to go to the trap address. */ needs to go to the trap address. */
int pending_trap; int m_pending_trap;
/* This is 1 if the next fir load gets the trap address, otherwise /* This is 1 if the next fir load gets the trap address, otherwise
it is 0 to get the ld.c address. This is set to 1 only when a it is 0 to get the ld.c address. This is set to 1 only when a
non-reset trap occurs. */ non-reset trap occurs. */
int fir_gets_trap_addr; int m_fir_gets_trap_addr;
/* Single stepping flag for internal use. */ /* Single stepping flag for internal use. */
int single_stepping; int m_single_stepping;
/* /*
* MAME-specific stuff. * MAME-specific stuff.
*/ */
legacy_cpu_device *device; address_space *m_program;
address_space *program; UINT32 m_ppc;
UINT32 ppc; int m_icount;
int icount; // For debugger
UINT32 m_freg[32];
void writememi_emu (UINT32 addr, int size, UINT32 data);
void fp_readmem_emu (UINT32 addr, int size, UINT8 *dest);
void fp_writemem_emu (UINT32 addr, int size, UINT8 *data, UINT32 wmask);
void dump_pipe (int type);
void dump_state ();
void unrecog_opcode (UINT32 pc, UINT32 insn);
void insn_ld_ctrl (UINT32 insn);
void insn_st_ctrl (UINT32 insn);
void insn_ldx (UINT32 insn);
void insn_stx (UINT32 insn);
void insn_fsty (UINT32 insn);
void insn_fldy (UINT32 insn);
void insn_pstd (UINT32 insn);
void insn_ixfr (UINT32 insn);
void insn_addu (UINT32 insn);
void insn_addu_imm (UINT32 insn);
void insn_adds (UINT32 insn);
void insn_adds_imm (UINT32 insn);
void insn_subu (UINT32 insn);
void insn_subu_imm (UINT32 insn);
void insn_subs (UINT32 insn);
void insn_subs_imm (UINT32 insn);
void insn_shl (UINT32 insn);
void insn_shl_imm (UINT32 insn);
void insn_shr (UINT32 insn);
void insn_shr_imm (UINT32 insn);
void insn_shra (UINT32 insn);
void insn_shra_imm (UINT32 insn);
void insn_shrd (UINT32 insn);
void insn_and (UINT32 insn);
void insn_and_imm (UINT32 insn);
void insn_andh_imm (UINT32 insn);
void insn_andnot (UINT32 insn);
void insn_andnot_imm (UINT32 insn);
void insn_andnoth_imm (UINT32 insn);
void insn_or (UINT32 insn);
void insn_or_imm (UINT32 insn);
void insn_orh_imm (UINT32 insn);
void insn_xor (UINT32 insn);
void insn_xor_imm (UINT32 insn);
void insn_xorh_imm (UINT32 insn);
void insn_trap (UINT32 insn);
void insn_intovr (UINT32 insn);
void insn_bte (UINT32 insn);
void insn_bte_imm (UINT32 insn);
void insn_btne (UINT32 insn);
void insn_btne_imm (UINT32 insn);
void insn_bc (UINT32 insn);
void insn_bnc (UINT32 insn);
void insn_bct (UINT32 insn);
void insn_bnct (UINT32 insn);
void insn_call (UINT32 insn);
void insn_br (UINT32 insn);
void insn_bri (UINT32 insn);
void insn_calli (UINT32 insn);
void insn_bla (UINT32 insn);
void insn_flush (UINT32 insn);
void insn_fmul (UINT32 insn);
void insn_fmlow (UINT32 insn);
void insn_fadd_sub (UINT32 insn);
void insn_dualop (UINT32 insn);
void insn_frcp (UINT32 insn);
void insn_frsqr (UINT32 insn);
void insn_fxfr (UINT32 insn);
void insn_ftrunc (UINT32 insn);
void insn_famov (UINT32 insn);
void insn_fiadd_sub (UINT32 insn);
void insn_fcmp (UINT32 insn);
void insn_fzchk (UINT32 insn);
void insn_form (UINT32 insn);
void insn_faddp (UINT32 insn);
void insn_faddz (UINT32 insn);
void decode_exec (UINT32 insn, UINT32 non_shadow);
void disasm (UINT32 addr, int len);
void dbg_db (UINT32 addr, int len);
float get_fregval_s (int fr);
double get_fregval_d (int fr);
void set_fregval_s (int fr, float s);
void set_fregval_d (int fr, double d);
int has_delay_slot(UINT32 insn);
UINT32 ifetch (UINT32 pc);
UINT32 get_address_translation (UINT32 vaddr, int is_dataref, int is_write);
UINT32 readmemi_emu (UINT32 addr, int size);
float get_fval_from_optype_s (UINT32 insn, int optype);
double get_fval_from_optype_d (UINT32 insn, int optype);
typedef void (i860_cpu_device::*insn_func)(UINT32);
struct decode_tbl_t
{
/* Execute function for this opcode. */
insn_func insn_exec;
/* Flags for this opcode. */
char flags;
};
static const decode_tbl_t decode_tbl[64];
static const decode_tbl_t core_esc_decode_tbl[8];
static const decode_tbl_t fp_decode_tbl[128];
}; };
INLINE i860_state_t *get_safe_token(device_t *device)
{
assert(device != NULL);
assert(device->type() == I860);
return (i860_state_t *)downcast<legacy_cpu_device *>(device)->token();
}
/***************************************************************************
PUBLIC FUNCTIONS
***************************************************************************/
/* This is the external interface for asserting an external interrupt
to the i860. */
extern void i860_gen_interrupt(i860_state_t*);
/* This is the external interface for asserting/deasserting a pin on
the i860. */
extern void i860_set_pin(device_t *, int, int);
/* Hard or soft reset. */
extern void reset_i860(i860_state_t*);
/* i860 pins. */ /* i860 pins. */
enum { enum {
@ -205,18 +315,7 @@ enum {
}; };
/* TODO: THESE WILL BE REPLACED BY MAME FUNCTIONS extern const device_type I860;
#define BYTE_REV32(t) \
do { \
(t) = ((UINT32)(t) >> 16) | ((UINT32)(t) << 16); \
(t) = (((UINT32)(t) >> 8) & 0x00ff00ff) | (((UINT32)(t) << 8) & 0xff00ff00); \
} while (0);
#define BYTE_REV16(t) \
do { \
(t) = (((UINT16)(t) >> 8) & 0x00ff) | (((UINT16)(t) << 8) & 0xff00); \
} while (0);
#endif
*/
#endif /* __I860_H__ */ #endif /* __I860_H__ */

1705
src/emu/cpu/i860/i860dec.c
View File

File diff suppressed because it is too large Load Diff

30
src/mame/drivers/vcombat.c
View File

@ -101,6 +101,8 @@ public:
m_framebuffer_ctrl(*this, "fb_control"), m_framebuffer_ctrl(*this, "fb_control"),
m_maincpu(*this, "maincpu"), m_maincpu(*this, "maincpu"),
m_soundcpu(*this, "soundcpu"), m_soundcpu(*this, "soundcpu"),
m_vid_0(*this, "vid_0"),
m_vid_1(*this, "vid_1"),
m_dac(*this, "dac") { } m_dac(*this, "dac") { }
UINT16* m_m68k_framebuffer[2]; UINT16* m_m68k_framebuffer[2];
@ -133,6 +135,8 @@ public:
UINT32 screen_update_vcombat_aux(screen_device &screen, bitmap_rgb32 &bitmap, const rectangle &cliprect); UINT32 screen_update_vcombat_aux(screen_device &screen, bitmap_rgb32 &bitmap, const rectangle &cliprect);
required_device<cpu_device> m_maincpu; required_device<cpu_device> m_maincpu;
required_device<cpu_device> m_soundcpu; required_device<cpu_device> m_soundcpu;
required_device<i860_cpu_device> m_vid_0;
optional_device<i860_cpu_device> m_vid_1;
required_device<dac_device> m_dac; required_device<dac_device> m_dac;
}; };
@ -228,7 +232,7 @@ READ16_MEMBER(vcombat_state::control_3_r)
return (ioport("IN2")->read() << 8); return (ioport("IN2")->read() << 8);
} }
static void wiggle_i860_common(device_t *device, UINT16 data) static void wiggle_i860_common(i860_cpu_device *device, UINT16 data)
{ {
int bus_hold = (data & 0x03) == 0x03; int bus_hold = (data & 0x03) == 0x03;
int reset = data & 0x10; int reset = data & 0x10;
@ -238,31 +242,31 @@ static void wiggle_i860_common(device_t *device, UINT16 data)
if (bus_hold) if (bus_hold)
{ {
fprintf(stderr, "M0 asserting bus HOLD to i860 %s\n", device->tag()); fprintf(stderr, "M0 asserting bus HOLD to i860 %s\n", device->tag());
i860_set_pin(device, DEC_PIN_BUS_HOLD, 1); device->i860_set_pin(DEC_PIN_BUS_HOLD, 1);
} }
else else
{ {
fprintf(stderr, "M0 clearing bus HOLD to i860 %s\n", device->tag()); fprintf(stderr, "M0 clearing bus HOLD to i860 %s\n", device->tag());
i860_set_pin(device, DEC_PIN_BUS_HOLD, 0); device->i860_set_pin(DEC_PIN_BUS_HOLD, 0);
} }
if (reset) if (reset)
{ {
fprintf(stderr, "M0 asserting RESET to i860 %s\n", device->tag()); fprintf(stderr, "M0 asserting RESET to i860 %s\n", device->tag());
i860_set_pin(device, DEC_PIN_RESET, 1); device->i860_set_pin(DEC_PIN_RESET, 1);
} }
else else
i860_set_pin(device, DEC_PIN_RESET, 0); device->i860_set_pin(DEC_PIN_RESET, 0);
} }
WRITE16_MEMBER(vcombat_state::wiggle_i860p0_pins_w) WRITE16_MEMBER(vcombat_state::wiggle_i860p0_pins_w)
{ {
wiggle_i860_common(machine().device("vid_0"), data); wiggle_i860_common(m_vid_0, data);
} }
WRITE16_MEMBER(vcombat_state::wiggle_i860p1_pins_w) WRITE16_MEMBER(vcombat_state::wiggle_i860p1_pins_w)
{ {
wiggle_i860_common(machine().device("vid_1"), data); wiggle_i860_common(m_vid_1, data);
} }
READ16_MEMBER(vcombat_state::main_irqiack_r) READ16_MEMBER(vcombat_state::main_irqiack_r)
@ -415,15 +419,15 @@ ADDRESS_MAP_END
MACHINE_RESET_MEMBER(vcombat_state,vcombat) MACHINE_RESET_MEMBER(vcombat_state,vcombat)
{ {
i860_set_pin(machine().device("vid_0"), DEC_PIN_BUS_HOLD, 1); m_vid_0->i860_set_pin(DEC_PIN_BUS_HOLD, 1);
i860_set_pin(machine().device("vid_1"), DEC_PIN_BUS_HOLD, 1); m_vid_1->i860_set_pin(DEC_PIN_BUS_HOLD, 1);
m_crtc_select = 0; m_crtc_select = 0;
} }
MACHINE_RESET_MEMBER(vcombat_state,shadfgtr) MACHINE_RESET_MEMBER(vcombat_state,shadfgtr)
{ {
i860_set_pin(machine().device("vid_0"), DEC_PIN_BUS_HOLD, 1); m_vid_0->i860_set_pin(DEC_PIN_BUS_HOLD, 1);
m_crtc_select = 0; m_crtc_select = 0;
} }
@ -455,10 +459,10 @@ DRIVER_INIT_MEMBER(vcombat_state,vcombat)
UINT8 *ROM = memregion("maincpu")->base(); UINT8 *ROM = memregion("maincpu")->base();
/* The two i860s execute out of RAM */ /* The two i860s execute out of RAM */
address_space &v0space = machine().device<i860_device>("vid_0")->space(AS_PROGRAM); address_space &v0space = m_vid_0->space(AS_PROGRAM);
v0space.set_direct_update_handler(direct_update_delegate(FUNC(vcombat_state::vcombat_vid_0_direct_handler), this)); v0space.set_direct_update_handler(direct_update_delegate(FUNC(vcombat_state::vcombat_vid_0_direct_handler), this));
address_space &v1space = machine().device<i860_device>("vid_1")->space(AS_PROGRAM); address_space &v1space = m_vid_1->space(AS_PROGRAM);
v1space.set_direct_update_handler(direct_update_delegate(FUNC(vcombat_state::vcombat_vid_1_direct_handler), this)); v1space.set_direct_update_handler(direct_update_delegate(FUNC(vcombat_state::vcombat_vid_1_direct_handler), this));
/* Allocate the 68000 framebuffers */ /* Allocate the 68000 framebuffers */
@ -502,7 +506,7 @@ DRIVER_INIT_MEMBER(vcombat_state,shadfgtr)
m_i860_framebuffer[1][1] = NULL; m_i860_framebuffer[1][1] = NULL;
/* The i860 executes out of RAM */ /* The i860 executes out of RAM */
address_space &space = machine().device<i860_device>("vid_0")->space(AS_PROGRAM); address_space &space = m_vid_0->space(AS_PROGRAM);
space.set_direct_update_handler(direct_update_delegate(FUNC(vcombat_state::vcombat_vid_0_direct_handler), this)); space.set_direct_update_handler(direct_update_delegate(FUNC(vcombat_state::vcombat_vid_0_direct_handler), this));
} }