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https://github.com/holub/mame
synced 2025-07-05 18:08:04 +03:00
sun4: pass 4/75 tests until MMU fault trap (nw)
This commit is contained in:
arbee
parent
97b08fe184
commit
a92cd6a8e3
@ -554,7 +554,7 @@ protected:
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UINT32 *m_rom_ptr;
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UINT32 m_context;
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UINT8 m_system_enable;
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UINT32 m_buserror[4];
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UINT32 m_buserr[4];
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UINT32 m_counter[4];
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private:
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@ -562,6 +562,7 @@ private:
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UINT8 m_segmap[16][4096];
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UINT32 m_pagemap[16384];
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UINT32 m_cachetags[0x4000];
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UINT32 m_cachedata[0x4000];
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UINT32 m_ram_size, m_ram_size_words;
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UINT8 m_ctx_mask; // SS2 is sun4c but has 16 contexts; most have 8
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UINT8 m_pmeg_mask; // SS2 is sun4c but has 16384 PTEs; most have 8192
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@ -609,6 +610,7 @@ READ32_MEMBER( sun4_state::sun4c_mmu_r )
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{
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UINT8 asi = m_maincpu->get_asi();
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int page;
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UINT32 retval = 0;
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// make debugger fetches emulate supervisor program for best compatibility with boot PROM execution
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if (space.debugger_access()) asi = 9;
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@ -632,16 +634,19 @@ READ32_MEMBER( sun4_state::sun4c_mmu_r )
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return m_system_enable<<24;
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case 6: // bus error register
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//printf("sun4c: read buserror, PC=%x (mask %08x)\n", m_maincpu->pc(), mem_mask);
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return 0;
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printf("sun4c: read buserror, PC=%x (mask %08x)\n", m_maincpu->pc(), mem_mask);
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m_maincpu->set_input_line(SPARC_MAE, CLEAR_LINE);
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retval = m_buserr[offset & 0xf];
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m_buserr[offset & 0xf] = 0; // clear on reading
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return retval;
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case 8: // (d-)cache tags
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//logerror("sun4: read dcache tags @ %x, PC = %x\n", offset, m_maincpu->pc());
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return m_cachetags[offset&0xfff];
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return m_cachetags[(offset>>3)&0x3fff];
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case 9: // (d-)cache data
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logerror("sun4c: read dcache data @ %x, PC = %x\n", offset, m_maincpu->pc());
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return 0xffffffff;
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//logerror("sun4c: read dcache data @ %x, PC = %x\n", offset, m_maincpu->pc());
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return m_cachedata[offset&0x3fff];
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case 0xf: // UART bypass
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//printf("read UART bypass @ %x mask %08x\n", offset<<2, mem_mask);
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@ -724,8 +729,8 @@ READ32_MEMBER( sun4_state::sun4c_mmu_r )
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{
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printf("sun4c: INVALID PTE entry %d %08x accessed! vaddr=%x PC=%x\n", entry, m_pagemap[entry], offset <<2, m_maincpu->pc());
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//m_maincpu->trap(SPARC_DATA_ACCESS_EXCEPTION);
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//m_buserror[0] = 0x88; // read, invalid PTE
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//m_buserror[1] = offset<<2;
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//m_buserr[0] = 0x88; // read, invalid PTE
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//m_buserr[1] = offset<<2;
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}
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return 0;
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}
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@ -762,15 +767,27 @@ WRITE32_MEMBER( sun4_state::sun4c_mmu_w )
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case 4: // system enable reg
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m_system_enable = data>>24;
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//printf("%08x to system enable, mask %08x\n", data, mem_mask);
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if (m_system_enable & ENA_RESET)
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{
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m_system_enable = 0;
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m_maincpu->set_input_line(INPUT_LINE_RESET, ASSERT_LINE);
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m_maincpu->set_input_line(INPUT_LINE_RESET, CLEAR_LINE);
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}
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return;
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case 6: // bus error
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printf("%08x to bus error @ %x, mask %08x\n", data, offset, mem_mask);
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m_buserr[offset & 0xf] = data;
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return;
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case 8: // cache tags
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//logerror("sun4: %08x to cache tags @ %x, PC = %x\n", data, offset, m_maincpu->pc());
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m_cachetags[offset&0xfff] = data;
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m_cachetags[(offset>>3)&0x3fff] = data & 0x03f8fffc;
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return;
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case 9: // cache data
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logerror("sun4c: %08x to cache data @ %x, PC = %x\n", data, offset, m_maincpu->pc());
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//logerror("sun4c: %08x to cache data @ %x, PC = %x\n", data, offset, m_maincpu->pc());
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m_cachedata[offset&0x3fff] = data;
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return;
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case 0xf: // UART bypass
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@ -818,12 +835,22 @@ WRITE32_MEMBER( sun4_state::sun4c_mmu_w )
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if (m_pagemap[entry] & PM_VALID)
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{
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m_pagemap[entry] |= PM_ACCESSED;
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if ((!(m_pagemap[entry] & PM_WRITEMASK)) ||
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((m_pagemap[entry] & PM_SYSMASK) && !(asi & 1)))
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{
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printf("sun4c: write protect MMU error (PC=%x)\n", m_maincpu->pc());
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m_buserr[0] = 0x8040; // write, protection error
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m_buserr[1] = offset<<2;
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m_maincpu->set_input_line(SPARC_MAE, ASSERT_LINE);
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return;
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}
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m_pagemap[entry] |= (PM_ACCESSED | PM_MODIFIED);
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UINT32 tmp = (m_pagemap[entry] & 0xffff) << 10;
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tmp |= (offset & 0x3ff);
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//printf("sun4: write translated vaddr %08x to phys %08x type %d, PTE %08x, PC=%x\n", offset<<2, tmp<<2, (m_pagemap[entry]>>26) & 3, m_pagemap[entry], m_maincpu->pc());
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printf("sun4: write translated vaddr %08x to phys %08x type %d, PTE %08x, ASI %d, PC=%x\n", offset<<2, tmp<<2, (m_pagemap[entry]>>26) & 3, m_pagemap[entry], asi, m_maincpu->pc());
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switch ((m_pagemap[entry] >> 26) & 3)
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{
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@ -844,8 +871,8 @@ WRITE32_MEMBER( sun4_state::sun4c_mmu_w )
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{
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printf("sun4c: INVALID PTE entry %d %08x accessed! vaddr=%x PC=%x\n", entry, m_pagemap[entry], offset <<2, m_maincpu->pc());
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//m_maincpu->trap(SPARC_DATA_ACCESS_EXCEPTION);
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//m_buserror[0] = 0x8; // invalid PTE
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//m_buserror[1] = offset<<2;
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//m_buserr[0] = 0x8; // invalid PTE
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//m_buserr[1] = offset<<2;
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return;
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}
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break;
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@ -978,8 +1005,8 @@ READ32_MEMBER( sun4_state::sun4_mmu_r )
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{
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printf("sun4: INVALID PTE entry %d %08x accessed! vaddr=%x PC=%x\n", entry, m_pagemap[entry], offset <<2, m_maincpu->pc());
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//m_maincpu->trap(SPARC_DATA_ACCESS_EXCEPTION);
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//m_buserror[0] = 0x88; // read, invalid PTE
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//m_buserror[1] = offset<<2;
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//m_buserr2qor[0] = 0x88; // read, invalid PTE
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//m_buserr[1] = offset<<2;
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}
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return 0;
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}
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@ -1016,6 +1043,12 @@ WRITE32_MEMBER( sun4_state::sun4_mmu_w )
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case 4: // system enable reg
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m_system_enable = data>>24;
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//printf("%08x to system enable, mask %08x\n", data, mem_mask);
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if (m_system_enable & ENA_RESET)
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{
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m_system_enable = 0;
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m_maincpu->set_input_line(INPUT_LINE_RESET, ASSERT_LINE);
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m_maincpu->set_input_line(INPUT_LINE_RESET, CLEAR_LINE);
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}
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return;
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case 7: // diag reg
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@ -1320,7 +1353,6 @@ static ADDRESS_MAP_START(type1space_map, AS_PROGRAM, 32, sun4_state)
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AM_RANGE(0x03000000, 0x0300000f) AM_READWRITE(timer_r, timer_w) AM_MIRROR(0xfffff0)
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AM_RANGE(0x05000000, 0x05000003) AM_READWRITE8(irq_r, irq_w, 0xffffffff)
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AM_RANGE(0x06000000, 0x0607ffff) AM_ROM AM_REGION("user1", 0)
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// AM_RANGE(0x07200000, 0x07200007) AM_DEVICE8(FDC_TAG, n82077aa_device, map, 0xffffffff)
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AM_RANGE(0x07200000, 0x07200003) AM_READWRITE8(fdc_r, fdc_w, 0xffffffff)
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AM_RANGE(0x08000000, 0x08000003) AM_READ(ss1_sl0_id) // slot 0 contains SCSI/DMA/Ethernet
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AM_RANGE(0x0e000000, 0x0e000003) AM_READ(ss1_sl3_id) // slot 3 contains video board
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