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https://github.com/holub/mame
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nds: added WRAM banking and more mirroring. [R. Belmont]
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arbee
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commit
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@ -2,7 +2,7 @@
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// copyright-holders:Ryan Holtz
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/***************************************************************************
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ds.cpp
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nds.cpp
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Skeleton driver for first-generation Nintendo DS.
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@ -33,12 +33,19 @@ READ32_MEMBER(nds_state::arm7_io_r)
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case IPCSYNC_OFFSET:
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return m_arm7_ipcsync;
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case GAMECARD_BUS_CTRL_OFFSET:
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return 0xffffffff;
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case POSTFLG_OFFSET:
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/* Bit Use
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* 0 0=Booting, 1=Booted (set by BIOS/firmware)
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*/
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return m_arm7_postflg;
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case WRAMSTAT_OFFSET:
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printf("ARM7: read WRAMSTAT mask %08x\n", mem_mask);
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return m_wramcnt;
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default:
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verboselog(*this, 0, "[ARM7] [IO] Unknown read: %08x (%08x)\n", offset*4, mem_mask);
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break;
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@ -108,6 +115,12 @@ WRITE32_MEMBER(nds_state::arm9_io_w)
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m_arm9_ipcsync |= (data & ~0xf);
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break;
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case WRAMCNT_OFFSET:
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m_wramcnt = (data>>24) & 0x3;
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m_arm7wrambnk->set_bank(m_wramcnt);
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m_arm9wrambnk->set_bank(m_wramcnt);
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break;
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case POSTFLG_OFFSET:
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/* Bit Use
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* 0 0=Booting, 1=Booted (set by BIOS/firmware)
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@ -130,17 +143,45 @@ WRITE32_MEMBER(nds_state::arm9_io_w)
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static ADDRESS_MAP_START( nds_arm7_map, AS_PROGRAM, 32, nds_state )
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AM_RANGE(0x00000000, 0x00003fff) AM_ROM AM_REGION("arm7", 0)
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AM_RANGE(0x02000000, 0x023fffff) AM_RAM AM_MIRROR(0x00400000) AM_SHARE("mainram")
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AM_RANGE(0x03800000, 0x0380ffff) AM_RAM
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AM_RANGE(0x03000000, 0x03007fff) AM_DEVICE("nds7wram", address_map_bank_device, amap32) AM_MIRROR(0x007f0000)
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AM_RANGE(0x03800000, 0x0380ffff) AM_RAM AM_MIRROR(0x007f0000) AM_SHARE("arm7ram")
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AM_RANGE(0x04000000, 0x0400ffff) AM_READWRITE(arm7_io_r, arm7_io_w)
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ADDRESS_MAP_END
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static ADDRESS_MAP_START( nds_arm9_map, AS_PROGRAM, 32, nds_state )
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AM_RANGE(0x00000000, 0x00007fff) AM_RAM // Instruction TCM
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AM_RANGE(0x02000000, 0x023fffff) AM_RAM AM_MIRROR(0x00400000) AM_SHARE("mainram")
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AM_RANGE(0x03000000, 0x03007fff) AM_DEVICE("nds9wram", address_map_bank_device, amap32) AM_MIRROR(0x00ff0000)
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AM_RANGE(0x04000000, 0x0400ffff) AM_READWRITE(arm9_io_r, arm9_io_w)
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AM_RANGE(0xffff0000, 0xffff0fff) AM_ROM AM_MIRROR(0x1000) AM_REGION("arm9", 0)
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ADDRESS_MAP_END
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// ARM7 views of WRAM
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static ADDRESS_MAP_START( nds7_wram_map, AS_PROGRAM, 32, nds_state )
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AM_RANGE(0x00000, 0x07fff) AM_READWRITE(wram_arm7mirror_r, wram_arm7mirror_w)
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AM_RANGE(0x08000, 0x0bfff) AM_READWRITE(wram_first_half_r, wram_first_half_w)
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AM_RANGE(0x0c000, 0x0ffff) AM_READWRITE(wram_first_half_r, wram_first_half_w)
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AM_RANGE(0x10000, 0x13fff) AM_READWRITE(wram_second_half_r, wram_second_half_w)
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AM_RANGE(0x14000, 0x17fff) AM_READWRITE(wram_second_half_r, wram_second_half_w)
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AM_RANGE(0x18000, 0x1ffff) AM_READWRITE(wram_first_half_r, wram_first_half_w)
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ADDRESS_MAP_END
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// ARM9 views of WRAM
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static ADDRESS_MAP_START( nds9_wram_map, AS_PROGRAM, 32, nds_state )
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AM_RANGE(0x00000, 0x07fff) AM_READWRITE(wram_first_half_r, wram_first_half_w)
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AM_RANGE(0x08000, 0x0bfff) AM_READWRITE(wram_second_half_r, wram_second_half_w)
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AM_RANGE(0x0c000, 0x0ffff) AM_READWRITE(wram_second_half_r, wram_second_half_w)
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AM_RANGE(0x10000, 0x13fff) AM_READWRITE(wram_first_half_r, wram_first_half_w)
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AM_RANGE(0x14000, 0x17fff) AM_READWRITE(wram_first_half_r, wram_first_half_w)
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AM_RANGE(0x18000, 0x1ffff) AM_NOP AM_WRITENOP // probably actually open bus? GBATEK describes as "random"
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ADDRESS_MAP_END
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READ32_MEMBER(nds_state::wram_first_half_r) { return m_WRAM[offset]; }
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READ32_MEMBER(nds_state::wram_second_half_r) { return m_WRAM[offset+0x4000]; }
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WRITE32_MEMBER(nds_state::wram_first_half_w) { COMBINE_DATA(&m_WRAM[offset]); }
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WRITE32_MEMBER(nds_state::wram_second_half_w) { COMBINE_DATA(&m_WRAM[offset+0x4000]); }
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READ32_MEMBER(nds_state::wram_arm7mirror_r) { return m_arm7ram[offset]; }
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WRITE32_MEMBER(nds_state::wram_arm7mirror_w) { COMBINE_DATA(&m_arm7ram[offset]); }
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static INPUT_PORTS_START( nds )
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INPUT_PORTS_END
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@ -149,6 +190,9 @@ void nds_state::machine_reset()
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{
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m_arm7_postflg = 0;
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m_arm9_postflg = 0;
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m_wramcnt = 0;
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m_arm7wrambnk->set_bank(0);
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m_arm9wrambnk->set_bank(0);
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}
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void nds_state::machine_start()
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@ -163,6 +207,18 @@ static MACHINE_CONFIG_START( nds )
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MCFG_ARM_HIGH_VECTORS()
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MCFG_CPU_PROGRAM_MAP(nds_arm9_map)
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// WRAM
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MCFG_DEVICE_ADD("nds7wram", ADDRESS_MAP_BANK, 0)
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MCFG_DEVICE_PROGRAM_MAP(nds7_wram_map)
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MCFG_ADDRESS_MAP_BANK_ENDIANNESS(ENDIANNESS_LITTLE)
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MCFG_ADDRESS_MAP_BANK_DATABUS_WIDTH(32)
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MCFG_ADDRESS_MAP_BANK_STRIDE(0x8000)
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MCFG_DEVICE_ADD("nds9wram", ADDRESS_MAP_BANK, 0)
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MCFG_DEVICE_PROGRAM_MAP(nds9_wram_map)
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MCFG_ADDRESS_MAP_BANK_ENDIANNESS(ENDIANNESS_LITTLE)
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MCFG_ADDRESS_MAP_BANK_DATABUS_WIDTH(32)
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MCFG_ADDRESS_MAP_BANK_STRIDE(0x8000)
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MACHINE_CONFIG_END
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/* Help identifying the region and revisions of the set would be greatly appreciated! */
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@ -1,10 +1,13 @@
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// license:BSD-3-Clause
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// copyright-holders:Ryan Holtz
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#pragma once
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#ifndef INCLUDES_NDS_H
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#define INCLUDES_NDS_H
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#include "cpu/arm7/arm7.h"
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#include "cpu/arm7/arm7core.h"
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#include "machine/bankdev.h"
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#include "machine/timer.h"
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class nds_state : public driver_device
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{
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@ -13,7 +16,10 @@ public:
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: driver_device(mconfig, type, tag),
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m_arm7(*this, "arm7"),
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m_arm9(*this, "arm9"),
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m_firmware(*this, "firmware")
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m_firmware(*this, "firmware"),
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m_arm7wrambnk(*this, "nds7wram"),
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m_arm9wrambnk(*this, "nds9wram"),
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m_arm7ram(*this, "arm7ram")
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{ }
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void machine_start() override;
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@ -27,14 +33,25 @@ public:
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DECLARE_READ32_MEMBER(arm9_io_r);
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DECLARE_WRITE32_MEMBER(arm9_io_w);
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DECLARE_READ32_MEMBER(wram_first_half_r);
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DECLARE_READ32_MEMBER(wram_second_half_r);
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DECLARE_WRITE32_MEMBER(wram_first_half_w);
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DECLARE_WRITE32_MEMBER(wram_second_half_w);
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DECLARE_READ32_MEMBER(wram_arm7mirror_r);
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DECLARE_WRITE32_MEMBER(wram_arm7mirror_w);
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protected:
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required_device<arm7_cpu_device> m_arm7;
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required_device<arm946es_cpu_device> m_arm9;
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required_region_ptr<uint32_t> m_firmware;
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required_device<address_map_bank_device> m_arm7wrambnk, m_arm9wrambnk;
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required_shared_ptr<uint32_t> m_arm7ram;
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enum {
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IPCSYNC_OFFSET = 0x180/4,
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GAMECARD_BUS_CTRL_OFFSET = 0x1a4/4,
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WRAMSTAT_OFFSET = 0x241/4,
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WRAMCNT_OFFSET = 0x247/4,
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POSTFLG_OFFSET = 0x300/4,
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POSTFLG_PBF_SHIFT = 0,
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POSTFLG_RAM_SHIFT = 1,
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@ -45,6 +62,8 @@ protected:
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uint32_t m_arm7_postflg;
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uint32_t m_arm9_postflg;
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uint16_t m_arm7_ipcsync, m_arm9_ipcsync;
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uint8_t m_WRAM[0x8000];
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uint8_t m_wramcnt;
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};
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#endif // INCLUDES_NDS_H
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