sync pc/ar/curpc (nw)
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@ -28,10 +28,10 @@
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#define DST_IS_RIGHT_BANK (opcode & 0x0008)
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#define SRC_LSB ((opcode & 0x0700) >> 8)
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#define DST_LSB (opcode & 0x0007)
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#define SET_PC(x) do { m_PC = (x); m_AR = m_PC; m_genPC = m_PC << 1; } while (0)
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#define SET_PC(x) do { m_PC = (x); m_AR = m_PC; } while (0)
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// for XEC intruction, which sets the AR, but not PC, so that after the instruction at the relative address is done, execution
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// returns back to next instruction after XEC, unless a JMP or successful NZT is there.
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#define SET_AR(x) do { m_AR = (x); m_genPC = m_AR << 1; m_PC--;} while (0)
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#define SET_AR(x) do { m_AR = (x); m_increment_pc = false; } while (0)
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#define SRC_LATCH do { if(SRC_IS_RIGHT_BANK) m_right_IV = READPORT(m_IVR+0x100); else m_left_IV = READPORT(m_IVL); } while (0)
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#define DST_LATCH do { if(DST_IS_RIGHT_BANK) m_right_IV = READPORT(m_IVR+0x100); else m_left_IV = READPORT(m_IVL); } while (0)
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#define SET_OVF do { if(result & 0xff00) m_OVF = 1; else m_OVF = 0; } while (0)
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@ -106,6 +106,8 @@ void n8x300_cpu_device::device_start()
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save_item(NAME(m_OVF));
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save_item(NAME(m_left_IV));
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save_item(NAME(m_right_IV));
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save_item(NAME(m_genPC));
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save_item(NAME(m_increment_pc));
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// reset registers here, since they are unchanged when /RESET goes low.
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m_R1 = 0;
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@ -119,15 +121,12 @@ void n8x300_cpu_device::device_start()
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m_IVR = 0;
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m_AUX = 0;
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m_PC = 0;
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m_AR = 0;
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m_IR = 0;
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m_OVF = 0;
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m_genPC = 0;
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// Register state for debugger
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state_add( _8X300_PC, "PC", m_PC).mask(0x1fff).formatstr("%04X");
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state_add( _8X300_AR, "AR", m_AR).mask(0x1fff).formatstr("%04X");
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state_add( _8X300_PC, "PC", m_PC).mask(0x1fff).callimport().formatstr("%04X");
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state_add( _8X300_AR, "AR", m_AR).mask(0x1fff).callimport().formatstr("%04X");
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state_add( _8X300_IR, "IR", m_IR).mask(0xffff).formatstr("%04X");
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state_add( _8X300_AUX, "AUX", m_AUX).mask(0xff).formatstr("%02X");
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state_add( _8X300_R1, "R1", m_R1).mask(0xff).formatstr("%02X");
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@ -140,18 +139,48 @@ void n8x300_cpu_device::device_start()
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state_add( _8X300_OVF, "OVF", m_OVF).mask(0x01).formatstr("%01X");
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state_add( _8X300_IVL, "IVL", m_IVL).mask(0xff).formatstr("%02X");
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state_add( _8X300_IVR, "IVR", m_IVR).mask(0xff).formatstr("%02X");
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state_add(STATE_GENPC, "GENPC", m_genPC).noshow();
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state_add(STATE_GENPCBASE, "CURPC", m_genPC).noshow();
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state_add(STATE_GENPC, "GENPC", m_genPC).mask(0x3ffe).callimport().noshow();
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state_add(STATE_GENPCBASE, "CURPC", m_genPC).mask(0x3ffe).callimport().noshow();
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m_icountptr = &m_icount;
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}
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//-------------------------------------------------
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// state_import - import state into the device,
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// after it has been set
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//-------------------------------------------------
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void n8x300_cpu_device::state_import(const device_state_entry &entry)
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{
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switch (entry.index())
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{
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case _8X300_PC:
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m_AR = m_PC;
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m_genPC = m_AR << 1;
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m_increment_pc = true;
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break;
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case _8X300_AR:
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m_genPC = m_AR << 1;
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m_increment_pc = false;
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break;
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case STATE_GENPC:
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case STATE_GENPCBASE:
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m_AR = m_genPC >> 1;
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m_PC = m_AR;
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m_increment_pc = true;
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break;
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}
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}
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void n8x300_cpu_device::device_reset()
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{
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/* zero registers */
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m_PC = 0;
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m_AR = 0;
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m_IR = 0;
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m_genPC = 0;
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m_increment_pc = true;
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}
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void n8x300_cpu_device::execute_run()
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@ -166,13 +195,22 @@ void n8x300_cpu_device::execute_run()
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uint16_t result;
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/* fetch the opcode */
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m_genPC = m_AR << 1;
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debugger_instruction_hook(this, m_genPC);
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opcode = FETCHOP(m_genPC);
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m_PC++;
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m_PC &= 0x1fff;
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if (m_increment_pc)
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{
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m_PC++;
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m_PC &= 0x1fff;
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}
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else
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{
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m_increment_pc = true;
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}
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m_AR = m_PC;
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m_IR = opcode;
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m_genPC = m_PC << 1;
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switch (OP)
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{
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@ -50,6 +50,9 @@ protected:
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virtual void device_start() override;
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virtual void device_reset() override;
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// device_state_interface overrides
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virtual void state_import(const device_state_entry &entry) override;
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// device_execute_interface overrides
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virtual uint32_t execute_min_cycles() const override { return 1; }
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virtual uint32_t execute_max_cycles() const override { return 1; }
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@ -76,6 +79,7 @@ protected:
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address_space_config m_io_config;
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int m_icount;
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bool m_increment_pc;
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address_space *m_program;
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direct_read_data *m_direct;
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