mirror of
https://github.com/holub/mame
synced 2025-05-23 22:20:01 +03:00
srccleaned + minor fixes. nw.
This commit is contained in:
Fabio Priuli
parent
24837775a4
commit
aa2b3bb471
File diff suppressed because it is too large
Load Diff
@ -1312,4 +1312,3 @@ DRIVER_INIT_MEMBER(snes_state,snesst)
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#include "machine/snesrtc.c"
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#include "machine/snessdd1.c"
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#include "machine/snes7110.c"
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@ -1,7 +1,7 @@
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/***********************************************************************************************************
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BS-X Satellaview cartridge emulation (for SNES/SFC)
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Copyright MESS Team.
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Visit http://mamedev.org for licensing and usage restrictions.
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@ -89,7 +89,7 @@ void sns_rom_bsmempak_device::device_start()
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m_command = 0;
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m_write_old = 0;
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m_write_new = 0;
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m_flash_enable = 0;
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m_read_enable = 0;
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m_write_enable = 0;
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@ -129,26 +129,26 @@ UINT8 BSX_base::read(UINT32 offset)
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mame_printf_debug("BS-X Base Unit reg read outside correct range!\n");
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return 0x00;
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}
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switch (offset)
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{
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switch (offset)
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{
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// no 218b? no 218d? no 2191? no 2195? no 219a-219f?
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case 0x2192:
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case 0x2192:
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{
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UINT8 counter = r2192_counter++;
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if (r2192_counter >= 18)
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if (r2192_counter >= 18)
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r2192_counter = 0;
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if (counter == 0)
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if (counter == 0)
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{
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system_time curtime, *systime = &curtime;
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m_machine.current_datetime(curtime);
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m_machine.current_datetime(curtime);
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r2192_hour = systime->local_time.hour;
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r2192_minute = systime->local_time.minute;
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r2192_second = systime->local_time.second;
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}
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switch (counter)
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switch (counter)
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{
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case 0: return 0x00; //???
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case 1: return 0x00; //???
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@ -169,7 +169,7 @@ UINT8 BSX_base::read(UINT32 offset)
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case 16: return 0x00; //???
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case 17: return 0x00; //???
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}
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}
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}
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break;
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case 0x2193:
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@ -191,25 +191,25 @@ void BSX_base::write(UINT32 offset, UINT8 data)
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mame_printf_debug("BS-X Base Unit reg write outside correct range!\n");
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return;
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}
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switch(offset)
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switch(offset)
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{
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// no 218d? no 2190? no 2195? no 2196? no 2198? no 219a-219f?
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case 0x218f:
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regs[6] >>= 1; // 0x218e
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regs[6] = regs[7] - regs[6]; // 0x218f - 0x218e
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regs[7] >>= 1; // 0x218f
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regs[6] >>= 1; // 0x218e
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regs[6] = regs[7] - regs[6]; // 0x218f - 0x218e
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regs[7] >>= 1; // 0x218f
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break;
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case 0x2191:
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regs[offset - 0x2188] = data;
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r2192_counter = 0;
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break;
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case 0x2192:
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regs[8] = data; // sets 0x2190
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regs[8] = data; // sets 0x2190
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break;
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default:
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regs[offset - 0x2188] = data;
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break;
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@ -266,8 +266,8 @@ void sns_rom_bsx_device::access_update()
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rom_access = 0;
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else
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{
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// rom_access = BIT(m_cart_regs[0x02], 7) + 1;
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rom_access = 1; // for whatever reason bsxsore changes access mode here and then fails to read the ROM properly!
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// rom_access = BIT(m_cart_regs[0x02], 7) + 1;
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rom_access = 1; // for whatever reason bsxsore changes access mode here and then fails to read the ROM properly!
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printf("rom_access %s\n", !BIT(m_cart_regs[0x02], 7) ? "Lo" : "Hi");
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}
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}
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@ -317,7 +317,7 @@ READ8_MEMBER(sns_rom_bsx_device::read_l)
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int bank = (rom_access == 1) ? (offset / 0x10000) : (offset / 0x8000);
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return m_rom[rom_bank_map[bank] * 0x8000 + (offset & 0x7fff)];
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}
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return 0x00;
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}
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@ -330,7 +330,7 @@ READ8_MEMBER(sns_rom_bsx_device::read_h)
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if (m_slot->m_cart && m_slot->m_cart->get_rom_size())
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return m_slot->m_cart->read_l(space, offset);
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}
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// if not in any of the cases above...
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//$00-3f|80-bf:8000-ffff
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//$40-7f|c0-ff:0000-ffff
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@ -341,7 +341,7 @@ READ8_MEMBER(sns_rom_bsx_device::read_h)
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int bank = (rom_access == 1) ? (offset / 0x10000) : (offset / 0x8000);
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return m_rom[rom_bank_map[bank] * 0x8000 + (offset & 0x7fff)];
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}
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return 0x00;
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}
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@ -378,7 +378,7 @@ WRITE8_MEMBER(sns_rom_bsx_device::write_l)
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// 0x70-0x77:0x0000-0xffff -> PRAM
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m_pram[offset & 0x7ffff] = data;
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}
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// if not in any of the cases above...
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//$00-3f|80-bf:8000-ffff
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//$40-7f|c0-ff:0000-ffff
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@ -394,7 +394,7 @@ WRITE8_MEMBER(sns_rom_bsx_device::write_h)
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// write to cart...
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return;
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}
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// if not in any of the cases above...
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//$00-3f|80-bf:8000-ffff
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//$40-7f|c0-ff:0000-ffff
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@ -407,18 +407,18 @@ READ8_MEMBER(sns_rom_bsx_device::chip_read)
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{
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if ((offset & 0xffff) >= 0x2188 && (offset & 0xffff) < 0x21a0)
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return m_base_unit->read(offset & 0xffff);
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if ((offset & 0xf0ffff) == 0x005000) //$[00-0f]:5000 reg access
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if ((offset & 0xf0ffff) == 0x005000) //$[00-0f]:5000 reg access
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{
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UINT8 n = (offset >> 16) & 0x0f;
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return m_cart_regs[n];
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}
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if ((offset & 0xf8f000) == 0x105000) //$[10-17]:[5000-5fff] SRAM access
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if ((offset & 0xf8f000) == 0x105000) //$[10-17]:[5000-5fff] SRAM access
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{
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return m_nvram[((offset >> 16) & 7) * 0x1000 + (offset & 0xfff)];
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}
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return 0x00;
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}
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@ -426,16 +426,16 @@ WRITE8_MEMBER(sns_rom_bsx_device::chip_write)
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{
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if ((offset & 0xffff) >= 0x2188 && (offset & 0xffff) < 0x21a0)
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m_base_unit->write(offset & 0xffff, data);
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if ((offset & 0xf0ffff) == 0x005000) //$[00-0f]:5000 reg access
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if ((offset & 0xf0ffff) == 0x005000) //$[00-0f]:5000 reg access
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{
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UINT8 n = (offset >> 16) & 0x0f;
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m_cart_regs[n] = data;
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if (n == 0x0e && data & 0x80)
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access_update();
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}
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if ((offset & 0xf8f000) == 0x105000) //$[10-17]:[5000-5fff] SRAM access
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if ((offset & 0xf8f000) == 0x105000) //$[10-17]:[5000-5fff] SRAM access
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{
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m_nvram[((offset >> 16) & 7) * 0x1000 + (offset & 0xfff)] = data;
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}
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@ -583,4 +583,3 @@ READ8_MEMBER(sns_rom_bsmempak_device::read_h)
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WRITE8_MEMBER(sns_rom_bsmempak_device::write_l)
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{
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}
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@ -17,7 +17,7 @@ public:
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private:
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// regs
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UINT8 regs[0x18]; // 0x2188-0x219f
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UINT8 regs[0x18]; // 0x2188-0x219f
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// counter + clock
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UINT8 r2192_counter;
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@ -34,12 +34,12 @@ public:
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// construction/destruction
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sns_rom_bsx_device(const machine_config &mconfig, device_type type, const char *name, const char *tag, device_t *owner, UINT32 clock);
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sns_rom_bsx_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
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// device-level overrides
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virtual void device_start();
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virtual void device_config_complete() { m_shortname = "sns_rom_bsx"; }
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virtual machine_config_constructor device_mconfig_additions() const;
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// additional reading and writing
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virtual DECLARE_READ8_MEMBER(read_l);
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virtual DECLARE_READ8_MEMBER(read_h);
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@ -47,23 +47,23 @@ public:
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virtual DECLARE_WRITE8_MEMBER(write_h);
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virtual DECLARE_READ8_MEMBER(chip_read);
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virtual DECLARE_WRITE8_MEMBER(chip_write);
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// base regs
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BSX_base *m_base_unit;
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// cart regs
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UINT8 m_cart_regs[16];
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UINT8 access_00_1f; // 1 = CART, 0 = NOTHING
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UINT8 access_80_9f; // 1 = CART, 0 = NOTHING
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UINT8 access_40_4f; // 1 = NOTHING, 0 = PRAM
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UINT8 access_50_5f; // 1 = NOTHING, 0 = PRAM
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UINT8 access_60_6f; // 1 = PRAM, 0 = NOTHING
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UINT8 rom_access; // 2 = HiROM, 1 = LoROM, 0 = PRAM
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UINT8 access_00_1f; // 1 = CART, 0 = NOTHING
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UINT8 access_80_9f; // 1 = CART, 0 = NOTHING
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UINT8 access_40_4f; // 1 = NOTHING, 0 = PRAM
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UINT8 access_50_5f; // 1 = NOTHING, 0 = PRAM
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UINT8 access_60_6f; // 1 = PRAM, 0 = NOTHING
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UINT8 rom_access; // 2 = HiROM, 1 = LoROM, 0 = PRAM
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void access_update();
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UINT8 m_pram[0x80000];
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private:
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required_device<sns_bsx_cart_slot_device> m_slot;
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};
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@ -75,20 +75,20 @@ class sns_rom_bsxlo_device : public sns_rom_device
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public:
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// construction/destruction
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sns_rom_bsxlo_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
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// device-level overrides
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virtual void device_start();
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virtual void device_config_complete() { m_shortname = "sns_rom_bsxlo"; }
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virtual machine_config_constructor device_mconfig_additions() const;
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// additional reading and writing
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virtual DECLARE_READ8_MEMBER(read_l);
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virtual DECLARE_READ8_MEMBER(read_h);
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// virtual DECLARE_WRITE8_MEMBER(write_l);
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// virtual DECLARE_WRITE8_MEMBER(write_h);
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// virtual DECLARE_READ8_MEMBER(chip_read);
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// virtual DECLARE_WRITE8_MEMBER(chip_write);
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// virtual DECLARE_WRITE8_MEMBER(write_l);
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// virtual DECLARE_WRITE8_MEMBER(write_h);
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// virtual DECLARE_READ8_MEMBER(chip_read);
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// virtual DECLARE_WRITE8_MEMBER(chip_write);
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private:
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required_device<sns_bsx_cart_slot_device> m_slot;
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};
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@ -100,20 +100,20 @@ class sns_rom_bsxhi_device : public sns_rom21_device
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public:
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// construction/destruction
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sns_rom_bsxhi_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
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// device-level overrides
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virtual void device_start();
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virtual void device_config_complete() { m_shortname = "sns_rom_bsxhi"; }
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virtual machine_config_constructor device_mconfig_additions() const;
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// additional reading and writing
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virtual DECLARE_READ8_MEMBER(read_l);
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virtual DECLARE_READ8_MEMBER(read_h);
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virtual DECLARE_WRITE8_MEMBER(write_l);
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virtual DECLARE_WRITE8_MEMBER(write_h);
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// virtual DECLARE_READ8_MEMBER(chip_read);
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// virtual DECLARE_WRITE8_MEMBER(chip_write);
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// virtual DECLARE_READ8_MEMBER(chip_read);
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// virtual DECLARE_WRITE8_MEMBER(chip_write);
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private:
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required_device<sns_bsx_cart_slot_device> m_slot;
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};
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@ -126,24 +126,24 @@ class sns_rom_bsmempak_device : public sns_rom_device
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public:
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// construction/destruction
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sns_rom_bsmempak_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
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// device-level overrides
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virtual void device_start();
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virtual void device_config_complete() { m_shortname = "sns_bsmempak"; }
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// additional reading and writing
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virtual DECLARE_READ8_MEMBER(read_l);
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virtual DECLARE_READ8_MEMBER(read_h);
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virtual DECLARE_WRITE8_MEMBER(write_l);
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// virtual DECLARE_WRITE8_MEMBER(write_h);
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// virtual DECLARE_READ8_MEMBER(chip_read);
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// virtual DECLARE_WRITE8_MEMBER(chip_write);
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// virtual DECLARE_WRITE8_MEMBER(write_h);
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// virtual DECLARE_READ8_MEMBER(chip_read);
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// virtual DECLARE_WRITE8_MEMBER(chip_write);
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// flash regs
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UINT32 m_command;
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UINT8 m_write_old;
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UINT8 m_write_new;
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int m_flash_enable;
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int m_read_enable;
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int m_write_enable;
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@ -1,10 +1,10 @@
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/***********************************************************************************************************
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Super NES/Famicom (LoROM) cartridge emulation (for SNES/SFC)
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Copyright MESS Team.
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Visit http://mamedev.org for licensing and usage restrictions.
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***********************************************************************************************************/
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@ -62,7 +62,7 @@ void sns_rom_obc1_device::device_start()
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// or from rom?
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m_offset = (m_ram[0x1ff5] & 0x01) ? 0x1800 : 0x1c00;
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m_address = (m_ram[0x1ff6] & 0x7f);
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m_shift = (m_ram[0x1ff6] & 0x03) << 1;
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m_shift = (m_ram[0x1ff6] & 0x03) << 1;
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save_item(NAME(m_ram));
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save_item(NAME(m_address));
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@ -84,7 +84,7 @@ READ8_MEMBER(sns_rom_device::read_h)
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{
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UINT8 value = 0xff;
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UINT16 address = offset & 0xffff;
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if (offset < 0x700000)
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{
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int bank = offset / 0x10000;
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@ -107,7 +107,7 @@ READ8_MEMBER(sns_rom_device::read_h)
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value = m_nvram[offset & mask];
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}
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else
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value = 0xff; // this should never happened...
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value = 0xff; // this should never happened...
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}
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else
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{
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@ -125,7 +125,7 @@ WRITE8_MEMBER(sns_rom_device::write_l)
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WRITE8_MEMBER(sns_rom_device::write_h)
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{
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if (offset >= 0x700000) // SRAM
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if (offset >= 0x700000) // SRAM
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{
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if (m_nvram_size > 0x8000)
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{
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@ -161,18 +161,18 @@ WRITE8_MEMBER( sns_rom_pokemon_device::chip_write )
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// same as above but additional read/write handling for the add-on chip
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/***************************************************************************
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Based on C++ implementation by Byuu in BSNES.
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Byuu's code is released under GNU General Public License
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version 2 as published by the Free Software Foundation.
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The implementation below is released under the MAME license
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for use in MAME, MESS and derivatives by permission of Byuu
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Copyright (for the implementation below) MESS Team.
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Visit http://mamedev.org for licensing and usage restrictions.
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***********************************************************************************************************/
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@ -180,34 +180,34 @@ READ8_MEMBER( sns_rom_obc1_device::chip_read )
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{
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UINT16 address = offset & 0x1fff;
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UINT8 value;
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switch (address)
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{
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case 0x1ff0:
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value = m_ram[m_offset + (m_address << 2) + 0];
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break;
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case 0x1ff1:
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value = m_ram[m_offset + (m_address << 2) + 1];
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break;
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case 0x1ff2:
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value = m_ram[m_offset + (m_address << 2) + 2];
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break;
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case 0x1ff3:
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||||
value = m_ram[m_offset + (m_address << 2) + 3];
|
||||
break;
|
||||
|
||||
|
||||
case 0x1ff4:
|
||||
value = m_ram[m_offset + (m_address >> 2) + 0x200];
|
||||
break;
|
||||
|
||||
|
||||
default:
|
||||
value = m_ram[address];
|
||||
break;
|
||||
}
|
||||
|
||||
|
||||
return value;
|
||||
}
|
||||
|
||||
@ -216,45 +216,44 @@ WRITE8_MEMBER( sns_rom_obc1_device::chip_write )
|
||||
{
|
||||
UINT16 address = offset & 0x1fff;
|
||||
UINT8 temp;
|
||||
|
||||
|
||||
switch(address)
|
||||
{
|
||||
case 0x1ff0:
|
||||
m_ram[m_offset + (m_address << 2) + 0] = data;
|
||||
break;
|
||||
|
||||
|
||||
case 0x1ff1:
|
||||
m_ram[m_offset + (m_address << 2) + 1] = data;
|
||||
break;
|
||||
|
||||
|
||||
case 0x1ff2:
|
||||
m_ram[m_offset + (m_address << 2) + 2] = data;
|
||||
break;
|
||||
|
||||
|
||||
case 0x1ff3:
|
||||
m_ram[m_offset + (m_address << 2) + 3] = data;
|
||||
break;
|
||||
|
||||
|
||||
case 0x1ff4:
|
||||
temp = m_ram[m_offset + (m_address >> 2) + 0x200];
|
||||
temp = (temp & ~(3 << m_shift)) | ((data & 0x03) << m_shift);
|
||||
m_ram[m_offset + (m_address >> 2) + 0x200] = temp;
|
||||
break;
|
||||
|
||||
|
||||
case 0x1ff5:
|
||||
m_offset = (data & 0x01) ? 0x1800 : 0x1c00;
|
||||
m_ram[address & 0x1fff] = data;
|
||||
break;
|
||||
|
||||
|
||||
case 0x1ff6:
|
||||
m_address = data & 0x7f;
|
||||
m_shift = (data & 0x03) << 1;
|
||||
m_ram[address & 0x1fff] = data;
|
||||
break;
|
||||
|
||||
|
||||
default:
|
||||
m_ram[address & 0x1fff] = data;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
@ -7,13 +7,13 @@
|
||||
// ======================> sns_rom_device
|
||||
|
||||
class sns_rom_device : public device_t,
|
||||
public device_sns_cart_interface
|
||||
public device_sns_cart_interface
|
||||
{
|
||||
public:
|
||||
// construction/destruction
|
||||
sns_rom_device(const machine_config &mconfig, device_type type, const char *name, const char *tag, device_t *owner, UINT32 clock);
|
||||
sns_rom_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
|
||||
|
||||
|
||||
// device-level overrides
|
||||
virtual void device_start();
|
||||
virtual void device_config_complete() { m_shortname = "sns_rom"; }
|
||||
@ -32,14 +32,14 @@ class sns_rom_pokemon_device : public sns_rom_device
|
||||
public:
|
||||
// construction/destruction
|
||||
sns_rom_pokemon_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
|
||||
|
||||
|
||||
// device-level overrides
|
||||
virtual void device_start();
|
||||
virtual void device_config_complete() { m_shortname = "sns_rom_pokemon"; }
|
||||
|
||||
|
||||
// reading and writing
|
||||
virtual DECLARE_READ8_MEMBER(chip_read); // protection device
|
||||
virtual DECLARE_WRITE8_MEMBER(chip_write); // protection device
|
||||
virtual DECLARE_READ8_MEMBER(chip_read); // protection device
|
||||
virtual DECLARE_WRITE8_MEMBER(chip_write); // protection device
|
||||
UINT8 m_latch;
|
||||
};
|
||||
|
||||
@ -50,15 +50,15 @@ class sns_rom_obc1_device : public sns_rom_device
|
||||
public:
|
||||
// construction/destruction
|
||||
sns_rom_obc1_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
|
||||
|
||||
|
||||
// device-level overrides
|
||||
virtual void device_start();
|
||||
virtual void device_config_complete() { m_shortname = "sns_rom_obc1"; }
|
||||
|
||||
|
||||
// additional reading and writing
|
||||
virtual DECLARE_READ8_MEMBER(chip_read);
|
||||
virtual DECLARE_WRITE8_MEMBER(chip_write);
|
||||
|
||||
|
||||
int m_address;
|
||||
int m_offset;
|
||||
int m_shift;
|
||||
|
||||
@ -1,10 +1,10 @@
|
||||
/***********************************************************************************************************
|
||||
|
||||
|
||||
Super NES/Famicom (HiROM) cartridge emulation (for SNES/SFC)
|
||||
|
||||
|
||||
Copyright MESS Team.
|
||||
Visit http://mamedev.org for licensing and usage restrictions.
|
||||
|
||||
|
||||
***********************************************************************************************************/
|
||||
|
||||
|
||||
@ -51,7 +51,7 @@ void sns_rom21_srtc_device::device_start()
|
||||
m_index = -1;
|
||||
|
||||
// at this stage, rtc_ram is not yet allocated. this will be fixed when converting RTC to be a separate device.
|
||||
// update_time();
|
||||
// update_time();
|
||||
|
||||
save_item(NAME(m_mode));
|
||||
save_item(NAME(m_index));
|
||||
@ -66,7 +66,7 @@ void sns_rom21_srtc_device::device_start()
|
||||
READ8_MEMBER(sns_rom21_device::read_l)
|
||||
{
|
||||
UINT16 address = offset & 0xffff;
|
||||
|
||||
|
||||
if (offset >= 0x300000 && offset < 0x400000 && address < 0x8000)
|
||||
{
|
||||
if (m_nvram_size > 0)
|
||||
@ -77,7 +77,7 @@ READ8_MEMBER(sns_rom21_device::read_l)
|
||||
return m_nvram[(offset - 0x6000) & mask];
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
// here ROM banks from 128 to 255, mirrored twice
|
||||
int bank = (offset & 0x3fffff) / 0x8000;
|
||||
return m_rom[rom_bank_map[bank + 0x80] * 0x8000 + (offset & 0x7fff)];
|
||||
@ -86,7 +86,7 @@ READ8_MEMBER(sns_rom21_device::read_l)
|
||||
READ8_MEMBER(sns_rom21_device::read_h)
|
||||
{
|
||||
UINT16 address = offset & 0xffff;
|
||||
|
||||
|
||||
if (offset >= 0x300000 && offset < 0x400000 && address < 0x8000)
|
||||
{
|
||||
if (m_nvram_size > 0)
|
||||
@ -97,7 +97,7 @@ READ8_MEMBER(sns_rom21_device::read_h)
|
||||
return m_nvram[(offset - 0x6000) & mask];
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
// here ROM banks from 0 to 127, mirrored twice
|
||||
int bank = (offset & 0x3fffff) / 0x8000;
|
||||
return m_rom[rom_bank_map[bank] * 0x8000 + (offset & 0x7fff)];
|
||||
@ -111,7 +111,7 @@ WRITE8_MEMBER(sns_rom21_device::write_l)
|
||||
WRITE8_MEMBER(sns_rom21_device::write_h)
|
||||
{
|
||||
UINT16 address = offset & 0xffff;
|
||||
|
||||
|
||||
if (offset >= 0x300000 && offset < 0x400000 && address < 0x8000)
|
||||
{
|
||||
if (m_nvram_size > 0)
|
||||
@ -127,18 +127,18 @@ WRITE8_MEMBER(sns_rom21_device::write_h)
|
||||
// Hi-ROM + S-RTC (used by Daikaijuu Monogatari II)
|
||||
// same as above but additional read/write handling for the RTC
|
||||
/***************************************************************************
|
||||
|
||||
|
||||
Based on C++ implementation by Byuu in BSNES.
|
||||
|
||||
|
||||
Byuu's code is released under GNU General Public License
|
||||
version 2 as published by the Free Software Foundation.
|
||||
|
||||
|
||||
The implementation below is released under the MAME license
|
||||
for use in MAME, MESS and derivatives by permission of Byuu
|
||||
|
||||
|
||||
Copyright (for the implementation below) MESS Team.
|
||||
Visit http://mamedev.org for licensing and usage restrictions.
|
||||
|
||||
|
||||
***************************************************************************/
|
||||
|
||||
static const UINT8 srtc_months[12] =
|
||||
@ -175,11 +175,11 @@ UINT8 sns_rom21_srtc_device::srtc_weekday( UINT32 year, UINT32 month, UINT32 day
|
||||
{
|
||||
UINT32 y = 1900, m = 1; // Epoch is 1900-01-01
|
||||
UINT32 sum = 0; // Number of days passed since epoch
|
||||
|
||||
|
||||
year = MAX(1900, year);
|
||||
month = MAX(1, MIN(12, month));
|
||||
day = MAX(1, MIN(31, day));
|
||||
|
||||
|
||||
while (y < year)
|
||||
{
|
||||
UINT8 leapyear = 0;
|
||||
@ -194,7 +194,7 @@ UINT8 sns_rom21_srtc_device::srtc_weekday( UINT32 year, UINT32 month, UINT32 day
|
||||
sum += leapyear ? 366 : 365;
|
||||
y++;
|
||||
}
|
||||
|
||||
|
||||
while (m < month)
|
||||
{
|
||||
UINT32 days = srtc_months[m - 1];
|
||||
@ -214,19 +214,19 @@ UINT8 sns_rom21_srtc_device::srtc_weekday( UINT32 year, UINT32 month, UINT32 day
|
||||
sum += days;
|
||||
m++;
|
||||
}
|
||||
|
||||
|
||||
sum += day - 1;
|
||||
return (sum + 1) % 7; // 1900-01-01 was a Monday
|
||||
}
|
||||
|
||||
|
||||
// this gets called only for accesses at 0x2800,
|
||||
// because for 0x2801 open bus gets returned...
|
||||
// because for 0x2801 open bus gets returned...
|
||||
READ8_MEMBER(sns_rom21_srtc_device::chip_read)
|
||||
{
|
||||
if (m_mode != RTCM_Read)
|
||||
return 0x00;
|
||||
|
||||
|
||||
if (m_index < 0)
|
||||
{
|
||||
update_time();
|
||||
@ -246,29 +246,29 @@ READ8_MEMBER(sns_rom21_srtc_device::chip_read)
|
||||
WRITE8_MEMBER(sns_rom21_srtc_device::chip_write)
|
||||
{
|
||||
data &= 0x0f; // Only the low four bits are used
|
||||
|
||||
|
||||
if (data == 0x0d)
|
||||
{
|
||||
m_mode = RTCM_Read;
|
||||
m_index = -1;
|
||||
return;
|
||||
}
|
||||
|
||||
|
||||
if (data == 0x0e)
|
||||
{
|
||||
m_mode = RTCM_Command;
|
||||
return;
|
||||
}
|
||||
|
||||
|
||||
if (data == 0x0f)
|
||||
return; // Unknown behaviour
|
||||
|
||||
|
||||
if (m_mode == RTCM_Write)
|
||||
{
|
||||
if (m_index >= 0 && m_index < 12)
|
||||
{
|
||||
m_rtc_ram[m_index++] = data;
|
||||
|
||||
|
||||
if (m_index == 12)
|
||||
{
|
||||
// Day of week is automatically calculated and written
|
||||
@ -276,7 +276,7 @@ WRITE8_MEMBER(sns_rom21_srtc_device::chip_write)
|
||||
UINT32 month = m_rtc_ram[8];
|
||||
UINT32 year = m_rtc_ram[9] + m_rtc_ram[10] * 10 + m_rtc_ram[11] * 100;
|
||||
year += 1000;
|
||||
|
||||
|
||||
m_rtc_ram[m_index++] = srtc_weekday(year, month, day);
|
||||
}
|
||||
}
|
||||
@ -303,4 +303,3 @@ WRITE8_MEMBER(sns_rom21_srtc_device::chip_write)
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
@ -7,13 +7,13 @@
|
||||
// ======================> sns_rom21_device
|
||||
|
||||
class sns_rom21_device : public device_t,
|
||||
public device_sns_cart_interface
|
||||
public device_sns_cart_interface
|
||||
{
|
||||
public:
|
||||
// construction/destruction
|
||||
sns_rom21_device(const machine_config &mconfig, device_type type, const char *name, const char *tag, device_t *owner, UINT32 clock);
|
||||
sns_rom21_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
|
||||
|
||||
|
||||
// device-level overrides
|
||||
virtual void device_start();
|
||||
virtual void device_config_complete() { m_shortname = "sns_rom21"; }
|
||||
@ -32,11 +32,11 @@ class sns_rom21_srtc_device : public sns_rom21_device
|
||||
public:
|
||||
// construction/destruction
|
||||
sns_rom21_srtc_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
|
||||
|
||||
|
||||
// device-level overrides
|
||||
virtual void device_start();
|
||||
virtual void device_config_complete() { m_shortname = "sns_rom21_srtc"; }
|
||||
|
||||
|
||||
// reading and writing
|
||||
virtual DECLARE_READ8_MEMBER(chip_read);
|
||||
virtual DECLARE_WRITE8_MEMBER(chip_write);
|
||||
@ -49,10 +49,10 @@ public:
|
||||
RTCM_Read,
|
||||
RTCM_Write
|
||||
};
|
||||
|
||||
|
||||
void update_time();
|
||||
UINT8 srtc_weekday(UINT32 year, UINT32 month, UINT32 day);
|
||||
|
||||
|
||||
//this is now allocated in the main snes cart class, to allow saving to nvram
|
||||
//UINT8 m_rtc_ram[13];
|
||||
INT32 m_mode;
|
||||
|
||||
@ -1,13 +1,13 @@
|
||||
/***********************************************************************************************************
|
||||
|
||||
|
||||
S-DD1 add-on chip emulation (for SNES/SFC)
|
||||
|
||||
|
||||
Based on Andreas Naive Public Domain code.
|
||||
Code ported by MooglyGuy and updated to slots by Fabio Priuli.
|
||||
|
||||
|
||||
Copyright MESS Team.
|
||||
Visit http://mamedev.org for licensing and usage restrictions.
|
||||
|
||||
|
||||
***********************************************************************************************************/
|
||||
|
||||
|
||||
@ -30,21 +30,21 @@ void SDD1__IM::IM_prepareDecomp(UINT32 in_buf)
|
||||
UINT8 SDD1__IM::IM_getCodeword(UINT8 *ROM, UINT32 *mmc, const UINT8 code_len)
|
||||
{
|
||||
UINT8 codeword = ROM[SSD1_ADD(m_byte_ptr)] << m_bit_count;
|
||||
|
||||
|
||||
++m_bit_count;
|
||||
|
||||
|
||||
if (codeword & 0x80)
|
||||
{
|
||||
codeword |= ROM[SSD1_ADD((m_byte_ptr + 1))] >> (9 - m_bit_count);
|
||||
m_bit_count += code_len;
|
||||
}
|
||||
|
||||
|
||||
if (m_bit_count & 0x08)
|
||||
{
|
||||
m_byte_ptr++;
|
||||
m_bit_count &= 0x07;
|
||||
}
|
||||
|
||||
|
||||
return codeword;
|
||||
}
|
||||
|
||||
@ -87,9 +87,9 @@ void SDD1__GCD::GCD_getRunCount(UINT8 *ROM, UINT32 *mmc, UINT8 code_num, UINT8*
|
||||
0x78, 0x38, 0x58, 0x18, 0x68, 0x28, 0x48, 0x08,
|
||||
0x70, 0x30, 0x50, 0x10, 0x60, 0x20, 0x40, 0x00,
|
||||
};
|
||||
|
||||
|
||||
UINT8 codeword = m_IM->IM_getCodeword(ROM, mmc, code_num);
|
||||
|
||||
|
||||
if (codeword & 0x80)
|
||||
{
|
||||
*LPSind = 1;
|
||||
@ -112,12 +112,12 @@ void SDD1__BG::BG_prepareDecomp()
|
||||
UINT8 SDD1__BG::BG_getBit(UINT8 *ROM, UINT32 *mmc, UINT8* endOfRun)
|
||||
{
|
||||
UINT8 bit;
|
||||
|
||||
|
||||
if (!(m_MPScount || m_LPSind))
|
||||
{
|
||||
m_GCD->GCD_getRunCount(ROM, mmc, m_code_num, &(m_MPScount), &(m_LPSind));
|
||||
}
|
||||
|
||||
|
||||
if (m_MPScount)
|
||||
{
|
||||
bit = 0;
|
||||
@ -128,7 +128,7 @@ UINT8 SDD1__BG::BG_getBit(UINT8 *ROM, UINT32 *mmc, UINT8* endOfRun)
|
||||
bit = 1;
|
||||
m_LPSind = 0;
|
||||
}
|
||||
|
||||
|
||||
if (m_MPScount || m_LPSind)
|
||||
{
|
||||
(*endOfRun) = 0;
|
||||
@ -137,7 +137,7 @@ UINT8 SDD1__BG::BG_getBit(UINT8 *ROM, UINT32 *mmc, UINT8* endOfRun)
|
||||
{
|
||||
(*endOfRun) = 1;
|
||||
}
|
||||
|
||||
|
||||
return bit;
|
||||
}
|
||||
|
||||
@ -200,14 +200,14 @@ UINT8 SDD1__PEM::PEM_getBit(UINT8 *ROM, UINT32 *mmc, UINT8 context)
|
||||
{
|
||||
UINT8 endOfRun;
|
||||
UINT8 bit;
|
||||
|
||||
|
||||
SDD1__PEM_ContextInfo *pContInfo = &(m_contextInfo)[context];
|
||||
UINT8 currStatus = pContInfo->status;
|
||||
const SDD1__PEM_state* pState = &(PEM_evolution_table[currStatus]);
|
||||
UINT8 currentMPS = pContInfo->MPS;
|
||||
|
||||
|
||||
bit = m_BG[pState->code_num]->BG_getBit(ROM, mmc, &endOfRun);
|
||||
|
||||
|
||||
if (endOfRun)
|
||||
{
|
||||
if (bit)
|
||||
@ -223,7 +223,7 @@ UINT8 SDD1__PEM::PEM_getBit(UINT8 *ROM, UINT32 *mmc, UINT8 context)
|
||||
pContInfo->status = pState->nextIfMPS;
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
return bit ^ currentMPS;
|
||||
}
|
||||
|
||||
@ -258,7 +258,7 @@ UINT8 SDD1__CM::CM_getBit(UINT8 *ROM, UINT32 *mmc)
|
||||
UINT8 currContext;
|
||||
UINT16 *context_bits;
|
||||
UINT8 bit = 0;
|
||||
|
||||
|
||||
switch (m_bitplanesInfo)
|
||||
{
|
||||
case 0x00:
|
||||
@ -278,9 +278,9 @@ UINT8 SDD1__CM::CM_getBit(UINT8 *ROM, UINT32 *mmc)
|
||||
m_currBitplane = m_bit_number & 0x07;
|
||||
break;
|
||||
}
|
||||
|
||||
|
||||
context_bits = &(m_prevBitplaneBits)[m_currBitplane];
|
||||
|
||||
|
||||
currContext = (m_currBitplane & 0x01) << 4;
|
||||
switch (m_contextBitsInfo)
|
||||
{
|
||||
@ -297,14 +297,14 @@ UINT8 SDD1__CM::CM_getBit(UINT8 *ROM, UINT32 *mmc)
|
||||
currContext |= ((*context_bits & 0x0180) >> 5) | (*context_bits & 0x0003);
|
||||
break;
|
||||
}
|
||||
|
||||
|
||||
bit = m_PEM->PEM_getBit(ROM, mmc, currContext);
|
||||
|
||||
|
||||
*context_bits <<= 1;
|
||||
*context_bits |= bit;
|
||||
|
||||
|
||||
m_bit_number++;
|
||||
|
||||
|
||||
return bit;
|
||||
}
|
||||
|
||||
@ -321,7 +321,7 @@ void SDD1__OL::OL_launch(UINT8 *ROM, UINT32 *mmc)
|
||||
{
|
||||
UINT8 i;
|
||||
UINT8 register1 = 0, register2 = 0;
|
||||
|
||||
|
||||
switch (m_bitplanesInfo)
|
||||
{
|
||||
case 0x00:
|
||||
@ -341,7 +341,7 @@ void SDD1__OL::OL_launch(UINT8 *ROM, UINT32 *mmc)
|
||||
{
|
||||
if (m_CM->CM_getBit(ROM, mmc))
|
||||
register1 |= i;
|
||||
|
||||
|
||||
if (m_CM->CM_getBit(ROM, mmc))
|
||||
register2 |= i;
|
||||
}
|
||||
@ -381,7 +381,7 @@ SDD1__emu::SDD1__emu(running_machine &machine)
|
||||
m_BG6 = auto_alloc(machine, SDD1__BG(m_GCD, 6));
|
||||
m_BG7 = auto_alloc(machine, SDD1__BG(m_GCD, 7));
|
||||
m_PEM = auto_alloc(machine, SDD1__PEM(m_BG0, m_BG1, m_BG2, m_BG3,
|
||||
m_BG4, m_BG5, m_BG6, m_BG7));
|
||||
m_BG4, m_BG5, m_BG6, m_BG7));
|
||||
m_CM = auto_alloc(machine, SDD1__CM(m_PEM));
|
||||
m_OL = auto_alloc(machine, SDD1__OL(m_CM));
|
||||
}
|
||||
@ -400,7 +400,7 @@ void SDD1__emu::SDD1emu_decompress(UINT8 *ROM, UINT32 *mmc, UINT32 in_buf, UINT1
|
||||
m_PEM->PEM_prepareDecomp();
|
||||
m_CM->CM_prepareDecomp(ROM, mmc, in_buf);
|
||||
m_OL->OL_prepareDecomp(ROM, mmc, in_buf, out_len, out_buf);
|
||||
|
||||
|
||||
m_OL->OL_launch(ROM, mmc);
|
||||
}
|
||||
|
||||
@ -428,23 +428,23 @@ sns_rom_sdd1_device::sns_rom_sdd1_device(const machine_config &mconfig, const ch
|
||||
void sns_rom_sdd1_device::device_start()
|
||||
{
|
||||
UINT8 i;
|
||||
|
||||
|
||||
m_sdd1_enable = 0x00;
|
||||
m_xfer_enable = 0x00;
|
||||
|
||||
|
||||
m_mmc[0] = 0 << 20;
|
||||
m_mmc[1] = 1 << 20;
|
||||
m_mmc[2] = 2 << 20;
|
||||
m_mmc[3] = 3 << 20;
|
||||
|
||||
|
||||
for(i = 0; i < 8; i++)
|
||||
{
|
||||
m_dma[i].addr = 0;
|
||||
m_dma[i].size = 0;
|
||||
}
|
||||
|
||||
|
||||
m_sdd1emu = auto_alloc(machine(), SDD1__emu(machine()));
|
||||
|
||||
|
||||
m_buffer.data = (UINT8*)auto_alloc_array(machine(), UINT8, 0x10000);
|
||||
m_buffer.ready = 0;
|
||||
|
||||
@ -461,7 +461,7 @@ void sns_rom_sdd1_device::device_start()
|
||||
READ8_MEMBER( sns_rom_sdd1_device::chip_read )
|
||||
{
|
||||
UINT16 addr = offset & 0xffff;
|
||||
|
||||
|
||||
switch (addr)
|
||||
{
|
||||
case 0x4804:
|
||||
@ -473,8 +473,8 @@ READ8_MEMBER( sns_rom_sdd1_device::chip_read )
|
||||
case 0x4807:
|
||||
return (m_mmc[3] >> 20) & 7;
|
||||
}
|
||||
|
||||
// we should never get here, but...
|
||||
|
||||
// we should never get here, but...
|
||||
return 0;
|
||||
}
|
||||
|
||||
@ -482,7 +482,7 @@ READ8_MEMBER( sns_rom_sdd1_device::chip_read )
|
||||
WRITE8_MEMBER( sns_rom_sdd1_device::chip_write )
|
||||
{
|
||||
UINT16 addr = offset & 0xffff;
|
||||
|
||||
|
||||
if ((addr & 0x4380) == 0x4300)
|
||||
{
|
||||
UINT8 channel = (addr >> 4) & 7;
|
||||
@ -507,7 +507,7 @@ WRITE8_MEMBER( sns_rom_sdd1_device::chip_write )
|
||||
}
|
||||
return;
|
||||
}
|
||||
|
||||
|
||||
switch(addr)
|
||||
{
|
||||
case 0x4800:
|
||||
@ -516,7 +516,7 @@ WRITE8_MEMBER( sns_rom_sdd1_device::chip_write )
|
||||
case 0x4801:
|
||||
m_xfer_enable = data;
|
||||
break;
|
||||
|
||||
|
||||
case 0x4804:
|
||||
m_mmc[0] = (data & 7) << 20;
|
||||
break;
|
||||
@ -530,7 +530,7 @@ WRITE8_MEMBER( sns_rom_sdd1_device::chip_write )
|
||||
m_mmc[3] = (data & 7) << 20;
|
||||
break;
|
||||
}
|
||||
|
||||
|
||||
}
|
||||
|
||||
UINT8 sns_rom_sdd1_device::read_helper(UINT32 addr)
|
||||
@ -552,14 +552,14 @@ UINT8 sns_rom_sdd1_device::read_helper(UINT32 addr)
|
||||
// this really should stream byte-by-byte, but it's not necessary since the size is known
|
||||
m_buffer.offset = 0;
|
||||
m_buffer.size = m_dma[i].size ? m_dma[i].size : 65536;
|
||||
|
||||
|
||||
// SDD1_emu calls this function; it needs to access uncompressed data;
|
||||
// so temporarily disable decompression mode for decompress() call.
|
||||
m_sdd1emu->SDD1emu_decompress(m_rom, m_mmc, addr, m_buffer.size, m_buffer.data);
|
||||
|
||||
|
||||
m_buffer.ready = 1;
|
||||
}
|
||||
|
||||
|
||||
// fetch a decompressed byte; once buffer is depleted, disable channel and invalidate buffer
|
||||
data = m_buffer.data[(UINT16)m_buffer.offset++];
|
||||
if (m_buffer.offset >= m_buffer.size)
|
||||
@ -567,7 +567,7 @@ UINT8 sns_rom_sdd1_device::read_helper(UINT32 addr)
|
||||
m_buffer.ready = 0;
|
||||
m_xfer_enable &= ~(1 << i);
|
||||
}
|
||||
|
||||
|
||||
return data;
|
||||
}
|
||||
}
|
||||
@ -597,6 +597,6 @@ READ8_MEMBER(sns_rom_sdd1_device::read_h)
|
||||
|
||||
WRITE8_MEMBER(sns_rom_sdd1_device::write_l)
|
||||
{
|
||||
if (offset >= 0x700000 && (offset & 0xffff) < 0x8000 && m_nvram_size > 0) // SRAM
|
||||
if (offset >= 0x700000 && (offset & 0xffff) < 0x8000 && m_nvram_size > 0) // SRAM
|
||||
m_nvram[offset & 0x1fff] = data;
|
||||
}
|
||||
|
||||
@ -9,10 +9,10 @@ class SDD1__IM //Input Manager
|
||||
{
|
||||
public:
|
||||
SDD1__IM() {}
|
||||
|
||||
|
||||
UINT32 m_byte_ptr;
|
||||
UINT8 m_bit_count;
|
||||
|
||||
|
||||
void IM_prepareDecomp(UINT32 in_buf);
|
||||
UINT8 IM_getCodeword(UINT8 *ROM, UINT32 *mmc, const UINT8 code_len);
|
||||
};
|
||||
@ -22,9 +22,9 @@ class SDD1__GCD //Golomb-Code Decoder
|
||||
public:
|
||||
SDD1__GCD(SDD1__IM* associatedIM)
|
||||
: m_IM(associatedIM) { }
|
||||
|
||||
|
||||
SDD1__IM* m_IM;
|
||||
|
||||
|
||||
void GCD_getRunCount(UINT8 *ROM, UINT32 *mmc, UINT8 code_num, UINT8* MPScount, UINT8* LPSind);
|
||||
};
|
||||
|
||||
@ -34,12 +34,12 @@ public:
|
||||
SDD1__BG(SDD1__GCD* associatedGCD, UINT8 code)
|
||||
: m_code_num(code),
|
||||
m_GCD(associatedGCD) { }
|
||||
|
||||
|
||||
UINT8 m_code_num;
|
||||
UINT8 m_MPScount;
|
||||
UINT8 m_LPSind;
|
||||
SDD1__GCD* m_GCD;
|
||||
|
||||
|
||||
void BG_prepareDecomp();
|
||||
UINT8 BG_getBit(UINT8 *ROM, UINT32 *mmc, UINT8* endOfRun);
|
||||
} ;
|
||||
@ -54,10 +54,10 @@ class SDD1__PEM //Probability Estimation Module
|
||||
{
|
||||
public:
|
||||
SDD1__PEM(
|
||||
SDD1__BG* associatedBG0, SDD1__BG* associatedBG1,
|
||||
SDD1__BG* associatedBG2, SDD1__BG* associatedBG3,
|
||||
SDD1__BG* associatedBG4, SDD1__BG* associatedBG5,
|
||||
SDD1__BG* associatedBG6, SDD1__BG* associatedBG7)
|
||||
SDD1__BG* associatedBG0, SDD1__BG* associatedBG1,
|
||||
SDD1__BG* associatedBG2, SDD1__BG* associatedBG3,
|
||||
SDD1__BG* associatedBG4, SDD1__BG* associatedBG5,
|
||||
SDD1__BG* associatedBG6, SDD1__BG* associatedBG7)
|
||||
{
|
||||
m_BG[0] = associatedBG0;
|
||||
m_BG[1] = associatedBG1;
|
||||
@ -68,10 +68,10 @@ public:
|
||||
m_BG[6] = associatedBG6;
|
||||
m_BG[7] = associatedBG7;
|
||||
}
|
||||
|
||||
|
||||
SDD1__PEM_ContextInfo m_contextInfo[32];
|
||||
SDD1__BG* m_BG[8];
|
||||
|
||||
|
||||
void PEM_prepareDecomp();
|
||||
UINT8 PEM_getBit(UINT8 *ROM, UINT32 *mmc, UINT8 context);
|
||||
} ;
|
||||
@ -82,14 +82,14 @@ class SDD1__CM
|
||||
public:
|
||||
SDD1__CM(SDD1__PEM* associatedPEM)
|
||||
: m_PEM(associatedPEM) { }
|
||||
|
||||
|
||||
UINT8 m_bitplanesInfo;
|
||||
UINT8 m_contextBitsInfo;
|
||||
UINT8 m_bit_number;
|
||||
UINT8 m_currBitplane;
|
||||
UINT16 m_prevBitplaneBits[8];
|
||||
SDD1__PEM* m_PEM;
|
||||
|
||||
|
||||
void CM_prepareDecomp(UINT8 *ROM, UINT32 *mmc, UINT32 first_byte);
|
||||
UINT8 CM_getBit(UINT8 *ROM, UINT32 *mmc);
|
||||
} ;
|
||||
@ -100,12 +100,12 @@ class SDD1__OL
|
||||
public:
|
||||
SDD1__OL(SDD1__CM* associatedCM)
|
||||
: m_CM(associatedCM) { }
|
||||
|
||||
|
||||
UINT8 m_bitplanesInfo;
|
||||
UINT16 m_length;
|
||||
UINT8* m_buffer;
|
||||
SDD1__CM* m_CM;
|
||||
|
||||
|
||||
void OL_prepareDecomp(UINT8 *ROM, UINT32 *mmc, UINT32 first_byte, UINT16 out_len, UINT8 *out_buf);
|
||||
void OL_launch(UINT8 *ROM, UINT32 *mmc);
|
||||
} ;
|
||||
@ -114,9 +114,9 @@ class SDD1__emu
|
||||
{
|
||||
public:
|
||||
SDD1__emu(running_machine &machine);
|
||||
|
||||
|
||||
running_machine &machine() const { return m_machine; }
|
||||
|
||||
|
||||
SDD1__IM* m_IM;
|
||||
SDD1__GCD* m_GCD;
|
||||
SDD1__BG* m_BG0; SDD1__BG* m_BG1; SDD1__BG* m_BG2; SDD1__BG* m_BG3;
|
||||
@ -124,9 +124,9 @@ public:
|
||||
SDD1__PEM* m_PEM;
|
||||
SDD1__CM* m_CM;
|
||||
SDD1__OL* m_OL;
|
||||
|
||||
|
||||
void SDD1emu_decompress(UINT8 *ROM, UINT32 *mmc, UINT32 in_buf, UINT16 out_len, UINT8 *out_buf);
|
||||
|
||||
|
||||
private:
|
||||
running_machine& m_machine;
|
||||
};
|
||||
@ -136,13 +136,13 @@ private:
|
||||
// ======================> sns_rom_sdd1_device
|
||||
|
||||
class sns_rom_sdd1_device : public device_t,
|
||||
public device_sns_cart_interface
|
||||
public device_sns_cart_interface
|
||||
{
|
||||
public:
|
||||
// construction/destruction
|
||||
sns_rom_sdd1_device(const machine_config &mconfig, device_type type, const char *name, const char *tag, device_t *owner, UINT32 clock);
|
||||
sns_rom_sdd1_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
|
||||
|
||||
|
||||
// device-level overrides
|
||||
virtual void device_start();
|
||||
virtual void device_config_complete() { m_shortname = "sns_rom_sdd1"; }
|
||||
@ -159,13 +159,13 @@ public:
|
||||
UINT8 m_sdd1_enable; // channel bit-mask
|
||||
UINT8 m_xfer_enable; // channel bit-mask
|
||||
UINT32 m_mmc[4]; // memory map controller ROM indices
|
||||
|
||||
|
||||
struct
|
||||
{
|
||||
UINT32 addr; // $43x2-$43x4 -- DMA transfer address
|
||||
UINT16 size; // $43x5-$43x6 -- DMA transfer size
|
||||
} m_dma[8];
|
||||
|
||||
|
||||
SDD1__emu* m_sdd1emu;
|
||||
|
||||
struct
|
||||
|
||||
@ -1,10 +1,10 @@
|
||||
/***********************************************************************************************************
|
||||
|
||||
|
||||
SuperFX add-on chip emulation (for SNES/SFC)
|
||||
|
||||
|
||||
Copyright MESS Team.
|
||||
Visit http://mamedev.org for licensing and usage restrictions.
|
||||
|
||||
|
||||
***********************************************************************************************************/
|
||||
|
||||
|
||||
@ -110,13 +110,13 @@ WRITE8_MEMBER( sns_rom_superfx_device::chip_write )
|
||||
READ8_MEMBER( sns_rom_superfx_device::read_l )
|
||||
{
|
||||
UINT16 address = offset & 0xffff;
|
||||
|
||||
|
||||
if (offset < 0x400000)
|
||||
{
|
||||
if (address >= 0x6000 && address < 0x8000)
|
||||
{
|
||||
if (superfx_access_ram(m_superfx))
|
||||
return sfx_ram[offset & 0x1fff];
|
||||
return sfx_ram[offset & 0x1fff];
|
||||
}
|
||||
if (address >= 0x8000)
|
||||
return m_rom[rom_bank_map[offset / 0x10000] * 0x8000 + (offset & 0x7fff)];
|
||||
@ -139,10 +139,10 @@ READ8_MEMBER( sns_rom_superfx_device::read_l )
|
||||
else
|
||||
{
|
||||
if (superfx_access_ram(m_superfx))
|
||||
return sfx_ram[offset & 0xfffff];
|
||||
return sfx_ram[offset & 0xfffff];
|
||||
}
|
||||
|
||||
return 0xff; // should be open bus...
|
||||
|
||||
return 0xff; // should be open bus...
|
||||
}
|
||||
|
||||
|
||||
@ -167,13 +167,13 @@ WRITE8_MEMBER( sns_rom_superfx_device::write_l )
|
||||
READ8_MEMBER(sns_rom_superfx_device::read_h)
|
||||
{
|
||||
UINT16 address = offset & 0xffff;
|
||||
|
||||
|
||||
if (offset < 0x400000)
|
||||
{
|
||||
if (address >= 0x6000 && address < 0x8000)
|
||||
{
|
||||
if (superfx_access_ram(m_superfx))
|
||||
return sfx_ram[offset & 0x1fff];
|
||||
return sfx_ram[offset & 0x1fff];
|
||||
}
|
||||
if (address >= 0x8000)
|
||||
return m_rom[rom_bank_map[offset / 0x10000] * 0x8000 + (offset & 0x7fff)];
|
||||
@ -196,10 +196,10 @@ READ8_MEMBER(sns_rom_superfx_device::read_h)
|
||||
else
|
||||
{
|
||||
if (superfx_access_ram(m_superfx))
|
||||
return sfx_ram[offset & 0xfffff];
|
||||
return sfx_ram[offset & 0xfffff];
|
||||
}
|
||||
|
||||
return 0xff; // should be open bus...
|
||||
|
||||
return 0xff; // should be open bus...
|
||||
}
|
||||
|
||||
WRITE8_MEMBER( sns_rom_superfx_device::write_h )
|
||||
@ -219,4 +219,3 @@ WRITE8_MEMBER( sns_rom_superfx_device::write_h )
|
||||
sfx_ram[offset & 0xfffff] = data;
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
@ -13,14 +13,14 @@ class sns_rom_superfx_device : public sns_rom_device
|
||||
public:
|
||||
// construction/destruction
|
||||
sns_rom_superfx_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
|
||||
|
||||
|
||||
// device-level overrides
|
||||
virtual void device_start();
|
||||
virtual void device_config_complete() { m_shortname = "sns_rom_superfx"; }
|
||||
virtual machine_config_constructor device_mconfig_additions() const;
|
||||
|
||||
|
||||
required_device<device_t> m_superfx;
|
||||
|
||||
|
||||
// additional reading and writing
|
||||
virtual DECLARE_READ8_MEMBER(read_l);
|
||||
virtual DECLARE_WRITE8_MEMBER(write_l);
|
||||
@ -28,7 +28,7 @@ public:
|
||||
virtual DECLARE_WRITE8_MEMBER(write_h);
|
||||
virtual DECLARE_READ8_MEMBER(chip_read);
|
||||
virtual DECLARE_WRITE8_MEMBER(chip_write);
|
||||
|
||||
|
||||
virtual DECLARE_READ8_MEMBER(superfx_r_bank1);
|
||||
virtual DECLARE_READ8_MEMBER(superfx_r_bank2);
|
||||
virtual DECLARE_READ8_MEMBER(superfx_r_bank3);
|
||||
@ -36,8 +36,8 @@ public:
|
||||
virtual DECLARE_WRITE8_MEMBER(superfx_w_bank2);
|
||||
virtual DECLARE_WRITE8_MEMBER(superfx_w_bank3);
|
||||
virtual DECLARE_WRITE_LINE_MEMBER(snes_extern_irq_w);
|
||||
|
||||
|
||||
|
||||
|
||||
UINT8 sfx_ram[0x200000];
|
||||
};
|
||||
|
||||
|
||||
@ -1,11 +1,11 @@
|
||||
/***********************************************************************************************************
|
||||
|
||||
|
||||
|
||||
SNES cart emulation
|
||||
(through slot devices)
|
||||
|
||||
|
||||
|
||||
|
||||
***********************************************************************************************************/
|
||||
|
||||
|
||||
@ -96,7 +96,7 @@ void device_sns_cart_interface::rtc_ram_alloc(running_machine &machine, UINT32 s
|
||||
|
||||
|
||||
//-------------------------------------------------
|
||||
// addon_bios_alloc - alloc the space for the
|
||||
// addon_bios_alloc - alloc the space for the
|
||||
// (optional) add-on CPU bios
|
||||
//-------------------------------------------------
|
||||
|
||||
@ -111,17 +111,17 @@ void device_sns_cart_interface::addon_bios_alloc(running_machine &machine, UINT3
|
||||
|
||||
|
||||
//-------------------------------------------------
|
||||
// rom_map_setup - setup map of rom banks in 32K
|
||||
// rom_map_setup - setup map of rom banks in 32K
|
||||
// blocks, so to simplify ROM access
|
||||
//-------------------------------------------------
|
||||
|
||||
void device_sns_cart_interface::rom_map_setup(UINT32 size)
|
||||
{
|
||||
int i;
|
||||
// setup the rom_bank_map array to faster ROM read
|
||||
// setup the rom_bank_map array to faster ROM read
|
||||
for (i = 0; i < size / 0x8000; i++)
|
||||
rom_bank_map[i] = i;
|
||||
|
||||
|
||||
// fill up remaining blocks with mirrors
|
||||
while (i % 256)
|
||||
{
|
||||
@ -135,12 +135,12 @@ void device_sns_cart_interface::rom_map_setup(UINT32 size)
|
||||
}
|
||||
|
||||
// check bank map!
|
||||
// for (i = 0; i < 256; i++)
|
||||
// {
|
||||
// printf("bank %3d = %3d\t", i, rom_bank_map[i]);
|
||||
// if ((i%8) == 7)
|
||||
// printf("\n");
|
||||
// }
|
||||
// for (i = 0; i < 256; i++)
|
||||
// {
|
||||
// printf("bank %3d = %3d\t", i, rom_bank_map[i]);
|
||||
// if ((i%8) == 7)
|
||||
// printf("\n");
|
||||
// }
|
||||
}
|
||||
|
||||
//**************************************************************************
|
||||
@ -244,8 +244,8 @@ static const sns_slot slot_list[] =
|
||||
{ SNES_STROM, "strom"},
|
||||
// pirate carts
|
||||
{ SNES_POKEMON, "lorom_poke"},
|
||||
{ SNES_BANANA, "lorom_paja"}, // wip
|
||||
{ SNES_SOULBLAD, "lorom_sbld"} // wip
|
||||
{ SNES_BANANA, "lorom_paja"}, // wip
|
||||
{ SNES_SOULBLAD, "lorom_sbld"} // wip
|
||||
};
|
||||
|
||||
static int sns_get_pcb_id(const char *slot)
|
||||
@ -255,7 +255,7 @@ static int sns_get_pcb_id(const char *slot)
|
||||
if (!mame_stricmp(slot_list[i].slot_option, slot))
|
||||
return slot_list[i].pcb_id;
|
||||
}
|
||||
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
@ -266,7 +266,7 @@ static const char *sns_get_slot(int type)
|
||||
if (slot_list[i].pcb_id == type)
|
||||
return slot_list[i].slot_option;
|
||||
}
|
||||
|
||||
|
||||
return "lorom";
|
||||
}
|
||||
|
||||
@ -285,10 +285,10 @@ UINT32 base_sns_cart_slot_device::snes_skip_header( UINT8 *ROM, UINT32 rom_size
|
||||
{
|
||||
UINT8 header[512];
|
||||
UINT32 offset = 512;
|
||||
|
||||
|
||||
/* Check for a header (512 bytes) */
|
||||
memcpy(header, ROM, 512);
|
||||
|
||||
|
||||
if ((header[8] == 0xaa) && (header[9] == 0xbb) && (header[10] == 0x04))
|
||||
{
|
||||
/* Found an SWC identifier */
|
||||
@ -310,7 +310,7 @@ UINT32 base_sns_cart_slot_device::snes_skip_header( UINT8 *ROM, UINT32 rom_size
|
||||
logerror("No header found.\n");
|
||||
offset = 0;
|
||||
}
|
||||
|
||||
|
||||
return offset;
|
||||
}
|
||||
|
||||
@ -326,17 +326,17 @@ static int snes_validate_infoblock( UINT8 *infoblock, UINT32 offset )
|
||||
UINT16 ichecksum = infoblock[offset + 0x1c] | (infoblock[offset + 0x1d] << 8);
|
||||
UINT8 reset_opcode = infoblock[(offset & ~0x7fff) | (reset_vector & 0x7fff)]; //first opcode executed upon reset
|
||||
UINT8 mapper = infoblock[offset + 0x15] & ~0x10; //mask off irrelevant FastROM-capable bit
|
||||
|
||||
|
||||
/* $00:[000-7fff] contains uninitialized RAM and MMIO.
|
||||
reset vector must point to ROM at $00:[8000-ffff] to be considered valid. */
|
||||
if (reset_vector < 0x8000)
|
||||
return 0;
|
||||
|
||||
|
||||
/* some images duplicate the header in multiple locations, and others have completely
|
||||
invalid header information that cannot be relied upon. The code below will analyze
|
||||
the first opcode executed at the specified reset vector to determine the probability
|
||||
that this is the correct header. Score is assigned accordingly. */
|
||||
|
||||
|
||||
/* most likely opcodes */
|
||||
if (reset_opcode == 0x78 //sei
|
||||
|| reset_opcode == 0x18 //clc (clc; xce)
|
||||
@ -346,7 +346,7 @@ static int snes_validate_infoblock( UINT8 *infoblock, UINT32 offset )
|
||||
|| reset_opcode == 0x5c //jml $nnnnnn
|
||||
)
|
||||
score += 8;
|
||||
|
||||
|
||||
/* plausible opcodes */
|
||||
if (reset_opcode == 0xc2 //rep #$nn
|
||||
|| reset_opcode == 0xe2 //sep #$nn
|
||||
@ -361,7 +361,7 @@ static int snes_validate_infoblock( UINT8 *infoblock, UINT32 offset )
|
||||
|| reset_opcode == 0x22 //jsl $nnnnnn
|
||||
)
|
||||
score += 4;
|
||||
|
||||
|
||||
/* implausible opcodes */
|
||||
if (reset_opcode == 0x40 //rti
|
||||
|| reset_opcode == 0x60 //rts
|
||||
@ -371,7 +371,7 @@ static int snes_validate_infoblock( UINT8 *infoblock, UINT32 offset )
|
||||
|| reset_opcode == 0xcc //cpy $nnnn
|
||||
)
|
||||
score -= 4;
|
||||
|
||||
|
||||
/* least likely opcodes */
|
||||
if (reset_opcode == 0x00 //brk #$nn
|
||||
|| reset_opcode == 0x02 //cop #$nn
|
||||
@ -380,47 +380,47 @@ static int snes_validate_infoblock( UINT8 *infoblock, UINT32 offset )
|
||||
|| reset_opcode == 0xff //sbc $nnnnnn,x
|
||||
)
|
||||
score -= 8;
|
||||
|
||||
|
||||
/* Sometimes, both the header and reset vector's first opcode will match ...
|
||||
fallback and rely on info validity in these cases to determine more likely header. */
|
||||
|
||||
|
||||
/* a valid checksum is the biggest indicator of a valid header. */
|
||||
if ((checksum + ichecksum) == 0xffff && (checksum != 0) && (ichecksum != 0))
|
||||
score += 4;
|
||||
|
||||
|
||||
/* then there are the expected mapper values */
|
||||
if (offset == 0x007fc0 && mapper == 0x20) // 0x20 is usually LoROM
|
||||
score += 2;
|
||||
|
||||
|
||||
if (offset == 0x00ffc0 && mapper == 0x21) // 0x21 is usually HiROM
|
||||
score += 2;
|
||||
|
||||
|
||||
if (offset == 0x007fc0 && mapper == 0x22) // 0x22 is usually ExLoROM
|
||||
score += 2;
|
||||
|
||||
|
||||
if (offset == 0x40ffc0 && mapper == 0x25) // 0x25 is usually ExHiROM
|
||||
score += 2;
|
||||
|
||||
|
||||
/* finally, there are valid values in the Company, Region etc. fields */
|
||||
if (infoblock[offset + 0x1a] == 0x33) // Company field: 0x33 indicates extended header
|
||||
score += 2;
|
||||
|
||||
|
||||
if (infoblock[offset + 0x16] < 0x08) // ROM Type field
|
||||
score++;
|
||||
|
||||
|
||||
if (infoblock[offset + 0x17] < 0x10) // ROM Size field
|
||||
score++;
|
||||
|
||||
|
||||
if (infoblock[offset + 0x18] < 0x08) // SRAM Size field
|
||||
score++;
|
||||
|
||||
|
||||
if (infoblock[offset + 0x19] < 14) // Region field
|
||||
score++;
|
||||
|
||||
|
||||
/* do we still have a positive score? */
|
||||
if (score < 0)
|
||||
score = 0;
|
||||
|
||||
|
||||
return score;
|
||||
}
|
||||
|
||||
@ -445,20 +445,20 @@ static UINT32 snes_find_hilo_mode( UINT8 *buffer, UINT32 buf_len )
|
||||
/* Images larger than 32mbits are likely ExHiRom */
|
||||
if (valid_mode25)
|
||||
valid_mode25 += 4;
|
||||
|
||||
|
||||
if ((valid_mode20 >= valid_mode21) && (valid_mode20 >= valid_mode25))
|
||||
retvalue = 0x007fc0;
|
||||
retvalue = 0x007fc0;
|
||||
else if (valid_mode21 >= valid_mode25)
|
||||
retvalue = 0x00ffc0;
|
||||
else
|
||||
retvalue = 0x40ffc0;
|
||||
|
||||
|
||||
logerror( "\t HiROM/LoROM id: %s (LoROM: %d , HiROM: %d, ExHiROM: %d)\n",
|
||||
(retvalue == 0x007fc0) ? "LoROM" :
|
||||
(retvalue == 0x00ffc0) ? "HiROM" :
|
||||
(retvalue == 0x40ffc0) ? "ExHiROM" : "Other",
|
||||
valid_mode20, valid_mode21, valid_mode25);
|
||||
|
||||
(retvalue == 0x007fc0) ? "LoROM" :
|
||||
(retvalue == 0x00ffc0) ? "HiROM" :
|
||||
(retvalue == 0x40ffc0) ? "ExHiROM" : "Other",
|
||||
valid_mode20, valid_mode21, valid_mode25);
|
||||
|
||||
return retvalue;
|
||||
}
|
||||
|
||||
@ -472,23 +472,23 @@ static int snes_find_addon_chip( UINT8 *buffer, UINT32 start_offs )
|
||||
case 0x01:
|
||||
case 0x02:
|
||||
break;
|
||||
|
||||
|
||||
case 0x03:
|
||||
if (buffer[start_offs + 0x15] == 0x30)
|
||||
return SNES_DSP4;
|
||||
else
|
||||
return SNES_DSP;
|
||||
|
||||
|
||||
case 0x04:
|
||||
return SNES_DSP;
|
||||
|
||||
|
||||
case 0x05:
|
||||
// DSP2 can be detected by (buffer[start_offs + 0x15] == 0x20)
|
||||
// DSP3 is harder to detect, and one has to rely on the manufacturer (Bandai)
|
||||
// DSP3 is harder to detect, and one has to rely on the manufacturer (Bandai)
|
||||
// by checking (buffer[start_offs + 0x15] == 0x30) && (buffer[start_offs + 0x1a] == 0xb2)
|
||||
// in other cases is DSP1, but we do treat all these together...
|
||||
return SNES_DSP;
|
||||
|
||||
|
||||
case 0x13: // Mario Chip 1
|
||||
case 0x14: // GSU-x
|
||||
case 0x15: // GSU-x
|
||||
@ -496,41 +496,41 @@ static int snes_find_addon_chip( UINT8 *buffer, UINT32 start_offs )
|
||||
if (buffer[start_offs + 0x15] == 0x20)
|
||||
return SNES_SFX;
|
||||
break;
|
||||
|
||||
|
||||
case 0x25:
|
||||
return SNES_OBC1;
|
||||
|
||||
|
||||
case 0x32: // needed by a Sample game (according to ZSNES)
|
||||
case 0x34:
|
||||
case 0x35:
|
||||
if (buffer[start_offs + 0x15] == 0x23)
|
||||
return SNES_SA1;
|
||||
break;
|
||||
|
||||
|
||||
case 0x43:
|
||||
case 0x45:
|
||||
if (buffer[start_offs + 0x15] == 0x32)
|
||||
return SNES_SDD1;
|
||||
break;
|
||||
|
||||
|
||||
case 0x55:
|
||||
if (buffer[start_offs + 0x15] == 0x35)
|
||||
return SNES_SRTC;
|
||||
break;
|
||||
|
||||
|
||||
case 0xe3:
|
||||
return SNES_Z80GB;
|
||||
|
||||
|
||||
case 0xf3:
|
||||
return SNES_CX4;
|
||||
|
||||
|
||||
case 0xf5:
|
||||
if (buffer[start_offs + 0x15] == 0x30)
|
||||
return SNES_ST018;
|
||||
else if (buffer[start_offs + 0x15] == 0x3a)
|
||||
return SNES_SPC7110;
|
||||
break;
|
||||
|
||||
|
||||
case 0xf6:
|
||||
/* These Seta ST-01X chips have both 0x30 at 0xffd5,
|
||||
they only differ for the 'size' at 0xffd7 */
|
||||
@ -538,12 +538,12 @@ static int snes_find_addon_chip( UINT8 *buffer, UINT32 start_offs )
|
||||
return SNES_ST011;
|
||||
else
|
||||
return SNES_ST010;
|
||||
|
||||
|
||||
case 0xf9:
|
||||
if (buffer[start_offs + 0x15] == 0x3a)
|
||||
return SNES_SPC7110_RTC;
|
||||
break;
|
||||
|
||||
|
||||
default:
|
||||
break;
|
||||
}
|
||||
@ -585,7 +585,7 @@ bool base_sns_cart_slot_device::call_load()
|
||||
|
||||
m_cart->rom_map_setup(len);
|
||||
|
||||
// check for on-cart CPU bios
|
||||
// check for on-cart CPU bios
|
||||
if (software_entry() != NULL)
|
||||
{
|
||||
if (get_software_region("addon"))
|
||||
@ -605,10 +605,10 @@ bool base_sns_cart_slot_device::call_load()
|
||||
else
|
||||
m_type = sns_get_pcb_id(slot_name);
|
||||
}
|
||||
|
||||
|
||||
|
||||
setup_custom_mappers();
|
||||
|
||||
|
||||
setup_nvram();
|
||||
|
||||
if (m_cart->get_nvram_size() || m_cart->get_rtc_ram_size())
|
||||
@ -620,18 +620,18 @@ bool base_sns_cart_slot_device::call_load()
|
||||
memcpy(m_cart->get_nvram_base(), temp_nvram, m_cart->get_nvram_size());
|
||||
if (m_cart->get_rtc_ram_size())
|
||||
memcpy(m_cart->get_rtc_ram_base(), temp_nvram + m_cart->get_nvram_size(), m_cart->get_rtc_ram_size());
|
||||
|
||||
|
||||
if (temp_nvram)
|
||||
auto_free(machine(), temp_nvram);
|
||||
}
|
||||
|
||||
|
||||
printf("Type %d\n", m_type);
|
||||
|
||||
internal_header_logging(ROM, len);
|
||||
|
||||
return IMAGE_INIT_PASS;
|
||||
}
|
||||
|
||||
|
||||
return IMAGE_INIT_PASS;
|
||||
}
|
||||
|
||||
@ -652,7 +652,7 @@ void base_sns_cart_slot_device::call_unload()
|
||||
memcpy(temp_nvram, m_cart->get_nvram_base(), m_cart->get_nvram_size());
|
||||
if (m_cart->get_rtc_ram_size())
|
||||
memcpy(temp_nvram + m_cart->get_nvram_size(), m_cart->get_rtc_ram_base(), m_cart->get_rtc_ram_size());
|
||||
|
||||
|
||||
battery_save(temp_nvram, tot_size);
|
||||
if (temp_nvram)
|
||||
auto_free(machine(), temp_nvram);
|
||||
@ -676,7 +676,7 @@ void base_sns_cart_slot_device::setup_nvram()
|
||||
UINT8 sram_size = (m_type == SNES_SFX) ? (ROM[0x00ffbd] & 0x07) : (ROM[hilo_mode + 0x18] & 0x07);
|
||||
if (sram_size)
|
||||
{
|
||||
UINT32 max = (hilo_mode == 0x007fc0) ? 0x80000 : 0x20000; // MODE20 vs MODE21
|
||||
UINT32 max = (hilo_mode == 0x007fc0) ? 0x80000 : 0x20000; // MODE20 vs MODE21
|
||||
size = 1024 << (ROM[0x00ffbd] & 0x07);
|
||||
if (size > max)
|
||||
size = max;
|
||||
@ -729,12 +729,12 @@ int base_sns_cart_slot_device::get_cart_type(UINT8 *ROM, UINT32 len)
|
||||
break;
|
||||
case 0x00ffc0: // HiRom
|
||||
case 0x40ffc0: // ExHiRom
|
||||
type = SNES_MODE21;
|
||||
type = SNES_MODE21;
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
|
||||
|
||||
// detect Sufami Turbo...
|
||||
if (type == SNES_MODE20 && !memcmp(ROM, "BANDAI SFC-ADX", 14))
|
||||
{
|
||||
@ -757,7 +757,7 @@ int base_sns_cart_slot_device::get_cart_type(UINT8 *ROM, UINT32 len)
|
||||
type = SNES_BSMEMPAK;
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
// check for add-on chips...
|
||||
if (len >= hilo_mode + 0x1a)
|
||||
{
|
||||
@ -808,13 +808,13 @@ const char * base_sns_cart_slot_device::get_default_card_software(const machine_
|
||||
int type;
|
||||
|
||||
core_fread(m_file, ROM, len);
|
||||
|
||||
|
||||
type = get_cart_type(ROM, len);
|
||||
slot_string = sns_get_slot(type);
|
||||
|
||||
|
||||
global_free(ROM);
|
||||
clear();
|
||||
|
||||
|
||||
return slot_string;
|
||||
}
|
||||
|
||||
@ -882,7 +882,7 @@ WRITE8_MEMBER(base_sns_cart_slot_device::chip_write)
|
||||
static int char_to_int_conv( char id )
|
||||
{
|
||||
int value;
|
||||
|
||||
|
||||
if (id == '1') value = 0x01;
|
||||
else if (id == '2') value = 0x02;
|
||||
else if (id == '3') value = 0x03;
|
||||
@ -899,7 +899,7 @@ static int char_to_int_conv( char id )
|
||||
else if (id == 'E') value = 0x0e;
|
||||
else if (id == 'F') value = 0x0f;
|
||||
else value = 0x00;
|
||||
|
||||
|
||||
return value;
|
||||
}
|
||||
|
||||
@ -939,7 +939,7 @@ void base_sns_cart_slot_device::internal_header_logging(UINT8 *ROM, UINT32 len)
|
||||
UNK,
|
||||
UNK
|
||||
};
|
||||
|
||||
|
||||
/* Some known countries */
|
||||
static const char *const countries[] =
|
||||
{
|
||||
@ -948,7 +948,7 @@ void base_sns_cart_slot_device::internal_header_logging(UINT8 *ROM, UINT32 len)
|
||||
/* 8*/ "Spain (PAL)", "Germany, Austria & Switzerland (PAL)", "Italy (PAL)", "Hong Kong & China (PAL)",
|
||||
/* c*/ "Indonesia (PAL)", "South Korea (NTSC)", UNK, UNK,
|
||||
};
|
||||
|
||||
|
||||
/* Some known companies (integrations to the list from Snes9x) */
|
||||
static const char *const companies[] =
|
||||
{
|
||||
@ -1007,7 +1007,7 @@ void base_sns_cart_slot_device::internal_header_logging(UINT8 *ROM, UINT32 len)
|
||||
default:
|
||||
break;
|
||||
}
|
||||
|
||||
|
||||
// detect Sufami Turbo...
|
||||
if (type == SNES_MODE20 && !memcmp(ROM, "BANDAI SFC-ADX", 14))
|
||||
{
|
||||
@ -1016,7 +1016,7 @@ void base_sns_cart_slot_device::internal_header_logging(UINT8 *ROM, UINT32 len)
|
||||
else
|
||||
type = SNES_STROM;
|
||||
}
|
||||
|
||||
|
||||
// detect BS-X Base Cart
|
||||
if (!memcmp(ROM + hilo_mode, "Satellaview BS-X ", 21))
|
||||
type = SNES_BSX;
|
||||
@ -1030,7 +1030,7 @@ void base_sns_cart_slot_device::internal_header_logging(UINT8 *ROM, UINT32 len)
|
||||
type = SNES_BSMEMPAK;
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
addon = snes_find_addon_chip(ROM, hilo_mode);
|
||||
if (addon != -1)
|
||||
{
|
||||
@ -1041,59 +1041,59 @@ void base_sns_cart_slot_device::internal_header_logging(UINT8 *ROM, UINT32 len)
|
||||
else
|
||||
type = addon;
|
||||
}
|
||||
|
||||
|
||||
/* Company */
|
||||
for (int i = 0; i < 2; i++)
|
||||
company_id[i] = ROM[hilo_mode - 0x10 + i];
|
||||
company = (char_to_int_conv(company_id[0]) << 4) + char_to_int_conv(company_id[1]);
|
||||
if (company == 0)
|
||||
company = ROM[hilo_mode + 0x1a];
|
||||
|
||||
|
||||
/* ROM ID */
|
||||
for(int i = 0; i < 4; i++ )
|
||||
rom_id[i] = ROM[hilo_mode - 0x0d + i];
|
||||
|
||||
|
||||
/* Title */
|
||||
for(int i = 0; i < 21; i++ )
|
||||
title[i] = ROM[hilo_mode + i];
|
||||
|
||||
|
||||
/* RAM */
|
||||
if (((ROM[hilo_mode + 0x16] & 0xf) == 1) ||
|
||||
((ROM[hilo_mode + 0x16] & 0xf) == 2) ||
|
||||
((ROM[hilo_mode + 0x16] & 0xf) == 4) ||
|
||||
((ROM[hilo_mode + 0x16] & 0xf) == 5))
|
||||
has_ram = 1;
|
||||
|
||||
|
||||
/* SRAM */
|
||||
if (((ROM[hilo_mode + 0x16] & 0xf) == 2) ||
|
||||
((ROM[hilo_mode + 0x16] & 0xf) == 5) ||
|
||||
((ROM[hilo_mode + 0x16] & 0xf) == 6))
|
||||
has_sram = 1;
|
||||
|
||||
|
||||
logerror( "ROM DETAILS\n" );
|
||||
logerror( "===========\n\n" );
|
||||
logerror( "\tTotal blocks: 0x%x\n", len);
|
||||
logerror( "\tROM bank size: %s \n",
|
||||
(type == SNES_MODE20) ? "LoROM" :
|
||||
(type == SNES_MODE21) ? "HiROM" :
|
||||
(type == SNES_MODE22) ? "ExLoROM" :
|
||||
(type == SNES_MODE25) ? "ExHiROM" : "Other (BSX or ST)" );
|
||||
(type == SNES_MODE20) ? "LoROM" :
|
||||
(type == SNES_MODE21) ? "HiROM" :
|
||||
(type == SNES_MODE22) ? "ExLoROM" :
|
||||
(type == SNES_MODE25) ? "ExHiROM" : "Other (BSX or ST)" );
|
||||
logerror( "\tCompany: %s [%.2s]\n", companies[company], company_id );
|
||||
logerror( "\tROM ID: %.4s\n\n", rom_id );
|
||||
|
||||
|
||||
logerror( "HEADER DETAILS\n" );
|
||||
logerror( "==============\n\n" );
|
||||
logerror( "\tName: %.21s\n", title );
|
||||
logerror( "\tSpeed: %s [%d]\n", (ROM[hilo_mode + 0x15] & 0xf0) ? "FastROM" : "SlowROM", (ROM[hilo_mode + 0x15] & 0xf0) >> 4);
|
||||
logerror( "\tBank size: %s [%d]\n", (ROM[hilo_mode + 0x15] & 0xf) ? "HiROM" : "LoROM", ROM[hilo_mode + 0x15] & 0xf);
|
||||
|
||||
|
||||
logerror( "\tType: %s", cart_types[type]);
|
||||
if (has_ram)
|
||||
logerror( ", RAM");
|
||||
if (has_sram)
|
||||
logerror( ", SRAM");
|
||||
logerror( " [%d]\n", ROM[hilo_mode + 0x16]);
|
||||
|
||||
|
||||
logerror( "\tSize: %d megabits [%d]\n", 1 << (ROM[hilo_mode + 0x17] - 7), ROM[hilo_mode + 0x17]);
|
||||
logerror( "\tSRAM: %d kilobits [%d]\n", ROM[hilo_mode + 0x18] * 8, ROM[hilo_mode + 0x18] );
|
||||
logerror( "\tCountry: %s [%d]\n", countries[ROM[hilo_mode + 0x19]], ROM[hilo_mode + 0x19]);
|
||||
@ -1103,6 +1103,6 @@ void base_sns_cart_slot_device::internal_header_logging(UINT8 *ROM, UINT32 len)
|
||||
logerror( "\tChecksum: %X %X\n", ROM[hilo_mode + 0x1f], ROM[hilo_mode + 0x1e]);
|
||||
logerror( "\tNMI Address: %2X%2Xh\n", ROM[hilo_mode + 0x2b], ROM[hilo_mode + 0x2a]);
|
||||
logerror( "\tStart Address: %2X%2Xh\n\n", ROM[hilo_mode + 0x2d], ROM[hilo_mode + 0x2c]);
|
||||
|
||||
|
||||
logerror( "\tMode: %d\n", type);
|
||||
}
|
||||
|
||||
@ -11,8 +11,8 @@ enum
|
||||
{
|
||||
SNES_MODE20 = 0,
|
||||
SNES_MODE21,
|
||||
SNES_MODE22, // ExLoROM - not used anymore in emulation (only to log info), will be removed
|
||||
SNES_MODE25, // ExHiROM - not used anymore in emulation (only to log info), will be removed
|
||||
SNES_MODE22, // ExLoROM - not used anymore in emulation (only to log info), will be removed
|
||||
SNES_MODE25, // ExHiROM - not used anymore in emulation (only to log info), will be removed
|
||||
SNES_CX4,
|
||||
SNES_DSP,
|
||||
SNES_DSP_MODE21,
|
||||
@ -36,8 +36,8 @@ enum
|
||||
SNES_STROM,
|
||||
// pirate carts
|
||||
SNES_POKEMON,
|
||||
SNES_BANANA, // wip
|
||||
SNES_SOULBLAD // wip
|
||||
SNES_BANANA, // wip
|
||||
SNES_SOULBLAD // wip
|
||||
};
|
||||
|
||||
|
||||
@ -79,18 +79,18 @@ public:
|
||||
virtual UINT32 get_rtc_ram_size() { return m_rtc_ram_size; };
|
||||
|
||||
virtual void rom_map_setup(UINT32 size);
|
||||
|
||||
|
||||
// internal state
|
||||
UINT8 *m_rom;
|
||||
UINT8 *m_nvram;
|
||||
UINT8 *m_bios;
|
||||
UINT8 *m_rtc_ram; // temp pointer to save RTC ram to nvram (will disappear when RTCs become devices)
|
||||
UINT8 *m_rtc_ram; // temp pointer to save RTC ram to nvram (will disappear when RTCs become devices)
|
||||
UINT32 m_rom_size;
|
||||
UINT32 m_nvram_size;
|
||||
UINT32 m_bios_size;
|
||||
UINT32 m_rtc_ram_size; // temp
|
||||
UINT32 m_rtc_ram_size; // temp
|
||||
|
||||
UINT8 rom_bank_map[256]; // 32K chunks of rom
|
||||
UINT8 rom_bank_map[256]; // 32K chunks of rom
|
||||
};
|
||||
|
||||
|
||||
@ -105,11 +105,11 @@ public:
|
||||
// construction/destruction
|
||||
base_sns_cart_slot_device(const machine_config &mconfig, device_type type, const char *name, const char *tag, device_t *owner, UINT32 clock);
|
||||
virtual ~base_sns_cart_slot_device();
|
||||
|
||||
|
||||
// device-level overrides
|
||||
virtual void device_start();
|
||||
virtual void device_config_complete();
|
||||
|
||||
|
||||
// image-level overrides
|
||||
virtual bool call_load();
|
||||
virtual void call_unload();
|
||||
@ -146,8 +146,8 @@ public:
|
||||
// this should be private, but then there is some problem installing delegates in the driver...
|
||||
//private:
|
||||
|
||||
device_sns_cart_interface* m_cart;
|
||||
|
||||
device_sns_cart_interface* m_cart;
|
||||
|
||||
int m_type;
|
||||
};
|
||||
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@ -23,18 +23,18 @@ class SPC7110_Decomp
|
||||
{
|
||||
public:
|
||||
SPC7110_Decomp(running_machine &machine);
|
||||
|
||||
|
||||
running_machine &machine() const { return m_machine; }
|
||||
|
||||
|
||||
void init(running_machine &machine, UINT8 *ROM, UINT32 len, UINT32 mode, UINT32 offset, UINT32 index);
|
||||
void reset();
|
||||
|
||||
|
||||
UINT8 read(UINT8 *ROM, UINT32 len);
|
||||
void write(UINT8 data);
|
||||
void mode0(UINT8 init, UINT8 *ROM, UINT32 len);
|
||||
void mode1(UINT8 init, UINT8 *ROM, UINT32 len);
|
||||
void mode2(UINT8 init, UINT8 *ROM, UINT32 len);
|
||||
|
||||
|
||||
UINT8 dataread(UINT8 *ROM, UINT32 len);
|
||||
UINT8 probability(UINT32 n);
|
||||
UINT8 next_lps(UINT32 n);
|
||||
@ -42,25 +42,25 @@ public:
|
||||
UINT8 toggle_invert(UINT32 n);
|
||||
UINT32 morton_2x8(UINT32 data);
|
||||
UINT32 morton_4x8(UINT32 data);
|
||||
|
||||
|
||||
UINT32 m_decomp_mode;
|
||||
UINT32 m_decomp_offset;
|
||||
|
||||
|
||||
UINT8 *m_decomp_buffer;
|
||||
UINT32 m_decomp_buffer_rdoffset;
|
||||
UINT32 m_decomp_buffer_wroffset;
|
||||
UINT32 m_decomp_buffer_length;
|
||||
|
||||
|
||||
struct ContextState
|
||||
{
|
||||
UINT8 index;
|
||||
UINT8 invert;
|
||||
} m_context[32];
|
||||
|
||||
|
||||
UINT32 m_morton16[2][256];
|
||||
UINT32 m_morton32[4][256];
|
||||
|
||||
|
||||
|
||||
|
||||
private:
|
||||
running_machine& m_machine;
|
||||
UINT32 m_rom_size;
|
||||
@ -74,7 +74,7 @@ public:
|
||||
// construction/destruction
|
||||
sns_rom_spc7110_device(const machine_config &mconfig, device_type type, const char *name, const char *tag, device_t *owner, UINT32 clock);
|
||||
sns_rom_spc7110_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
|
||||
|
||||
|
||||
// device-level overrides
|
||||
virtual void device_start();
|
||||
virtual void device_config_complete() { m_shortname = "sns_rom_spc7110"; }
|
||||
@ -95,7 +95,7 @@ public:
|
||||
void spc7110_set_data_pointer(UINT32 addr);
|
||||
void spc7110_set_data_adjust(UINT32 addr);
|
||||
void spc7110_update_time(UINT8 offset);
|
||||
|
||||
|
||||
|
||||
//==================
|
||||
//decompression unit
|
||||
@ -112,9 +112,9 @@ public:
|
||||
UINT8 m_r480a; // compression length high
|
||||
UINT8 m_r480b; // decompression control register
|
||||
UINT8 m_r480c; // decompression status
|
||||
|
||||
|
||||
SPC7110_Decomp* m_decomp;
|
||||
|
||||
|
||||
UINT8 m_r4811; // data pointer low
|
||||
UINT8 m_r4812; // data pointer high
|
||||
UINT8 m_r4813; // data pointer bank
|
||||
@ -123,12 +123,12 @@ public:
|
||||
UINT8 m_r4816; // data increment low
|
||||
UINT8 m_r4817; // data increment high
|
||||
UINT8 m_r4818; // data port control register
|
||||
|
||||
|
||||
UINT8 m_r481x;
|
||||
|
||||
|
||||
UINT8 m_r4814_latch;
|
||||
UINT8 m_r4815_latch;
|
||||
|
||||
|
||||
//=========
|
||||
//math unit
|
||||
//=========
|
||||
@ -148,7 +148,7 @@ public:
|
||||
UINT8 m_r482d; // 16-bit remainder B1
|
||||
UINT8 m_r482e; // math control register
|
||||
UINT8 m_r482f; // math status
|
||||
|
||||
|
||||
//===================
|
||||
//memory mapping unit
|
||||
//===================
|
||||
@ -157,27 +157,27 @@ public:
|
||||
UINT8 m_r4832; // $[e0-ef]:[0000-ffff] mapping
|
||||
UINT8 m_r4833; // $[f0-ff]:[0000-ffff] mapping
|
||||
UINT8 m_r4834; // ???
|
||||
|
||||
|
||||
UINT32 m_dx_offset;
|
||||
UINT32 m_ex_offset;
|
||||
UINT32 m_fx_offset;
|
||||
|
||||
|
||||
//====================
|
||||
//real-time clock unit
|
||||
//====================
|
||||
UINT8 m_r4840; // RTC latch
|
||||
UINT8 m_r4841; // RTC index/data port
|
||||
UINT8 m_r4842; // RTC status
|
||||
|
||||
|
||||
UINT32 m_rtc_state;
|
||||
UINT32 m_rtc_mode;
|
||||
UINT32 m_rtc_index;
|
||||
|
||||
|
||||
UINT64 m_rtc_offset;
|
||||
|
||||
//this is now allocated in the main snes cart class, to allow saving to nvram
|
||||
//UINT8 m_rtc_ram[16]; // 0-12 secs, min, hrs, etc.; 13-14-15 control registers
|
||||
|
||||
|
||||
UINT8 m_ram[0x2000];
|
||||
};
|
||||
|
||||
@ -188,22 +188,22 @@ class sns_rom_spc7110rtc_device : public sns_rom_spc7110_device
|
||||
public:
|
||||
// construction/destruction
|
||||
sns_rom_spc7110rtc_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
|
||||
|
||||
|
||||
// device-level overrides
|
||||
virtual void device_start();
|
||||
virtual void device_config_complete() { m_shortname = "sns_rom_spc7110rtc"; }
|
||||
|
||||
|
||||
// reading and writing
|
||||
|
||||
// we just use the spc7110 ones for the moment, pending the split of regs 0x4840-0x4842 (RTC) from the base add-on
|
||||
// virtual DECLARE_READ8_MEMBER(read_l);
|
||||
// virtual DECLARE_READ8_MEMBER(read_h);
|
||||
// virtual DECLARE_WRITE8_MEMBER(write_l);
|
||||
|
||||
// virtual DECLARE_READ8_MEMBER(chip_read);
|
||||
// virtual DECLARE_WRITE8_MEMBER(chip_write);
|
||||
// virtual DECLARE_READ8_MEMBER(read_l);
|
||||
// virtual DECLARE_READ8_MEMBER(read_h);
|
||||
// virtual DECLARE_WRITE8_MEMBER(write_l);
|
||||
|
||||
// virtual DECLARE_READ8_MEMBER(chip_read);
|
||||
// virtual DECLARE_WRITE8_MEMBER(chip_write);
|
||||
};
|
||||
|
||||
|
||||
// device type definition
|
||||
extern const device_type SNS_HIROM_SPC7110;
|
||||
extern const device_type SNS_HIROM_SPC7110_RTC;
|
||||
|
||||
@ -1,15 +1,15 @@
|
||||
/***********************************************************************************************************
|
||||
|
||||
|
||||
Bandai Sufami Turbo cartridge emulation (for SNES/SFC)
|
||||
|
||||
|
||||
Copyright MESS Team.
|
||||
Visit http://mamedev.org for licensing and usage restrictions.
|
||||
|
||||
|
||||
This is basically a standard LoROM cart with two slots for ST minicarts
|
||||
The content of each slot (with ROM and RAM) is mapped to a separate memory range
|
||||
Slot 1: ROM [20-3f][8000-ffff], RAM [60-63][8000-ffff]
|
||||
Slot 2: ROM [40-5f][8000-ffff], RAM [70-73][8000-ffff]
|
||||
|
||||
|
||||
***********************************************************************************************************/
|
||||
|
||||
|
||||
@ -81,32 +81,32 @@ READ8_MEMBER(sns_rom_sufami_device::read_l)
|
||||
|
||||
READ8_MEMBER(sns_rom_sufami_device::read_h)
|
||||
{
|
||||
if (offset < 0x200000) // SUFAMI TURBO ROM
|
||||
if (offset < 0x200000) // SUFAMI TURBO ROM
|
||||
{
|
||||
int bank = offset / 0x10000;
|
||||
return m_rom[rom_bank_map[bank] * 0x8000 + (offset & 0x7fff)];
|
||||
}
|
||||
if (offset >= 0x200000 && offset < 0x400000) // SLOT1 STROM
|
||||
if (offset >= 0x200000 && offset < 0x400000) // SLOT1 STROM
|
||||
{
|
||||
if (m_slot1->m_cart)
|
||||
return m_slot1->m_cart->read_l(space, offset - 0x200000);
|
||||
}
|
||||
if (offset >= 0x400000 && offset < 0x600000) // SLOT2 STROM
|
||||
if (offset >= 0x400000 && offset < 0x600000) // SLOT2 STROM
|
||||
{
|
||||
if (m_slot2->m_cart)
|
||||
return m_slot2->m_cart->read_l(space, offset - 0x400000);
|
||||
}
|
||||
if (offset >= 0x600000 && offset < 0x640000) // SLOT1 RAM
|
||||
if (offset >= 0x600000 && offset < 0x640000) // SLOT1 RAM
|
||||
{
|
||||
if (m_slot1->m_cart && (offset & 0xffff) > 0x8000)
|
||||
return m_slot1->m_cart->read_h(space, offset - 0x600000);
|
||||
}
|
||||
if (offset >= 0x700000 && offset < 0x740000) // SLOT2 RAM
|
||||
if (offset >= 0x700000 && offset < 0x740000) // SLOT2 RAM
|
||||
{
|
||||
if (m_slot2->m_cart && (offset & 0xffff) > 0x8000)
|
||||
return m_slot2->m_cart->read_h(space, offset - 0x700000);
|
||||
}
|
||||
|
||||
|
||||
return 0xff;
|
||||
}
|
||||
|
||||
@ -117,18 +117,18 @@ WRITE8_MEMBER(sns_rom_sufami_device::write_l)
|
||||
|
||||
WRITE8_MEMBER(sns_rom_sufami_device::write_h)
|
||||
{
|
||||
if (offset >= 0x600000 && offset < 0x640000) // SLOT1 RAM
|
||||
if (offset >= 0x600000 && offset < 0x640000) // SLOT1 RAM
|
||||
{
|
||||
if (m_slot1->m_cart && (offset & 0xffff) > 0x8000)
|
||||
return m_slot1->m_cart->write_h(space, offset - 0x600000, data);
|
||||
}
|
||||
|
||||
if (offset >= 0x700000 && offset < 0x740000) // SLOT2 RAM
|
||||
|
||||
if (offset >= 0x700000 && offset < 0x740000) // SLOT2 RAM
|
||||
{
|
||||
if (m_slot2->m_cart && (offset & 0xffff) > 0x8000)
|
||||
return m_slot2->m_cart->write_h(space, offset - 0x700000, data);
|
||||
}
|
||||
|
||||
|
||||
}
|
||||
|
||||
/*-------------------------------------------------
|
||||
@ -172,5 +172,3 @@ WRITE8_MEMBER(sns_rom_strom_device::write_h)
|
||||
m_nvram[bank * 0x8000 + (offset & 0x7fff)] = data;
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
|
||||
@ -12,12 +12,12 @@ class sns_rom_sufami_device : public sns_rom_device
|
||||
public:
|
||||
// construction/destruction
|
||||
sns_rom_sufami_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
|
||||
|
||||
|
||||
// device-level overrides
|
||||
virtual void device_start();
|
||||
virtual void device_config_complete() { m_shortname = "sns_rom_sufami"; }
|
||||
virtual machine_config_constructor device_mconfig_additions() const;
|
||||
|
||||
|
||||
// additional reading and writing
|
||||
virtual DECLARE_READ8_MEMBER(read_l);
|
||||
virtual DECLARE_READ8_MEMBER(read_h);
|
||||
@ -36,16 +36,16 @@ class sns_rom_strom_device : public sns_rom_device
|
||||
public:
|
||||
// construction/destruction
|
||||
sns_rom_strom_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
|
||||
|
||||
|
||||
// device-level overrides
|
||||
virtual void device_start();
|
||||
virtual void device_config_complete() { m_shortname = "sns_strom"; }
|
||||
|
||||
|
||||
// additional reading and writing
|
||||
virtual DECLARE_READ8_MEMBER(read_l); // used for ROM
|
||||
virtual DECLARE_READ8_MEMBER(read_h); // used for ROM
|
||||
virtual DECLARE_WRITE8_MEMBER(write_l); // used for RAM
|
||||
virtual DECLARE_WRITE8_MEMBER(write_h); // used for RAM
|
||||
virtual DECLARE_READ8_MEMBER(read_l); // used for ROM
|
||||
virtual DECLARE_READ8_MEMBER(read_h); // used for ROM
|
||||
virtual DECLARE_WRITE8_MEMBER(write_l); // used for RAM
|
||||
virtual DECLARE_WRITE8_MEMBER(write_h); // used for RAM
|
||||
};
|
||||
|
||||
|
||||
|
||||
@ -1,11 +1,11 @@
|
||||
/***********************************************************************************************************
|
||||
|
||||
|
||||
UPD7725 / UPD96050 add-on chip emulation (for SNES/SFC)
|
||||
used in carts with DSP-1, DSP-1A, DSP-1B, DSP-2, DSP-3, DSP-4, ST-010 & ST-011 add-on chips
|
||||
|
||||
|
||||
Copyright MESS Team.
|
||||
Visit http://mamedev.org for licensing and usage restrictions.
|
||||
|
||||
|
||||
***********************************************************************************************************/
|
||||
|
||||
|
||||
@ -24,19 +24,19 @@ const device_type SNS_LOROM_SETA11 = &device_creator<sns_rom_seta11dsp_device>;
|
||||
|
||||
sns_rom20_necdsp_device::sns_rom20_necdsp_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
|
||||
: sns_rom_device(mconfig, SNS_LOROM_NECDSP, "SNES Cart (LoROM) + NEC DSP", tag, owner, clock),
|
||||
m_upd7725(*this, "dsp")
|
||||
m_upd7725(*this, "dsp")
|
||||
{
|
||||
}
|
||||
|
||||
sns_rom21_necdsp_device::sns_rom21_necdsp_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
|
||||
: sns_rom21_device(mconfig, SNS_HIROM_NECDSP, "SNES Cart (HiROM) + NEC DSP", tag, owner, clock),
|
||||
m_upd7725(*this, "dsp")
|
||||
m_upd7725(*this, "dsp")
|
||||
{
|
||||
}
|
||||
|
||||
sns_rom_setadsp_device::sns_rom_setadsp_device(const machine_config &mconfig, device_type type, const char *name, const char *tag, device_t *owner, UINT32 clock)
|
||||
: sns_rom_device(mconfig, type, name, tag, owner, clock),
|
||||
m_upd96050(*this, "dsp")
|
||||
m_upd96050(*this, "dsp")
|
||||
{
|
||||
}
|
||||
|
||||
@ -223,6 +223,9 @@ READ8_MEMBER( sns_rom_setadsp_device::chip_read )
|
||||
else
|
||||
return temp & 0xff;
|
||||
}
|
||||
if (offset == 0x600000 || offset == 0x600001)
|
||||
return (offset & 1) ? m_upd96050->snesdsp_read(FALSE) : m_upd96050->snesdsp_read(TRUE);
|
||||
|
||||
return 0xff;
|
||||
}
|
||||
|
||||
@ -233,7 +236,7 @@ WRITE8_MEMBER( sns_rom_setadsp_device::chip_write )
|
||||
{
|
||||
UINT16 address = offset & 0xffff;
|
||||
UINT16 temp = m_upd96050->dataram_r(address/2);
|
||||
|
||||
|
||||
if (offset & 1)
|
||||
{
|
||||
temp &= 0xff;
|
||||
@ -244,10 +247,14 @@ WRITE8_MEMBER( sns_rom_setadsp_device::chip_write )
|
||||
temp &= 0xff00;
|
||||
temp |= data;
|
||||
}
|
||||
|
||||
|
||||
m_upd96050->dataram_w(address/2, temp);
|
||||
return;
|
||||
}
|
||||
if (offset == 0x600000)
|
||||
m_upd96050->snesdsp_write(TRUE, data);
|
||||
if (offset == 0x600001)
|
||||
m_upd96050->snesdsp_write(FALSE, data);
|
||||
}
|
||||
|
||||
|
||||
@ -316,4 +323,3 @@ machine_config_constructor sns_rom_seta11dsp_device::device_mconfig_additions()
|
||||
{
|
||||
return MACHINE_CONFIG_NAME( snes_st011 );
|
||||
}
|
||||
|
||||
|
||||
@ -13,18 +13,18 @@ class sns_rom20_necdsp_device : public sns_rom_device
|
||||
public:
|
||||
// construction/destruction
|
||||
sns_rom20_necdsp_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
|
||||
|
||||
|
||||
// device-level overrides
|
||||
virtual void device_start();
|
||||
virtual void device_config_complete() { m_shortname = "sns_rom_necdsp"; }
|
||||
virtual machine_config_constructor device_mconfig_additions() const;
|
||||
|
||||
|
||||
required_device<upd7725_device> m_upd7725;
|
||||
|
||||
|
||||
// additional reading and writing
|
||||
virtual DECLARE_READ8_MEMBER(chip_read);
|
||||
virtual DECLARE_WRITE8_MEMBER(chip_write);
|
||||
|
||||
|
||||
virtual DECLARE_READ32_MEMBER(necdsp_prg_r);
|
||||
virtual DECLARE_READ16_MEMBER(necdsp_data_r);
|
||||
};
|
||||
@ -36,18 +36,18 @@ class sns_rom21_necdsp_device : public sns_rom21_device
|
||||
public:
|
||||
// construction/destruction
|
||||
sns_rom21_necdsp_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
|
||||
|
||||
|
||||
// device-level overrides
|
||||
virtual void device_start();
|
||||
virtual void device_config_complete() { m_shortname = "sns_rom21_necdsp"; }
|
||||
virtual machine_config_constructor device_mconfig_additions() const;
|
||||
|
||||
|
||||
required_device<upd7725_device> m_upd7725;
|
||||
|
||||
|
||||
// additional reading and writing
|
||||
virtual DECLARE_READ8_MEMBER(chip_read);
|
||||
virtual DECLARE_WRITE8_MEMBER(chip_write);
|
||||
|
||||
|
||||
virtual DECLARE_READ32_MEMBER(necdsp_prg_r);
|
||||
virtual DECLARE_READ16_MEMBER(necdsp_data_r);
|
||||
};
|
||||
@ -59,17 +59,17 @@ class sns_rom_setadsp_device : public sns_rom_device
|
||||
public:
|
||||
// construction/destruction
|
||||
sns_rom_setadsp_device(const machine_config &mconfig, device_type type, const char *name, const char *tag, device_t *owner, UINT32 clock);
|
||||
|
||||
|
||||
// device-level overrides
|
||||
virtual void device_start();
|
||||
virtual void device_config_complete() { m_shortname = "sns_rom_setadsp"; }
|
||||
|
||||
|
||||
required_device<upd96050_device> m_upd96050;
|
||||
|
||||
|
||||
// additional reading and writing
|
||||
virtual DECLARE_READ8_MEMBER(chip_read);
|
||||
virtual DECLARE_WRITE8_MEMBER(chip_write);
|
||||
|
||||
|
||||
virtual DECLARE_READ32_MEMBER(setadsp_prg_r);
|
||||
virtual DECLARE_READ16_MEMBER(setadsp_data_r);
|
||||
};
|
||||
@ -81,7 +81,7 @@ class sns_rom_seta10dsp_device : public sns_rom_setadsp_device
|
||||
public:
|
||||
// construction/destruction
|
||||
sns_rom_seta10dsp_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
|
||||
|
||||
|
||||
// device-level overrides
|
||||
virtual void device_config_complete() { m_shortname = "sns_rom_seta10"; }
|
||||
virtual machine_config_constructor device_mconfig_additions() const;
|
||||
@ -94,7 +94,7 @@ class sns_rom_seta11dsp_device : public sns_rom_setadsp_device
|
||||
public:
|
||||
// construction/destruction
|
||||
sns_rom_seta11dsp_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
|
||||
|
||||
|
||||
// device-level overrides
|
||||
virtual void device_config_complete() { m_shortname = "sns_rom_seta11"; }
|
||||
virtual machine_config_constructor device_mconfig_additions() const;
|
||||
|
||||
Loading…
Reference in New Issue
Block a user