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New GROM implementation (TMC0430)
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Michael Zapf
parent
ee6684ac85
commit
ac3d3e5e41
@ -61,28 +61,28 @@
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8 GROMs can be used to cover a whole 16-bit address space, but only
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48 KiB of memory can be used. Each GROM has a burnt-in 3 bit identifier
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which allows us to put 8 GROMs in parallel, each one answering only
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when its area is currently selected.
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when its area is currently selected.
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The address that is loaded into the address register contains two parts:
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The address that is loaded into the address register contains two parts:
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[ I I I A A A A A A A A A A A A A ]
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The I bits indicate which GROM to use. They are latched inside every GROM,
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and when the address is read from the register, they are delivered as the
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most significant three address bits.
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The I bits indicate which GROM to use. They are latched inside every GROM,
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and when the address is read from the register, they are delivered as the
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most significant three address bits.
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All GROMs are wired in parallel, and only the circuits whose ID matches the
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prefix actually delivers the data to the outside. Apart from that, all
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GROMs perform the same internal operations. This means that each one of
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them holds the same address value and delivers it on request.
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All GROMs are wired in parallel, and only the circuits whose ID matches the
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prefix actually delivers the data to the outside. Apart from that, all
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GROMs perform the same internal operations. This means that each one of
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them holds the same address value and delivers it on request.
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Timing. GROMs have a CPU-bound operation phase and a non-CPU-bound operation
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phase. After being selected, the READY line is immediately lowered, and
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it raises as soon as the data is ready for access. After that, a prefetch
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is done to get the next data byte from the memory banks, advancing the
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address counter. This prefetch is also done when loading the address.
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Hence, reading the address register will always deliver a value increased
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by one.
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Timing. GROMs have a CPU-bound operation phase and a non-CPU-bound operation
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phase. After being selected, the READY line is immediately lowered, and
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it raises as soon as the data is ready for access. After that, a prefetch
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is done to get the next data byte from the memory banks, advancing the
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address counter. This prefetch is also done when loading the address.
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Hence, reading the address register will always deliver a value increased
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by one.
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[1] Michael L. Bunyard: Hardware Manual for the Texas Instruments 99/4A Home Computer, section 2.5
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@ -104,20 +104,20 @@
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Constructor.
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*/
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tmc0430_device::tmc0430_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
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: device_t(mconfig, TMC0430, "TMC0430 device (GROM)", tag, owner, clock, "grom", __FILE__),
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m_gromready(*this),
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m_current_clock_level(CLEAR_LINE),
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m_current_ident(0),
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m_phase(0),
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m_address_mode(false),
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m_read_mode(false),
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m_selected(false),
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m_address_lowbyte(false),
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m_regionname(nullptr),
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m_ident(0),
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m_address(0),
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m_buffer(0),
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m_memptr(nullptr)
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: device_t(mconfig, TMC0430, "TMC0430 device (GROM)", tag, owner, clock, "grom", __FILE__),
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m_gromready(*this),
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m_current_clock_level(CLEAR_LINE),
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m_current_ident(0),
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m_phase(0),
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m_address_mode(false),
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m_read_mode(false),
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m_selected(false),
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m_address_lowbyte(false),
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m_regionname(nullptr),
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m_ident(0),
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m_address(0),
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m_buffer(0),
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m_memptr(nullptr)
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{
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}
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@ -129,7 +129,7 @@ tmc0430_device::tmc0430_device(const machine_config &mconfig, const char *tag, d
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// ========================================================================
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/*
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Direction. When ASSERTed, GROM is set to be read by CPU.
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Direction. When ASSERTed, GROM is set to be read by CPU.
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*/
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WRITE_LINE_MEMBER( tmc0430_device::m_line )
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{
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@ -138,7 +138,7 @@ WRITE_LINE_MEMBER( tmc0430_device::m_line )
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}
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/*
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Mode. When ASSERTed, the address counter will be accessed (read or write).
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Mode. When ASSERTed, the address counter will be accessed (read or write).
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*/
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WRITE_LINE_MEMBER( tmc0430_device::mo_line )
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{
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@ -147,11 +147,11 @@ WRITE_LINE_MEMBER( tmc0430_device::mo_line )
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}
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/*
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Select. When ASSERTed, the read/write operation is started.
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Select. When ASSERTed, the read/write operation is started.
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*/
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WRITE_LINE_MEMBER( tmc0430_device::gsq_line )
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{
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if (state==ASSERT_LINE && !m_selected) // check for edge
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if (state==ASSERT_LINE && !m_selected) // check for edge
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{
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if (TRACE_READY) logerror("GROM %d selected, pulling down READY\n", m_ident>>13);
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m_gromready(CLEAR_LINE);
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@ -161,20 +161,20 @@ WRITE_LINE_MEMBER( tmc0430_device::gsq_line )
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}
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/*
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Combined select lines. Avoids separate calls to the chip.
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Address:
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0 -> MO=0, M=0
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1 -> MO=0, M=1
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2 -> MO=1, M=0
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3 -> MO=1, M=1
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Data: gsq line (ASSERT, CLEAR)
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Combined select lines. Avoids separate calls to the chip.
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Address:
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0 -> MO=0, M=0
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1 -> MO=0, M=1
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2 -> MO=1, M=0
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3 -> MO=1, M=1
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Data: gsq line (ASSERT, CLEAR)
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*/
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WRITE8_MEMBER( tmc0430_device::set_lines )
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{
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m_read_mode = ((offset & GROM_M_LINE)!=0);
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m_address_mode = ((offset & GROM_MO_LINE)!=0);
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if (data!=CLEAR_LINE && !m_selected) // check for edge
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if (data!=CLEAR_LINE && !m_selected) // check for edge
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{
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if (TRACE_READY) logerror("GROM %d selected, pulling down READY\n", m_ident>>13);
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m_gromready(CLEAR_LINE);
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@ -184,20 +184,20 @@ WRITE8_MEMBER( tmc0430_device::set_lines )
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}
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/*
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Clock in.
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Clock in.
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Note about the GREADY line:
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Inside the TI-99/4A console, the GREADY outputs of all GROMs are directly
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connected in parallel and pulled up. This implies that the GROMs are
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open-drain outputs pulling down. There are two options:
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- Only the currently addressed GROM pulls down the line; all others keep
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their output open.
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- All GROMs act strictly in parallel. In the case that some circuits are
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slightly out of sync, the GREADY line goes up when the last circuit releases
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the line.
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Note about the GREADY line:
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Inside the TI-99/4A console, the GREADY outputs of all GROMs are directly
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connected in parallel and pulled up. This implies that the GROMs are
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open-drain outputs pulling down. There are two options:
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- Only the currently addressed GROM pulls down the line; all others keep
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their output open.
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- All GROMs act strictly in parallel. In the case that some circuits are
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slightly out of sync, the GREADY line goes up when the last circuit releases
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the line.
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For the emulation we may assume that all GROMs at the same clock line
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raise their outputs synchronously.
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For the emulation we may assume that all GROMs at the same clock line
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raise their outputs synchronously.
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*/
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WRITE_LINE_MEMBER( tmc0430_device::gclock_in )
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{
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@ -266,8 +266,8 @@ WRITE_LINE_MEMBER( tmc0430_device::gclock_in )
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}
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/*
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Read operation. For MO=Address, delivers the address register (and destroys its contents).
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For MO=Data, delivers the byte inside the buffer and prefetches the next one.
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Read operation. For MO=Address, delivers the address register (and destroys its contents).
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For MO=Data, delivers the byte inside the buffer and prefetches the next one.
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*/
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READ8Z_MEMBER( tmc0430_device::readz )
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{
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@ -278,7 +278,7 @@ READ8Z_MEMBER( tmc0430_device::readz )
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// Address reading is destructive
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*value = (m_address & 0xff00)>>8;
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UINT8 lsb = (m_address & 0x00ff);
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m_address = (lsb << 8) | lsb; // see [1], section 2.5.3
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m_address = (lsb << 8) | lsb; // see [1], section 2.5.3
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if (TRACE_DETAIL) logerror("GROM %d return address %02x\n", m_ident>>13, *value);
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}
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else
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@ -298,13 +298,13 @@ READ8Z_MEMBER( tmc0430_device::readz )
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}
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/*
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Write operation. For MO=Address, shifts value in the address register
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by 8 bits and copies the new value into the low byte. After every two
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write operations, prefetches the byte from the new location. For MO=Data,
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do nothing, because GRAMs were never seen in the wild.
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Write operation. For MO=Address, shifts value in the address register
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by 8 bits and copies the new value into the low byte. After every two
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write operations, prefetches the byte from the new location. For MO=Data,
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do nothing, because GRAMs were never seen in the wild.
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This operation occurs in parallel to phase 4. The real GROM will pick up
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the value from the data bus some phases later.
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This operation occurs in parallel to phase 4. The real GROM will pick up
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the value from the data bus some phases later.
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*/
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WRITE8_MEMBER( tmc0430_device::write )
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{
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@ -312,7 +312,7 @@ WRITE8_MEMBER( tmc0430_device::write )
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if (m_address_mode)
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{
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m_address = ((m_address << 8) | data); // [1], section 2.5.7
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m_address = ((m_address << 8) | data); // [1], section 2.5.7
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m_current_ident = m_address & 0xe000;
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if (TRACE_DETAIL) logerror("GROM %d new address %04x (%s)\n", m_ident>>13, m_address, m_address_lowbyte? "complete" : "incomplete");
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// Toggle the lowbyte flag
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@ -77,17 +77,17 @@ private:
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bool m_read_mode;
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// Selected?
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bool m_selected;
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bool m_selected;
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// Toggle for address loading
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bool m_address_lowbyte;
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bool m_address_lowbyte;
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// Region name
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const char* m_regionname;
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// Offset in the region. We cannot rely on the ident because the GROMs
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// in the cartridges begin with ident 3, but start at the beginning of their region.
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int m_offset;
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int m_offset;
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// Identification of this GROM (0-7 <<13)
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int m_ident;
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