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https://github.com/holub/mame
synced 2025-05-25 07:15:25 +03:00
(mess) pc9801: pipe bitmap 7220 vram access though grcg, enable ready line which fixes disk change detection (nw)
--- Also disabled reads while grcg is in rmw mode, this I'm not 100% certain about and needs more testing.
This commit is contained in:
cracyc
parent
3c55af4b4c
commit
ad6fdd5ed6
@ -591,13 +591,17 @@ public:
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DECLARE_READ8_MEMBER(pc9801_mouse_r);
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DECLARE_WRITE8_MEMBER(pc9801_mouse_w);
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DECLARE_WRITE8_MEMBER(pc9801rs_mouse_freq_w);
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inline UINT8 m_pc9801rs_grcg_r(UINT32 offset,int vbank);
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inline void m_pc9801rs_grcg_w(UINT32 offset,int vbank,UINT8 data);
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inline UINT8 m_pc9801rs_grcg_r(UINT32 offset,int vbank,int vrambank);
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inline UINT8 m_pc9801rs_grcg_r(UINT32 offset,int vbank) { return m_pc9801rs_grcg_r(offset, vbank, m_vram_bank); }
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inline void m_pc9801rs_grcg_w(UINT32 offset,int vbank,int vrambank,UINT8 data);
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inline void m_pc9801rs_grcg_w(UINT32 offset,int vbank,UINT8 data) { m_pc9801rs_grcg_w(offset, vbank, m_vram_bank, data); }
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DECLARE_CUSTOM_INPUT_MEMBER(system_type_r);
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DECLARE_READ8_MEMBER(pc9801ux_gvram_r);
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DECLARE_WRITE8_MEMBER(pc9801ux_gvram_w);
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DECLARE_READ8_MEMBER(pc9801ux_gvram0_r);
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DECLARE_WRITE8_MEMBER(pc9801ux_gvram0_w);
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DECLARE_READ8_MEMBER(upd7220_grcg_r);
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DECLARE_WRITE8_MEMBER(upd7220_grcg_w);
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UINT32 pc9801_286_a20(bool state);
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DECLARE_READ8_MEMBER(ide_hack_r);
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@ -750,7 +754,7 @@ public:
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TIMER_DEVICE_CALLBACK_MEMBER( mouse_irq_cb );
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void pc9801_fdc_2hd_update_ready(floppy_image_device *, int);
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inline UINT32 m_calc_grcg_addr(int i,UINT32 offset);
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inline UINT32 m_calc_grcg_addr(int i,UINT32 offset,int vrambank);
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DECLARE_DRIVER_INIT(pc9801_kanji);
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inline void set_dma_channel(int channel, int state);
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@ -1645,18 +1649,18 @@ WRITE8_MEMBER(pc9801_state::pc9801_gvram_w)
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m_video_ram_2[offset+0x08000+m_vram_bank*0x20000] = data;
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}
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inline UINT32 pc9801_state::m_calc_grcg_addr(int i,UINT32 offset)
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inline UINT32 pc9801_state::m_calc_grcg_addr(int i,UINT32 offset,int vrambank)
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{
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return (offset) + (((i+1)*0x8000) & 0x1ffff) + (m_vram_bank*0x20000);
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return (offset) + (((i+1)*0x8000) & 0x1ffff) + (vrambank*0x20000);
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}
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inline UINT8 pc9801_state::m_pc9801rs_grcg_r(UINT32 offset,int vbank)
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inline UINT8 pc9801_state::m_pc9801rs_grcg_r(UINT32 offset,int vbank,int vrambank)
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{
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UINT8 res;
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UINT8 res = 0;
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if((m_grcg.mode & 0x80) == 0 || (m_grcg.mode & 0x40))
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res = m_video_ram_2[offset+vbank*0x8000+m_vram_bank*0x20000];
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else
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if(!(m_grcg.mode & 0x80))
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res = m_video_ram_2[offset+vbank*0x8000+vrambank*0x20000];
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else if(!(m_grcg.mode & 0x40))
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{
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int i;
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@ -1664,7 +1668,7 @@ inline UINT8 pc9801_state::m_pc9801rs_grcg_r(UINT32 offset,int vbank)
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for(i=0;i<4;i++)
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{
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if((m_grcg.mode & (1 << i)) == 0)
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res |= (m_video_ram_2[m_calc_grcg_addr(i,offset)] ^ m_grcg.tile[i]);
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res |= (m_video_ram_2[m_calc_grcg_addr(i,offset,vrambank)] ^ m_grcg.tile[i]);
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}
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res ^= 0xff;
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@ -1673,10 +1677,10 @@ inline UINT8 pc9801_state::m_pc9801rs_grcg_r(UINT32 offset,int vbank)
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return res;
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}
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inline void pc9801_state::m_pc9801rs_grcg_w(UINT32 offset,int vbank,UINT8 data)
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inline void pc9801_state::m_pc9801rs_grcg_w(UINT32 offset,int vbank,int vrambank,UINT8 data)
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{
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if((m_grcg.mode & 0x80) == 0)
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m_video_ram_2[offset+vbank*0x8000+m_vram_bank*0x20000] = data;
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m_video_ram_2[offset+vbank*0x8000+vrambank*0x20000] = data;
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else
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{
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int i;
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@ -1687,8 +1691,8 @@ inline void pc9801_state::m_pc9801rs_grcg_w(UINT32 offset,int vbank,UINT8 data)
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{
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if((m_grcg.mode & (1 << i)) == 0)
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{
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m_video_ram_2[m_calc_grcg_addr(i,offset)] &= ~data;
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m_video_ram_2[m_calc_grcg_addr(i,offset)] |= m_grcg.tile[i] & data;
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m_video_ram_2[m_calc_grcg_addr(i,offset,vrambank)] &= ~data;
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m_video_ram_2[m_calc_grcg_addr(i,offset,vrambank)] |= m_grcg.tile[i] & data;
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}
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}
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}
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@ -1698,13 +1702,22 @@ inline void pc9801_state::m_pc9801rs_grcg_w(UINT32 offset,int vbank,UINT8 data)
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{
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if((m_grcg.mode & (1 << i)) == 0)
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{
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m_video_ram_2[m_calc_grcg_addr(i,offset)] = m_grcg.tile[i];
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m_video_ram_2[m_calc_grcg_addr(i,offset,vrambank)] = m_grcg.tile[i];
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}
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}
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}
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}
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}
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READ8_MEMBER(pc9801_state::upd7220_grcg_r)
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{
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return m_pc9801rs_grcg_r(offset & 0x7fff, (offset >> 15) & 3, offset >> 17);
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}
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WRITE8_MEMBER(pc9801_state::upd7220_grcg_w)
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{
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m_pc9801rs_grcg_w(offset & 0x7fff, (offset >> 15) & 3, offset >> 17, data);
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}
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READ8_MEMBER(pc9801_state::pc9801_mouse_r)
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{
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@ -2776,6 +2789,9 @@ static ADDRESS_MAP_START( upd7220_2_map, AS_0, 8, pc9801_state )
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AM_RANGE(0x00000, 0x3ffff) AM_RAM AM_SHARE("video_ram_2")
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ADDRESS_MAP_END
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static ADDRESS_MAP_START( upd7220_grcg_2_map, AS_0, 8, pc9801_state )
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AM_RANGE(0x00000, 0x3ffff) AM_READWRITE(upd7220_grcg_r, upd7220_grcg_w) AM_SHARE("video_ram_2")
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ADDRESS_MAP_END
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CUSTOM_INPUT_MEMBER(pc9801_state::system_type_r)
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{
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@ -3730,10 +3746,10 @@ static MACHINE_CONFIG_START( pc9801rs, pc9801_state )
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MCFG_FRAGMENT_ADD(pc9801_keyboard)
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MCFG_FRAGMENT_ADD(pc9801_mouse)
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MCFG_FRAGMENT_ADD(pc9801_ide)
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MCFG_UPD1990A_ADD("upd1990a", XTAL_32_768kHz, NULL, NULL)
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MCFG_UPD4990A_ADD("upd1990a", XTAL_32_768kHz, NULL, NULL)
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MCFG_DEVICE_ADD(UPD8251_TAG, I8251, 0)
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MCFG_UPD765A_ADD("upd765_2hd", false, true)
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MCFG_UPD765A_ADD("upd765_2hd", true, true)
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MCFG_UPD765_INTRQ_CALLBACK(WRITELINE(pc9801_state, pc9801rs_fdc_irq))
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MCFG_UPD765_DRQ_CALLBACK(WRITELINE(pc9801_state, pc9801rs_fdc_drq))
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//"upd765_2dd"
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@ -3761,7 +3777,7 @@ static MACHINE_CONFIG_START( pc9801rs, pc9801_state )
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MCFG_UPD7220_VSYNC_CALLBACK(DEVWRITELINE("upd7220_btm", upd7220_device, ext_sync_w))
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MCFG_DEVICE_ADD("upd7220_btm", UPD7220, 5000000/2)
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MCFG_DEVICE_ADDRESS_MAP(AS_0, upd7220_2_map)
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MCFG_DEVICE_ADDRESS_MAP(AS_0, upd7220_grcg_2_map)
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MCFG_UPD7220_DISPLAY_PIXELS_CALLBACK_OWNER(pc9801_state, hgdc_display_pixels)
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MCFG_PALETTE_ADD("palette", 16+16)
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@ -3847,7 +3863,7 @@ static MACHINE_CONFIG_START( pc9821, pc9801_state )
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MCFG_FRAGMENT_ADD(pc9801_keyboard)
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MCFG_FRAGMENT_ADD(pc9801_mouse)
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MCFG_FRAGMENT_ADD(pc9801_ide)
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MCFG_UPD1990A_ADD("upd1990a", XTAL_32_768kHz, NULL, NULL)
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MCFG_UPD4990A_ADD("upd1990a", XTAL_32_768kHz, NULL, NULL)
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MCFG_DEVICE_ADD(UPD8251_TAG, I8251, 0)
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MCFG_UPD765A_ADD("upd765_2hd", false, true)
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@ -3878,7 +3894,7 @@ static MACHINE_CONFIG_START( pc9821, pc9801_state )
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MCFG_UPD7220_VSYNC_CALLBACK(DEVWRITELINE("upd7220_btm", upd7220_device, ext_sync_w))
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MCFG_DEVICE_ADD("upd7220_btm", UPD7220, 5000000/2)
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MCFG_DEVICE_ADDRESS_MAP(AS_0, upd7220_2_map)
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MCFG_DEVICE_ADDRESS_MAP(AS_0, upd7220_grcg_2_map)
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MCFG_UPD7220_DISPLAY_PIXELS_CALLBACK_OWNER(pc9801_state, hgdc_display_pixels)
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MCFG_PALETTE_ADD("palette", 16+16+256)
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