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Pointer-ified the MC68HC11 core.

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This commit is contained in:
Aaron Giles 2008-12-10 17:16:04 +00:00
parent eadc13bd94
commit b0136c9952
3 changed files with 1034 additions and 1041 deletions
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1834
src/emu/cpu/mc68hc11/hc11ops.c
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File diff suppressed because it is too large Load Diff

2
src/emu/cpu/mc68hc11/hc11ops.h
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@ -3,7 +3,7 @@ struct _hc11_opcode_list_struct
{ {
int page; int page;
int opcode; int opcode;
void (*handler)(void); void (*handler)(hc11_state *cpustate);
}; };
static const hc11_opcode_list_struct hc11_opcode_list[] = static const hc11_opcode_list_struct hc11_opcode_list[] =

239
src/emu/cpu/mc68hc11/mc68hc11.c
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@ -26,7 +26,8 @@ enum
#define CC_V 0x02 #define CC_V 0x02
#define CC_C 0x01 #define CC_C 0x01
typedef struct typedef struct _hc11_state hc11_state;
struct _hc11_state
{ {
union { union {
struct { struct {
@ -58,25 +59,23 @@ typedef struct
int icount; int icount;
int ram_position; int ram_position;
int reg_position; int reg_position;
} HC11_REGS; UINT8 *internal_ram;
int internal_ram_size;
static HC11_REGS hc11; };
static UINT8 *internal_ram;
static int internal_ram_size;
#define HC11OP(XX) hc11_##XX #define HC11OP(XX) hc11_##XX
/*****************************************************************************/ /*****************************************************************************/
/* Internal registers */ /* Internal registers */
static UINT8 hc11_regs_r(UINT32 address) static UINT8 hc11_regs_r(hc11_state *cpustate, UINT32 address)
{ {
int reg = address & 0xff; int reg = address & 0xff;
switch(reg) switch(reg)
{ {
case 0x00: /* PORTA */ case 0x00: /* PORTA */
return memory_read_byte(hc11.io, MC68HC11_IO_PORTA); return memory_read_byte(cpustate->io, MC68HC11_IO_PORTA);
case 0x01: /* DDRA */ case 0x01: /* DDRA */
return 0; return 0;
case 0x09: /* DDRD */ case 0x09: /* DDRD */
@ -87,46 +86,46 @@ static UINT8 hc11_regs_r(UINT32 address)
return 0x80; return 0x80;
case 0x31: /* ADR1 */ case 0x31: /* ADR1 */
{ {
if (hc11.adctl & 0x10) if (cpustate->adctl & 0x10)
{ {
return memory_read_byte(hc11.io, (hc11.adctl & 0x4) + MC68HC11_IO_AD0); return memory_read_byte(cpustate->io, (cpustate->adctl & 0x4) + MC68HC11_IO_AD0);
} }
else else
{ {
return memory_read_byte(hc11.io, (hc11.adctl & 0x7) + MC68HC11_IO_AD0); return memory_read_byte(cpustate->io, (cpustate->adctl & 0x7) + MC68HC11_IO_AD0);
} }
} }
case 0x32: /* ADR2 */ case 0x32: /* ADR2 */
{ {
if (hc11.adctl & 0x10) if (cpustate->adctl & 0x10)
{ {
return memory_read_byte(hc11.io, (hc11.adctl & 0x4) + MC68HC11_IO_AD1); return memory_read_byte(cpustate->io, (cpustate->adctl & 0x4) + MC68HC11_IO_AD1);
} }
else else
{ {
return memory_read_byte(hc11.io, (hc11.adctl & 0x7) + MC68HC11_IO_AD0); return memory_read_byte(cpustate->io, (cpustate->adctl & 0x7) + MC68HC11_IO_AD0);
} }
} }
case 0x33: /* ADR3 */ case 0x33: /* ADR3 */
{ {
if (hc11.adctl & 0x10) if (cpustate->adctl & 0x10)
{ {
return memory_read_byte(hc11.io, (hc11.adctl & 0x4) + MC68HC11_IO_AD2); return memory_read_byte(cpustate->io, (cpustate->adctl & 0x4) + MC68HC11_IO_AD2);
} }
else else
{ {
return memory_read_byte(hc11.io, (hc11.adctl & 0x7) + MC68HC11_IO_AD0); return memory_read_byte(cpustate->io, (cpustate->adctl & 0x7) + MC68HC11_IO_AD0);
} }
} }
case 0x34: /* ADR4 */ case 0x34: /* ADR4 */
{ {
if (hc11.adctl & 0x10) if (cpustate->adctl & 0x10)
{ {
return memory_read_byte(hc11.io, (hc11.adctl & 0x4) + MC68HC11_IO_AD3); return memory_read_byte(cpustate->io, (cpustate->adctl & 0x4) + MC68HC11_IO_AD3);
} }
else else
{ {
return memory_read_byte(hc11.io, (hc11.adctl & 0x7) + MC68HC11_IO_AD0); return memory_read_byte(cpustate->io, (cpustate->adctl & 0x7) + MC68HC11_IO_AD0);
} }
} }
case 0x38: /* OPT2 */ case 0x38: /* OPT2 */
@ -142,9 +141,9 @@ static UINT8 hc11_regs_r(UINT32 address)
case 0x74: /* SCSR1 */ case 0x74: /* SCSR1 */
return 0x40; return 0x40;
case 0x7c: /* PORTH */ case 0x7c: /* PORTH */
return memory_read_byte(hc11.io, MC68HC11_IO_PORTH); return memory_read_byte(cpustate->io, MC68HC11_IO_PORTH);
case 0x7e: /* PORTG */ case 0x7e: /* PORTG */
return memory_read_byte(hc11.io, MC68HC11_IO_PORTG); return memory_read_byte(cpustate->io, MC68HC11_IO_PORTG);
case 0x7f: /* DDRG */ case 0x7f: /* DDRG */
return 0; return 0;
@ -153,7 +152,7 @@ static UINT8 hc11_regs_r(UINT32 address)
case 0x89: /* SPSR2 */ case 0x89: /* SPSR2 */
return 0x80; return 0x80;
case 0x8a: /* SPDR2 */ case 0x8a: /* SPDR2 */
return memory_read_byte(hc11.io, MC68HC11_IO_SPI2_DATA); return memory_read_byte(cpustate->io, MC68HC11_IO_SPI2_DATA);
case 0x8b: /* OPT4 */ case 0x8b: /* OPT4 */
return 0; return 0;
@ -163,20 +162,20 @@ static UINT8 hc11_regs_r(UINT32 address)
return 0; // Dummy return 0; // Dummy
} }
static void hc11_regs_w(UINT32 address, UINT8 value) static void hc11_regs_w(hc11_state *cpustate, UINT32 address, UINT8 value)
{ {
int reg = address & 0xff; int reg = address & 0xff;
switch(reg) switch(reg)
{ {
case 0x00: /* PORTA */ case 0x00: /* PORTA */
memory_write_byte(hc11.io, MC68HC11_IO_PORTA, value); memory_write_byte(cpustate->io, MC68HC11_IO_PORTA, value);
return; return;
case 0x01: /* DDRA */ case 0x01: /* DDRA */
//mame_printf_debug("HC11: ddra = %02X\n", value); //mame_printf_debug("HC11: ddra = %02X\n", value);
return; return;
case 0x08: /* PORTD */ case 0x08: /* PORTD */
memory_write_byte(hc11.io, MC68HC11_IO_PORTD, value); memory_write_byte(cpustate->io, MC68HC11_IO_PORTD, value);
return; return;
case 0x09: /* DDRD */ case 0x09: /* DDRD */
//mame_printf_debug("HC11: ddrd = %02X\n", value); //mame_printf_debug("HC11: ddrd = %02X\n", value);
@ -188,7 +187,7 @@ static void hc11_regs_w(UINT32 address, UINT8 value)
case 0x28: /* SPCR1 */ case 0x28: /* SPCR1 */
return; return;
case 0x30: /* ADCTL */ case 0x30: /* ADCTL */
hc11.adctl = value; cpustate->adctl = value;
return; return;
case 0x38: /* OPT2 */ case 0x38: /* OPT2 */
return; return;
@ -201,11 +200,11 @@ static void hc11_regs_w(UINT32 address, UINT8 value)
int ram_page = (value >> 4) & 0xf; int ram_page = (value >> 4) & 0xf;
if (reg_page == ram_page) { if (reg_page == ram_page) {
hc11.reg_position = reg_page << 12; cpustate->reg_position = reg_page << 12;
hc11.ram_position = (ram_page << 12) + 0x100; cpustate->ram_position = (ram_page << 12) + 0x100;
} else { } else {
hc11.reg_position = reg_page << 12; cpustate->reg_position = reg_page << 12;
hc11.ram_position = ram_page << 12; cpustate->ram_position = ram_page << 12;
} }
return; return;
} }
@ -224,16 +223,16 @@ static void hc11_regs_w(UINT32 address, UINT8 value)
case 0x77: /* SCDRL */ case 0x77: /* SCDRL */
return; return;
case 0x7c: /* PORTH */ case 0x7c: /* PORTH */
memory_write_byte(hc11.io, MC68HC11_IO_PORTH, value); memory_write_byte(cpustate->io, MC68HC11_IO_PORTH, value);
return; return;
case 0x7d: /* DDRH */ case 0x7d: /* DDRH */
//mame_printf_debug("HC11: ddrh = %02X at %04X\n", value, hc11.pc); //mame_printf_debug("HC11: ddrh = %02X at %04X\n", value, cpustate->pc);
return; return;
case 0x7e: /* PORTG */ case 0x7e: /* PORTG */
memory_write_byte(hc11.io, MC68HC11_IO_PORTG, value); memory_write_byte(cpustate->io, MC68HC11_IO_PORTG, value);
return; return;
case 0x7f: /* DDRG */ case 0x7f: /* DDRG */
//mame_printf_debug("HC11: ddrg = %02X at %04X\n", value, hc11.pc); //mame_printf_debug("HC11: ddrg = %02X at %04X\n", value, cpustate->pc);
return; return;
case 0x88: /* SPCR2 */ case 0x88: /* SPCR2 */
@ -241,7 +240,7 @@ static void hc11_regs_w(UINT32 address, UINT8 value)
case 0x89: /* SPSR2 */ case 0x89: /* SPSR2 */
return; return;
case 0x8a: /* SPDR2 */ case 0x8a: /* SPDR2 */
memory_write_byte(hc11.io, MC68HC11_IO_SPI2_DATA, value); memory_write_byte(cpustate->io, MC68HC11_IO_SPI2_DATA, value);
return; return;
case 0x8b: /* OPT4 */ case 0x8b: /* OPT4 */
@ -253,70 +252,71 @@ static void hc11_regs_w(UINT32 address, UINT8 value)
/*****************************************************************************/ /*****************************************************************************/
INLINE UINT8 FETCH(void) INLINE UINT8 FETCH(hc11_state *cpustate)
{ {
return memory_decrypted_read_byte(hc11.program, hc11.pc++); return memory_decrypted_read_byte(cpustate->program, cpustate->pc++);
} }
INLINE UINT16 FETCH16(void) INLINE UINT16 FETCH16(hc11_state *cpustate)
{ {
UINT16 w; UINT16 w;
w = (memory_decrypted_read_byte(hc11.program, hc11.pc) << 8) | (memory_decrypted_read_byte(hc11.program, hc11.pc+1)); w = (memory_decrypted_read_byte(cpustate->program, cpustate->pc) << 8) | (memory_decrypted_read_byte(cpustate->program, cpustate->pc+1));
hc11.pc += 2; cpustate->pc += 2;
return w; return w;
} }
INLINE UINT8 READ8(UINT32 address) INLINE UINT8 READ8(hc11_state *cpustate, UINT32 address)
{ {
if(address >= hc11.reg_position && address < hc11.reg_position+0x100) if(address >= cpustate->reg_position && address < cpustate->reg_position+0x100)
{ {
return hc11_regs_r(address); return hc11_regs_r(cpustate, address);
} }
else if(address >= hc11.ram_position && address < hc11.ram_position+internal_ram_size) else if(address >= cpustate->ram_position && address < cpustate->ram_position+cpustate->internal_ram_size)
{ {
return internal_ram[address-hc11.ram_position]; return cpustate->internal_ram[address-cpustate->ram_position];
} }
return memory_read_byte(hc11.program, address); return memory_read_byte(cpustate->program, address);
} }
INLINE void WRITE8(UINT32 address, UINT8 value) INLINE void WRITE8(hc11_state *cpustate, UINT32 address, UINT8 value)
{ {
if(address >= hc11.reg_position && address < hc11.reg_position+0x100) if(address >= cpustate->reg_position && address < cpustate->reg_position+0x100)
{ {
hc11_regs_w(address, value); hc11_regs_w(cpustate, address, value);
return; return;
} }
else if(address >= hc11.ram_position && address < hc11.ram_position+internal_ram_size) else if(address >= cpustate->ram_position && address < cpustate->ram_position+cpustate->internal_ram_size)
{ {
internal_ram[address-hc11.ram_position] = value; cpustate->internal_ram[address-cpustate->ram_position] = value;
return; return;
} }
memory_write_byte(hc11.program, address, value); memory_write_byte(cpustate->program, address, value);
} }
INLINE UINT16 READ16(UINT32 address) INLINE UINT16 READ16(hc11_state *cpustate, UINT32 address)
{ {
return (READ8(address) << 8) | (READ8(address+1)); return (READ8(cpustate, address) << 8) | (READ8(cpustate, address+1));
} }
INLINE void WRITE16(UINT32 address, UINT16 value) INLINE void WRITE16(hc11_state *cpustate, UINT32 address, UINT16 value)
{ {
WRITE8(address+0, (value >> 8) & 0xff); WRITE8(cpustate, address+0, (value >> 8) & 0xff);
WRITE8(address+1, (value >> 0) & 0xff); WRITE8(cpustate, address+1, (value >> 0) & 0xff);
} }
/*****************************************************************************/ /*****************************************************************************/
static void (*hc11_optable[256])(void); static void (*hc11_optable[256])(hc11_state *cpustate);
static void (*hc11_optable_page2[256])(void); static void (*hc11_optable_page2[256])(hc11_state *cpustate);
static void (*hc11_optable_page3[256])(void); static void (*hc11_optable_page3[256])(hc11_state *cpustate);
static void (*hc11_optable_page4[256])(void); static void (*hc11_optable_page4[256])(hc11_state *cpustate);
#include "hc11ops.c" #include "hc11ops.c"
#include "hc11ops.h" #include "hc11ops.h"
static CPU_INIT( hc11 ) static CPU_INIT( hc11 )
{ {
hc11_state *cpustate = device->token;
int i; int i;
/* clear the opcode tables */ /* clear the opcode tables */
@ -346,20 +346,21 @@ static CPU_INIT( hc11 )
} }
} }
internal_ram_size = 1280; /* FIXME: this is for MC68HC11M0 */ cpustate->internal_ram_size = 1280; /* FIXME: this is for MC68HC11M0 */
internal_ram = auto_malloc(internal_ram_size); cpustate->internal_ram = auto_malloc(cpustate->internal_ram_size);
hc11.reg_position = 0; cpustate->reg_position = 0;
hc11.ram_position = 0x100; cpustate->ram_position = 0x100;
hc11.irq_callback = irqcallback; cpustate->irq_callback = irqcallback;
hc11.device = device; cpustate->device = device;
hc11.program = memory_find_address_space(device, ADDRESS_SPACE_PROGRAM); cpustate->program = memory_find_address_space(device, ADDRESS_SPACE_PROGRAM);
hc11.io = memory_find_address_space(device, ADDRESS_SPACE_IO); cpustate->io = memory_find_address_space(device, ADDRESS_SPACE_IO);
} }
static CPU_RESET( hc11 ) static CPU_RESET( hc11 )
{ {
hc11.pc = READ16(0xfffe); hc11_state *cpustate = device->token;
cpustate->pc = READ16(cpustate, 0xfffe);
} }
static CPU_EXIT( hc11 ) static CPU_EXIT( hc11 )
@ -367,61 +368,53 @@ static CPU_EXIT( hc11 )
} }
static CPU_GET_CONTEXT( hc11 )
{
if (dst) {
*(HC11_REGS*)dst = hc11;
}
}
static CPU_SET_CONTEXT( hc11 )
{
if (src) {
hc11 = *(HC11_REGS*)src;
}
}
static CPU_EXECUTE( hc11 ) static CPU_EXECUTE( hc11 )
{ {
hc11.icount = cycles; hc11_state *cpustate = device->token;
cpustate->icount = cycles;
while(hc11.icount > 0) while(cpustate->icount > 0)
{ {
UINT8 op; UINT8 op;
hc11.ppc = hc11.pc; cpustate->ppc = cpustate->pc;
debugger_instruction_hook(device, hc11.pc); debugger_instruction_hook(device, cpustate->pc);
op = FETCH(); op = FETCH(cpustate);
hc11_optable[op](); hc11_optable[op](cpustate);
} }
return cycles-hc11.icount; return cycles-cpustate->icount;
} }
/*****************************************************************************/ /*****************************************************************************/
static CPU_SET_INFO( mc68hc11 ) static CPU_SET_INFO( mc68hc11 )
{ {
hc11_state *cpustate = device->token;
switch (state) switch (state)
{ {
/* --- the following bits of info are set as 64-bit signed integers --- */ /* --- the following bits of info are set as 64-bit signed integers --- */
case CPUINFO_INT_PC: hc11.pc = info->i; break; case CPUINFO_INT_PC: cpustate->pc = info->i; break;
case CPUINFO_INT_REGISTER + HC11_PC: hc11.pc = info->i; break; case CPUINFO_INT_REGISTER + HC11_PC: cpustate->pc = info->i; break;
case CPUINFO_INT_REGISTER + HC11_SP: hc11.sp = info->i; break; case CPUINFO_INT_REGISTER + HC11_SP: cpustate->sp = info->i; break;
case CPUINFO_INT_REGISTER + HC11_A: hc11.d.d8.a = info->i; break; case CPUINFO_INT_REGISTER + HC11_A: cpustate->d.d8.a = info->i; break;
case CPUINFO_INT_REGISTER + HC11_B: hc11.d.d8.b = info->i; break; case CPUINFO_INT_REGISTER + HC11_B: cpustate->d.d8.b = info->i; break;
case CPUINFO_INT_REGISTER + HC11_IX: hc11.ix = info->i; break; case CPUINFO_INT_REGISTER + HC11_IX: cpustate->ix = info->i; break;
case CPUINFO_INT_REGISTER + HC11_IY: hc11.iy = info->i; break; case CPUINFO_INT_REGISTER + HC11_IY: cpustate->iy = info->i; break;
} }
} }
CPU_GET_INFO( mc68hc11 ) CPU_GET_INFO( mc68hc11 )
{ {
hc11_state *cpustate = (device != NULL) ? device->token : NULL;
switch(state) switch(state)
{ {
/* --- the following bits of info are returned as 64-bit signed integers --- */ /* --- the following bits of info are returned as 64-bit signed integers --- */
case CPUINFO_INT_CONTEXT_SIZE: info->i = sizeof(hc11); break; case CPUINFO_INT_CONTEXT_SIZE: info->i = sizeof(hc11_state); break;
case CPUINFO_INT_INPUT_LINES: info->i = 1; break; case CPUINFO_INT_INPUT_LINES: info->i = 1; break;
case CPUINFO_INT_DEFAULT_IRQ_VECTOR: info->i = 0; break; case CPUINFO_INT_DEFAULT_IRQ_VECTOR: info->i = 0; break;
case CPUINFO_INT_ENDIANNESS: info->i = ENDIANNESS_BIG; break; case CPUINFO_INT_ENDIANNESS: info->i = ENDIANNESS_BIG; break;
@ -447,24 +440,24 @@ CPU_GET_INFO( mc68hc11 )
case CPUINFO_INT_PREVIOUSPC: /* not implemented */ break; case CPUINFO_INT_PREVIOUSPC: /* not implemented */ break;
case CPUINFO_INT_PC: /* intentional fallthrough */ case CPUINFO_INT_PC: /* intentional fallthrough */
case CPUINFO_INT_REGISTER + HC11_PC: info->i = hc11.pc; break; case CPUINFO_INT_REGISTER + HC11_PC: info->i = cpustate->pc; break;
case CPUINFO_INT_REGISTER + HC11_SP: info->i = hc11.sp; break; case CPUINFO_INT_REGISTER + HC11_SP: info->i = cpustate->sp; break;
case CPUINFO_INT_REGISTER + HC11_A: info->i = hc11.d.d8.a; break; case CPUINFO_INT_REGISTER + HC11_A: info->i = cpustate->d.d8.a; break;
case CPUINFO_INT_REGISTER + HC11_B: info->i = hc11.d.d8.b; break; case CPUINFO_INT_REGISTER + HC11_B: info->i = cpustate->d.d8.b; break;
case CPUINFO_INT_REGISTER + HC11_IX: info->i = hc11.ix; break; case CPUINFO_INT_REGISTER + HC11_IX: info->i = cpustate->ix; break;
case CPUINFO_INT_REGISTER + HC11_IY: info->i = hc11.iy; break; case CPUINFO_INT_REGISTER + HC11_IY: info->i = cpustate->iy; break;
/* --- the following bits of info are returned as pointers to data or functions --- */ /* --- the following bits of info are returned as pointers to data or functions --- */
case CPUINFO_PTR_SET_INFO: info->setinfo = CPU_SET_INFO_NAME(mc68hc11); break; case CPUINFO_PTR_SET_INFO: info->setinfo = CPU_SET_INFO_NAME(mc68hc11); break;
case CPUINFO_PTR_GET_CONTEXT: info->getcontext = CPU_GET_CONTEXT_NAME(hc11); break; case CPUINFO_PTR_GET_CONTEXT: info->getcontext = CPU_GET_CONTEXT_NAME(dummy); break;
case CPUINFO_PTR_SET_CONTEXT: info->setcontext = CPU_SET_CONTEXT_NAME(hc11); break; case CPUINFO_PTR_SET_CONTEXT: info->setcontext = CPU_SET_CONTEXT_NAME(dummy); break;
case CPUINFO_PTR_INIT: info->init = CPU_INIT_NAME(hc11); break; case CPUINFO_PTR_INIT: info->init = CPU_INIT_NAME(hc11); break;
case CPUINFO_PTR_RESET: info->reset = CPU_RESET_NAME(hc11); break; case CPUINFO_PTR_RESET: info->reset = CPU_RESET_NAME(hc11); break;
case CPUINFO_PTR_EXIT: info->exit = CPU_EXIT_NAME(hc11); break; case CPUINFO_PTR_EXIT: info->exit = CPU_EXIT_NAME(hc11); break;
case CPUINFO_PTR_EXECUTE: info->execute = CPU_EXECUTE_NAME(hc11); break; case CPUINFO_PTR_EXECUTE: info->execute = CPU_EXECUTE_NAME(hc11); break;
case CPUINFO_PTR_BURN: info->burn = NULL; break; case CPUINFO_PTR_BURN: info->burn = NULL; break;
case CPUINFO_PTR_DISASSEMBLE: info->disassemble = hc11_disasm; break; case CPUINFO_PTR_DISASSEMBLE: info->disassemble = hc11_disasm; break;
case CPUINFO_PTR_INSTRUCTION_COUNTER: info->icount = &hc11.icount; break; case CPUINFO_PTR_INSTRUCTION_COUNTER: info->icount = &cpustate->icount; break;
/* --- the following bits of info are returned as NULL-terminated strings --- */ /* --- the following bits of info are returned as NULL-terminated strings --- */
case CPUINFO_STR_NAME: strcpy(info->s, "MC68HC11"); break; case CPUINFO_STR_NAME: strcpy(info->s, "MC68HC11"); break;
@ -475,21 +468,21 @@ CPU_GET_INFO( mc68hc11 )
case CPUINFO_STR_FLAGS: case CPUINFO_STR_FLAGS:
sprintf(info->s, "%c%c%c%c%c%c%c%c", sprintf(info->s, "%c%c%c%c%c%c%c%c",
(hc11.ccr & CC_S) ? 'S' : '.', (cpustate->ccr & CC_S) ? 'S' : '.',
(hc11.ccr & CC_X) ? 'X' : '.', (cpustate->ccr & CC_X) ? 'X' : '.',
(hc11.ccr & CC_H) ? 'H' : '.', (cpustate->ccr & CC_H) ? 'H' : '.',
(hc11.ccr & CC_I) ? 'I' : '.', (cpustate->ccr & CC_I) ? 'I' : '.',
(hc11.ccr & CC_N) ? 'N' : '.', (cpustate->ccr & CC_N) ? 'N' : '.',
(hc11.ccr & CC_Z) ? 'Z' : '.', (cpustate->ccr & CC_Z) ? 'Z' : '.',
(hc11.ccr & CC_V) ? 'V' : '.', (cpustate->ccr & CC_V) ? 'V' : '.',
(hc11.ccr & CC_C) ? 'C' : '.'); (cpustate->ccr & CC_C) ? 'C' : '.');
break; break;
case CPUINFO_STR_REGISTER + HC11_PC: sprintf(info->s, "PC: %04X", hc11.pc); break; case CPUINFO_STR_REGISTER + HC11_PC: sprintf(info->s, "PC: %04X", cpustate->pc); break;
case CPUINFO_STR_REGISTER + HC11_SP: sprintf(info->s, "SP: %04X", hc11.sp); break; case CPUINFO_STR_REGISTER + HC11_SP: sprintf(info->s, "SP: %04X", cpustate->sp); break;
case CPUINFO_STR_REGISTER + HC11_A: sprintf(info->s, "A: %02X", hc11.d.d8.a); break; case CPUINFO_STR_REGISTER + HC11_A: sprintf(info->s, "A: %02X", cpustate->d.d8.a); break;
case CPUINFO_STR_REGISTER + HC11_B: sprintf(info->s, "B: %02X", hc11.d.d8.b); break; case CPUINFO_STR_REGISTER + HC11_B: sprintf(info->s, "B: %02X", cpustate->d.d8.b); break;
case CPUINFO_STR_REGISTER + HC11_IX: sprintf(info->s, "IX: %04X", hc11.ix); break; case CPUINFO_STR_REGISTER + HC11_IX: sprintf(info->s, "IX: %04X", cpustate->ix); break;
case CPUINFO_STR_REGISTER + HC11_IY: sprintf(info->s, "IY: %04X", hc11.iy); break; case CPUINFO_STR_REGISTER + HC11_IY: sprintf(info->s, "IY: %04X", cpustate->iy); break;
} }
} }