mirror of
https://github.com/holub/mame
synced 2025-05-24 06:30:04 +03:00
Pointer-ified the MC68HC11 core.
This commit is contained in:
Aaron Giles
parent
eadc13bd94
commit
b0136c9952
File diff suppressed because it is too large
Load Diff
@ -3,7 +3,7 @@ struct _hc11_opcode_list_struct
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{
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int page;
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int opcode;
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void (*handler)(void);
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void (*handler)(hc11_state *cpustate);
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};
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static const hc11_opcode_list_struct hc11_opcode_list[] =
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@ -26,7 +26,8 @@ enum
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#define CC_V 0x02
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#define CC_C 0x01
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typedef struct
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typedef struct _hc11_state hc11_state;
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struct _hc11_state
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{
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union {
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struct {
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@ -58,25 +59,23 @@ typedef struct
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int icount;
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int ram_position;
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int reg_position;
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} HC11_REGS;
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static HC11_REGS hc11;
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static UINT8 *internal_ram;
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static int internal_ram_size;
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UINT8 *internal_ram;
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int internal_ram_size;
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};
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#define HC11OP(XX) hc11_##XX
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/*****************************************************************************/
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/* Internal registers */
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static UINT8 hc11_regs_r(UINT32 address)
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static UINT8 hc11_regs_r(hc11_state *cpustate, UINT32 address)
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{
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int reg = address & 0xff;
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switch(reg)
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{
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case 0x00: /* PORTA */
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return memory_read_byte(hc11.io, MC68HC11_IO_PORTA);
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return memory_read_byte(cpustate->io, MC68HC11_IO_PORTA);
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case 0x01: /* DDRA */
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return 0;
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case 0x09: /* DDRD */
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@ -87,46 +86,46 @@ static UINT8 hc11_regs_r(UINT32 address)
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return 0x80;
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case 0x31: /* ADR1 */
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{
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if (hc11.adctl & 0x10)
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if (cpustate->adctl & 0x10)
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{
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return memory_read_byte(hc11.io, (hc11.adctl & 0x4) + MC68HC11_IO_AD0);
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return memory_read_byte(cpustate->io, (cpustate->adctl & 0x4) + MC68HC11_IO_AD0);
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}
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else
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{
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return memory_read_byte(hc11.io, (hc11.adctl & 0x7) + MC68HC11_IO_AD0);
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return memory_read_byte(cpustate->io, (cpustate->adctl & 0x7) + MC68HC11_IO_AD0);
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}
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}
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case 0x32: /* ADR2 */
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{
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if (hc11.adctl & 0x10)
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if (cpustate->adctl & 0x10)
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{
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return memory_read_byte(hc11.io, (hc11.adctl & 0x4) + MC68HC11_IO_AD1);
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return memory_read_byte(cpustate->io, (cpustate->adctl & 0x4) + MC68HC11_IO_AD1);
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}
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else
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{
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return memory_read_byte(hc11.io, (hc11.adctl & 0x7) + MC68HC11_IO_AD0);
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return memory_read_byte(cpustate->io, (cpustate->adctl & 0x7) + MC68HC11_IO_AD0);
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}
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}
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case 0x33: /* ADR3 */
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{
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if (hc11.adctl & 0x10)
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if (cpustate->adctl & 0x10)
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{
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return memory_read_byte(hc11.io, (hc11.adctl & 0x4) + MC68HC11_IO_AD2);
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return memory_read_byte(cpustate->io, (cpustate->adctl & 0x4) + MC68HC11_IO_AD2);
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}
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else
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{
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return memory_read_byte(hc11.io, (hc11.adctl & 0x7) + MC68HC11_IO_AD0);
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return memory_read_byte(cpustate->io, (cpustate->adctl & 0x7) + MC68HC11_IO_AD0);
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}
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}
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case 0x34: /* ADR4 */
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{
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if (hc11.adctl & 0x10)
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if (cpustate->adctl & 0x10)
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{
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return memory_read_byte(hc11.io, (hc11.adctl & 0x4) + MC68HC11_IO_AD3);
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return memory_read_byte(cpustate->io, (cpustate->adctl & 0x4) + MC68HC11_IO_AD3);
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}
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else
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{
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return memory_read_byte(hc11.io, (hc11.adctl & 0x7) + MC68HC11_IO_AD0);
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return memory_read_byte(cpustate->io, (cpustate->adctl & 0x7) + MC68HC11_IO_AD0);
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}
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}
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case 0x38: /* OPT2 */
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@ -142,9 +141,9 @@ static UINT8 hc11_regs_r(UINT32 address)
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case 0x74: /* SCSR1 */
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return 0x40;
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case 0x7c: /* PORTH */
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return memory_read_byte(hc11.io, MC68HC11_IO_PORTH);
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return memory_read_byte(cpustate->io, MC68HC11_IO_PORTH);
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case 0x7e: /* PORTG */
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return memory_read_byte(hc11.io, MC68HC11_IO_PORTG);
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return memory_read_byte(cpustate->io, MC68HC11_IO_PORTG);
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case 0x7f: /* DDRG */
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return 0;
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@ -153,7 +152,7 @@ static UINT8 hc11_regs_r(UINT32 address)
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case 0x89: /* SPSR2 */
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return 0x80;
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case 0x8a: /* SPDR2 */
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return memory_read_byte(hc11.io, MC68HC11_IO_SPI2_DATA);
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return memory_read_byte(cpustate->io, MC68HC11_IO_SPI2_DATA);
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case 0x8b: /* OPT4 */
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return 0;
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@ -163,20 +162,20 @@ static UINT8 hc11_regs_r(UINT32 address)
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return 0; // Dummy
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}
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static void hc11_regs_w(UINT32 address, UINT8 value)
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static void hc11_regs_w(hc11_state *cpustate, UINT32 address, UINT8 value)
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{
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int reg = address & 0xff;
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switch(reg)
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{
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case 0x00: /* PORTA */
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memory_write_byte(hc11.io, MC68HC11_IO_PORTA, value);
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memory_write_byte(cpustate->io, MC68HC11_IO_PORTA, value);
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return;
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case 0x01: /* DDRA */
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//mame_printf_debug("HC11: ddra = %02X\n", value);
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return;
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case 0x08: /* PORTD */
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memory_write_byte(hc11.io, MC68HC11_IO_PORTD, value);
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memory_write_byte(cpustate->io, MC68HC11_IO_PORTD, value);
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return;
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case 0x09: /* DDRD */
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//mame_printf_debug("HC11: ddrd = %02X\n", value);
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@ -188,7 +187,7 @@ static void hc11_regs_w(UINT32 address, UINT8 value)
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case 0x28: /* SPCR1 */
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return;
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case 0x30: /* ADCTL */
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hc11.adctl = value;
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cpustate->adctl = value;
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return;
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case 0x38: /* OPT2 */
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return;
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@ -201,11 +200,11 @@ static void hc11_regs_w(UINT32 address, UINT8 value)
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int ram_page = (value >> 4) & 0xf;
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if (reg_page == ram_page) {
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hc11.reg_position = reg_page << 12;
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hc11.ram_position = (ram_page << 12) + 0x100;
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cpustate->reg_position = reg_page << 12;
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cpustate->ram_position = (ram_page << 12) + 0x100;
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} else {
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hc11.reg_position = reg_page << 12;
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hc11.ram_position = ram_page << 12;
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cpustate->reg_position = reg_page << 12;
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cpustate->ram_position = ram_page << 12;
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}
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return;
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}
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@ -224,16 +223,16 @@ static void hc11_regs_w(UINT32 address, UINT8 value)
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case 0x77: /* SCDRL */
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return;
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case 0x7c: /* PORTH */
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memory_write_byte(hc11.io, MC68HC11_IO_PORTH, value);
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memory_write_byte(cpustate->io, MC68HC11_IO_PORTH, value);
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return;
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case 0x7d: /* DDRH */
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//mame_printf_debug("HC11: ddrh = %02X at %04X\n", value, hc11.pc);
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//mame_printf_debug("HC11: ddrh = %02X at %04X\n", value, cpustate->pc);
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return;
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case 0x7e: /* PORTG */
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memory_write_byte(hc11.io, MC68HC11_IO_PORTG, value);
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memory_write_byte(cpustate->io, MC68HC11_IO_PORTG, value);
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return;
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case 0x7f: /* DDRG */
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//mame_printf_debug("HC11: ddrg = %02X at %04X\n", value, hc11.pc);
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//mame_printf_debug("HC11: ddrg = %02X at %04X\n", value, cpustate->pc);
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return;
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case 0x88: /* SPCR2 */
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@ -241,7 +240,7 @@ static void hc11_regs_w(UINT32 address, UINT8 value)
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case 0x89: /* SPSR2 */
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return;
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case 0x8a: /* SPDR2 */
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memory_write_byte(hc11.io, MC68HC11_IO_SPI2_DATA, value);
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memory_write_byte(cpustate->io, MC68HC11_IO_SPI2_DATA, value);
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return;
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case 0x8b: /* OPT4 */
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@ -253,70 +252,71 @@ static void hc11_regs_w(UINT32 address, UINT8 value)
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/*****************************************************************************/
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INLINE UINT8 FETCH(void)
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INLINE UINT8 FETCH(hc11_state *cpustate)
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{
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return memory_decrypted_read_byte(hc11.program, hc11.pc++);
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return memory_decrypted_read_byte(cpustate->program, cpustate->pc++);
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}
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INLINE UINT16 FETCH16(void)
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INLINE UINT16 FETCH16(hc11_state *cpustate)
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{
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UINT16 w;
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w = (memory_decrypted_read_byte(hc11.program, hc11.pc) << 8) | (memory_decrypted_read_byte(hc11.program, hc11.pc+1));
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hc11.pc += 2;
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w = (memory_decrypted_read_byte(cpustate->program, cpustate->pc) << 8) | (memory_decrypted_read_byte(cpustate->program, cpustate->pc+1));
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cpustate->pc += 2;
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return w;
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}
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INLINE UINT8 READ8(UINT32 address)
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INLINE UINT8 READ8(hc11_state *cpustate, UINT32 address)
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{
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if(address >= hc11.reg_position && address < hc11.reg_position+0x100)
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if(address >= cpustate->reg_position && address < cpustate->reg_position+0x100)
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{
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return hc11_regs_r(address);
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return hc11_regs_r(cpustate, address);
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}
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else if(address >= hc11.ram_position && address < hc11.ram_position+internal_ram_size)
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else if(address >= cpustate->ram_position && address < cpustate->ram_position+cpustate->internal_ram_size)
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{
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return internal_ram[address-hc11.ram_position];
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return cpustate->internal_ram[address-cpustate->ram_position];
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}
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return memory_read_byte(hc11.program, address);
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return memory_read_byte(cpustate->program, address);
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}
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INLINE void WRITE8(UINT32 address, UINT8 value)
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INLINE void WRITE8(hc11_state *cpustate, UINT32 address, UINT8 value)
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{
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if(address >= hc11.reg_position && address < hc11.reg_position+0x100)
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if(address >= cpustate->reg_position && address < cpustate->reg_position+0x100)
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{
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hc11_regs_w(address, value);
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hc11_regs_w(cpustate, address, value);
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return;
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}
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else if(address >= hc11.ram_position && address < hc11.ram_position+internal_ram_size)
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else if(address >= cpustate->ram_position && address < cpustate->ram_position+cpustate->internal_ram_size)
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{
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internal_ram[address-hc11.ram_position] = value;
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cpustate->internal_ram[address-cpustate->ram_position] = value;
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return;
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}
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memory_write_byte(hc11.program, address, value);
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memory_write_byte(cpustate->program, address, value);
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}
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INLINE UINT16 READ16(UINT32 address)
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INLINE UINT16 READ16(hc11_state *cpustate, UINT32 address)
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{
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return (READ8(address) << 8) | (READ8(address+1));
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return (READ8(cpustate, address) << 8) | (READ8(cpustate, address+1));
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}
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INLINE void WRITE16(UINT32 address, UINT16 value)
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INLINE void WRITE16(hc11_state *cpustate, UINT32 address, UINT16 value)
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{
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WRITE8(address+0, (value >> 8) & 0xff);
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WRITE8(address+1, (value >> 0) & 0xff);
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WRITE8(cpustate, address+0, (value >> 8) & 0xff);
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WRITE8(cpustate, address+1, (value >> 0) & 0xff);
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}
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/*****************************************************************************/
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static void (*hc11_optable[256])(void);
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static void (*hc11_optable_page2[256])(void);
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static void (*hc11_optable_page3[256])(void);
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static void (*hc11_optable_page4[256])(void);
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static void (*hc11_optable[256])(hc11_state *cpustate);
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static void (*hc11_optable_page2[256])(hc11_state *cpustate);
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static void (*hc11_optable_page3[256])(hc11_state *cpustate);
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static void (*hc11_optable_page4[256])(hc11_state *cpustate);
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#include "hc11ops.c"
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#include "hc11ops.h"
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static CPU_INIT( hc11 )
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{
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hc11_state *cpustate = device->token;
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int i;
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/* clear the opcode tables */
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@ -346,20 +346,21 @@ static CPU_INIT( hc11 )
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}
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}
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internal_ram_size = 1280; /* FIXME: this is for MC68HC11M0 */
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internal_ram = auto_malloc(internal_ram_size);
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cpustate->internal_ram_size = 1280; /* FIXME: this is for MC68HC11M0 */
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cpustate->internal_ram = auto_malloc(cpustate->internal_ram_size);
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hc11.reg_position = 0;
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hc11.ram_position = 0x100;
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hc11.irq_callback = irqcallback;
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hc11.device = device;
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hc11.program = memory_find_address_space(device, ADDRESS_SPACE_PROGRAM);
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hc11.io = memory_find_address_space(device, ADDRESS_SPACE_IO);
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cpustate->reg_position = 0;
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cpustate->ram_position = 0x100;
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cpustate->irq_callback = irqcallback;
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cpustate->device = device;
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cpustate->program = memory_find_address_space(device, ADDRESS_SPACE_PROGRAM);
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cpustate->io = memory_find_address_space(device, ADDRESS_SPACE_IO);
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}
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static CPU_RESET( hc11 )
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{
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hc11.pc = READ16(0xfffe);
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hc11_state *cpustate = device->token;
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cpustate->pc = READ16(cpustate, 0xfffe);
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}
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static CPU_EXIT( hc11 )
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@ -367,61 +368,53 @@ static CPU_EXIT( hc11 )
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}
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static CPU_GET_CONTEXT( hc11 )
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{
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if (dst) {
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*(HC11_REGS*)dst = hc11;
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}
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}
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static CPU_SET_CONTEXT( hc11 )
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{
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if (src) {
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hc11 = *(HC11_REGS*)src;
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}
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}
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static CPU_EXECUTE( hc11 )
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{
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hc11.icount = cycles;
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hc11_state *cpustate = device->token;
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while(hc11.icount > 0)
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cpustate->icount = cycles;
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while(cpustate->icount > 0)
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{
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UINT8 op;
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hc11.ppc = hc11.pc;
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debugger_instruction_hook(device, hc11.pc);
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cpustate->ppc = cpustate->pc;
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debugger_instruction_hook(device, cpustate->pc);
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op = FETCH();
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hc11_optable[op]();
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op = FETCH(cpustate);
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hc11_optable[op](cpustate);
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}
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return cycles-hc11.icount;
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return cycles-cpustate->icount;
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}
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/*****************************************************************************/
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static CPU_SET_INFO( mc68hc11 )
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{
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hc11_state *cpustate = device->token;
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switch (state)
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{
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/* --- the following bits of info are set as 64-bit signed integers --- */
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case CPUINFO_INT_PC: hc11.pc = info->i; break;
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case CPUINFO_INT_REGISTER + HC11_PC: hc11.pc = info->i; break;
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case CPUINFO_INT_REGISTER + HC11_SP: hc11.sp = info->i; break;
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case CPUINFO_INT_REGISTER + HC11_A: hc11.d.d8.a = info->i; break;
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case CPUINFO_INT_REGISTER + HC11_B: hc11.d.d8.b = info->i; break;
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case CPUINFO_INT_REGISTER + HC11_IX: hc11.ix = info->i; break;
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case CPUINFO_INT_REGISTER + HC11_IY: hc11.iy = info->i; break;
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case CPUINFO_INT_PC: cpustate->pc = info->i; break;
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case CPUINFO_INT_REGISTER + HC11_PC: cpustate->pc = info->i; break;
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case CPUINFO_INT_REGISTER + HC11_SP: cpustate->sp = info->i; break;
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case CPUINFO_INT_REGISTER + HC11_A: cpustate->d.d8.a = info->i; break;
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case CPUINFO_INT_REGISTER + HC11_B: cpustate->d.d8.b = info->i; break;
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case CPUINFO_INT_REGISTER + HC11_IX: cpustate->ix = info->i; break;
|
||||
case CPUINFO_INT_REGISTER + HC11_IY: cpustate->iy = info->i; break;
|
||||
}
|
||||
}
|
||||
|
||||
CPU_GET_INFO( mc68hc11 )
|
||||
{
|
||||
hc11_state *cpustate = (device != NULL) ? device->token : NULL;
|
||||
|
||||
switch(state)
|
||||
{
|
||||
/* --- the following bits of info are returned as 64-bit signed integers --- */
|
||||
case CPUINFO_INT_CONTEXT_SIZE: info->i = sizeof(hc11); break;
|
||||
case CPUINFO_INT_CONTEXT_SIZE: info->i = sizeof(hc11_state); break;
|
||||
case CPUINFO_INT_INPUT_LINES: info->i = 1; break;
|
||||
case CPUINFO_INT_DEFAULT_IRQ_VECTOR: info->i = 0; break;
|
||||
case CPUINFO_INT_ENDIANNESS: info->i = ENDIANNESS_BIG; break;
|
||||
@ -447,24 +440,24 @@ CPU_GET_INFO( mc68hc11 )
|
||||
case CPUINFO_INT_PREVIOUSPC: /* not implemented */ break;
|
||||
|
||||
case CPUINFO_INT_PC: /* intentional fallthrough */
|
||||
case CPUINFO_INT_REGISTER + HC11_PC: info->i = hc11.pc; break;
|
||||
case CPUINFO_INT_REGISTER + HC11_SP: info->i = hc11.sp; break;
|
||||
case CPUINFO_INT_REGISTER + HC11_A: info->i = hc11.d.d8.a; break;
|
||||
case CPUINFO_INT_REGISTER + HC11_B: info->i = hc11.d.d8.b; break;
|
||||
case CPUINFO_INT_REGISTER + HC11_IX: info->i = hc11.ix; break;
|
||||
case CPUINFO_INT_REGISTER + HC11_IY: info->i = hc11.iy; break;
|
||||
case CPUINFO_INT_REGISTER + HC11_PC: info->i = cpustate->pc; break;
|
||||
case CPUINFO_INT_REGISTER + HC11_SP: info->i = cpustate->sp; break;
|
||||
case CPUINFO_INT_REGISTER + HC11_A: info->i = cpustate->d.d8.a; break;
|
||||
case CPUINFO_INT_REGISTER + HC11_B: info->i = cpustate->d.d8.b; break;
|
||||
case CPUINFO_INT_REGISTER + HC11_IX: info->i = cpustate->ix; break;
|
||||
case CPUINFO_INT_REGISTER + HC11_IY: info->i = cpustate->iy; break;
|
||||
|
||||
/* --- the following bits of info are returned as pointers to data or functions --- */
|
||||
case CPUINFO_PTR_SET_INFO: info->setinfo = CPU_SET_INFO_NAME(mc68hc11); break;
|
||||
case CPUINFO_PTR_GET_CONTEXT: info->getcontext = CPU_GET_CONTEXT_NAME(hc11); break;
|
||||
case CPUINFO_PTR_SET_CONTEXT: info->setcontext = CPU_SET_CONTEXT_NAME(hc11); break;
|
||||
case CPUINFO_PTR_GET_CONTEXT: info->getcontext = CPU_GET_CONTEXT_NAME(dummy); break;
|
||||
case CPUINFO_PTR_SET_CONTEXT: info->setcontext = CPU_SET_CONTEXT_NAME(dummy); break;
|
||||
case CPUINFO_PTR_INIT: info->init = CPU_INIT_NAME(hc11); break;
|
||||
case CPUINFO_PTR_RESET: info->reset = CPU_RESET_NAME(hc11); break;
|
||||
case CPUINFO_PTR_EXIT: info->exit = CPU_EXIT_NAME(hc11); break;
|
||||
case CPUINFO_PTR_EXECUTE: info->execute = CPU_EXECUTE_NAME(hc11); break;
|
||||
case CPUINFO_PTR_BURN: info->burn = NULL; break;
|
||||
case CPUINFO_PTR_DISASSEMBLE: info->disassemble = hc11_disasm; break;
|
||||
case CPUINFO_PTR_INSTRUCTION_COUNTER: info->icount = &hc11.icount; break;
|
||||
case CPUINFO_PTR_INSTRUCTION_COUNTER: info->icount = &cpustate->icount; break;
|
||||
|
||||
/* --- the following bits of info are returned as NULL-terminated strings --- */
|
||||
case CPUINFO_STR_NAME: strcpy(info->s, "MC68HC11"); break;
|
||||
@ -475,21 +468,21 @@ CPU_GET_INFO( mc68hc11 )
|
||||
|
||||
case CPUINFO_STR_FLAGS:
|
||||
sprintf(info->s, "%c%c%c%c%c%c%c%c",
|
||||
(hc11.ccr & CC_S) ? 'S' : '.',
|
||||
(hc11.ccr & CC_X) ? 'X' : '.',
|
||||
(hc11.ccr & CC_H) ? 'H' : '.',
|
||||
(hc11.ccr & CC_I) ? 'I' : '.',
|
||||
(hc11.ccr & CC_N) ? 'N' : '.',
|
||||
(hc11.ccr & CC_Z) ? 'Z' : '.',
|
||||
(hc11.ccr & CC_V) ? 'V' : '.',
|
||||
(hc11.ccr & CC_C) ? 'C' : '.');
|
||||
(cpustate->ccr & CC_S) ? 'S' : '.',
|
||||
(cpustate->ccr & CC_X) ? 'X' : '.',
|
||||
(cpustate->ccr & CC_H) ? 'H' : '.',
|
||||
(cpustate->ccr & CC_I) ? 'I' : '.',
|
||||
(cpustate->ccr & CC_N) ? 'N' : '.',
|
||||
(cpustate->ccr & CC_Z) ? 'Z' : '.',
|
||||
(cpustate->ccr & CC_V) ? 'V' : '.',
|
||||
(cpustate->ccr & CC_C) ? 'C' : '.');
|
||||
break;
|
||||
|
||||
case CPUINFO_STR_REGISTER + HC11_PC: sprintf(info->s, "PC: %04X", hc11.pc); break;
|
||||
case CPUINFO_STR_REGISTER + HC11_SP: sprintf(info->s, "SP: %04X", hc11.sp); break;
|
||||
case CPUINFO_STR_REGISTER + HC11_A: sprintf(info->s, "A: %02X", hc11.d.d8.a); break;
|
||||
case CPUINFO_STR_REGISTER + HC11_B: sprintf(info->s, "B: %02X", hc11.d.d8.b); break;
|
||||
case CPUINFO_STR_REGISTER + HC11_IX: sprintf(info->s, "IX: %04X", hc11.ix); break;
|
||||
case CPUINFO_STR_REGISTER + HC11_IY: sprintf(info->s, "IY: %04X", hc11.iy); break;
|
||||
case CPUINFO_STR_REGISTER + HC11_PC: sprintf(info->s, "PC: %04X", cpustate->pc); break;
|
||||
case CPUINFO_STR_REGISTER + HC11_SP: sprintf(info->s, "SP: %04X", cpustate->sp); break;
|
||||
case CPUINFO_STR_REGISTER + HC11_A: sprintf(info->s, "A: %02X", cpustate->d.d8.a); break;
|
||||
case CPUINFO_STR_REGISTER + HC11_B: sprintf(info->s, "B: %02X", cpustate->d.d8.b); break;
|
||||
case CPUINFO_STR_REGISTER + HC11_IX: sprintf(info->s, "IX: %04X", cpustate->ix); break;
|
||||
case CPUINFO_STR_REGISTER + HC11_IY: sprintf(info->s, "IY: %04X", cpustate->iy); break;
|
||||
}
|
||||
}
|
||||
|
||||
Loading…
Reference in New Issue
Block a user