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Some harmless mods to DC GD-Rom

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This commit is contained in:
Angelo Salese 2013-07-01 16:23:54 +00:00
parent 9927fa5faa
commit b0d73da8db
3 changed files with 26 additions and 23 deletions
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2
src/mess/drivers/dccons.c
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@ -116,7 +116,7 @@ static ADDRESS_MAP_START( dc_map, AS_PROGRAM, 64, dc_cons_state )
AM_RANGE(0x005f6800, 0x005f69ff) AM_READWRITE(dc_sysctrl_r, dc_sysctrl_w ) AM_RANGE(0x005f6800, 0x005f69ff) AM_READWRITE(dc_sysctrl_r, dc_sysctrl_w )
AM_RANGE(0x005f6c00, 0x005f6cff) AM_DEVICE32( "maple_dc", maple_dc_device, amap, U64(0xffffffffffffffff) ) AM_RANGE(0x005f6c00, 0x005f6cff) AM_DEVICE32( "maple_dc", maple_dc_device, amap, U64(0xffffffffffffffff) )
AM_RANGE(0x005f7000, 0x005f70ff) AM_READWRITE(dc_mess_gdrom_r, dc_mess_gdrom_w ) AM_RANGE(0x005f7000, 0x005f70ff) AM_READWRITE(dc_mess_gdrom_r, dc_mess_gdrom_w )
AM_RANGE(0x005f7400, 0x005f74ff) AM_READWRITE(dc_mess_g1_ctrl_r, dc_mess_g1_ctrl_w ) AM_RANGE(0x005f7400, 0x005f74ff) AM_READWRITE32(dc_mess_g1_ctrl_r, dc_mess_g1_ctrl_w, U64(0xffffffffffffffff) )
AM_RANGE(0x005f7800, 0x005f78ff) AM_READWRITE(dc_g2_ctrl_r, dc_g2_ctrl_w ) AM_RANGE(0x005f7800, 0x005f78ff) AM_READWRITE(dc_g2_ctrl_r, dc_g2_ctrl_w )
AM_RANGE(0x005f7c00, 0x005f7cff) AM_DEVICE32("powervr2", powervr2_device, pd_dma_map, U64(0xffffffffffffffff)) AM_RANGE(0x005f7c00, 0x005f7cff) AM_DEVICE32("powervr2", powervr2_device, pd_dma_map, U64(0xffffffffffffffff))
AM_RANGE(0x005f8000, 0x005f9fff) AM_DEVICE32("powervr2", powervr2_device, ta_map, U64(0xffffffffffffffff)) AM_RANGE(0x005f8000, 0x005f9fff) AM_DEVICE32("powervr2", powervr2_device, ta_map, U64(0xffffffffffffffff))

4
src/mess/includes/dccons.h
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@ -30,8 +30,8 @@ public:
inline int decode_reg32_64(UINT32 offset, UINT64 mem_mask, UINT64 *shift); inline int decode_reg32_64(UINT32 offset, UINT64 mem_mask, UINT64 *shift);
READ64_MEMBER( dc_mess_gdrom_r ); READ64_MEMBER( dc_mess_gdrom_r );
WRITE64_MEMBER( dc_mess_gdrom_w ); WRITE64_MEMBER( dc_mess_gdrom_w );
READ64_MEMBER( dc_mess_g1_ctrl_r ); READ32_MEMBER( dc_mess_g1_ctrl_r );
WRITE64_MEMBER( dc_mess_g1_ctrl_w ); WRITE32_MEMBER( dc_mess_g1_ctrl_w );
private: private:
UINT64 PDTRA, PCTRA; UINT64 PDTRA, PCTRA;

43
src/mess/machine/dccons.c
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@ -11,6 +11,9 @@
cfffee0 - stack location when bad happens cfffee0 - stack location when bad happens
TODO:
- gdrom_alt_status is identical to normal status except that "but it does not clear DMA status information when it is accessed"
*/ */
#include "emu.h" #include "emu.h"
@ -267,6 +270,8 @@ WRITE32_MEMBER(dc_cons_state::atapi_w )
atapi_data[atapi_data_ptr++] = data & 0xff; atapi_data[atapi_data_ptr++] = data & 0xff;
atapi_data[atapi_data_ptr++] = data >> 8; atapi_data[atapi_data_ptr++] = data >> 8;
//printf("%02x %02x %d\n",data & 0xff, data >> 8,atapi_data_ptr);
if (atapi_cdata_wait) if (atapi_cdata_wait)
{ {
// printf("ATAPI: waiting, ptr %d wait %d\n", atapi_data_ptr, atapi_cdata_wait); // printf("ATAPI: waiting, ptr %d wait %d\n", atapi_data_ptr, atapi_cdata_wait);
@ -651,32 +656,30 @@ int dc_cons_state::decode_reg32_64( UINT32 offset, UINT64 mem_mask, UINT64 *shif
return reg; return reg;
} }
READ64_MEMBER(dc_cons_state::dc_mess_g1_ctrl_r ) READ32_MEMBER(dc_cons_state::dc_mess_g1_ctrl_r )
{ {
int reg; switch(offset)
UINT64 shift; {
case SB_GDST:
reg = decode_reg32_64(offset, mem_mask, &shift); break;
mame_printf_verbose("G1CTRL: Unmapped read %08x\n", 0x5f7400+reg*4); case SB_GDLEND:
return (UINT64)g1bus_regs[reg] << shift; //debugger_break(machine());
return atapi_xferlen; // TODO: check me
default:
printf("G1CTRL: Unmapped read %08x\n", 0x5f7400+offset*4);
debugger_break(machine());
}
return g1bus_regs[offset];
} }
WRITE64_MEMBER(dc_cons_state::dc_mess_g1_ctrl_w ) WRITE32_MEMBER(dc_cons_state::dc_mess_g1_ctrl_w )
{ {
int reg; g1bus_regs[offset] = data; // 5f7400+reg*4=dat
UINT64 shift; // mame_printf_verbose("G1CTRL: [%08x=%x] write %" I64FMT "x to %x, mask %" I64FMT "x\n", 0x5f7400+reg*4, dat, data, offset, mem_mask);
UINT32 dat; //, old switch (offset)
reg = decode_reg32_64(offset, mem_mask, &shift);
dat = (UINT32)(data >> shift);
// old = g1bus_regs[reg];
g1bus_regs[reg] = dat; // 5f7400+reg*4=dat
mame_printf_verbose("G1CTRL: [%08x=%x] write %" I64FMT "x to %x, mask %" I64FMT "x\n", 0x5f7400+reg*4, dat, data, offset, mem_mask);
switch (reg)
{ {
case SB_GDST: case SB_GDST:
if (dat & 1 && g1bus_regs[SB_GDEN] == 1) // 0 -> 1 if (data & 1 && g1bus_regs[SB_GDEN] == 1) // 0 -> 1
{ {
if (g1bus_regs[SB_GDDIR] == 0) if (g1bus_regs[SB_GDDIR] == 0)
{ {