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m6805 disassembler: m_* ==> md_*
This commit is contained in:
Nathan Woods
parent
a09c98ed62
commit
b4dd43d14c
@ -15,16 +15,16 @@
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#include "m6805.h"
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enum addr_mode {
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m_imp=0, /* implicit */
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m_btr, /* bit test and relative */
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m_bit, /* bit set/clear */
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m_rel, /* relative */
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m_imm, /* immediate */
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m_dir, /* direct address */
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m_ext, /* extended address */
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m_idx, /* indexed */
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m_ix1, /* indexed + byte offset */
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m_ix2 /* indexed + word offset */
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md_imp=0, /* implicit */
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md_btr, /* bit test and relative */
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md_bit, /* bit set/clear */
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md_rel, /* relative */
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md_imm, /* immediate */
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md_dir, /* direct address */
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md_ext, /* extended address */
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md_idx, /* indexed */
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md_ix1, /* indexed + byte offset */
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md_ix2 /* indexed + word offset */
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};
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enum op_names {
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@ -56,70 +56,70 @@ static const char *const op_name_str[] = {
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};
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static const unsigned char disasm[0x100][2] = {
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{brset,m_btr},{brclr,m_btr},{brset,m_btr},{brclr,m_btr},/* 00 */
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{brset,m_btr},{brclr,m_btr},{brset,m_btr},{brclr,m_btr},
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{brset,m_btr},{brclr,m_btr},{brset,m_btr},{brclr,m_btr},
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{brset,m_btr},{brclr,m_btr},{brset,m_btr},{brclr,m_btr},
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{bset, m_bit},{bclr, m_bit},{bset, m_bit},{bclr, m_bit},/* 10 */
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{bset, m_bit},{bclr, m_bit},{bset, m_bit},{bclr, m_bit},
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{bset, m_bit},{bclr, m_bit},{bset, m_bit},{bclr, m_bit},
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{bset, m_bit},{bclr, m_bit},{bset, m_bit},{bclr, m_bit},
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{bra, m_rel},{brn, m_rel},{bhi, m_rel},{bls, m_rel},/* 20 */
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{bcc, m_rel},{bcs, m_rel},{bne, m_rel},{beq, m_rel},
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{bhcc, m_rel},{bhcs, m_rel},{bpl, m_rel},{bmi, m_rel},
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{bmc, m_rel},{bms, m_rel},{bil, m_rel},{bih, m_rel},
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{neg, m_dir},{ill, m_imp},{ill, m_imp},{com, m_dir},/* 30 */
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{lsr, m_dir},{ill, m_imp},{ror, m_dir},{asr, m_dir},
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{asl, m_dir},{rol, m_dir},{dec, m_dir},{ill, m_imp},
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{inc, m_dir},{tst, m_dir},{ill, m_imp},{clr, m_dir},
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{nega, m_imp},{ill, m_imp},{ill, m_imp},{coma, m_imp},/* 40 */
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{lsra, m_imp},{ill, m_imp},{rora, m_imp},{asra, m_imp},
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{asla, m_imp},{rola, m_imp},{deca, m_imp},{ill, m_imp},
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{inca, m_imp},{tsta, m_imp},{ill, m_imp},{clra, m_imp},
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{negx, m_imp},{ill, m_imp},{ill, m_imp},{comx, m_imp},/* 50 */
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{lsrx, m_imp},{ill, m_imp},{rorx, m_imp},{asrx, m_imp},
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{aslx, m_imp},{rolx, m_imp},{decx, m_imp},{ill, m_imp},
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{incx, m_imp},{tstx, m_imp},{ill, m_imp},{clrx, m_imp},
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{neg, m_ix1},{ill, m_imp},{ill, m_imp},{com, m_ix1},/* 60 */
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{lsr, m_ix1},{ill, m_imp},{ror, m_ix1},{asr, m_ix1},
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{asl, m_ix1},{rol, m_ix1},{dec, m_ix1},{ill, m_imp},
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{inc, m_ix1},{tst, m_ix1},{jmp, m_ix1},{clr, m_ix1},
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{neg, m_idx},{ill, m_imp},{ill, m_imp},{com, m_idx},/* 70 */
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{lsr, m_idx},{ill, m_imp},{ror, m_idx},{asr, m_idx},
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{asl, m_idx},{rol, m_idx},{dec, m_idx},{ill, m_imp},
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{inc, m_idx},{tst, m_idx},{jmp, m_idx},{clr, m_idx},
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{rti, m_imp},{rts, m_imp},{ill, m_imp},{swi, m_imp},/* 80 */
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{ill, m_imp},{ill, m_imp},{ill, m_imp},{ill, m_imp},
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{ill, m_imp},{ill, m_imp},{ill, m_imp},{ill, m_imp},
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{ill, m_imp},{ill, m_imp},{ill, m_imp},{ill, m_imp},
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{ill, m_imp},{ill, m_imp},{ill, m_imp},{ill, m_imp},/* 90 */
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{ill, m_imp},{ill, m_imp},{ill, m_imp},{tax, m_imp},
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{clc, m_imp},{sec, m_imp},{cli, m_imp},{sei, m_imp},
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{rsp, m_imp},{nop, m_imp},{ill, m_imp},{txa, m_imp},
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{suba, m_imm},{cmpa, m_imm},{sbca, m_imm},{cpx, m_imm},/* a0 */
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{anda, m_imm},{bita, m_imm},{lda, m_imm},{ill, m_imp},
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{eora, m_imm},{adca, m_imm},{ora, m_imm},{adda, m_imm},
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{ill, m_imp},{bsr, m_rel},{ldx, m_imm},{ill, m_imp},
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{suba, m_dir},{cmpa, m_dir},{sbca, m_dir},{cpx, m_dir},/* b0 */
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{anda, m_dir},{bita, m_dir},{lda, m_dir},{sta, m_dir},
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{eora, m_dir},{adca, m_dir},{ora, m_dir},{adda, m_dir},
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{jmp, m_dir},{jsr, m_dir},{ldx, m_dir},{stx, m_dir},
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{suba, m_ext},{cmpa, m_ext},{sbca, m_ext},{cpx, m_ext},/* c0 */
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{anda, m_ext},{bita, m_ext},{lda, m_ext},{sta, m_ext},
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{eora, m_ext},{adca, m_ext},{ora, m_ext},{adda, m_ext},
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{jmp, m_ext},{jsr, m_ext},{ldx, m_ext},{stx, m_ext},
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{suba, m_ix2},{cmpa, m_ix2},{sbca, m_ix2},{cpx, m_ix2},/* d0 */
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{anda, m_ix2},{bita, m_ix2},{lda, m_ix2},{sta, m_ix2},
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{eora, m_ix2},{adca, m_ix2},{ora, m_ix2},{adda, m_ix2},
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{jmp, m_ix2},{jsr, m_ix2},{ldx, m_ix2},{stx, m_ix2},
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{suba, m_ix1},{cmpa, m_ix1},{sbca, m_ix1},{cpx, m_ix1},/* e0 */
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{anda, m_ix1},{bita, m_ix1},{lda, m_ix1},{sta, m_ix1},
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{eora, m_ix1},{adca, m_ix1},{ora, m_ix1},{adda, m_ix1},
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{jmp, m_ix1},{jsr, m_ix1},{ldx, m_ix1},{stx, m_ix1},
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{suba, m_idx},{cmpa, m_idx},{sbca, m_idx},{cpx, m_idx},/* f0 */
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{anda, m_idx},{bita, m_idx},{lda, m_idx},{sta, m_idx},
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{eora, m_idx},{adca, m_idx},{ora, m_idx},{adda, m_idx},
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{jmp, m_idx},{jsr, m_idx},{ldx, m_idx},{stx, m_idx}
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{brset,md_btr},{brclr,md_btr},{brset,md_btr},{brclr,md_btr},/* 00 */
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{brset,md_btr},{brclr,md_btr},{brset,md_btr},{brclr,md_btr},
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{brset,md_btr},{brclr,md_btr},{brset,md_btr},{brclr,md_btr},
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{brset,md_btr},{brclr,md_btr},{brset,md_btr},{brclr,md_btr},
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{bset, md_bit},{bclr, md_bit},{bset, md_bit},{bclr, md_bit},/* 10 */
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{bset, md_bit},{bclr, md_bit},{bset, md_bit},{bclr, md_bit},
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{bset, md_bit},{bclr, md_bit},{bset, md_bit},{bclr, md_bit},
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{bset, md_bit},{bclr, md_bit},{bset, md_bit},{bclr, md_bit},
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{bra, md_rel},{brn, md_rel},{bhi, md_rel},{bls, md_rel},/* 20 */
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{bcc, md_rel},{bcs, md_rel},{bne, md_rel},{beq, md_rel},
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{bhcc, md_rel},{bhcs, md_rel},{bpl, md_rel},{bmi, md_rel},
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{bmc, md_rel},{bms, md_rel},{bil, md_rel},{bih, md_rel},
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{neg, md_dir},{ill, md_imp},{ill, md_imp},{com, md_dir},/* 30 */
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{lsr, md_dir},{ill, md_imp},{ror, md_dir},{asr, md_dir},
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{asl, md_dir},{rol, md_dir},{dec, md_dir},{ill, md_imp},
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{inc, md_dir},{tst, md_dir},{ill, md_imp},{clr, md_dir},
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{nega, md_imp},{ill, md_imp},{ill, md_imp},{coma, md_imp},/* 40 */
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{lsra, md_imp},{ill, md_imp},{rora, md_imp},{asra, md_imp},
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{asla, md_imp},{rola, md_imp},{deca, md_imp},{ill, md_imp},
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{inca, md_imp},{tsta, md_imp},{ill, md_imp},{clra, md_imp},
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{negx, md_imp},{ill, md_imp},{ill, md_imp},{comx, md_imp},/* 50 */
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{lsrx, md_imp},{ill, md_imp},{rorx, md_imp},{asrx, md_imp},
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{aslx, md_imp},{rolx, md_imp},{decx, md_imp},{ill, md_imp},
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{incx, md_imp},{tstx, md_imp},{ill, md_imp},{clrx, md_imp},
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{neg, md_ix1},{ill, md_imp},{ill, md_imp},{com, md_ix1},/* 60 */
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{lsr, md_ix1},{ill, md_imp},{ror, md_ix1},{asr, md_ix1},
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{asl, md_ix1},{rol, md_ix1},{dec, md_ix1},{ill, md_imp},
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{inc, md_ix1},{tst, md_ix1},{jmp, md_ix1},{clr, md_ix1},
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{neg, md_idx},{ill, md_imp},{ill, md_imp},{com, md_idx},/* 70 */
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{lsr, md_idx},{ill, md_imp},{ror, md_idx},{asr, md_idx},
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{asl, md_idx},{rol, md_idx},{dec, md_idx},{ill, md_imp},
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{inc, md_idx},{tst, md_idx},{jmp, md_idx},{clr, md_idx},
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{rti, md_imp},{rts, md_imp},{ill, md_imp},{swi, md_imp},/* 80 */
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{ill, md_imp},{ill, md_imp},{ill, md_imp},{ill, md_imp},
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{ill, md_imp},{ill, md_imp},{ill, md_imp},{ill, md_imp},
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{ill, md_imp},{ill, md_imp},{ill, md_imp},{ill, md_imp},
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{ill, md_imp},{ill, md_imp},{ill, md_imp},{ill, md_imp},/* 90 */
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{ill, md_imp},{ill, md_imp},{ill, md_imp},{tax, md_imp},
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{clc, md_imp},{sec, md_imp},{cli, md_imp},{sei, md_imp},
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{rsp, md_imp},{nop, md_imp},{ill, md_imp},{txa, md_imp},
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{suba, md_imm},{cmpa, md_imm},{sbca, md_imm},{cpx, md_imm},/* a0 */
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{anda, md_imm},{bita, md_imm},{lda, md_imm},{ill, md_imp},
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{eora, md_imm},{adca, md_imm},{ora, md_imm},{adda, md_imm},
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{ill, md_imp},{bsr, md_rel},{ldx, md_imm},{ill, md_imp},
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{suba, md_dir},{cmpa, md_dir},{sbca, md_dir},{cpx, md_dir},/* b0 */
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{anda, md_dir},{bita, md_dir},{lda, md_dir},{sta, md_dir},
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{eora, md_dir},{adca, md_dir},{ora, md_dir},{adda, md_dir},
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{jmp, md_dir},{jsr, md_dir},{ldx, md_dir},{stx, md_dir},
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{suba, md_ext},{cmpa, md_ext},{sbca, md_ext},{cpx, md_ext},/* c0 */
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{anda, md_ext},{bita, md_ext},{lda, md_ext},{sta, md_ext},
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{eora, md_ext},{adca, md_ext},{ora, md_ext},{adda, md_ext},
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{jmp, md_ext},{jsr, md_ext},{ldx, md_ext},{stx, md_ext},
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{suba, md_ix2},{cmpa, md_ix2},{sbca, md_ix2},{cpx, md_ix2},/* d0 */
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{anda, md_ix2},{bita, md_ix2},{lda, md_ix2},{sta, md_ix2},
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{eora, md_ix2},{adca, md_ix2},{ora, md_ix2},{adda, md_ix2},
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{jmp, md_ix2},{jsr, md_ix2},{ldx, md_ix2},{stx, md_ix2},
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{suba, md_ix1},{cmpa, md_ix1},{sbca, md_ix1},{cpx, md_ix1},/* e0 */
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{anda, md_ix1},{bita, md_ix1},{lda, md_ix1},{sta, md_ix1},
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{eora, md_ix1},{adca, md_ix1},{ora, md_ix1},{adda, md_ix1},
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{jmp, md_ix1},{jsr, md_ix1},{ldx, md_ix1},{stx, md_ix1},
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{suba, md_idx},{cmpa, md_idx},{sbca, md_idx},{cpx, md_idx},/* f0 */
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{anda, md_idx},{bita, md_idx},{lda, md_idx},{sta, md_idx},
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{eora, md_idx},{adca, md_idx},{ora, md_idx},{adda, md_idx},
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{jmp, md_idx},{jsr, md_idx},{ldx, md_idx},{stx, md_idx}
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};
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#if 0
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@ -178,42 +178,42 @@ static offs_t internal_disasm_m6805(cpu_device *device, std::ostream &stream, of
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switch( disasm[code][1] )
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{
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case m_btr: /* bit test and relative branch */
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case md_btr: /* bit test and relative branch */
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bit = (code >> 1) & 7;
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util::stream_format(stream, "%d,$%02X,$%03X", bit, opram[1], pc + 3 + (int8_t)opram[2]);
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result = 3 | flags | DASMFLAG_SUPPORTED;
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break;
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case m_bit: /* bit test */
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case md_bit: /* bit test */
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bit = (code >> 1) & 7;
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util::stream_format(stream, "%d,$%03X", bit, opram[1]);
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result = 2 | flags | DASMFLAG_SUPPORTED;
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break;
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case m_rel: /* relative */
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case md_rel: /* relative */
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util::stream_format(stream, "$%03X", pc + 2 + (int8_t)opram[1]);
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result = 2 | flags | DASMFLAG_SUPPORTED;
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break;
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case m_imm: /* immediate */
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case md_imm: /* immediate */
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util::stream_format(stream, "#$%02X", opram[1]);
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result = 2 | flags | DASMFLAG_SUPPORTED;
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break;
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case m_dir: /* direct (zero page address) */
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case md_dir: /* direct (zero page address) */
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util::stream_format(stream, "$%02X", opram[1]);
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result = 2 | flags | DASMFLAG_SUPPORTED;
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break;
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case m_ext: /* extended (16 bit address) */
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case md_ext: /* extended (16 bit address) */
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ea = (opram[1] << 8) + opram[2];
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util::stream_format(stream, "$%04X", ea);
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result = 3 | flags | DASMFLAG_SUPPORTED;
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break;
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case m_idx: /* indexed */
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case md_idx: /* indexed */
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util::stream_format(stream, "(x)");
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result = 1 | flags | DASMFLAG_SUPPORTED;
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break;
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case m_ix1: /* indexed + byte (zero page) */
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case md_ix1: /* indexed + byte (zero page) */
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util::stream_format(stream, "(x+$%02X)", opram[1]);
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result = 2 | flags | DASMFLAG_SUPPORTED;
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break;
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case m_ix2: /* indexed + word (16 bit address) */
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case md_ix2: /* indexed + word (16 bit address) */
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ea = (opram[1] << 8) + opram[2];
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util::stream_format(stream, "(x+$%04X)", ea);
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result = 3 | flags | DASMFLAG_SUPPORTED;
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