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sh4: Modernized cpu core (nw)

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This commit is contained in:
Wilbert Pol 2014-07-07 20:02:49 +00:00
parent 5fe4dda582
commit b63e1f9fdd
19 changed files with 3578 additions and 3065 deletions
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383
src/emu/cpu/sh4/sh3comn.c
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@ -10,59 +10,58 @@
/* High internal area (ffffxxxx) */ /* High internal area (ffffxxxx) */
WRITE32_MEMBER( sh3_device::sh3_internal_high_w ) WRITE32_MEMBER( sh3_base_device::sh3_internal_high_w )
{ {
sh4_state *sh4 = get_safe_token(this); COMBINE_DATA(&m_sh3internal_upper[offset]);
COMBINE_DATA(&sh4->m_sh3internal_upper[offset]);
switch (offset) switch (offset)
{ {
case SH3_ICR0_IPRA_ADDR: case SH3_ICR0_IPRA_ADDR:
if (mem_mask & 0xffff0000) if (mem_mask & 0xffff0000)
{ {
logerror("'%s' (%08x): INTC internal write to %08x = %08x & %08x (SH3_ICR0_IPRA_ADDR - ICR0)\n",sh4->device->tag(), sh4->pc & AM,(offset *4)+SH3_UPPER_REGBASE,data,mem_mask); logerror("'%s' (%08x): INTC internal write to %08x = %08x & %08x (SH3_ICR0_IPRA_ADDR - ICR0)\n",tag(), m_pc & AM,(offset *4)+SH3_UPPER_REGBASE,data,mem_mask);
} }
if (mem_mask & 0x0000ffff) if (mem_mask & 0x0000ffff)
{ {
logerror("'%s' (%08x): INTC internal write to %08x = %08x & %08x (SH3_ICR0_IPRA_ADDR - IPRA)\n",sh4->device->tag(), sh4->pc & AM,(offset *4)+SH3_UPPER_REGBASE,data,mem_mask); logerror("'%s' (%08x): INTC internal write to %08x = %08x & %08x (SH3_ICR0_IPRA_ADDR - IPRA)\n",tag(), m_pc & AM,(offset *4)+SH3_UPPER_REGBASE,data,mem_mask);
sh4_handler_ipra_w(sh4,data&0xffff,mem_mask&0xffff); sh4_handler_ipra_w(data&0xffff,mem_mask&0xffff);
} }
break; break;
case SH3_IPRB_ADDR: case SH3_IPRB_ADDR:
logerror("'%s' (%08x): INTC internal write to %08x = %08x & %08x (SH3_IPRB_ADDR)\n",sh4->device->tag(), sh4->pc & AM,(offset *4)+SH3_UPPER_REGBASE,data,mem_mask); logerror("'%s' (%08x): INTC internal write to %08x = %08x & %08x (SH3_IPRB_ADDR)\n",tag(), m_pc & AM,(offset *4)+SH3_UPPER_REGBASE,data,mem_mask);
break; break;
case SH3_TOCR_TSTR_ADDR: case SH3_TOCR_TSTR_ADDR:
logerror("'%s' (%08x): TMU internal write to %08x = %08x & %08x (SH3_TOCR_TSTR_ADDR)\n",sh4->device->tag(), sh4->pc & AM,(offset *4)+SH3_UPPER_REGBASE,data,mem_mask); logerror("'%s' (%08x): TMU internal write to %08x = %08x & %08x (SH3_TOCR_TSTR_ADDR)\n",tag(), m_pc & AM,(offset *4)+SH3_UPPER_REGBASE,data,mem_mask);
if (mem_mask&0xff000000) if (mem_mask&0xff000000)
{ {
sh4_handle_tocr_addr_w(sh4, (data>>24)&0xffff, (mem_mask>>24)&0xff); sh4_handle_tocr_addr_w((data>>24)&0xffff, (mem_mask>>24)&0xff);
} }
if (mem_mask&0x0000ff00) if (mem_mask&0x0000ff00)
{ {
sh4_handle_tstr_addr_w(sh4, (data>>8)&0xff, (mem_mask>>8)&0xff); sh4_handle_tstr_addr_w((data>>8)&0xff, (mem_mask>>8)&0xff);
} }
if (mem_mask&0x00ff00ff) if (mem_mask&0x00ff00ff)
{ {
fatalerror("SH3_TOCR_TSTR_ADDR unused bits accessed (write)\n"); fatalerror("SH3_TOCR_TSTR_ADDR unused bits accessed (write)\n");
} }
break; break;
case SH3_TCOR0_ADDR: sh4_handle_tcor0_addr_w(sh4, data, mem_mask);break; case SH3_TCOR0_ADDR: sh4_handle_tcor0_addr_w(data, mem_mask);break;
case SH3_TCOR1_ADDR: sh4_handle_tcor1_addr_w(sh4, data, mem_mask);break; case SH3_TCOR1_ADDR: sh4_handle_tcor1_addr_w(data, mem_mask);break;
case SH3_TCOR2_ADDR: sh4_handle_tcor2_addr_w(sh4, data, mem_mask);break; case SH3_TCOR2_ADDR: sh4_handle_tcor2_addr_w(data, mem_mask);break;
case SH3_TCNT0_ADDR: sh4_handle_tcnt0_addr_w(sh4, data, mem_mask);break; case SH3_TCNT0_ADDR: sh4_handle_tcnt0_addr_w(data, mem_mask);break;
case SH3_TCNT1_ADDR: sh4_handle_tcnt1_addr_w(sh4, data, mem_mask);break; case SH3_TCNT1_ADDR: sh4_handle_tcnt1_addr_w(data, mem_mask);break;
case SH3_TCNT2_ADDR: sh4_handle_tcnt2_addr_w(sh4, data, mem_mask);break; case SH3_TCNT2_ADDR: sh4_handle_tcnt2_addr_w(data, mem_mask);break;
case SH3_TCR0_ADDR: sh4_handle_tcr0_addr_w(sh4, data>>16, mem_mask>>16);break; case SH3_TCR0_ADDR: sh4_handle_tcr0_addr_w(data>>16, mem_mask>>16);break;
case SH3_TCR1_ADDR: sh4_handle_tcr1_addr_w(sh4, data>>16, mem_mask>>16);break; case SH3_TCR1_ADDR: sh4_handle_tcr1_addr_w(data>>16, mem_mask>>16);break;
case SH3_TCR2_ADDR: sh4_handle_tcr2_addr_w(sh4, data>>16, mem_mask>>16);break; case SH3_TCR2_ADDR: sh4_handle_tcr2_addr_w(data>>16, mem_mask>>16);break;
case SH3_TCPR2_ADDR: sh4_handle_tcpr2_addr_w(sh4,data, mem_mask);break; case SH3_TCPR2_ADDR: sh4_handle_tcpr2_addr_w(data, mem_mask);break;
default: default:
logerror("'%s' (%08x): unmapped internal write to %08x = %08x & %08x (unk)\n",sh4->device->tag(), sh4->pc & AM,(offset *4)+SH3_UPPER_REGBASE,data,mem_mask); logerror("'%s' (%08x): unmapped internal write to %08x = %08x & %08x (unk)\n",tag(), m_pc & AM,(offset *4)+SH3_UPPER_REGBASE,data,mem_mask);
break; break;
} }
@ -72,101 +71,97 @@ WRITE32_MEMBER( sh3_device::sh3_internal_high_w )
} }
READ32_MEMBER( sh3_device::sh3_internal_high_r ) READ32_MEMBER( sh3_base_device::sh3_internal_high_r )
{ {
sh4_state *sh4 = get_safe_token(this);
UINT32 ret = 0; UINT32 ret = 0;
switch (offset) switch (offset)
{ {
case SH3_ICR0_IPRA_ADDR: case SH3_ICR0_IPRA_ADDR:
logerror("'%s' (%08x): INTC internal read from %08x mask %08x (SH3_ICR0_IPRA_ADDR - %08x)\n",sh4->device->tag(), sh4->pc & AM,(offset *4)+SH3_UPPER_REGBASE,mem_mask, sh4->m_sh3internal_upper[offset]); logerror("'%s' (%08x): INTC internal read from %08x mask %08x (SH3_ICR0_IPRA_ADDR - %08x)\n",tag(), m_pc & AM,(offset *4)+SH3_UPPER_REGBASE,mem_mask, m_sh3internal_upper[offset]);
return (sh4->m_sh3internal_upper[offset] & 0xffff0000) | (sh4->SH4_IPRA & 0xffff); return (m_sh3internal_upper[offset] & 0xffff0000) | (m_SH4_IPRA & 0xffff);
case SH3_IPRB_ADDR: case SH3_IPRB_ADDR:
logerror("'%s' (%08x): INTC internal read from %08x mask %08x (SH3_IPRB_ADDR - %08x)\n",sh4->device->tag(), sh4->pc & AM,(offset *4)+SH3_UPPER_REGBASE,mem_mask, sh4->m_sh3internal_upper[offset]); logerror("'%s' (%08x): INTC internal read from %08x mask %08x (SH3_IPRB_ADDR - %08x)\n",tag(), m_pc & AM,(offset *4)+SH3_UPPER_REGBASE,mem_mask, m_sh3internal_upper[offset]);
return sh4->m_sh3internal_upper[offset]; return m_sh3internal_upper[offset];
case SH3_TOCR_TSTR_ADDR: case SH3_TOCR_TSTR_ADDR:
if (mem_mask&0xff00000) if (mem_mask&0xff00000)
{ {
ret |= (sh4_handle_tocr_addr_r(sh4, mem_mask)&0xff)<<24; ret |= (sh4_handle_tocr_addr_r(mem_mask)&0xff)<<24;
} }
if (mem_mask&0x0000ff00) if (mem_mask&0x0000ff00)
{ {
ret |= (sh4_handle_tstr_addr_r(sh4, mem_mask)&0xff)<<8; ret |= (sh4_handle_tstr_addr_r(mem_mask)&0xff)<<8;
} }
if (mem_mask&0x00ff00ff) if (mem_mask&0x00ff00ff)
{ {
fatalerror("SH3_TOCR_TSTR_ADDR unused bits accessed (read)\n"); fatalerror("SH3_TOCR_TSTR_ADDR unused bits accessed (read)\n");
} }
return ret; return ret;
case SH3_TCOR0_ADDR: return sh4_handle_tcor0_addr_r(sh4, mem_mask); case SH3_TCOR0_ADDR: return sh4_handle_tcor0_addr_r(mem_mask);
case SH3_TCOR1_ADDR: return sh4_handle_tcor1_addr_r(sh4, mem_mask); case SH3_TCOR1_ADDR: return sh4_handle_tcor1_addr_r(mem_mask);
case SH3_TCOR2_ADDR: return sh4_handle_tcor2_addr_r(sh4, mem_mask); case SH3_TCOR2_ADDR: return sh4_handle_tcor2_addr_r(mem_mask);
case SH3_TCNT0_ADDR: return sh4_handle_tcnt0_addr_r(sh4, mem_mask); case SH3_TCNT0_ADDR: return sh4_handle_tcnt0_addr_r(mem_mask);
case SH3_TCNT1_ADDR: return sh4_handle_tcnt1_addr_r(sh4, mem_mask); case SH3_TCNT1_ADDR: return sh4_handle_tcnt1_addr_r(mem_mask);
case SH3_TCNT2_ADDR: return sh4_handle_tcnt2_addr_r(sh4, mem_mask); case SH3_TCNT2_ADDR: return sh4_handle_tcnt2_addr_r(mem_mask);
case SH3_TCR0_ADDR: return sh4_handle_tcr0_addr_r(sh4, mem_mask)<<16; case SH3_TCR0_ADDR: return sh4_handle_tcr0_addr_r(mem_mask)<<16;
case SH3_TCR1_ADDR: return sh4_handle_tcr1_addr_r(sh4, mem_mask)<<16; case SH3_TCR1_ADDR: return sh4_handle_tcr1_addr_r(mem_mask)<<16;
case SH3_TCR2_ADDR: return sh4_handle_tcr2_addr_r(sh4, mem_mask)<<16; case SH3_TCR2_ADDR: return sh4_handle_tcr2_addr_r(mem_mask)<<16;
case SH3_TCPR2_ADDR: return sh4_handle_tcpr2_addr_r(sh4, mem_mask); case SH3_TCPR2_ADDR: return sh4_handle_tcpr2_addr_r(mem_mask);
case SH3_TRA_ADDR: case SH3_TRA_ADDR:
logerror("'%s' (%08x): unmapped internal read from %08x mask %08x (SH3 TRA - %08x)\n",sh4->device->tag(), sh4->pc & AM,(offset *4)+SH3_UPPER_REGBASE,mem_mask, sh4->m_sh3internal_upper[offset]); logerror("'%s' (%08x): unmapped internal read from %08x mask %08x (SH3 TRA - %08x)\n",tag(), m_pc & AM,(offset *4)+SH3_UPPER_REGBASE,mem_mask, m_sh3internal_upper[offset]);
return sh4->m_sh3internal_upper[offset]; return m_sh3internal_upper[offset];
case SH3_EXPEVT_ADDR: case SH3_EXPEVT_ADDR:
logerror("'%s' (%08x): unmapped internal read from %08x mask %08x (SH3 EXPEVT - %08x)\n",sh4->device->tag(), sh4->pc & AM,(offset *4)+SH3_UPPER_REGBASE,mem_mask, sh4->m_sh3internal_upper[offset]); logerror("'%s' (%08x): unmapped internal read from %08x mask %08x (SH3 EXPEVT - %08x)\n",tag(), m_pc & AM,(offset *4)+SH3_UPPER_REGBASE,mem_mask, m_sh3internal_upper[offset]);
return sh4->m_sh3internal_upper[offset]; return m_sh3internal_upper[offset];
case SH3_INTEVT_ADDR: case SH3_INTEVT_ADDR:
logerror("'%s' (%08x): unmapped internal read from %08x mask %08x (SH3 INTEVT - %08x)\n",sh4->device->tag(), sh4->pc & AM,(offset *4)+SH3_UPPER_REGBASE,mem_mask, sh4->m_sh3internal_upper[offset]); logerror("'%s' (%08x): unmapped internal read from %08x mask %08x (SH3 INTEVT - %08x)\n",tag(), m_pc & AM,(offset *4)+SH3_UPPER_REGBASE,mem_mask, m_sh3internal_upper[offset]);
fatalerror("INTEVT unsupported on SH3\n"); fatalerror("INTEVT unsupported on SH3\n");
return sh4->m_sh3internal_upper[offset]; return m_sh3internal_upper[offset];
default: default:
logerror("'%s' (%08x): unmapped internal read from %08x mask %08x\n",sh4->device->tag(), sh4->pc & AM,(offset *4)+SH3_UPPER_REGBASE,mem_mask); logerror("'%s' (%08x): unmapped internal read from %08x mask %08x\n",tag(), m_pc & AM,(offset *4)+SH3_UPPER_REGBASE,mem_mask);
return sh4->m_sh3internal_upper[offset]; return m_sh3internal_upper[offset];
} }
} }
READ32_MEMBER( sh3_device::sh3_internal_r ) READ32_MEMBER( sh3_base_device::sh3_internal_r )
{ {
sh4_state *sh4 = get_safe_token(this);
if (offset<0x1000) if (offset<0x1000)
{ {
switch (offset) switch (offset)
{ {
case SH3_SAR0_ADDR: return sh4_handle_sar0_addr_r(sh4,mem_mask); case SH3_SAR0_ADDR: return sh4_handle_sar0_addr_r(mem_mask);
case SH3_SAR1_ADDR: return sh4_handle_sar1_addr_r(sh4,mem_mask); case SH3_SAR1_ADDR: return sh4_handle_sar1_addr_r(mem_mask);
case SH3_SAR2_ADDR: return sh4_handle_sar2_addr_r(sh4,mem_mask); case SH3_SAR2_ADDR: return sh4_handle_sar2_addr_r(mem_mask);
case SH3_SAR3_ADDR: return sh4_handle_sar3_addr_r(sh4,mem_mask); case SH3_SAR3_ADDR: return sh4_handle_sar3_addr_r(mem_mask);
case SH3_DAR0_ADDR: return sh4_handle_dar0_addr_r(sh4,mem_mask); case SH3_DAR0_ADDR: return sh4_handle_dar0_addr_r(mem_mask);
case SH3_DAR1_ADDR: return sh4_handle_dar1_addr_r(sh4,mem_mask); case SH3_DAR1_ADDR: return sh4_handle_dar1_addr_r(mem_mask);
case SH3_DAR2_ADDR: return sh4_handle_dar2_addr_r(sh4,mem_mask); case SH3_DAR2_ADDR: return sh4_handle_dar2_addr_r(mem_mask);
case SH3_DAR3_ADDR: return sh4_handle_dar3_addr_r(sh4,mem_mask); case SH3_DAR3_ADDR: return sh4_handle_dar3_addr_r(mem_mask);
case SH3_DMATCR0_ADDR: return sh4_handle_dmatcr0_addr_r(sh4,mem_mask); case SH3_DMATCR0_ADDR: return sh4_handle_dmatcr0_addr_r(mem_mask);
case SH3_DMATCR1_ADDR: return sh4_handle_dmatcr1_addr_r(sh4,mem_mask); case SH3_DMATCR1_ADDR: return sh4_handle_dmatcr1_addr_r(mem_mask);
case SH3_DMATCR2_ADDR: return sh4_handle_dmatcr2_addr_r(sh4,mem_mask); case SH3_DMATCR2_ADDR: return sh4_handle_dmatcr2_addr_r(mem_mask);
case SH3_DMATCR3_ADDR: return sh4_handle_dmatcr3_addr_r(sh4,mem_mask); case SH3_DMATCR3_ADDR: return sh4_handle_dmatcr3_addr_r(mem_mask);
case SH3_CHCR0_ADDR: return sh4_handle_chcr0_addr_r(sh4,mem_mask); case SH3_CHCR0_ADDR: return sh4_handle_chcr0_addr_r(mem_mask);
case SH3_CHCR1_ADDR: return sh4_handle_chcr1_addr_r(sh4,mem_mask); case SH3_CHCR1_ADDR: return sh4_handle_chcr1_addr_r(mem_mask);
case SH3_CHCR2_ADDR: return sh4_handle_chcr2_addr_r(sh4,mem_mask); case SH3_CHCR2_ADDR: return sh4_handle_chcr2_addr_r(mem_mask);
case SH3_CHCR3_ADDR: return sh4_handle_chcr3_addr_r(sh4,mem_mask); case SH3_CHCR3_ADDR: return sh4_handle_chcr3_addr_r(mem_mask);
case SH3_DMAOR_ADDR: return sh4_handle_dmaor_addr_r(sh4,mem_mask)<<16; case SH3_DMAOR_ADDR: return sh4_handle_dmaor_addr_r(mem_mask)<<16;
case INTEVT2: case INTEVT2:
{ {
// logerror("'%s' (%08x): unmapped internal read from %08x mask %08x (INTEVT2)\n",sh4->device->tag(), sh4->pc & AM,(offset *4)+0x4000000,mem_mask); // logerror("'%s' (%08x): unmapped internal read from %08x mask %08x (INTEVT2)\n",tag(), m_pc & AM,(offset *4)+0x4000000,mem_mask);
return sh4->m_sh3internal_lower[offset]; return m_sh3internal_lower[offset];
} }
break; break;
@ -176,17 +171,17 @@ READ32_MEMBER( sh3_device::sh3_internal_r )
{ {
if (mem_mask & 0xff000000) if (mem_mask & 0xff000000)
{ {
logerror("'%s' (%08x): unmapped internal read from %08x mask %08x (IRR0)\n",sh4->device->tag(), sh4->pc & AM,(offset *4)+0x4000000,mem_mask); logerror("'%s' (%08x): unmapped internal read from %08x mask %08x (IRR0)\n",tag(), m_pc & AM,(offset *4)+0x4000000,mem_mask);
return sh4->m_sh3internal_lower[offset]; return m_sh3internal_lower[offset];
} }
if (mem_mask & 0x0000ff00) if (mem_mask & 0x0000ff00)
{ {
logerror("'%s' (%08x): unmapped internal read from %08x mask %08x (IRR1)\n",sh4->device->tag(), sh4->pc & AM,(offset *4)+0x4000000,mem_mask); logerror("'%s' (%08x): unmapped internal read from %08x mask %08x (IRR1)\n",tag(), m_pc & AM,(offset *4)+0x4000000,mem_mask);
return sh4->m_sh3internal_lower[offset]; return m_sh3internal_lower[offset];
} }
fatalerror("'%s' (%08x): unmapped internal read from %08x mask %08x (IRR0/1 unused bits)\n",sh4->device->tag(), sh4->pc & AM,(offset *4)+0x4000000,mem_mask); fatalerror("'%s' (%08x): unmapped internal read from %08x mask %08x (IRR0/1 unused bits)\n",tag(), m_pc & AM,(offset *4)+0x4000000,mem_mask);
} }
} }
break; break;
@ -195,14 +190,14 @@ READ32_MEMBER( sh3_device::sh3_internal_r )
{ {
if (mem_mask & 0xffff0000) if (mem_mask & 0xffff0000)
{ {
//logerror("'%s' (%08x): unmapped internal read from %08x mask %08x (PADR)\n",sh4->device->tag(), sh4->pc & AM,(offset *4)+0x4000000,mem_mask); //logerror("'%s' (%08x): unmapped internal read from %08x mask %08x (PADR)\n",tag(), m_pc & AM,(offset *4)+0x4000000,mem_mask);
return sh4->io->read_qword(SH3_PORT_A)<<24; return m_io->read_qword(SH3_PORT_A)<<24;
} }
if (mem_mask & 0x0000ffff) if (mem_mask & 0x0000ffff)
{ {
//logerror("'%s' (%08x): unmapped internal read from %08x mask %08x (PBDR)\n",sh4->device->tag(), sh4->pc & AM,(offset *4)+0x4000000,mem_mask); //logerror("'%s' (%08x): unmapped internal read from %08x mask %08x (PBDR)\n",tag(), m_pc & AM,(offset *4)+0x4000000,mem_mask);
return sh4->io->read_qword(SH3_PORT_B)<<8; return m_io->read_qword(SH3_PORT_B)<<8;
} }
} }
break; break;
@ -211,14 +206,14 @@ READ32_MEMBER( sh3_device::sh3_internal_r )
{ {
if (mem_mask & 0xffff0000) if (mem_mask & 0xffff0000)
{ {
//logerror("'%s' (%08x): unmapped internal read from %08x mask %08x (PCDR)\n",sh4->device->tag(), sh4->pc & AM,(offset *4)+0x4000000,mem_mask); //logerror("'%s' (%08x): unmapped internal read from %08x mask %08x (PCDR)\n",tag(), m_pc & AM,(offset *4)+0x4000000,mem_mask);
return sh4->io->read_qword(SH3_PORT_C)<<24; return m_io->read_qword(SH3_PORT_C)<<24;
} }
if (mem_mask & 0x0000ffff) if (mem_mask & 0x0000ffff)
{ {
//logerror("'%s' (%08x): unmapped internal read from %08x mask %08x (PDDR)\n",sh4->device->tag(), sh4->pc & AM,(offset *4)+0x4000000,mem_mask); //logerror("'%s' (%08x): unmapped internal read from %08x mask %08x (PDDR)\n",tag(), m_pc & AM,(offset *4)+0x4000000,mem_mask);
return sh4->io->read_qword(SH3_PORT_D)<<8; return m_io->read_qword(SH3_PORT_D)<<8;
} }
} }
break; break;
@ -227,14 +222,14 @@ READ32_MEMBER( sh3_device::sh3_internal_r )
{ {
if (mem_mask & 0xffff0000) if (mem_mask & 0xffff0000)
{ {
//logerror("'%s' (%08x): unmapped internal read from %08x mask %08x (PEDR)\n",sh4->device->tag(), sh4->pc & AM,(offset *4)+0x4000000,mem_mask); //logerror("'%s' (%08x): unmapped internal read from %08x mask %08x (PEDR)\n",tag(), m_pc & AM,(offset *4)+0x4000000,mem_mask);
return sh4->io->read_qword(SH3_PORT_E)<<24; return m_io->read_qword(SH3_PORT_E)<<24;
} }
if (mem_mask & 0x0000ffff) if (mem_mask & 0x0000ffff)
{ {
//logerror("'%s' (%08x): unmapped internal read from %08x mask %08x (PFDR)\n",sh4->device->tag(), sh4->pc & AM,(offset *4)+0x4000000,mem_mask); //logerror("'%s' (%08x): unmapped internal read from %08x mask %08x (PFDR)\n",tag(), m_pc & AM,(offset *4)+0x4000000,mem_mask);
return sh4->io->read_qword(SH3_PORT_F)<<8; return m_io->read_qword(SH3_PORT_F)<<8;
} }
} }
break; break;
@ -243,14 +238,14 @@ READ32_MEMBER( sh3_device::sh3_internal_r )
{ {
if (mem_mask & 0xffff0000) if (mem_mask & 0xffff0000)
{ {
//logerror("'%s' (%08x): unmapped internal read from %08x mask %08x (PGDR)\n",sh4->device->tag(), sh4->pc & AM,(offset *4)+0x4000000,mem_mask); //logerror("'%s' (%08x): unmapped internal read from %08x mask %08x (PGDR)\n",tag(), m_pc & AM,(offset *4)+0x4000000,mem_mask);
return sh4->io->read_qword(SH3_PORT_G)<<24; return m_io->read_qword(SH3_PORT_G)<<24;
} }
if (mem_mask & 0x0000ffff) if (mem_mask & 0x0000ffff)
{ {
//logerror("'%s' (%08x): unmapped internal read from %08x mask %08x (PHDR)\n",sh4->device->tag(), sh4->pc & AM,(offset *4)+0x4000000,mem_mask); //logerror("'%s' (%08x): unmapped internal read from %08x mask %08x (PHDR)\n",tag(), m_pc & AM,(offset *4)+0x4000000,mem_mask);
return sh4->io->read_qword(SH3_PORT_H)<<8; return m_io->read_qword(SH3_PORT_H)<<8;
} }
} }
break; break;
@ -259,14 +254,14 @@ READ32_MEMBER( sh3_device::sh3_internal_r )
{ {
if (mem_mask & 0xffff0000) if (mem_mask & 0xffff0000)
{ {
//logerror("'%s' (%08x): unmapped internal read from %08x mask %08x (PJDR)\n",sh4->device->tag(), sh4->pc & AM,(offset *4)+0x4000000,mem_mask); //logerror("'%s' (%08x): unmapped internal read from %08x mask %08x (PJDR)\n",tag(), m_pc & AM,(offset *4)+0x4000000,mem_mask);
return sh4->io->read_qword(SH3_PORT_J)<<24; return m_io->read_qword(SH3_PORT_J)<<24;
} }
if (mem_mask & 0x0000ffff) if (mem_mask & 0x0000ffff)
{ {
//logerror("'%s' (%08x): unmapped internal read from %08x mask %08x (PKDR)\n",sh4->device->tag(), sh4->pc & AM,(offset *4)+0x4000000,mem_mask); //logerror("'%s' (%08x): unmapped internal read from %08x mask %08x (PKDR)\n",tag(), m_pc & AM,(offset *4)+0x4000000,mem_mask);
return sh4->io->read_qword(SH3_PORT_K)<<8; return m_io->read_qword(SH3_PORT_K)<<8;
} }
} }
break; break;
@ -275,14 +270,14 @@ READ32_MEMBER( sh3_device::sh3_internal_r )
{ {
if (mem_mask & 0xffff0000) if (mem_mask & 0xffff0000)
{ {
//logerror("'%s' (%08x): unmapped internal read from %08x mask %08x (PLDR)\n",sh4->device->tag(), sh4->pc & AM,(offset *4)+0x4000000,mem_mask); //logerror("'%s' (%08x): unmapped internal read from %08x mask %08x (PLDR)\n",tag(), m_pc & AM,(offset *4)+0x4000000,mem_mask);
return sh4->io->read_qword(SH3_PORT_L)<<24; return m_io->read_qword(SH3_PORT_L)<<24;
} }
if (mem_mask & 0x0000ffff) if (mem_mask & 0x0000ffff)
{ {
logerror("'%s' (%08x): unmapped internal read from %08x mask %08x (SCPDR)\n",sh4->device->tag(), sh4->pc & AM,(offset *4)+0x4000000,mem_mask); logerror("'%s' (%08x): unmapped internal read from %08x mask %08x (SCPDR)\n",tag(), m_pc & AM,(offset *4)+0x4000000,mem_mask);
//return sh4->io->read_qword(SH3_PORT_K)<<8; //return m_io->read_qword(SH3_PORT_K)<<8;
} }
} }
break; break;
@ -292,14 +287,14 @@ READ32_MEMBER( sh3_device::sh3_internal_r )
{ {
if (mem_mask & 0xff000000) if (mem_mask & 0xff000000)
{ {
logerror("'%s' (%08x): SCIF internal read from %08x mask %08x (SCSMR2 - Serial Mode Register 2)\n",sh4->device->tag(), sh4->pc & AM,(offset *4)+0x4000000,mem_mask); logerror("'%s' (%08x): SCIF internal read from %08x mask %08x (SCSMR2 - Serial Mode Register 2)\n",tag(), m_pc & AM,(offset *4)+0x4000000,mem_mask);
return sh4->m_sh3internal_lower[offset]; return m_sh3internal_lower[offset];
} }
if (mem_mask & 0x0000ff00) if (mem_mask & 0x0000ff00)
{ {
logerror("'%s' (%08x): SCIF internal read from %08x mask %08x (SCBRR2 - Bit Rate Register 2)\n",sh4->device->tag(), sh4->pc & AM,(offset *4)+0x4000000,mem_mask); logerror("'%s' (%08x): SCIF internal read from %08x mask %08x (SCBRR2 - Bit Rate Register 2)\n",tag(), m_pc & AM,(offset *4)+0x4000000,mem_mask);
return sh4->m_sh3internal_lower[offset]; return m_sh3internal_lower[offset];
} }
} }
break; break;
@ -308,14 +303,14 @@ READ32_MEMBER( sh3_device::sh3_internal_r )
{ {
if (mem_mask & 0xff000000) if (mem_mask & 0xff000000)
{ {
logerror("'%s' (%08x): SCIF internal read from %08x mask %08x (SCSCR2 - Serial Control Register 2)\n",sh4->device->tag(), sh4->pc & AM,(offset *4)+0x4000000,mem_mask); logerror("'%s' (%08x): SCIF internal read from %08x mask %08x (SCSCR2 - Serial Control Register 2)\n",tag(), m_pc & AM,(offset *4)+0x4000000,mem_mask);
return sh4->m_sh3internal_lower[offset]; return m_sh3internal_lower[offset];
} }
if (mem_mask & 0x0000ff00) if (mem_mask & 0x0000ff00)
{ {
logerror("'%s' (%08x): SCIF internal read from %08x mask %08x (SCFTDR2 - Transmit FIFO Data Register 2)\n",sh4->device->tag(), sh4->pc & AM,(offset *4)+0x4000000,mem_mask); logerror("'%s' (%08x): SCIF internal read from %08x mask %08x (SCFTDR2 - Transmit FIFO Data Register 2)\n",tag(), m_pc & AM,(offset *4)+0x4000000,mem_mask);
return sh4->m_sh3internal_lower[offset]; return m_sh3internal_lower[offset];
} }
} }
break; break;
@ -324,14 +319,14 @@ READ32_MEMBER( sh3_device::sh3_internal_r )
{ {
if (mem_mask & 0xffff0000) if (mem_mask & 0xffff0000)
{ {
logerror("'%s' (%08x): SCIF internal read from %08x mask %08x (SCSSR2 - Serial Status Register 2)\n",sh4->device->tag(), sh4->pc & AM,(offset *4)+0x4000000,mem_mask); logerror("'%s' (%08x): SCIF internal read from %08x mask %08x (SCSSR2 - Serial Status Register 2)\n",tag(), m_pc & AM,(offset *4)+0x4000000,mem_mask);
return sh4->m_sh3internal_lower[offset]; return m_sh3internal_lower[offset];
} }
if (mem_mask & 0x0000ff00) if (mem_mask & 0x0000ff00)
{ {
logerror("'%s' (%08x): SCIF internal read from %08x mask %08x (SCFRDR2 - Receive FIFO Data Register 2)\n",sh4->device->tag(), sh4->pc & AM,(offset *4)+0x4000000,mem_mask); logerror("'%s' (%08x): SCIF internal read from %08x mask %08x (SCFRDR2 - Receive FIFO Data Register 2)\n",tag(), m_pc & AM,(offset *4)+0x4000000,mem_mask);
return sh4->m_sh3internal_lower[offset]; return m_sh3internal_lower[offset];
} }
} }
break; break;
@ -340,14 +335,14 @@ READ32_MEMBER( sh3_device::sh3_internal_r )
{ {
if (mem_mask & 0xff000000) if (mem_mask & 0xff000000)
{ {
logerror("'%s' (%08x): SCIF internal read from %08x mask %08x (SCFCR2 - Fifo Control Register 2)\n",sh4->device->tag(), sh4->pc & AM,(offset *4)+0x4000000,mem_mask); logerror("'%s' (%08x): SCIF internal read from %08x mask %08x (SCFCR2 - Fifo Control Register 2)\n",tag(), m_pc & AM,(offset *4)+0x4000000,mem_mask);
return sh4->m_sh3internal_lower[offset]; return m_sh3internal_lower[offset];
} }
if (mem_mask & 0x0000ffff) if (mem_mask & 0x0000ffff)
{ {
logerror("'%s' (%08x): SCIF internal read from %08x mask %08x (SCFDR2 - Fifo Data Count Register 2)\n",sh4->device->tag(), sh4->pc & AM,(offset *4)+0x4000000,mem_mask); logerror("'%s' (%08x): SCIF internal read from %08x mask %08x (SCFDR2 - Fifo Data Count Register 2)\n",tag(), m_pc & AM,(offset *4)+0x4000000,mem_mask);
return sh4->m_sh3internal_lower[offset]; return m_sh3internal_lower[offset];
} }
} }
break; break;
@ -356,7 +351,7 @@ READ32_MEMBER( sh3_device::sh3_internal_r )
default: default:
{ {
logerror("'%s' (%08x): unmapped internal read from %08x mask %08x\n", logerror("'%s' (%08x): unmapped internal read from %08x mask %08x\n",
sh4->device->tag(), sh4->pc & AM, tag(), m_pc & AM,
(offset *4)+0x4000000, (offset *4)+0x4000000,
mem_mask); mem_mask);
} }
@ -368,7 +363,7 @@ READ32_MEMBER( sh3_device::sh3_internal_r )
else else
{ {
logerror("'%s' (%08x): unmapped internal read from %08x mask %08x\n", logerror("'%s' (%08x): unmapped internal read from %08x mask %08x\n",
sh4->device->tag(), sh4->pc & AM, tag(), m_pc & AM,
(offset *4)+0x4000000, (offset *4)+0x4000000,
mem_mask); mem_mask);
} }
@ -378,36 +373,32 @@ READ32_MEMBER( sh3_device::sh3_internal_r )
/* Lower internal area */ /* Lower internal area */
WRITE32_MEMBER( sh3_device::sh3_internal_w ) WRITE32_MEMBER( sh3_base_device::sh3_internal_w )
{ {
sh4_state *sh4 = get_safe_token(this);
if (offset<0x1000) if (offset<0x1000)
{ {
//UINT32 old = sh4->m_sh3internal_lower[offset]; //UINT32 old = m_sh3internal_lower[offset];
COMBINE_DATA(&sh4->m_sh3internal_lower[offset]); COMBINE_DATA(&m_sh3internal_lower[offset]);
switch (offset) switch (offset)
{ {
case SH3_SAR0_ADDR: sh4_handle_sar0_addr_w(sh4,data,mem_mask); break; case SH3_SAR0_ADDR: sh4_handle_sar0_addr_w(data,mem_mask); break;
case SH3_SAR1_ADDR: sh4_handle_sar1_addr_w(sh4,data,mem_mask); break; case SH3_SAR1_ADDR: sh4_handle_sar1_addr_w(data,mem_mask); break;
case SH3_SAR2_ADDR: sh4_handle_sar2_addr_w(sh4,data,mem_mask); break; case SH3_SAR2_ADDR: sh4_handle_sar2_addr_w(data,mem_mask); break;
case SH3_SAR3_ADDR: sh4_handle_sar3_addr_w(sh4,data,mem_mask); break; case SH3_SAR3_ADDR: sh4_handle_sar3_addr_w(data,mem_mask); break;
case SH3_DAR0_ADDR: sh4_handle_dar0_addr_w(sh4,data,mem_mask); break; case SH3_DAR0_ADDR: sh4_handle_dar0_addr_w(data,mem_mask); break;
case SH3_DAR1_ADDR: sh4_handle_dar1_addr_w(sh4,data,mem_mask); break; case SH3_DAR1_ADDR: sh4_handle_dar1_addr_w(data,mem_mask); break;
case SH3_DAR2_ADDR: sh4_handle_dar2_addr_w(sh4,data,mem_mask); break; case SH3_DAR2_ADDR: sh4_handle_dar2_addr_w(data,mem_mask); break;
case SH3_DAR3_ADDR: sh4_handle_dar3_addr_w(sh4,data,mem_mask); break; case SH3_DAR3_ADDR: sh4_handle_dar3_addr_w(data,mem_mask); break;
case SH3_DMATCR0_ADDR: sh4_handle_dmatcr0_addr_w(sh4,data,mem_mask); break; case SH3_DMATCR0_ADDR: sh4_handle_dmatcr0_addr_w(data,mem_mask); break;
case SH3_DMATCR1_ADDR: sh4_handle_dmatcr1_addr_w(sh4,data,mem_mask); break; case SH3_DMATCR1_ADDR: sh4_handle_dmatcr1_addr_w(data,mem_mask); break;
case SH3_DMATCR2_ADDR: sh4_handle_dmatcr2_addr_w(sh4,data,mem_mask); break; case SH3_DMATCR2_ADDR: sh4_handle_dmatcr2_addr_w(data,mem_mask); break;
case SH3_DMATCR3_ADDR: sh4_handle_dmatcr3_addr_w(sh4,data,mem_mask); break; case SH3_DMATCR3_ADDR: sh4_handle_dmatcr3_addr_w(data,mem_mask); break;
case SH3_CHCR0_ADDR: sh4_handle_chcr0_addr_w(sh4,data,mem_mask); break; case SH3_CHCR0_ADDR: sh4_handle_chcr0_addr_w(data,mem_mask); break;
case SH3_CHCR1_ADDR: sh4_handle_chcr1_addr_w(sh4,data,mem_mask); break; case SH3_CHCR1_ADDR: sh4_handle_chcr1_addr_w(data,mem_mask); break;
case SH3_CHCR2_ADDR: sh4_handle_chcr2_addr_w(sh4,data,mem_mask); break; case SH3_CHCR2_ADDR: sh4_handle_chcr2_addr_w(data,mem_mask); break;
case SH3_CHCR3_ADDR: sh4_handle_chcr3_addr_w(sh4,data,mem_mask); break; case SH3_CHCR3_ADDR: sh4_handle_chcr3_addr_w(data,mem_mask); break;
case SH3_DMAOR_ADDR: sh4_handle_dmaor_addr_w(sh4,data>>16,mem_mask>>16); break; case SH3_DMAOR_ADDR: sh4_handle_dmaor_addr_w(data>>16,mem_mask>>16); break;
case IRR0_IRR1: case IRR0_IRR1:
@ -415,21 +406,21 @@ WRITE32_MEMBER( sh3_device::sh3_internal_w )
{ {
if (mem_mask & 0xff000000) if (mem_mask & 0xff000000)
{ {
logerror("'%s' (%08x): unmapped internal write to %08x = %08x & %08x (IRR0)\n",sh4->device->tag(), sh4->pc & AM,(offset *4)+0x4000000,data,mem_mask); logerror("'%s' (%08x): unmapped internal write to %08x = %08x & %08x (IRR0)\n",tag(), m_pc & AM,(offset *4)+0x4000000,data,mem_mask);
// not sure if this is how we should clear lines in this core... // not sure if this is how we should clear lines in this core...
if (!(data & 0x01000000)) sh4_set_irq_line(sh4, 0, CLEAR_LINE); if (!(data & 0x01000000)) execute_set_input(0, CLEAR_LINE);
if (!(data & 0x02000000)) sh4_set_irq_line(sh4, 1, CLEAR_LINE); if (!(data & 0x02000000)) execute_set_input(1, CLEAR_LINE);
if (!(data & 0x04000000)) sh4_set_irq_line(sh4, 2, CLEAR_LINE); if (!(data & 0x04000000)) execute_set_input(2, CLEAR_LINE);
if (!(data & 0x08000000)) sh4_set_irq_line(sh4, 3, CLEAR_LINE); if (!(data & 0x08000000)) execute_set_input(3, CLEAR_LINE);
} }
if (mem_mask & 0x0000ff00) if (mem_mask & 0x0000ff00)
{ {
logerror("'%s' (%08x): unmapped internal write to %08x = %08x & %08x (IRR1)\n",sh4->device->tag(), sh4->pc & AM,(offset *4)+0x4000000,data,mem_mask); logerror("'%s' (%08x): unmapped internal write to %08x = %08x & %08x (IRR1)\n",tag(), m_pc & AM,(offset *4)+0x4000000,data,mem_mask);
} }
if (mem_mask & 0x00ff00ff) if (mem_mask & 0x00ff00ff)
{ {
fatalerror("'%s' (%08x): unmapped internal write to %08x = %08x & %08x (IRR0/1 unused bits)\n",sh4->device->tag(), sh4->pc & AM,(offset *4)+0x4000000,data,mem_mask); fatalerror("'%s' (%08x): unmapped internal write to %08x = %08x & %08x (IRR0/1 unused bits)\n",tag(), m_pc & AM,(offset *4)+0x4000000,data,mem_mask);
} }
} }
} }
@ -439,19 +430,19 @@ WRITE32_MEMBER( sh3_device::sh3_internal_w )
{ {
if (mem_mask & 0xffff0000) if (mem_mask & 0xffff0000)
{ {
logerror("'%s' (%08x): unmapped internal write to %08x = %08x & %08x (PINTER)\n",sh4->device->tag(), sh4->pc & AM,(offset *4)+0x4000000,data,mem_mask); logerror("'%s' (%08x): unmapped internal write to %08x = %08x & %08x (PINTER)\n",tag(), m_pc & AM,(offset *4)+0x4000000,data,mem_mask);
} }
if (mem_mask & 0x0000ffff) if (mem_mask & 0x0000ffff)
{ {
data &= 0xffff; mem_mask &= 0xffff; data &= 0xffff; mem_mask &= 0xffff;
COMBINE_DATA(&sh4->SH4_IPRC); COMBINE_DATA(&m_SH4_IPRC);
logerror("'%s' (%08x): INTC internal write to %08x = %08x & %08x (IPRC)\n",sh4->device->tag(), sh4->pc & AM,(offset *4)+0x4000000,data,mem_mask); logerror("'%s' (%08x): INTC internal write to %08x = %08x & %08x (IPRC)\n",tag(), m_pc & AM,(offset *4)+0x4000000,data,mem_mask);
sh4->exception_priority[SH4_INTC_IRL0] = INTPRI((sh4->SH4_IPRC & 0x000f)>>0, SH4_INTC_IRL0); m_exception_priority[SH4_INTC_IRL0] = INTPRI((m_SH4_IPRC & 0x000f)>>0, SH4_INTC_IRL0);
sh4->exception_priority[SH4_INTC_IRL1] = INTPRI((sh4->SH4_IPRC & 0x00f0)>>4, SH4_INTC_IRL1); m_exception_priority[SH4_INTC_IRL1] = INTPRI((m_SH4_IPRC & 0x00f0)>>4, SH4_INTC_IRL1);
sh4->exception_priority[SH4_INTC_IRL2] = INTPRI((sh4->SH4_IPRC & 0x0f00)>>8, SH4_INTC_IRL2); m_exception_priority[SH4_INTC_IRL2] = INTPRI((m_SH4_IPRC & 0x0f00)>>8, SH4_INTC_IRL2);
sh4->exception_priority[SH4_INTC_IRL3] = INTPRI((sh4->SH4_IPRC & 0xf000)>>12,SH4_INTC_IRL3); m_exception_priority[SH4_INTC_IRL3] = INTPRI((m_SH4_IPRC & 0xf000)>>12,SH4_INTC_IRL3);
sh4_exception_recompute(sh4); sh4_exception_recompute();
} }
} }
break; break;
@ -460,12 +451,12 @@ WRITE32_MEMBER( sh3_device::sh3_internal_w )
{ {
if (mem_mask & 0xffff0000) if (mem_mask & 0xffff0000)
{ {
logerror("'%s' (%08x): unmapped internal write to %08x = %08x & %08x (PCCR)\n",sh4->device->tag(), sh4->pc & AM,(offset *4)+0x4000000,data,mem_mask); logerror("'%s' (%08x): unmapped internal write to %08x = %08x & %08x (PCCR)\n",tag(), m_pc & AM,(offset *4)+0x4000000,data,mem_mask);
} }
if (mem_mask & 0x0000ffff) if (mem_mask & 0x0000ffff)
{ {
logerror("'%s' (%08x): unmapped internal write to %08x = %08x & %08x (PDCR)\n",sh4->device->tag(), sh4->pc & AM,(offset *4)+0x4000000,data,mem_mask); logerror("'%s' (%08x): unmapped internal write to %08x = %08x & %08x (PDCR)\n",tag(), m_pc & AM,(offset *4)+0x4000000,data,mem_mask);
} }
} }
break; break;
@ -474,12 +465,12 @@ WRITE32_MEMBER( sh3_device::sh3_internal_w )
{ {
if (mem_mask & 0xffff0000) if (mem_mask & 0xffff0000)
{ {
logerror("'%s' (%08x): unmapped internal write to %08x = %08x & %08x (PECR)\n",sh4->device->tag(), sh4->pc & AM,(offset *4)+0x4000000,data,mem_mask); logerror("'%s' (%08x): unmapped internal write to %08x = %08x & %08x (PECR)\n",tag(), m_pc & AM,(offset *4)+0x4000000,data,mem_mask);
} }
if (mem_mask & 0x0000ffff) if (mem_mask & 0x0000ffff)
{ {
logerror("'%s' (%08x): unmapped internal write to %08x = %08x & %08x (PFCR)\n",sh4->device->tag(), sh4->pc & AM,(offset *4)+0x4000000,data,mem_mask); logerror("'%s' (%08x): unmapped internal write to %08x = %08x & %08x (PFCR)\n",tag(), m_pc & AM,(offset *4)+0x4000000,data,mem_mask);
} }
} }
break; break;
@ -489,12 +480,12 @@ WRITE32_MEMBER( sh3_device::sh3_internal_w )
{ {
if (mem_mask & 0xffff0000) if (mem_mask & 0xffff0000)
{ {
logerror("'%s' (%08x): unmapped internal write to %08x = %08x & %08x (PGCR)\n",sh4->device->tag(), sh4->pc & AM,(offset *4)+0x4000000,data,mem_mask); logerror("'%s' (%08x): unmapped internal write to %08x = %08x & %08x (PGCR)\n",tag(), m_pc & AM,(offset *4)+0x4000000,data,mem_mask);
} }
if (mem_mask & 0x0000ffff) if (mem_mask & 0x0000ffff)
{ {
logerror("'%s' (%08x): unmapped internal write to %08x = %08x & %08x (PHCR)\n",sh4->device->tag(), sh4->pc & AM,(offset *4)+0x4000000,data,mem_mask); logerror("'%s' (%08x): unmapped internal write to %08x = %08x & %08x (PHCR)\n",tag(), m_pc & AM,(offset *4)+0x4000000,data,mem_mask);
} }
} }
break; break;
@ -504,12 +495,12 @@ WRITE32_MEMBER( sh3_device::sh3_internal_w )
{ {
if (mem_mask & 0xffff0000) if (mem_mask & 0xffff0000)
{ {
logerror("'%s' (%08x): unmapped internal write to %08x = %08x & %08x (PJCR)\n",sh4->device->tag(), sh4->pc & AM,(offset *4)+0x4000000,data,mem_mask); logerror("'%s' (%08x): unmapped internal write to %08x = %08x & %08x (PJCR)\n",tag(), m_pc & AM,(offset *4)+0x4000000,data,mem_mask);
} }
if (mem_mask & 0x0000ffff) if (mem_mask & 0x0000ffff)
{ {
logerror("'%s' (%08x): unmapped internal write to %08x = %08x & %08x (PKCR)\n",sh4->device->tag(), sh4->pc & AM,(offset *4)+0x4000000,data,mem_mask); logerror("'%s' (%08x): unmapped internal write to %08x = %08x & %08x (PKCR)\n",tag(), m_pc & AM,(offset *4)+0x4000000,data,mem_mask);
} }
} }
break; break;
@ -519,12 +510,12 @@ WRITE32_MEMBER( sh3_device::sh3_internal_w )
{ {
if (mem_mask & 0xffff0000) if (mem_mask & 0xffff0000)
{ {
logerror("'%s' (%08x): unmapped internal write to %08x = %08x & %08x (PLCR)\n",sh4->device->tag(), sh4->pc & AM,(offset *4)+0x4000000,data,mem_mask); logerror("'%s' (%08x): unmapped internal write to %08x = %08x & %08x (PLCR)\n",tag(), m_pc & AM,(offset *4)+0x4000000,data,mem_mask);
} }
if (mem_mask & 0x0000ffff) if (mem_mask & 0x0000ffff)
{ {
logerror("'%s' (%08x): unmapped internal write to %08x = %08x & %08x (SCPCR)\n",sh4->device->tag(), sh4->pc & AM,(offset *4)+0x4000000,data,mem_mask); logerror("'%s' (%08x): unmapped internal write to %08x = %08x & %08x (SCPCR)\n",tag(), m_pc & AM,(offset *4)+0x4000000,data,mem_mask);
} }
} }
break; break;
@ -533,14 +524,14 @@ WRITE32_MEMBER( sh3_device::sh3_internal_w )
{ {
if (mem_mask & 0xffff0000) if (mem_mask & 0xffff0000)
{ {
sh4->io->write_qword(SH3_PORT_A, (data>>24)&0xff); m_io->write_qword(SH3_PORT_A, (data>>24)&0xff);
// logerror("'%s' (%08x): unmapped internal write to %08x = %08x & %08x (PADR)\n",sh4->device->tag(), sh4->pc & AM,(offset *4)+0x4000000,data,mem_mask); // logerror("'%s' (%08x): unmapped internal write to %08x = %08x & %08x (PADR)\n",tag(), m_pc & AM,(offset *4)+0x4000000,data,mem_mask);
} }
if (mem_mask & 0x0000ffff) if (mem_mask & 0x0000ffff)
{ {
sh4->io->write_qword(SH3_PORT_B, (data>>8)&0xff); m_io->write_qword(SH3_PORT_B, (data>>8)&0xff);
// logerror("'%s' (%08x): unmapped internal write to %08x = %08x & %08x (PBDR)\n",sh4->device->tag(), sh4->pc & AM,(offset *4)+0x4000000,data,mem_mask); // logerror("'%s' (%08x): unmapped internal write to %08x = %08x & %08x (PBDR)\n",tag(), m_pc & AM,(offset *4)+0x4000000,data,mem_mask);
} }
} }
break; break;
@ -549,14 +540,14 @@ WRITE32_MEMBER( sh3_device::sh3_internal_w )
{ {
if (mem_mask & 0xffff0000) if (mem_mask & 0xffff0000)
{ {
sh4->io->write_qword(SH3_PORT_C, (data>>24)&0xff); m_io->write_qword(SH3_PORT_C, (data>>24)&0xff);
// logerror("'%s' (%08x): unmapped internal write to %08x = %08x & %08x (PADR)\n",sh4->device->tag(), sh4->pc & AM,(offset *4)+0x4000000,data,mem_mask); // logerror("'%s' (%08x): unmapped internal write to %08x = %08x & %08x (PADR)\n",tag(), m_pc & AM,(offset *4)+0x4000000,data,mem_mask);
} }
if (mem_mask & 0x0000ffff) if (mem_mask & 0x0000ffff)
{ {
sh4->io->write_qword(SH3_PORT_D, (data>>8)&0xff); m_io->write_qword(SH3_PORT_D, (data>>8)&0xff);
// logerror("'%s' (%08x): unmapped internal write to %08x = %08x & %08x (PBDR)\n",sh4->device->tag(), sh4->pc & AM,(offset *4)+0x4000000,data,mem_mask); // logerror("'%s' (%08x): unmapped internal write to %08x = %08x & %08x (PBDR)\n",tag(), m_pc & AM,(offset *4)+0x4000000,data,mem_mask);
} }
} }
break; break;
@ -564,14 +555,14 @@ WRITE32_MEMBER( sh3_device::sh3_internal_w )
{ {
if (mem_mask & 0xffff0000) if (mem_mask & 0xffff0000)
{ {
sh4->io->write_qword(SH3_PORT_E, (data>>24)&0xff); m_io->write_qword(SH3_PORT_E, (data>>24)&0xff);
// logerror("'%s' (%08x): unmapped internal write to %08x = %08x & %08x (PEDR)\n",sh4->device->tag(), sh4->pc & AM,(offset *4)+0x4000000,data,mem_mask); // logerror("'%s' (%08x): unmapped internal write to %08x = %08x & %08x (PEDR)\n",tag(), m_pc & AM,(offset *4)+0x4000000,data,mem_mask);
} }
if (mem_mask & 0x0000ffff) if (mem_mask & 0x0000ffff)
{ {
sh4->io->write_qword(SH3_PORT_F, (data>>8)&0xff); m_io->write_qword(SH3_PORT_F, (data>>8)&0xff);
// logerror("'%s' (%08x): unmapped internal write to %08x = %08x & %08x (PFDR)\n",sh4->device->tag(), sh4->pc & AM,(offset *4)+0x4000000,data,mem_mask); // logerror("'%s' (%08x): unmapped internal write to %08x = %08x & %08x (PFDR)\n",tag(), m_pc & AM,(offset *4)+0x4000000,data,mem_mask);
} }
} }
break; break;
@ -580,14 +571,14 @@ WRITE32_MEMBER( sh3_device::sh3_internal_w )
{ {
if (mem_mask & 0xffff0000) if (mem_mask & 0xffff0000)
{ {
sh4->io->write_qword(SH3_PORT_G, (data>>24)&0xff); m_io->write_qword(SH3_PORT_G, (data>>24)&0xff);
// logerror("'%s' (%08x): unmapped internal write to %08x = %08x & %08x (PGDR)\n",sh4->device->tag(), sh4->pc & AM,(offset *4)+0x4000000,data,mem_mask); // logerror("'%s' (%08x): unmapped internal write to %08x = %08x & %08x (PGDR)\n",tag(), m_pc & AM,(offset *4)+0x4000000,data,mem_mask);
} }
if (mem_mask & 0x0000ffff) if (mem_mask & 0x0000ffff)
{ {
sh4->io->write_qword(SH3_PORT_H, (data>>8)&0xff); m_io->write_qword(SH3_PORT_H, (data>>8)&0xff);
// logerror("'%s' (%08x): unmapped internal write to %08x = %08x & %08x (PHDR)\n",sh4->device->tag(), sh4->pc & AM,(offset *4)+0x4000000,data,mem_mask); // logerror("'%s' (%08x): unmapped internal write to %08x = %08x & %08x (PHDR)\n",tag(), m_pc & AM,(offset *4)+0x4000000,data,mem_mask);
} }
} }
break; break;
@ -597,14 +588,14 @@ WRITE32_MEMBER( sh3_device::sh3_internal_w )
{ {
if (mem_mask & 0xffff0000) if (mem_mask & 0xffff0000)
{ {
sh4->io->write_qword(SH3_PORT_J, (data>>24)&0xff); m_io->write_qword(SH3_PORT_J, (data>>24)&0xff);
// logerror("'%s' (%08x): unmapped internal write to %08x = %08x & %08x (PJDR)\n",sh4->device->tag(), sh4->pc & AM,(offset *4)+0x4000000,data,mem_mask); // logerror("'%s' (%08x): unmapped internal write to %08x = %08x & %08x (PJDR)\n",tag(), m_pc & AM,(offset *4)+0x4000000,data,mem_mask);
} }
if (mem_mask & 0x0000ffff) if (mem_mask & 0x0000ffff)
{ {
sh4->io->write_qword(SH3_PORT_K, (data>>8)&0xff); m_io->write_qword(SH3_PORT_K, (data>>8)&0xff);
//logerror("'%s' (%08x): unmapped internal write to %08x = %08x & %08x (PKDR)\n",sh4->device->tag(), sh4->pc & AM,(offset *4)+0x4000000,data,mem_mask); //logerror("'%s' (%08x): unmapped internal write to %08x = %08x & %08x (PKDR)\n",tag(), m_pc & AM,(offset *4)+0x4000000,data,mem_mask);
} }
} }
break; break;
@ -613,12 +604,12 @@ WRITE32_MEMBER( sh3_device::sh3_internal_w )
{ {
if (mem_mask & 0xff000000) if (mem_mask & 0xff000000)
{ {
logerror("'%s' (%08x): SCIF internal write to %08x = %08x & %08x (SCSMR2 - Serial Mode Register 2)\n",sh4->device->tag(), sh4->pc & AM,(offset *4)+0x4000000,data,mem_mask); logerror("'%s' (%08x): SCIF internal write to %08x = %08x & %08x (SCSMR2 - Serial Mode Register 2)\n",tag(), m_pc & AM,(offset *4)+0x4000000,data,mem_mask);
} }
if (mem_mask & 0x0000ff00) if (mem_mask & 0x0000ff00)
{ {
logerror("'%s' (%08x): SCIF internal write to %08x = %08x & %08x (SCBRR2 - Bit Rate Register 2)\n",sh4->device->tag(), sh4->pc & AM,(offset *4)+0x4000000,data,mem_mask); logerror("'%s' (%08x): SCIF internal write to %08x = %08x & %08x (SCBRR2 - Bit Rate Register 2)\n",tag(), m_pc & AM,(offset *4)+0x4000000,data,mem_mask);
} }
} }
break; break;
@ -627,12 +618,12 @@ WRITE32_MEMBER( sh3_device::sh3_internal_w )
{ {
if (mem_mask & 0xff000000) if (mem_mask & 0xff000000)
{ {
logerror("'%s' (%08x): SCIF internal write to %08x = %08x & %08x (SCSCR2 - Serial Control Register 2)\n",sh4->device->tag(), sh4->pc & AM,(offset *4)+0x4000000,data,mem_mask); logerror("'%s' (%08x): SCIF internal write to %08x = %08x & %08x (SCSCR2 - Serial Control Register 2)\n",tag(), m_pc & AM,(offset *4)+0x4000000,data,mem_mask);
} }
if (mem_mask & 0x0000ff00) if (mem_mask & 0x0000ff00)
{ {
logerror("'%s' (%08x): SCIF internal write to %08x = %08x & %08x (SCFTDR2 - Transmit FIFO Data Register 2)\n",sh4->device->tag(), sh4->pc & AM,(offset *4)+0x4000000,data,mem_mask); logerror("'%s' (%08x): SCIF internal write to %08x = %08x & %08x (SCFTDR2 - Transmit FIFO Data Register 2)\n",tag(), m_pc & AM,(offset *4)+0x4000000,data,mem_mask);
} }
} }
break; break;
@ -641,12 +632,12 @@ WRITE32_MEMBER( sh3_device::sh3_internal_w )
{ {
if (mem_mask & 0xffff0000) if (mem_mask & 0xffff0000)
{ {
logerror("'%s' (%08x): SCIF internal write to %08x = %08x & %08x (SCSSR2 - Serial Status Register 2)\n",sh4->device->tag(), sh4->pc & AM,(offset *4)+0x4000000,data,mem_mask); logerror("'%s' (%08x): SCIF internal write to %08x = %08x & %08x (SCSSR2 - Serial Status Register 2)\n",tag(), m_pc & AM,(offset *4)+0x4000000,data,mem_mask);
} }
if (mem_mask & 0x0000ff00) if (mem_mask & 0x0000ff00)
{ {
logerror("'%s' (%08x): SCIF internal write to %08x = %08x & %08x (SCFRDR2 - Receive FIFO Data Register 2)\n",sh4->device->tag(), sh4->pc & AM,(offset *4)+0x4000000,data,mem_mask); logerror("'%s' (%08x): SCIF internal write to %08x = %08x & %08x (SCFRDR2 - Receive FIFO Data Register 2)\n",tag(), m_pc & AM,(offset *4)+0x4000000,data,mem_mask);
} }
} }
break; break;
@ -655,12 +646,12 @@ WRITE32_MEMBER( sh3_device::sh3_internal_w )
{ {
if (mem_mask & 0xff000000) if (mem_mask & 0xff000000)
{ {
logerror("'%s' (%08x): SCIF internal write to %08x = %08x & %08x (SCFCR2 - Fifo Control Register 2)\n",sh4->device->tag(), sh4->pc & AM,(offset *4)+0x4000000,data,mem_mask); logerror("'%s' (%08x): SCIF internal write to %08x = %08x & %08x (SCFCR2 - Fifo Control Register 2)\n",tag(), m_pc & AM,(offset *4)+0x4000000,data,mem_mask);
} }
if (mem_mask & 0x0000ffff) if (mem_mask & 0x0000ffff)
{ {
logerror("'%s' (%08x): SCIF internal write to %08x = %08x & %08x (SCFDR2 - Fifo Data Count Register 2)\n",sh4->device->tag(), sh4->pc & AM,(offset *4)+0x4000000,data,mem_mask); logerror("'%s' (%08x): SCIF internal write to %08x = %08x & %08x (SCFDR2 - Fifo Data Count Register 2)\n",tag(), m_pc & AM,(offset *4)+0x4000000,data,mem_mask);
} }
} }
break; break;
@ -668,7 +659,7 @@ WRITE32_MEMBER( sh3_device::sh3_internal_w )
default: default:
{ {
logerror("'%s' (%08x): unmapped internal write to %08x = %08x & %08x\n", logerror("'%s' (%08x): unmapped internal write to %08x = %08x & %08x\n",
sh4->device->tag(), sh4->pc & AM, tag(), m_pc & AM,
(offset *4)+0x4000000, (offset *4)+0x4000000,
data, data,
mem_mask); mem_mask);
@ -680,7 +671,7 @@ WRITE32_MEMBER( sh3_device::sh3_internal_w )
else else
{ {
logerror("'%s' (%08x): unmapped internal write to %08x = %08x & %08x\n", logerror("'%s' (%08x): unmapped internal write to %08x = %08x & %08x\n",
sh4->device->tag(), sh4->pc & AM, tag(), m_pc & AM,
(offset *4)+0x4000000, (offset *4)+0x4000000,
data, data,
mem_mask); mem_mask);

3592
src/emu/cpu/sh4/sh4.c
View File

File diff suppressed because it is too large Load Diff

659
src/emu/cpu/sh4/sh4.h
View File

@ -111,20 +111,6 @@ enum
SH4_IOPORT_SCIF=8*4 SH4_IOPORT_SCIF=8*4
}; };
struct sh4_config
{
int md2;
int md1;
int md0;
int md6;
int md4;
int md3;
int md5;
int md7;
int md8;
int clock;
};
struct sh4_device_dma struct sh4_device_dma
{ {
UINT32 length; UINT32 length;
@ -147,69 +133,644 @@ struct sh4_ddt_dma
typedef void (*sh4_ftcsr_callback)(UINT32); typedef void (*sh4_ftcsr_callback)(UINT32);
CPU_GET_INFO( sh3 );
class sh3_device : public legacy_cpu_device #define MCFG_SH4_MD0(_md0) \
sh34_base_device::set_md0(*device, _md0);
#define MCFG_SH4_MD1(_md1) \
sh34_base_device::set_md1(*device, _md1);
#define MCFG_SH4_MD2(_md2) \
sh34_base_device::set_md2(*device, _md2);
#define MCFG_SH4_MD3(_md3) \
sh34_base_device::set_md3(*device, _md3);
#define MCFG_SH4_MD4(_md4) \
sh34_base_device::set_md4(*device, _md4);
#define MCFG_SH4_MD5(_md5) \
sh34_base_device::set_md5(*device, _md5);
#define MCFG_SH4_MD6(_md6) \
sh34_base_device::set_md6(*device, _md6);
#define MCFG_SH4_MD7(_md7) \
sh34_base_device::set_md7(*device, _md7);
#define MCFG_SH4_MD8(_md8) \
sh34_base_device::set_md8(*device, _md8);
#define MCFG_SH4_CLOCK(_clock) \
sh34_base_device::set_sh4_clock(*device, _clock);
class sh34_base_device : public cpu_device
{ {
public: public:
sh3_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, UINT32 clock); // construction/destruction
sh3_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, UINT32 clock, cpu_get_info_func info); sh34_base_device(const machine_config &mconfig, device_type type, const char *name, const char *tag, device_t *owner, UINT32 clock, const char *shortname, endianness_t endianness, address_map_constructor internal);
static void set_md0(device_t &device, int md0) { downcast<sh34_base_device &>(device).c_md0 = md0; }
static void set_md1(device_t &device, int md0) { downcast<sh34_base_device &>(device).c_md1 = md0; }
static void set_md2(device_t &device, int md0) { downcast<sh34_base_device &>(device).c_md2 = md0; }
static void set_md3(device_t &device, int md0) { downcast<sh34_base_device &>(device).c_md3 = md0; }
static void set_md4(device_t &device, int md0) { downcast<sh34_base_device &>(device).c_md4 = md0; }
static void set_md5(device_t &device, int md0) { downcast<sh34_base_device &>(device).c_md5 = md0; }
static void set_md6(device_t &device, int md0) { downcast<sh34_base_device &>(device).c_md6 = md0; }
static void set_md7(device_t &device, int md0) { downcast<sh34_base_device &>(device).c_md7 = md0; }
static void set_md8(device_t &device, int md0) { downcast<sh34_base_device &>(device).c_md8 = md0; }
static void set_sh4_clock(device_t &device, int clock) { downcast<sh34_base_device &>(device).c_clock = clock; }
TIMER_CALLBACK_MEMBER( sh4_refresh_timer_callback );
TIMER_CALLBACK_MEMBER( sh4_rtc_timer_callback );
TIMER_CALLBACK_MEMBER( sh4_timer_callback );
TIMER_CALLBACK_MEMBER( sh4_dmac_callback );
void sh4_set_frt_input(int state);
void sh4_set_irln_input(int value);
void sh4_set_ftcsr_callback(sh4_ftcsr_callback callback);
int sh4_dma_data(struct sh4_device_dma *s);
void sh4_dma_ddt(struct sh4_ddt_dma *s);
protected:
// device-level overrides
virtual void device_start();
virtual void device_reset();
// device_execute_interface overrides
virtual UINT32 execute_min_cycles() const { return 1; }
virtual UINT32 execute_max_cycles() const { return 4; }
virtual UINT32 execute_input_lines() const { return 5; }
virtual void execute_run();
virtual void execute_set_input(int inputnum, int state);
// device_memory_interface overrides
virtual const address_space_config *memory_space_config(address_spacenum spacenum = AS_0) const { return (spacenum == AS_PROGRAM) ? &m_program_config : ((spacenum == AS_IO) ? &m_io_config : NULL); }
// device_state_interface overrides
virtual void state_import(const device_state_entry &entry);
virtual void state_export(const device_state_entry &entry);
virtual void state_string_export(const device_state_entry &entry, astring &string);
// device_disasm_interface overrides
virtual UINT32 disasm_min_opcode_bytes() const { return 2; }
virtual UINT32 disasm_max_opcode_bytes() const { return 2; }
virtual offs_t disasm_disassemble(char *buffer, offs_t pc, const UINT8 *oprom, const UINT8 *opram, UINT32 options);
protected:
address_space_config m_program_config;
address_space_config m_io_config;
int c_md2;
int c_md1;
int c_md0;
int c_md6;
int c_md4;
int c_md3;
int c_md5;
int c_md7;
int c_md8;
int c_clock;
UINT32 m_ppc;
UINT32 m_pc;
UINT32 m_spc;
UINT32 m_pr;
UINT32 m_sr;
UINT32 m_ssr;
UINT32 m_gbr;
UINT32 m_vbr;
UINT32 m_mach;
UINT32 m_macl;
UINT32 m_r[16];
UINT32 m_rbnk[2][8];
UINT32 m_sgr;
UINT32 m_fr[16];
UINT32 m_xf[16];
UINT32 m_ea;
UINT32 m_delay;
UINT32 m_cpu_off;
UINT32 m_pending_irq;
UINT32 m_test_irq;
UINT32 m_fpscr;
UINT32 m_fpul;
UINT32 m_dbr;
UINT32 m_exception_priority[128];
int m_exception_requesting[128];
INT8 m_irq_line_state[17];
address_space *m_internal;
address_space *m_program;
direct_read_data *m_direct;
address_space *m_io;
// sh4 internal
UINT32 m_m[16384];
// timer regs handled manually for reuse
UINT32 m_SH4_TSTR;
UINT32 m_SH4_TCNT0;
UINT32 m_SH4_TCNT1;
UINT32 m_SH4_TCNT2;
UINT32 m_SH4_TCR0;
UINT32 m_SH4_TCR1;
UINT32 m_SH4_TCR2;
UINT32 m_SH4_TCOR0;
UINT32 m_SH4_TCOR1;
UINT32 m_SH4_TCOR2;
UINT32 m_SH4_TOCR;
UINT32 m_SH4_TCPR2;
// INTC regs
UINT32 m_SH4_IPRA;
UINT32 m_SH4_IPRC;
// DMAC regs
UINT32 m_SH4_SAR0;
UINT32 m_SH4_SAR1;
UINT32 m_SH4_SAR2;
UINT32 m_SH4_SAR3;
UINT32 m_SH4_DAR0;
UINT32 m_SH4_DAR1;
UINT32 m_SH4_DAR2;
UINT32 m_SH4_DAR3;
UINT32 m_SH4_CHCR0;
UINT32 m_SH4_CHCR1;
UINT32 m_SH4_CHCR2;
UINT32 m_SH4_CHCR3;
UINT32 m_SH4_DMATCR0;
UINT32 m_SH4_DMATCR1;
UINT32 m_SH4_DMATCR2;
UINT32 m_SH4_DMATCR3;
UINT32 m_SH4_DMAOR;
INT8 m_nmi_line_state;
UINT8 m_sleep_mode;
int m_frt_input;
int m_irln;
int m_internal_irq_level;
int m_internal_irq_vector;
emu_timer *m_dma_timer[4];
emu_timer *m_refresh_timer;
emu_timer *m_rtc_timer;
emu_timer *m_timer[3];
UINT32 m_refresh_timer_base;
int m_dma_timer_active[4];
UINT32 m_dma_source[4];
UINT32 m_dma_destination[4];
UINT32 m_dma_count[4];
int m_dma_wordsize[4];
int m_dma_source_increment[4];
int m_dma_destination_increment[4];
int m_dma_mode[4];
int m_sh4_icount;
int m_is_slave;
int m_cpu_clock;
int m_bus_clock;
int m_pm_clock;
int m_fpu_sz;
int m_fpu_pr;
int m_ioport16_pullup;
int m_ioport16_direction;
int m_ioport4_pullup;
int m_ioport4_direction;
void (*m_ftcsr_read_callback)(UINT32 data);
/* This MMU simulation is good for the simple remap used on Naomi GD-ROM SQ access *ONLY* */
UINT32 m_sh4_tlb_address[64];
UINT32 m_sh4_tlb_data[64];
UINT8 m_sh4_mmu_enabled;
int m_cpu_type;
// sh3 internal
UINT32 m_sh3internal_upper[0x3000/4];
UINT32 m_sh3internal_lower[0x1000];
UINT64 m_debugger_temp;
typedef void (sh34_base_device::*sh4ophandler)(const UINT16);
static sh4ophandler s_master_ophandler_table[0x10000];
static const sh4ophandler s_op1111_0x13_handlers[16];
static const sh4ophandler s_op1000_handler[16];
static const sh4ophandler s_op1100_handler[16];
static const sh4ophandler s_op0000_handlers[256];
static const sh4ophandler s_op0100_handlers[256];
static const sh4ophandler s_upper4bits[256];
inline void sh4_check_pending_irq(const char *message) // look for highest priority active exception and handle it
{
int a,irq,z;
irq = 0;
z = -1;
for (a=0;a <= SH4_INTC_ROVI;a++)
{
if (m_exception_requesting[a])
{
if ((int)m_exception_priority[a] > z)
{
z = m_exception_priority[a];
irq = a;
}
}
}
if (z >= 0)
{
sh4_exception(message, irq);
}
}
void TODO(const UINT16 opcode);
void WB(offs_t A, UINT8 V);
void WW(offs_t A, UINT16 V);
void WL(offs_t A, UINT32 V);
void ADD(const UINT16 opcode);
void ADDI(const UINT16 opcode);
void ADDC(const UINT16 opcode);
void ADDV(const UINT16 opcode);
void AND(const UINT16 opcode);
void ANDI(const UINT16 opcode);
void ANDM(const UINT16 opcode);
void BF(const UINT16 opcode);
void BFS(const UINT16 opcode);
void BRA(const UINT16 opcode);
void BRAF(const UINT16 opcode);
void BSR(const UINT16 opcode);
void BSRF(const UINT16 opcode);
void BT(const UINT16 opcode);
void BTS(const UINT16 opcode);
void CLRMAC(const UINT16 opcode);
void CLRT(const UINT16 opcode);
void CMPEQ(const UINT16 opcode);
void CMPGE(const UINT16 opcode);
void CMPGT(const UINT16 opcode);
void CMPHI(const UINT16 opcode);
void CMPHS(const UINT16 opcode);
void CMPPL(const UINT16 opcode);
void CMPPZ(const UINT16 opcode);
void CMPSTR(const UINT16 opcode);
void CMPIM(const UINT16 opcode);
void DIV0S(const UINT16 opcode);
void DIV0U(const UINT16 opcode);
void DIV1(const UINT16 opcode);
void DMULS(const UINT16 opcode);
void DMULU(const UINT16 opcode);
void DT(const UINT16 opcode);
void EXTSB(const UINT16 opcode);
void EXTSW(const UINT16 opcode);
void EXTUB(const UINT16 opcode);
void EXTUW(const UINT16 opcode);
void JMP(const UINT16 opcode);
void JSR(const UINT16 opcode);
void LDCSR(const UINT16 opcode);
void LDCGBR(const UINT16 opcode);
void LDCVBR(const UINT16 opcode);
void LDCMSR(const UINT16 opcode);
void LDCMGBR(const UINT16 opcode);
void LDCMVBR(const UINT16 opcode);
void LDSMACH(const UINT16 opcode);
void LDSMACL(const UINT16 opcode);
void LDSPR(const UINT16 opcode);
void LDSMMACH(const UINT16 opcode);
void LDSMMACL(const UINT16 opcode);
void LDSMPR(const UINT16 opcode);
void MAC_L(const UINT16 opcode);
void MAC_W(const UINT16 opcode);
void MOV(const UINT16 opcode);
void MOVBS(const UINT16 opcode);
void MOVWS(const UINT16 opcode);
void MOVLS(const UINT16 opcode);
void MOVBL(const UINT16 opcode);
void MOVWL(const UINT16 opcode);
void MOVLL(const UINT16 opcode);
void MOVBM(const UINT16 opcode);
void MOVWM(const UINT16 opcode);
void MOVLM(const UINT16 opcode);
void MOVBP(const UINT16 opcode);
void MOVWP(const UINT16 opcode);
void MOVLP(const UINT16 opcode);
void MOVBS0(const UINT16 opcode);
void MOVWS0(const UINT16 opcode);
void MOVLS0(const UINT16 opcode);
void MOVBL0(const UINT16 opcode);
void MOVWL0(const UINT16 opcode);
void MOVLL0(const UINT16 opcode);
void MOVI(const UINT16 opcode);
void MOVWI(const UINT16 opcode);
void MOVLI(const UINT16 opcode);
void MOVBLG(const UINT16 opcode);
void MOVWLG(const UINT16 opcode);
void MOVLLG(const UINT16 opcode);
void MOVBSG(const UINT16 opcode);
void MOVWSG(const UINT16 opcode);
void MOVLSG(const UINT16 opcode);
void MOVBS4(const UINT16 opcode);
void MOVWS4(const UINT16 opcode);
void MOVLS4(const UINT16 opcode);
void MOVBL4(const UINT16 opcode);
void MOVWL4(const UINT16 opcode);
void MOVLL4(const UINT16 opcode);
void MOVA(const UINT16 opcode);
void MOVT(const UINT16 opcode);
void MULL(const UINT16 opcode);
void MULS(const UINT16 opcode);
void MULU(const UINT16 opcode);
void NEG(const UINT16 opcode);
void NEGC(const UINT16 opcode);
void NOP(const UINT16 opcode);
void NOT(const UINT16 opcode);
void OR(const UINT16 opcode);
void ORI(const UINT16 opcode);
void ORM(const UINT16 opcode);
void ROTCL(const UINT16 opcode);
void ROTCR(const UINT16 opcode);
void ROTL(const UINT16 opcode);
void ROTR(const UINT16 opcode);
void RTE(const UINT16 opcode);
void RTS(const UINT16 opcode);
void SETT(const UINT16 opcode);
void SHAL(const UINT16 opcode);
void SHAR(const UINT16 opcode);
void SHLL(const UINT16 opcode);
void SHLL2(const UINT16 opcode);
void SHLL8(const UINT16 opcode);
void SHLL16(const UINT16 opcode);
void SHLR(const UINT16 opcode);
void SHLR2(const UINT16 opcode);
void SHLR8(const UINT16 opcode);
void SHLR16(const UINT16 opcode);
void SLEEP(const UINT16 opcode);
void STCSR(const UINT16 opcode);
void STCGBR(const UINT16 opcode);
void STCVBR(const UINT16 opcode);
void STCMSR(const UINT16 opcode);
void STCMGBR(const UINT16 opcode);
void STCMVBR(const UINT16 opcode);
void STSMACH(const UINT16 opcode);
void STSMACL(const UINT16 opcode);
void STSPR(const UINT16 opcode);
void STSMMACH(const UINT16 opcode);
void STSMMACL(const UINT16 opcode);
void STSMPR(const UINT16 opcode);
void SUB(const UINT16 opcode);
void SUBC(const UINT16 opcode);
void SUBV(const UINT16 opcode);
void SWAPB(const UINT16 opcode);
void SWAPW(const UINT16 opcode);
void TAS(const UINT16 opcode);
void TRAPA(const UINT16 opcode);
void TST(const UINT16 opcode);
void TSTI(const UINT16 opcode);
void TSTM(const UINT16 opcode);
void XOR(const UINT16 opcode);
void XORI(const UINT16 opcode);
void XORM(const UINT16 opcode);
void XTRCT(const UINT16 opcode);
void STCSSR(const UINT16 opcode);
void STCSPC(const UINT16 opcode);
void STCSGR(const UINT16 opcode);
void STSFPUL(const UINT16 opcode);
void STSFPSCR(const UINT16 opcode);
void STCDBR(const UINT16 opcode);
void STCRBANK(const UINT16 opcode);
void STCMRBANK(const UINT16 opcode);
void MOVCAL(const UINT16 opcode);
void CLRS(const UINT16 opcode);
void SETS(const UINT16 opcode);
void STCMSGR(const UINT16 opcode);
void STSMFPUL(const UINT16 opcode);
void STSMFPSCR(const UINT16 opcode);
void STCMDBR(const UINT16 opcode);
void STCMSSR(const UINT16 opcode);
void STCMSPC(const UINT16 opcode);
void LDSMFPUL(const UINT16 opcode);
void LDSMFPSCR(const UINT16 opcode);
void LDCMDBR(const UINT16 opcode);
void LDCMRBANK(const UINT16 opcode);
void LDCMSSR(const UINT16 opcode);
void LDCMSPC(const UINT16 opcode);
void LDSFPUL(const UINT16 opcode);
void LDSFPSCR(const UINT16 opcode);
void LDCDBR(const UINT16 opcode);
void SHAD(const UINT16 opcode);
void SHLD(const UINT16 opcode);
void LDCRBANK(const UINT16 opcode);
void LDCSSR(const UINT16 opcode);
void LDCSPC(const UINT16 opcode);
void PREFM(const UINT16 opcode);
void FMOVMRIFR(const UINT16 opcode);
void FMOVFRMR(const UINT16 opcode);
void FMOVFRMDR(const UINT16 opcode);
void FMOVFRS0(const UINT16 opcode);
void FMOVS0FR(const UINT16 opcode);
void FMOVMRFR(const UINT16 opcode);
void FMOVFR(const UINT16 opcode);
void FLDI1(const UINT16 opcode);
void FLDI0(const UINT16 opcode);
void FLDS(const UINT16 opcode);
void FSTS(const UINT16 opcode);
void FRCHG();
void FSCHG();
void FTRC(const UINT16 opcode);
void FLOAT(const UINT16 opcode);
void FNEG(const UINT16 opcode);
void FABS(const UINT16 opcode);
void FCMP_EQ(const UINT16 opcode);
void FCMP_GT(const UINT16 opcode);
void FCNVDS(const UINT16 opcode);
void FCNVSD(const UINT16 opcode);
void FADD(const UINT16 opcode);
void FSUB(const UINT16 opcode);
void FMUL(const UINT16 opcode);
void FDIV(const UINT16 opcode);
void FMAC(const UINT16 opcode);
void FSQRT(const UINT16 opcode);
void FSRRA(const UINT16 opcode);
void FSSCA(const UINT16 opcode);
void FIPR(const UINT16 opcode);
void FTRV(const UINT16 opcode);
void op1111_0xf13(const UINT16 opcode);
void dbreak(const UINT16 opcode);
void op1111_0x13(UINT16 opcode);
UINT8 RB(offs_t A);
UINT16 RW(offs_t A);
UINT32 RL(offs_t A);
void sh4_change_register_bank(int to);
void sh4_swap_fp_registers();
void sh4_swap_fp_couples();
void sh4_syncronize_register_bank(int to);
void sh4_default_exception_priorities();
void sh4_exception_recompute();
void sh4_exception_request(int exception);
void sh4_exception_unrequest(int exception);
void sh4_exception_checkunrequest(int exception);
void sh4_exception(const char *message, int exception);
UINT32 compute_ticks_refresh_timer(emu_timer *timer, int hertz, int base, int divisor);
void sh4_refresh_timer_recompute();
void increment_rtc_time(int mode);
void sh4_dmac_nmi();
void sh4_handler_ipra_w(UINT32 data, UINT32 mem_mask);
UINT32 sh4_getsqremap(UINT32 address);
void sh4_build_optable();
void sh4_parse_configuration();
void sh4_timer_recompute(int which);
UINT32 sh4_handle_tcnt0_addr_r(UINT32 mem_mask);
UINT32 sh4_handle_tcnt1_addr_r(UINT32 mem_mask);
UINT32 sh4_handle_tcnt2_addr_r(UINT32 mem_mask);
UINT32 sh4_handle_tcor0_addr_r(UINT32 mem_mask);
UINT32 sh4_handle_tcor1_addr_r(UINT32 mem_mask);
UINT32 sh4_handle_tcor2_addr_r(UINT32 mem_mask);
UINT32 sh4_handle_tcr0_addr_r(UINT32 mem_mask);
UINT32 sh4_handle_tcr1_addr_r(UINT32 mem_mask);
UINT32 sh4_handle_tcr2_addr_r(UINT32 mem_mask);
UINT32 sh4_handle_tstr_addr_r(UINT32 mem_mask);
UINT32 sh4_handle_tocr_addr_r(UINT32 mem_mask);
UINT32 sh4_handle_tcpr2_addr_r(UINT32 mem_mask);
void sh4_handle_tstr_addr_w(UINT32 data, UINT32 mem_mask);
void sh4_handle_tcr0_addr_w(UINT32 data, UINT32 mem_mask);
void sh4_handle_tcr1_addr_w(UINT32 data, UINT32 mem_mask);
void sh4_handle_tcr2_addr_w(UINT32 data, UINT32 mem_mask);
void sh4_handle_tcor0_addr_w(UINT32 data, UINT32 mem_mask);
void sh4_handle_tcor1_addr_w(UINT32 data, UINT32 mem_mask);
void sh4_handle_tcor2_addr_w(UINT32 data, UINT32 mem_mask);
void sh4_handle_tcnt0_addr_w(UINT32 data, UINT32 mem_mask);
void sh4_handle_tcnt1_addr_w(UINT32 data, UINT32 mem_mask);
void sh4_handle_tcnt2_addr_w(UINT32 data, UINT32 mem_mask);
void sh4_handle_tocr_addr_w(UINT32 data, UINT32 mem_mask);
void sh4_handle_tcpr2_addr_w(UINT32 data, UINT32 mem_mask);
int sh4_dma_transfer(int channel, int timermode, UINT32 chcr, UINT32 *sar, UINT32 *dar, UINT32 *dmatcr);
int sh4_dma_transfer_device(int channel, UINT32 chcr, UINT32 *sar, UINT32 *dar, UINT32 *dmatcr);
void sh4_dmac_check(int channel);
void sh4_handle_sar0_addr_w(UINT32 data, UINT32 mem_mask);
void sh4_handle_sar1_addr_w(UINT32 data, UINT32 mem_mask);
void sh4_handle_sar2_addr_w(UINT32 data, UINT32 mem_mask);
void sh4_handle_sar3_addr_w(UINT32 data, UINT32 mem_mask);
void sh4_handle_dar0_addr_w(UINT32 data, UINT32 mem_mask);
void sh4_handle_dar1_addr_w(UINT32 data, UINT32 mem_mask);
void sh4_handle_dar2_addr_w(UINT32 data, UINT32 mem_mask);
void sh4_handle_dar3_addr_w(UINT32 data, UINT32 mem_mask);
void sh4_handle_dmatcr0_addr_w(UINT32 data, UINT32 mem_mask);
void sh4_handle_dmatcr1_addr_w(UINT32 data, UINT32 mem_mask);
void sh4_handle_dmatcr2_addr_w(UINT32 data, UINT32 mem_mask);
void sh4_handle_dmatcr3_addr_w(UINT32 data, UINT32 mem_mask);
void sh4_handle_chcr0_addr_w(UINT32 data, UINT32 mem_mask);
void sh4_handle_chcr1_addr_w(UINT32 data, UINT32 mem_mask);
void sh4_handle_chcr2_addr_w(UINT32 data, UINT32 mem_mask);
void sh4_handle_chcr3_addr_w(UINT32 data, UINT32 mem_mask);
void sh4_handle_dmaor_addr_w(UINT32 data, UINT32 mem_mask);
UINT32 sh4_handle_sar0_addr_r(UINT32 mem_mask) { return m_SH4_SAR0; }
UINT32 sh4_handle_sar1_addr_r(UINT32 mem_mask) { return m_SH4_SAR1; }
UINT32 sh4_handle_sar2_addr_r(UINT32 mem_mask) { return m_SH4_SAR2; }
UINT32 sh4_handle_sar3_addr_r(UINT32 mem_mask) { return m_SH4_SAR3; }
UINT32 sh4_handle_dar0_addr_r(UINT32 mem_mask) { return m_SH4_DAR0; }
UINT32 sh4_handle_dar1_addr_r(UINT32 mem_mask) { return m_SH4_DAR1; }
UINT32 sh4_handle_dar2_addr_r(UINT32 mem_mask) { return m_SH4_DAR2; }
UINT32 sh4_handle_dar3_addr_r(UINT32 mem_mask) { return m_SH4_DAR3; }
UINT32 sh4_handle_dmatcr0_addr_r(UINT32 mem_mask) { return m_SH4_DMATCR0; }
UINT32 sh4_handle_dmatcr1_addr_r(UINT32 mem_mask) { return m_SH4_DMATCR1; }
UINT32 sh4_handle_dmatcr2_addr_r(UINT32 mem_mask) { return m_SH4_DMATCR2; }
UINT32 sh4_handle_dmatcr3_addr_r(UINT32 mem_mask) { return m_SH4_DMATCR3; }
UINT32 sh4_handle_chcr0_addr_r(UINT32 mem_mask) { return m_SH4_CHCR0; }
UINT32 sh4_handle_chcr1_addr_r(UINT32 mem_mask) { return m_SH4_CHCR1; }
UINT32 sh4_handle_chcr2_addr_r(UINT32 mem_mask) { return m_SH4_CHCR2; }
UINT32 sh4_handle_chcr3_addr_r(UINT32 mem_mask) { return m_SH4_CHCR3; }
UINT32 sh4_handle_dmaor_addr_r(UINT32 mem_mask) { return m_SH4_DMAOR; }
};
class sh3_base_device : public sh34_base_device
{
public:
// construction/destruction
sh3_base_device(const machine_config &mconfig, device_type type, const char *name, const char *tag, device_t *owner, UINT32 clock, const char *shortname, endianness_t endianness);
DECLARE_WRITE32_MEMBER( sh3_internal_w ); DECLARE_WRITE32_MEMBER( sh3_internal_w );
DECLARE_READ32_MEMBER( sh3_internal_r ); DECLARE_READ32_MEMBER( sh3_internal_r );
DECLARE_WRITE32_MEMBER( sh3_internal_high_w ); DECLARE_WRITE32_MEMBER( sh3_internal_high_w );
DECLARE_READ32_MEMBER( sh3_internal_high_r ); DECLARE_READ32_MEMBER( sh3_internal_high_r );
protected:
virtual void device_reset();
}; };
extern const device_type SH3LE;
CPU_GET_INFO( sh3be ); class sh4_base_device : public sh34_base_device
class sh3be_device : public sh3_device
{ {
public: public:
sh3be_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, UINT32 clock); // construction/destruction
}; sh4_base_device(const machine_config &mconfig, device_type type, const char *name, const char *tag, device_t *owner, UINT32 clock, const char *shortname, endianness_t endianness);
extern const device_type SH3BE;
CPU_GET_INFO( sh4 );
class sh4_device : public legacy_cpu_device
{
public:
sh4_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, UINT32 clock);
sh4_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, UINT32 clock, cpu_get_info_func info);
DECLARE_WRITE32_MEMBER( sh4_internal_w ); DECLARE_WRITE32_MEMBER( sh4_internal_w );
DECLARE_READ32_MEMBER( sh4_internal_r ); DECLARE_READ32_MEMBER( sh4_internal_r );
DECLARE_READ64_MEMBER( sh4_tlb_r ); DECLARE_READ64_MEMBER( sh4_tlb_r );
DECLARE_WRITE64_MEMBER( sh4_tlb_w ); DECLARE_WRITE64_MEMBER( sh4_tlb_w );
protected:
virtual void device_reset();
}; };
extern const device_type SH4LE;
CPU_GET_INFO( sh4be ); class sh3_device : public sh3_base_device
class sh4be_device : public sh4_device
{ {
public: public:
sh4be_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, UINT32 clock); sh3_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
}; };
class sh3be_device : public sh3_base_device
{
public:
sh3be_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
protected:
virtual void execute_run();
virtual offs_t disasm_disassemble(char *buffer, offs_t pc, const UINT8 *oprom, const UINT8 *opram, UINT32 options);
};
class sh4_device : public sh4_base_device
{
public:
sh4_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
};
class sh4be_device : public sh4_base_device
{
public:
sh4be_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
protected:
virtual void execute_run();
virtual offs_t disasm_disassemble(char *buffer, offs_t pc, const UINT8 *oprom, const UINT8 *opram, UINT32 options);
};
extern const device_type SH3LE;
extern const device_type SH3BE;
extern const device_type SH4LE;
extern const device_type SH4BE; extern const device_type SH4BE;
void sh4_set_frt_input(device_t *device, int state);
void sh4_set_irln_input(device_t *device, int value);
void sh4_set_ftcsr_callback(device_t *device, sh4_ftcsr_callback callback);
int sh4_dma_data(device_t *device, struct sh4_device_dma *s);
void sh4_dma_ddt(device_t *device, struct sh4_ddt_dma *s);
/*************************************************************************** /***************************************************************************
COMPILER-SPECIFIC OPTIONS COMPILER-SPECIFIC OPTIONS
***************************************************************************/ ***************************************************************************/

876
src/emu/cpu/sh4/sh4comn.c
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File diff suppressed because it is too large Load Diff

198
src/emu/cpu/sh4/sh4comn.h
View File

@ -35,141 +35,23 @@ class sh4_frontend;
#define NMIPRI() EXPPRI(3,0,16,SH4_INTC_NMI) #define NMIPRI() EXPPRI(3,0,16,SH4_INTC_NMI)
#define INTPRI(p,n) EXPPRI(4,2,p,n) #define INTPRI(p,n) EXPPRI(4,2,p,n)
#define FP_RS(r) sh4->fr[(r)] // binary representation of single precision floating point register r #define FP_RS(r) m_fr[(r)] // binary representation of single precision floating point register r
#define FP_RFS(r) *( (float *)(sh4->fr+(r)) ) // single precision floating point register r #define FP_RFS(r) *( (float *)(m_fr+(r)) ) // single precision floating point register r
#define FP_RFD(r) *( (double *)(sh4->fr+(r)) ) // double precision floating point register r #define FP_RFD(r) *( (double *)(m_fr+(r)) ) // double precision floating point register r
#define FP_XS(r) sh4->xf[(r)] // binary representation of extended single precision floating point register r #define FP_XS(r) m_xf[(r)] // binary representation of extended single precision floating point register r
#define FP_XFS(r) *( (float *)(sh4->xf+(r)) ) // single precision extended floating point register r #define FP_XFS(r) *( (float *)(m_xf+(r)) ) // single precision extended floating point register r
#define FP_XFD(r) *( (double *)(sh4->xf+(r)) ) // double precision extended floating point register r #define FP_XFD(r) *( (double *)(m_xf+(r)) ) // double precision extended floating point register r
#ifdef LSB_FIRST #ifdef LSB_FIRST
#define FP_RS2(r) sh4->fr[(r) ^ sh4->fpu_pr] #define FP_RS2(r) m_fr[(r) ^ m_fpu_pr]
#define FP_RFS2(r) *( (float *)(sh4->fr+((r) ^ sh4->fpu_pr)) ) #define FP_RFS2(r) *( (float *)(m_fr+((r) ^ m_fpu_pr)) )
#define FP_XS2(r) sh4->xf[(r) ^ sh4->fpu_pr] #define FP_XS2(r) m_xf[(r) ^ m_fpu_pr]
#define FP_XFS2(r) *( (float *)(sh4->xf+((r) ^ sh4->fpu_pr)) ) #define FP_XFS2(r) *( (float *)(m_xf+((r) ^ m_fpu_pr)) )
#endif #endif
#ifdef USE_SH4DRC
struct sh4_state struct sh4_state
{ {
UINT32 ppc;
UINT32 pc, spc;
UINT32 pr;
UINT32 sr, ssr;
UINT32 gbr, vbr;
UINT32 mach, macl;
UINT32 r[16], rbnk[2][8], sgr;
UINT32 fr[16], xf[16];
UINT32 ea;
UINT32 delay;
UINT32 cpu_off;
UINT32 pending_irq;
UINT32 test_irq;
UINT32 fpscr;
UINT32 fpul;
UINT32 dbr;
UINT32 exception_priority[128];
int exception_requesting[128];
INT8 irq_line_state[17];
device_irq_acknowledge_delegate irq_callback;
legacy_cpu_device *device;
address_space *internal;
address_space *program;
direct_read_data *direct;
address_space *io;
// sh4 internal
UINT32 m[16384];
// timer regs handled manually for reuse
UINT32 SH4_TSTR;
UINT32 SH4_TCNT0;
UINT32 SH4_TCNT1;
UINT32 SH4_TCNT2;
UINT32 SH4_TCR0;
UINT32 SH4_TCR1;
UINT32 SH4_TCR2;
UINT32 SH4_TCOR0;
UINT32 SH4_TCOR1;
UINT32 SH4_TCOR2;
UINT32 SH4_TOCR;
UINT32 SH4_TCPR2;
// INTC regs
UINT32 SH4_IPRA;
UINT32 SH4_IPRC;
// DMAC regs
UINT32 SH4_SAR0;
UINT32 SH4_SAR1;
UINT32 SH4_SAR2;
UINT32 SH4_SAR3;
UINT32 SH4_DAR0;
UINT32 SH4_DAR1;
UINT32 SH4_DAR2;
UINT32 SH4_DAR3;
UINT32 SH4_CHCR0;
UINT32 SH4_CHCR1;
UINT32 SH4_CHCR2;
UINT32 SH4_CHCR3;
UINT32 SH4_DMATCR0;
UINT32 SH4_DMATCR1;
UINT32 SH4_DMATCR2;
UINT32 SH4_DMATCR3;
UINT32 SH4_DMAOR;
INT8 nmi_line_state;
UINT8 sleep_mode;
int frt_input;
int irln;
int internal_irq_level;
int internal_irq_vector;
emu_timer *dma_timer[4];
emu_timer *refresh_timer;
emu_timer *rtc_timer;
emu_timer *timer[3];
UINT32 refresh_timer_base;
int dma_timer_active[4];
UINT32 dma_source[4];
UINT32 dma_destination[4];
UINT32 dma_count[4];
int dma_wordsize[4];
int dma_source_increment[4];
int dma_destination_increment[4];
int dma_mode[4];
int sh4_icount;
int is_slave;
int cpu_clock, bus_clock, pm_clock;
int fpu_sz, fpu_pr;
int ioport16_pullup, ioport16_direction;
int ioport4_pullup, ioport4_direction;
void (*ftcsr_read_callback)(UINT32 data);
/* This MMU simulation is good for the simple remap used on Naomi GD-ROM SQ access *ONLY* */
UINT32 sh4_tlb_address[64];
UINT32 sh4_tlb_data[64];
UINT8 sh4_mmu_enabled;
int cpu_type;
// sh3 internal
UINT32 m_sh3internal_upper[0x3000/4];
UINT32 m_sh3internal_lower[0x1000];
#ifdef USE_SH4DRC
int icount; int icount;
int pcfsel; // last pcflush entry set int pcfsel; // last pcflush entry set
@ -207,8 +89,8 @@ struct sh4_state
UINT32 prefadr; UINT32 prefadr;
UINT32 target; UINT32 target;
#endif
}; };
#endif
#ifdef USE_SH4DRC #ifdef USE_SH4DRC
class sh4_frontend : public drc_frontend class sh4_frontend : public drc_frontend
@ -231,22 +113,6 @@ private:
sh4_state &m_context; sh4_state &m_context;
}; };
INLINE sh4_state *get_safe_token(device_t *device)
{
assert(device != NULL);
assert(device->type() == SH3LE || device->type() == SH3BE ||
device->type() == SH4LE || device->type() == SH4BE );
return *(sh4_state **)downcast<legacy_cpu_device *>(device)->token();
}
#else
INLINE sh4_state *get_safe_token(device_t *device)
{
assert(device != NULL);
assert(device->type() == SH3LE || device->type() == SH3BE ||
device->type() == SH4LE || device->type() == SH4BE );
return (sh4_state *)downcast<legacy_cpu_device *>(device)->token();
}
#endif #endif
@ -302,45 +168,5 @@ enum
#define REGFLAG_SSR (1 << 10) #define REGFLAG_SSR (1 << 10)
#define REGFLAG_SPC (1 << 11) #define REGFLAG_SPC (1 << 11)
void sh4_exception_recompute(sh4_state *sh4); // checks if there is any interrupt with high enough priority
void sh4_exception_request(sh4_state *sh4, int exception); // start requesting an exception
void sh4_exception_unrequest(sh4_state *sh4, int exception); // stop requesting an exception
void sh4_exception_checkunrequest(sh4_state *sh4, int exception);
void sh4_exception(sh4_state *sh4, const char *message, int exception); // handle exception
void sh4_change_register_bank(sh4_state *sh4, int to);
void sh4_syncronize_register_bank(sh4_state *sh4, int to);
void sh4_swap_fp_registers(sh4_state *sh4);
void sh4_default_exception_priorities(sh4_state *sh4); // setup default priorities for exceptions
void sh4_parse_configuration(sh4_state *sh4, const struct sh4_config *conf);
void sh4_set_irq_line(sh4_state *sh4, int irqline, int state); // set state of external interrupt line
#ifdef LSB_FIRST
void sh4_swap_fp_couples(sh4_state *sh4);
#endif
void sh4_common_init(device_t *device);
UINT32 sh4_getsqremap(sh4_state *sh4, UINT32 address);
void sh4_handler_ipra_w(sh4_state *sh4, UINT32 data, UINT32 mem_mask);
INLINE void sh4_check_pending_irq(sh4_state *sh4, const char *message) // look for highest priority active exception and handle it
{
int a,irq,z;
irq = 0;
z = -1;
for (a=0;a <= SH4_INTC_ROVI;a++)
{
if (sh4->exception_requesting[a])
{
if ((int)sh4->exception_priority[a] > z)
{
z = sh4->exception_priority[a];
irq = a;
}
}
}
if (z >= 0)
{
sh4_exception(sh4, message, irq);
}
}
#endif /* __SH4COMN_H__ */ #endif /* __SH4COMN_H__ */

463
src/emu/cpu/sh4/sh4dmac.c
View File

@ -11,43 +11,42 @@ static const int dmasize[8] = { 8, 1, 2, 4, 32, 0, 0, 0 };
static const int sh3_dmasize[4] = { 1, 2, 4, 16 }; static const int sh3_dmasize[4] = { 1, 2, 4, 16 };
TIMER_CALLBACK( sh4_dmac_callback ) TIMER_CALLBACK_MEMBER( sh34_base_device::sh4_dmac_callback )
{ {
sh4_state *sh4 = (sh4_state *)ptr;
int channel = param; int channel = param;
LOG(("SH4 '%s': DMA %d complete\n", sh4->device->tag(), channel)); LOG(("SH4 '%s': DMA %d complete\n", tag(), channel));
sh4->dma_timer_active[channel] = 0; m_dma_timer_active[channel] = 0;
switch (channel) switch (channel)
{ {
case 0: case 0:
sh4->SH4_DMATCR0 = 0; m_SH4_DMATCR0 = 0;
sh4->SH4_CHCR0 |= CHCR_TE; m_SH4_CHCR0 |= CHCR_TE;
if (sh4->SH4_CHCR0 & CHCR_IE) if (m_SH4_CHCR0 & CHCR_IE)
sh4_exception_request(sh4, SH4_INTC_DMTE0); sh4_exception_request(SH4_INTC_DMTE0);
break; break;
case 1: case 1:
sh4->SH4_DMATCR1 = 0; m_SH4_DMATCR1 = 0;
sh4->SH4_CHCR1 |= CHCR_TE; m_SH4_CHCR1 |= CHCR_TE;
if (sh4->SH4_CHCR1 & CHCR_IE) if (m_SH4_CHCR1 & CHCR_IE)
sh4_exception_request(sh4, SH4_INTC_DMTE1); sh4_exception_request(SH4_INTC_DMTE1);
break; break;
case 2: case 2:
sh4->SH4_DMATCR2 = 0; m_SH4_DMATCR2 = 0;
sh4->SH4_CHCR2 |= CHCR_TE; m_SH4_CHCR2 |= CHCR_TE;
if (sh4->SH4_CHCR2 & CHCR_IE) if (m_SH4_CHCR2 & CHCR_IE)
sh4_exception_request(sh4, SH4_INTC_DMTE2); sh4_exception_request(SH4_INTC_DMTE2);
break; break;
case 3: case 3:
sh4->SH4_DMATCR3 = 0; m_SH4_DMATCR3 = 0;
sh4->SH4_CHCR3 |= CHCR_TE; m_SH4_CHCR3 |= CHCR_TE;
if (sh4->SH4_CHCR3 & CHCR_IE) if (m_SH4_CHCR3 & CHCR_IE)
sh4_exception_request(sh4, SH4_INTC_DMTE3); sh4_exception_request(SH4_INTC_DMTE3);
break; break;
} }
} }
static int sh4_dma_transfer(sh4_state *sh4, int channel, int timermode, UINT32 chcr, UINT32 *sar, UINT32 *dar, UINT32 *dmatcr) int sh34_base_device::sh4_dma_transfer(int channel, int timermode, UINT32 chcr, UINT32 *sar, UINT32 *dar, UINT32 *dmatcr)
{ {
int incs, incd, size; int incs, incd, size;
UINT32 src, dst, count; UINT32 src, dst, count;
@ -55,7 +54,7 @@ static int sh4_dma_transfer(sh4_state *sh4, int channel, int timermode, UINT32 c
incd = (chcr & CHCR_DM) >> 14; incd = (chcr & CHCR_DM) >> 14;
incs = (chcr & CHCR_SM) >> 12; incs = (chcr & CHCR_SM) >> 12;
if (sh4->cpu_type == CPU_TYPE_SH4) if (m_cpu_type == CPU_TYPE_SH4)
{ {
size = dmasize[(chcr & CHCR_TS) >> 4]; size = dmasize[(chcr & CHCR_TS) >> 4];
} }
@ -79,13 +78,13 @@ static int sh4_dma_transfer(sh4_state *sh4, int channel, int timermode, UINT32 c
if (timermode == 1) // timer actvated after a time based on the number of words to transfer if (timermode == 1) // timer actvated after a time based on the number of words to transfer
{ {
sh4->dma_timer_active[channel] = 1; m_dma_timer_active[channel] = 1;
sh4->dma_timer[channel]->adjust(sh4->device->cycles_to_attotime(2*count+1), channel); m_dma_timer[channel]->adjust(cycles_to_attotime(2*count+1), channel);
} }
else if (timermode == 2) // timer activated immediately else if (timermode == 2) // timer activated immediately
{ {
sh4->dma_timer_active[channel] = 1; m_dma_timer_active[channel] = 1;
sh4->dma_timer[channel]->adjust(attotime::zero, channel); m_dma_timer[channel]->adjust(attotime::zero, channel);
} }
src &= AM; src &= AM;
@ -100,7 +99,7 @@ static int sh4_dma_transfer(sh4_state *sh4, int channel, int timermode, UINT32 c
src --; src --;
if(incd == 2) if(incd == 2)
dst --; dst --;
sh4->program->write_byte(dst, sh4->program->read_byte(src)); m_program->write_byte(dst, m_program->read_byte(src));
if(incs == 1) if(incs == 1)
src ++; src ++;
if(incd == 1) if(incd == 1)
@ -116,7 +115,7 @@ static int sh4_dma_transfer(sh4_state *sh4, int channel, int timermode, UINT32 c
src -= 2; src -= 2;
if(incd == 2) if(incd == 2)
dst -= 2; dst -= 2;
sh4->program->write_word(dst, sh4->program->read_word(src)); m_program->write_word(dst, m_program->read_word(src));
if(incs == 1) if(incs == 1)
src += 2; src += 2;
if(incd == 1) if(incd == 1)
@ -132,7 +131,7 @@ static int sh4_dma_transfer(sh4_state *sh4, int channel, int timermode, UINT32 c
src -= 8; src -= 8;
if(incd == 2) if(incd == 2)
dst -= 8; dst -= 8;
sh4->program->write_qword(dst, sh4->program->read_qword(src)); m_program->write_qword(dst, m_program->read_qword(src));
if(incs == 1) if(incs == 1)
src += 8; src += 8;
if(incd == 1) if(incd == 1)
@ -149,7 +148,7 @@ static int sh4_dma_transfer(sh4_state *sh4, int channel, int timermode, UINT32 c
src -= 4; src -= 4;
if(incd == 2) if(incd == 2)
dst -= 4; dst -= 4;
sh4->program->write_dword(dst, sh4->program->read_dword(src)); m_program->write_dword(dst, m_program->read_dword(src));
if(incs == 1) if(incs == 1)
src += 4; src += 4;
if(incd == 1) if(incd == 1)
@ -166,10 +165,10 @@ static int sh4_dma_transfer(sh4_state *sh4, int channel, int timermode, UINT32 c
src -= 32; src -= 32;
if(incd == 2) if(incd == 2)
dst -= 32; dst -= 32;
sh4->program->write_qword(dst, sh4->program->read_qword(src)); m_program->write_qword(dst, m_program->read_qword(src));
sh4->program->write_qword(dst+8, sh4->program->read_qword(src+8)); m_program->write_qword(dst+8, m_program->read_qword(src+8));
sh4->program->write_qword(dst+16, sh4->program->read_qword(src+16)); m_program->write_qword(dst+16, m_program->read_qword(src+16));
sh4->program->write_qword(dst+24, sh4->program->read_qword(src+24)); m_program->write_qword(dst+24, m_program->read_qword(src+24));
if(incs == 1) if(incs == 1)
src += 32; src += 32;
if(incd == 1) if(incd == 1)
@ -183,7 +182,7 @@ static int sh4_dma_transfer(sh4_state *sh4, int channel, int timermode, UINT32 c
return 1; return 1;
} }
static int sh4_dma_transfer_device(sh4_state *sh4, int channel, UINT32 chcr, UINT32 *sar, UINT32 *dar, UINT32 *dmatcr) int sh34_base_device::sh4_dma_transfer_device(int channel, UINT32 chcr, UINT32 *sar, UINT32 *dar, UINT32 *dmatcr)
{ {
int incs, incd, size, mod; int incs, incd, size, mod;
UINT32 src, dst, count; UINT32 src, dst, count;
@ -192,7 +191,7 @@ static int sh4_dma_transfer_device(sh4_state *sh4, int channel, UINT32 chcr, UIN
incs = (chcr & CHCR_SM) >> 12; incs = (chcr & CHCR_SM) >> 12;
if (sh4->cpu_type == CPU_TYPE_SH4) if (m_cpu_type == CPU_TYPE_SH4)
{ {
size = dmasize[(chcr & CHCR_TS) >> 4]; size = dmasize[(chcr & CHCR_TS) >> 4];
} }
@ -215,207 +214,205 @@ static int sh4_dma_transfer_device(sh4_state *sh4, int channel, UINT32 chcr, UIN
LOG(("SH4: DMA %d start device<->memory %x, %x, %x, %04x, %d, %d, %d\n", channel, src, dst, count, chcr, incs, incd, size)); LOG(("SH4: DMA %d start device<->memory %x, %x, %x, %04x, %d, %d, %d\n", channel, src, dst, count, chcr, incs, incd, size));
sh4->dma_timer_active[channel] = 1; m_dma_timer_active[channel] = 1;
src &= AM; src &= AM;
dst &= AM; dst &= AM;
// remember parameters // remember parameters
sh4->dma_source[channel]=src; m_dma_source[channel]=src;
sh4->dma_destination[channel]=dst; m_dma_destination[channel]=dst;
sh4->dma_count[channel]=count; m_dma_count[channel]=count;
sh4->dma_wordsize[channel]=size; m_dma_wordsize[channel]=size;
sh4->dma_source_increment[channel]=incs; m_dma_source_increment[channel]=incs;
sh4->dma_destination_increment[channel]=incd; m_dma_destination_increment[channel]=incd;
sh4->dma_mode[channel]=mod; m_dma_mode[channel]=mod;
// inform device its ready to transfer // inform device its ready to transfer
sh4->io->write_dword(SH4_IOPORT_DMA, channel | (mod << 16)); m_io->write_dword(SH4_IOPORT_DMA, channel | (mod << 16));
return 1; return 1;
} }
static void sh4_dmac_check(sh4_state *sh4, int channel) void sh34_base_device::sh4_dmac_check(int channel)
{ {
UINT32 dmatcr, chcr, sar, dar; UINT32 dmatcr, chcr, sar, dar;
switch (channel) switch (channel)
{ {
case 0: case 0:
sar = sh4->SH4_SAR0; sar = m_SH4_SAR0;
dar = sh4->SH4_DAR0; dar = m_SH4_DAR0;
chcr = sh4->SH4_CHCR0; chcr = m_SH4_CHCR0;
dmatcr = sh4->SH4_DMATCR0; dmatcr = m_SH4_DMATCR0;
break; break;
case 1: case 1:
sar = sh4->SH4_SAR1; sar = m_SH4_SAR1;
dar = sh4->SH4_DAR1; dar = m_SH4_DAR1;
chcr = sh4->SH4_CHCR1; chcr = m_SH4_CHCR1;
dmatcr = sh4->SH4_DMATCR1; dmatcr = m_SH4_DMATCR1;
break; break;
case 2: case 2:
sar = sh4->SH4_SAR2; sar = m_SH4_SAR2;
dar = sh4->SH4_DAR2; dar = m_SH4_DAR2;
chcr = sh4->SH4_CHCR2; chcr = m_SH4_CHCR2;
dmatcr = sh4->SH4_DMATCR2; dmatcr = m_SH4_DMATCR2;
break; break;
case 3: case 3:
sar = sh4->SH4_SAR3; sar = m_SH4_SAR3;
dar = sh4->SH4_DAR3; dar = m_SH4_DAR3;
chcr = sh4->SH4_CHCR3; chcr = m_SH4_CHCR3;
dmatcr = sh4->SH4_DMATCR3; dmatcr = m_SH4_DMATCR3;
break; break;
default: default:
return; return;
} }
if (chcr & sh4->SH4_DMAOR & DMAOR_DME) if (chcr & m_SH4_DMAOR & DMAOR_DME)
{ {
if ((((chcr & CHCR_RS) >> 8) < 2) || (((chcr & CHCR_RS) >> 8) > 6)) if ((((chcr & CHCR_RS) >> 8) < 2) || (((chcr & CHCR_RS) >> 8) > 6))
return; return;
if (!sh4->dma_timer_active[channel] && !(chcr & CHCR_TE) && !(sh4->SH4_DMAOR & (DMAOR_AE | DMAOR_NMIF))) if (!m_dma_timer_active[channel] && !(chcr & CHCR_TE) && !(m_SH4_DMAOR & (DMAOR_AE | DMAOR_NMIF)))
{ {
if (((chcr & CHCR_RS) >> 8) > 3) if (((chcr & CHCR_RS) >> 8) > 3)
sh4_dma_transfer(sh4, channel, 1, chcr, &sar, &dar, &dmatcr); sh4_dma_transfer(channel, 1, chcr, &sar, &dar, &dmatcr);
else if ((sh4->SH4_DMAOR & DMAOR_DDT) == 0) else if ((m_SH4_DMAOR & DMAOR_DDT) == 0)
sh4_dma_transfer_device(sh4, channel, chcr, &sar, &dar, &dmatcr); // tell device we are ready to transfer sh4_dma_transfer_device(channel, chcr, &sar, &dar, &dmatcr); // tell device we are ready to transfer
} }
} }
else else
{ {
if (sh4->dma_timer_active[channel]) if (m_dma_timer_active[channel])
{ {
logerror("SH4: DMA %d cancelled in-flight but all data transferred", channel); logerror("SH4: DMA %d cancelled in-flight but all data transferred", channel);
sh4->dma_timer[channel]->adjust(attotime::never, channel); m_dma_timer[channel]->adjust(attotime::never, channel);
sh4->dma_timer_active[channel] = 0; m_dma_timer_active[channel] = 0;
} }
} }
} }
// called by drivers to transfer data in a cpu<->device dma. 'device' must be a SH4 cpu // called by drivers to transfer data in a cpu<->device dma. 'device' must be a SH4 cpu
int sh4_dma_data(device_t *device, struct sh4_device_dma *s) int sh34_base_device::sh4_dma_data(struct sh4_device_dma *s)
{ {
UINT32 pos, len, siz; UINT32 pos, len, siz;
int channel = s->channel; int channel = s->channel;
void *data = s->buffer; void *data = s->buffer;
sh4_state *sh4 = get_safe_token(device); if (!m_dma_timer_active[channel])
if (!sh4->dma_timer_active[channel])
return 0; return 0;
if (sh4->dma_mode[channel] == 2) if (m_dma_mode[channel] == 2)
{ {
// device receives data // device receives data
len = sh4->dma_count[channel]; len = m_dma_count[channel];
if (s->length < len) if (s->length < len)
len = s->length; len = s->length;
siz = sh4->dma_wordsize[channel]; siz = m_dma_wordsize[channel];
for (pos = 0;pos < len;pos++) { for (pos = 0;pos < len;pos++) {
switch (siz) switch (siz)
{ {
case 8: case 8:
if (sh4->dma_source_increment[channel] == 2) if (m_dma_source_increment[channel] == 2)
sh4->dma_source[channel] -= 8; m_dma_source[channel] -= 8;
*(UINT64 *)data = sh4->program->read_qword(sh4->dma_source[channel] & ~7); *(UINT64 *)data = m_program->read_qword(m_dma_source[channel] & ~7);
if (sh4->dma_source_increment[channel] == 1) if (m_dma_source_increment[channel] == 1)
sh4->dma_source[channel] += 8; m_dma_source[channel] += 8;
break; break;
case 1: case 1:
if (sh4->dma_source_increment[channel] == 2) if (m_dma_source_increment[channel] == 2)
sh4->dma_source[channel]--; m_dma_source[channel]--;
*(UINT8 *)data = sh4->program->read_byte(sh4->dma_source[channel]); *(UINT8 *)data = m_program->read_byte(m_dma_source[channel]);
if (sh4->dma_source_increment[channel] == 1) if (m_dma_source_increment[channel] == 1)
sh4->dma_source[channel]++; m_dma_source[channel]++;
break; break;
case 2: case 2:
if (sh4->dma_source_increment[channel] == 2) if (m_dma_source_increment[channel] == 2)
sh4->dma_source[channel] -= 2; m_dma_source[channel] -= 2;
*(UINT16 *)data = sh4->program->read_word(sh4->dma_source[channel] & ~1); *(UINT16 *)data = m_program->read_word(m_dma_source[channel] & ~1);
if (sh4->dma_source_increment[channel] == 1) if (m_dma_source_increment[channel] == 1)
sh4->dma_source[channel] += 2; m_dma_source[channel] += 2;
break; break;
case 4: case 4:
if (sh4->dma_source_increment[channel] == 2) if (m_dma_source_increment[channel] == 2)
sh4->dma_source[channel] -= 4; m_dma_source[channel] -= 4;
*(UINT32 *)data = sh4->program->read_dword(sh4->dma_source[channel] & ~3); *(UINT32 *)data = m_program->read_dword(m_dma_source[channel] & ~3);
if (sh4->dma_source_increment[channel] == 1) if (m_dma_source_increment[channel] == 1)
sh4->dma_source[channel] += 4; m_dma_source[channel] += 4;
break; break;
case 32: case 32:
if (sh4->dma_source_increment[channel] == 2) if (m_dma_source_increment[channel] == 2)
sh4->dma_source[channel] -= 32; m_dma_source[channel] -= 32;
*(UINT64 *)data = sh4->program->read_qword(sh4->dma_source[channel] & ~31); *(UINT64 *)data = m_program->read_qword(m_dma_source[channel] & ~31);
*((UINT64 *)data+1) = sh4->program->read_qword((sh4->dma_source[channel] & ~31)+8); *((UINT64 *)data+1) = m_program->read_qword((m_dma_source[channel] & ~31)+8);
*((UINT64 *)data+2) = sh4->program->read_qword((sh4->dma_source[channel] & ~31)+16); *((UINT64 *)data+2) = m_program->read_qword((m_dma_source[channel] & ~31)+16);
*((UINT64 *)data+3) = sh4->program->read_qword((sh4->dma_source[channel] & ~31)+24); *((UINT64 *)data+3) = m_program->read_qword((m_dma_source[channel] & ~31)+24);
if (sh4->dma_source_increment[channel] == 1) if (m_dma_source_increment[channel] == 1)
sh4->dma_source[channel] += 32; m_dma_source[channel] += 32;
break; break;
} }
sh4->dma_count[channel]--; m_dma_count[channel]--;
} }
if (sh4->dma_count[channel] == 0) // all data transferred ? if (m_dma_count[channel] == 0) // all data transferred ?
{ {
sh4->dma_timer[channel]->adjust(attotime::zero, channel); m_dma_timer[channel]->adjust(attotime::zero, channel);
return 2; return 2;
} }
return 1; return 1;
} }
else if (sh4->dma_mode[channel] == 3) else if (m_dma_mode[channel] == 3)
{ {
// device sends data // device sends data
len = sh4->dma_count[channel]; len = m_dma_count[channel];
if (s->length < len) if (s->length < len)
len = s->length; len = s->length;
siz = sh4->dma_wordsize[channel]; siz = m_dma_wordsize[channel];
for (pos = 0;pos < len;pos++) { for (pos = 0;pos < len;pos++) {
switch (siz) switch (siz)
{ {
case 8: case 8:
if (sh4->dma_destination_increment[channel] == 2) if (m_dma_destination_increment[channel] == 2)
sh4->dma_destination[channel]-=8; m_dma_destination[channel]-=8;
sh4->program->write_qword(sh4->dma_destination[channel] & ~7, *(UINT64 *)data); m_program->write_qword(m_dma_destination[channel] & ~7, *(UINT64 *)data);
if (sh4->dma_destination_increment[channel] == 1) if (m_dma_destination_increment[channel] == 1)
sh4->dma_destination[channel]+=8; m_dma_destination[channel]+=8;
break; break;
case 1: case 1:
if (sh4->dma_destination_increment[channel] == 2) if (m_dma_destination_increment[channel] == 2)
sh4->dma_destination[channel]--; m_dma_destination[channel]--;
sh4->program->write_byte(sh4->dma_destination[channel], *(UINT8 *)data); m_program->write_byte(m_dma_destination[channel], *(UINT8 *)data);
if (sh4->dma_destination_increment[channel] == 1) if (m_dma_destination_increment[channel] == 1)
sh4->dma_destination[channel]++; m_dma_destination[channel]++;
break; break;
case 2: case 2:
if (sh4->dma_destination_increment[channel] == 2) if (m_dma_destination_increment[channel] == 2)
sh4->dma_destination[channel]-=2; m_dma_destination[channel]-=2;
sh4->program->write_word(sh4->dma_destination[channel] & ~1, *(UINT16 *)data); m_program->write_word(m_dma_destination[channel] & ~1, *(UINT16 *)data);
if (sh4->dma_destination_increment[channel] == 1) if (m_dma_destination_increment[channel] == 1)
sh4->dma_destination[channel]+=2; m_dma_destination[channel]+=2;
break; break;
case 4: case 4:
if (sh4->dma_destination_increment[channel] == 2) if (m_dma_destination_increment[channel] == 2)
sh4->dma_destination[channel]-=4; m_dma_destination[channel]-=4;
sh4->program->write_dword(sh4->dma_destination[channel] & ~3, *(UINT32 *)data); m_program->write_dword(m_dma_destination[channel] & ~3, *(UINT32 *)data);
if (sh4->dma_destination_increment[channel] == 1) if (m_dma_destination_increment[channel] == 1)
sh4->dma_destination[channel]+=4; m_dma_destination[channel]+=4;
break; break;
case 32: case 32:
if (sh4->dma_destination_increment[channel] == 2) if (m_dma_destination_increment[channel] == 2)
sh4->dma_destination[channel]-=32; m_dma_destination[channel]-=32;
sh4->program->write_qword(sh4->dma_destination[channel] & ~31, *(UINT64 *)data); m_program->write_qword(m_dma_destination[channel] & ~31, *(UINT64 *)data);
sh4->program->write_qword((sh4->dma_destination[channel] & ~31)+8, *((UINT64 *)data+1)); m_program->write_qword((m_dma_destination[channel] & ~31)+8, *((UINT64 *)data+1));
sh4->program->write_qword((sh4->dma_destination[channel] & ~31)+16, *((UINT64 *)data+2)); m_program->write_qword((m_dma_destination[channel] & ~31)+16, *((UINT64 *)data+2));
sh4->program->write_qword((sh4->dma_destination[channel] & ~31)+24, *((UINT64 *)data+3)); m_program->write_qword((m_dma_destination[channel] & ~31)+24, *((UINT64 *)data+3));
if (sh4->dma_destination_increment[channel] == 1) if (m_dma_destination_increment[channel] == 1)
sh4->dma_destination[channel]+=32; m_dma_destination[channel]+=32;
break; break;
} }
sh4->dma_count[channel]--; m_dma_count[channel]--;
} }
if (sh4->dma_count[channel] == 0) // all data transferred ? if (m_dma_count[channel] == 0) // all data transferred ?
{ {
sh4->dma_timer[channel]->adjust(attotime::zero, channel); m_dma_timer[channel]->adjust(attotime::zero, channel);
return 2; return 2;
} }
return 1; return 1;
@ -424,83 +421,82 @@ int sh4_dma_data(device_t *device, struct sh4_device_dma *s)
return 0; return 0;
} }
// called by drivers to transfer data in a DDT dma. 'device' must be a SH4 cpu // called by drivers to transfer data in a DDT dma.
void sh4_dma_ddt(device_t *device, struct sh4_ddt_dma *s) void sh34_base_device::sh4_dma_ddt(struct sh4_ddt_dma *s)
{ {
sh4_state *sh4 = get_safe_token(device);
UINT32 chcr; UINT32 chcr;
UINT32 *p32bits; UINT32 *p32bits;
UINT64 *p32bytes; UINT64 *p32bytes;
UINT32 pos,len,siz; UINT32 pos,len,siz;
if (sh4->cpu_type != CPU_TYPE_SH4) if (m_cpu_type != CPU_TYPE_SH4)
fatalerror("sh4_dma_ddt uses sh4->m[] with SH3\n"); fatalerror("sh4_dma_ddt uses m_m[] with SH3\n");
if (sh4->dma_timer_active[s->channel]) if (m_dma_timer_active[s->channel])
return; return;
if (s->mode >= 0) { if (s->mode >= 0) {
switch (s->channel) switch (s->channel)
{ {
case 0: case 0:
if (s->mode & 1) if (s->mode & 1)
s->source = sh4->SH4_SAR0; s->source = m_SH4_SAR0;
if (s->mode & 2) if (s->mode & 2)
sh4->SH4_SAR0 = s->source; m_SH4_SAR0 = s->source;
if (s->mode & 4) if (s->mode & 4)
s->destination = sh4->SH4_DAR0; s->destination = m_SH4_DAR0;
if (s->mode & 8) if (s->mode & 8)
sh4->SH4_DAR0 = s->destination; m_SH4_DAR0 = s->destination;
break; break;
case 1: case 1:
if (s->mode & 1) if (s->mode & 1)
s->source = sh4->SH4_SAR1; s->source = m_SH4_SAR1;
if (s->mode & 2) if (s->mode & 2)
sh4->SH4_SAR1 = s->source; m_SH4_SAR1 = s->source;
if (s->mode & 4) if (s->mode & 4)
s->destination = sh4->SH4_DAR1; s->destination = m_SH4_DAR1;
if (s->mode & 8) if (s->mode & 8)
sh4->SH4_DAR1 = s->destination; m_SH4_DAR1 = s->destination;
break; break;
case 2: case 2:
if (s->mode & 1) if (s->mode & 1)
s->source = sh4->SH4_SAR2; s->source = m_SH4_SAR2;
if (s->mode & 2) if (s->mode & 2)
sh4->SH4_SAR2 = s->source; m_SH4_SAR2 = s->source;
if (s->mode & 4) if (s->mode & 4)
s->destination = sh4->SH4_DAR2; s->destination = m_SH4_DAR2;
if (s->mode & 8) if (s->mode & 8)
sh4->SH4_DAR2 = s->destination; m_SH4_DAR2 = s->destination;
break; break;
case 3: case 3:
default: default:
if (s->mode & 1) if (s->mode & 1)
s->source = sh4->SH4_SAR3; s->source = m_SH4_SAR3;
if (s->mode & 2) if (s->mode & 2)
sh4->SH4_SAR3 = s->source; m_SH4_SAR3 = s->source;
if (s->mode & 4) if (s->mode & 4)
s->destination = sh4->SH4_DAR3; s->destination = m_SH4_DAR3;
if (s->mode & 8) if (s->mode & 8)
sh4->SH4_DAR3 = s->destination; m_SH4_DAR3 = s->destination;
break; break;
} }
switch (s->channel) switch (s->channel)
{ {
case 0: case 0:
chcr = sh4->SH4_CHCR0; chcr = m_SH4_CHCR0;
len = sh4->SH4_DMATCR0; len = m_SH4_DMATCR0;
break; break;
case 1: case 1:
chcr = sh4->SH4_CHCR1; chcr = m_SH4_CHCR1;
len = sh4->SH4_DMATCR1; len = m_SH4_DMATCR1;
break; break;
case 2: case 2:
chcr = sh4->SH4_CHCR2; chcr = m_SH4_CHCR2;
len = sh4->SH4_DMATCR2; len = m_SH4_DMATCR2;
break; break;
case 3: case 3:
default: default:
chcr = sh4->SH4_CHCR3; chcr = m_SH4_CHCR3;
len = sh4->SH4_DMATCR3; len = m_SH4_DMATCR3;
break; break;
} }
if ((s->direction) == 0) { if ((s->direction) == 0) {
@ -510,7 +506,7 @@ void sh4_dma_ddt(device_t *device, struct sh4_ddt_dma *s)
} }
if (sh4->cpu_type == CPU_TYPE_SH4) if (m_cpu_type == CPU_TYPE_SH4)
{ {
//siz = dmasize[(chcr & CHCR_TS) >> 4]; //siz = dmasize[(chcr & CHCR_TS) >> 4];
siz = dmasize[(chcr >> 4) & 7]; siz = dmasize[(chcr >> 4) & 7];
@ -524,14 +520,14 @@ void sh4_dma_ddt(device_t *device, struct sh4_ddt_dma *s)
if (siz && (s->size)) if (siz && (s->size))
if ((len * siz) != (s->length * s->size)) if ((len * siz) != (s->length * s->size))
return; return;
sh4_dma_transfer(sh4, s->channel, 0, chcr, &s->source, &s->destination, &len); sh4_dma_transfer(s->channel, 0, chcr, &s->source, &s->destination, &len);
} else { } else {
if (s->size == 4) { if (s->size == 4) {
if ((s->direction) == 0) { if ((s->direction) == 0) {
len = s->length; len = s->length;
p32bits = (UINT32 *)(s->buffer); p32bits = (UINT32 *)(s->buffer);
for (pos = 0;pos < len;pos++) { for (pos = 0;pos < len;pos++) {
*p32bits = sh4->program->read_dword(s->source); *p32bits = m_program->read_dword(s->source);
p32bits++; p32bits++;
s->source = s->source + 4; s->source = s->source + 4;
} }
@ -539,7 +535,7 @@ void sh4_dma_ddt(device_t *device, struct sh4_ddt_dma *s)
len = s->length; len = s->length;
p32bits = (UINT32 *)(s->buffer); p32bits = (UINT32 *)(s->buffer);
for (pos = 0;pos < len;pos++) { for (pos = 0;pos < len;pos++) {
sh4->program->write_dword(s->destination, *p32bits); m_program->write_dword(s->destination, *p32bits);
p32bits++; p32bits++;
s->destination = s->destination + 4; s->destination = s->destination + 4;
} }
@ -550,7 +546,7 @@ void sh4_dma_ddt(device_t *device, struct sh4_ddt_dma *s)
len = s->length * 4; len = s->length * 4;
p32bytes = (UINT64 *)(s->buffer); p32bytes = (UINT64 *)(s->buffer);
for (pos = 0;pos < len;pos++) { for (pos = 0;pos < len;pos++) {
*p32bytes = sh4->program->read_qword(s->source); *p32bytes = m_program->read_qword(s->source);
p32bytes++; p32bytes++;
s->destination = s->destination + 8; s->destination = s->destination + 8;
} }
@ -558,7 +554,7 @@ void sh4_dma_ddt(device_t *device, struct sh4_ddt_dma *s)
len = s->length * 4; len = s->length * 4;
p32bytes = (UINT64 *)(s->buffer); p32bytes = (UINT64 *)(s->buffer);
for (pos = 0;pos < len;pos++) { for (pos = 0;pos < len;pos++) {
sh4->program->write_qword(s->destination, *p32bytes); m_program->write_qword(s->destination, *p32bytes);
p32bytes++; p32bytes++;
s->destination = s->destination + 8; s->destination = s->destination + 8;
} }
@ -568,119 +564,102 @@ void sh4_dma_ddt(device_t *device, struct sh4_ddt_dma *s)
} }
void sh4_handle_sar0_addr_w(sh4_state *sh4, UINT32 data, UINT32 mem_mask) void sh34_base_device::sh4_handle_sar0_addr_w(UINT32 data, UINT32 mem_mask)
{ {
COMBINE_DATA(&sh4->SH4_SAR0); COMBINE_DATA(&m_SH4_SAR0);
} }
void sh4_handle_sar1_addr_w(sh4_state *sh4, UINT32 data, UINT32 mem_mask) void sh34_base_device::sh4_handle_sar1_addr_w(UINT32 data, UINT32 mem_mask)
{ {
COMBINE_DATA(&sh4->SH4_SAR1); COMBINE_DATA(&m_SH4_SAR1);
} }
void sh4_handle_sar2_addr_w(sh4_state *sh4, UINT32 data, UINT32 mem_mask) void sh34_base_device::sh4_handle_sar2_addr_w(UINT32 data, UINT32 mem_mask)
{ {
COMBINE_DATA(&sh4->SH4_SAR2); COMBINE_DATA(&m_SH4_SAR2);
} }
void sh4_handle_sar3_addr_w(sh4_state *sh4, UINT32 data, UINT32 mem_mask) void sh34_base_device::sh4_handle_sar3_addr_w(UINT32 data, UINT32 mem_mask)
{ {
COMBINE_DATA(&sh4->SH4_SAR3); COMBINE_DATA(&m_SH4_SAR3);
} }
void sh4_handle_dar0_addr_w(sh4_state *sh4, UINT32 data, UINT32 mem_mask) void sh34_base_device::sh4_handle_dar0_addr_w(UINT32 data, UINT32 mem_mask)
{ {
COMBINE_DATA(&sh4->SH4_DAR0); COMBINE_DATA(&m_SH4_DAR0);
} }
void sh4_handle_dar1_addr_w(sh4_state *sh4, UINT32 data, UINT32 mem_mask) void sh34_base_device::sh4_handle_dar1_addr_w(UINT32 data, UINT32 mem_mask)
{ {
COMBINE_DATA(&sh4->SH4_DAR1); COMBINE_DATA(&m_SH4_DAR1);
} }
void sh4_handle_dar2_addr_w(sh4_state *sh4, UINT32 data, UINT32 mem_mask) void sh34_base_device::sh4_handle_dar2_addr_w(UINT32 data, UINT32 mem_mask)
{ {
COMBINE_DATA(&sh4->SH4_DAR2); COMBINE_DATA(&m_SH4_DAR2);
} }
void sh4_handle_dar3_addr_w(sh4_state *sh4, UINT32 data, UINT32 mem_mask) void sh34_base_device::sh4_handle_dar3_addr_w(UINT32 data, UINT32 mem_mask)
{ {
COMBINE_DATA(&sh4->SH4_DAR3); COMBINE_DATA(&m_SH4_DAR3);
} }
void sh4_handle_dmatcr0_addr_w(sh4_state *sh4, UINT32 data, UINT32 mem_mask) void sh34_base_device::sh4_handle_dmatcr0_addr_w(UINT32 data, UINT32 mem_mask)
{ {
COMBINE_DATA(&sh4->SH4_DMATCR0); COMBINE_DATA(&m_SH4_DMATCR0);
} }
void sh4_handle_dmatcr1_addr_w(sh4_state *sh4, UINT32 data, UINT32 mem_mask) void sh34_base_device::sh4_handle_dmatcr1_addr_w(UINT32 data, UINT32 mem_mask)
{ {
COMBINE_DATA(&sh4->SH4_DMATCR1); COMBINE_DATA(&m_SH4_DMATCR1);
} }
void sh4_handle_dmatcr2_addr_w(sh4_state *sh4, UINT32 data, UINT32 mem_mask) void sh34_base_device::sh4_handle_dmatcr2_addr_w(UINT32 data, UINT32 mem_mask)
{ {
COMBINE_DATA(&sh4->SH4_DMATCR2); COMBINE_DATA(&m_SH4_DMATCR2);
} }
void sh4_handle_dmatcr3_addr_w(sh4_state *sh4, UINT32 data, UINT32 mem_mask) void sh34_base_device::sh4_handle_dmatcr3_addr_w(UINT32 data, UINT32 mem_mask)
{ {
COMBINE_DATA(&sh4->SH4_DMATCR3); COMBINE_DATA(&m_SH4_DMATCR3);
} }
void sh4_handle_chcr0_addr_w(sh4_state *sh4, UINT32 data, UINT32 mem_mask) void sh34_base_device::sh4_handle_chcr0_addr_w(UINT32 data, UINT32 mem_mask)
{ {
COMBINE_DATA(&sh4->SH4_CHCR0); COMBINE_DATA(&m_SH4_CHCR0);
sh4_dmac_check(sh4, 0); sh4_dmac_check(0);
} }
void sh4_handle_chcr1_addr_w(sh4_state *sh4, UINT32 data, UINT32 mem_mask) void sh34_base_device::sh4_handle_chcr1_addr_w(UINT32 data, UINT32 mem_mask)
{ {
COMBINE_DATA(&sh4->SH4_CHCR1); COMBINE_DATA(&m_SH4_CHCR1);
sh4_dmac_check(sh4, 1); sh4_dmac_check(1);
} }
void sh4_handle_chcr2_addr_w(sh4_state *sh4, UINT32 data, UINT32 mem_mask) void sh34_base_device::sh4_handle_chcr2_addr_w(UINT32 data, UINT32 mem_mask)
{ {
COMBINE_DATA(&sh4->SH4_CHCR2); COMBINE_DATA(&m_SH4_CHCR2);
sh4_dmac_check(sh4, 2); sh4_dmac_check(2);
} }
void sh4_handle_chcr3_addr_w(sh4_state *sh4, UINT32 data, UINT32 mem_mask) void sh34_base_device::sh4_handle_chcr3_addr_w(UINT32 data, UINT32 mem_mask)
{ {
COMBINE_DATA(&sh4->SH4_CHCR3); COMBINE_DATA(&m_SH4_CHCR3);
sh4_dmac_check(sh4, 3); sh4_dmac_check(3);
} }
void sh4_handle_dmaor_addr_w(sh4_state *sh4, UINT32 data, UINT32 mem_mask) void sh34_base_device::sh4_handle_dmaor_addr_w(UINT32 data, UINT32 mem_mask)
{ {
UINT32 old = sh4->SH4_DMAOR; UINT32 old = m_SH4_DMAOR;
COMBINE_DATA(&sh4->SH4_DMAOR); COMBINE_DATA(&m_SH4_DMAOR);
if ((sh4->SH4_DMAOR & DMAOR_AE) && (~old & DMAOR_AE)) if ((m_SH4_DMAOR & DMAOR_AE) && (~old & DMAOR_AE))
sh4->SH4_DMAOR &= ~DMAOR_AE; m_SH4_DMAOR &= ~DMAOR_AE;
if ((sh4->SH4_DMAOR & DMAOR_NMIF) && (~old & DMAOR_NMIF)) if ((m_SH4_DMAOR & DMAOR_NMIF) && (~old & DMAOR_NMIF))
sh4->SH4_DMAOR &= ~DMAOR_NMIF; m_SH4_DMAOR &= ~DMAOR_NMIF;
sh4_dmac_check(sh4, 0); sh4_dmac_check(0);
sh4_dmac_check(sh4, 1); sh4_dmac_check(1);
sh4_dmac_check(sh4, 2); sh4_dmac_check(2);
sh4_dmac_check(sh4, 3); sh4_dmac_check(3);
} }
UINT32 sh4_handle_sar0_addr_r(sh4_state *sh4, UINT32 mem_mask) { return sh4->SH4_SAR0; }
UINT32 sh4_handle_sar1_addr_r(sh4_state *sh4, UINT32 mem_mask) { return sh4->SH4_SAR1; }
UINT32 sh4_handle_sar2_addr_r(sh4_state *sh4, UINT32 mem_mask) { return sh4->SH4_SAR2; }
UINT32 sh4_handle_sar3_addr_r(sh4_state *sh4, UINT32 mem_mask) { return sh4->SH4_SAR3; }
UINT32 sh4_handle_dar0_addr_r(sh4_state *sh4, UINT32 mem_mask) { return sh4->SH4_DAR0; }
UINT32 sh4_handle_dar1_addr_r(sh4_state *sh4, UINT32 mem_mask) { return sh4->SH4_DAR1; }
UINT32 sh4_handle_dar2_addr_r(sh4_state *sh4, UINT32 mem_mask) { return sh4->SH4_DAR2; }
UINT32 sh4_handle_dar3_addr_r(sh4_state *sh4, UINT32 mem_mask) { return sh4->SH4_DAR3; }
UINT32 sh4_handle_dmatcr0_addr_r(sh4_state *sh4, UINT32 mem_mask) { return sh4->SH4_DMATCR0; }
UINT32 sh4_handle_dmatcr1_addr_r(sh4_state *sh4, UINT32 mem_mask) { return sh4->SH4_DMATCR1; }
UINT32 sh4_handle_dmatcr2_addr_r(sh4_state *sh4, UINT32 mem_mask) { return sh4->SH4_DMATCR2; }
UINT32 sh4_handle_dmatcr3_addr_r(sh4_state *sh4, UINT32 mem_mask) { return sh4->SH4_DMATCR3; }
UINT32 sh4_handle_chcr0_addr_r(sh4_state *sh4, UINT32 mem_mask) { return sh4->SH4_CHCR0; }
UINT32 sh4_handle_chcr1_addr_r(sh4_state *sh4, UINT32 mem_mask) { return sh4->SH4_CHCR1; }
UINT32 sh4_handle_chcr2_addr_r(sh4_state *sh4, UINT32 mem_mask) { return sh4->SH4_CHCR2; }
UINT32 sh4_handle_chcr3_addr_r(sh4_state *sh4, UINT32 mem_mask) { return sh4->SH4_CHCR3; }
UINT32 sh4_handle_dmaor_addr_r(sh4_state *sh4, UINT32 mem_mask) { return sh4->SH4_DMAOR; }

68
src/emu/cpu/sh4/sh4dmac.h
View File

@ -27,37 +27,37 @@
TIMER_CALLBACK( sh4_dmac_callback ); TIMER_CALLBACK( sh4_dmac_callback );
void sh4_handle_sar0_addr_w(sh4_state *sh4, UINT32 data, UINT32 mem_mask); void sh4_handle_sar0_addr_w(UINT32 data, UINT32 mem_mask);
void sh4_handle_sar1_addr_w(sh4_state *sh4, UINT32 data, UINT32 mem_mask); void sh4_handle_sar1_addr_w(UINT32 data, UINT32 mem_mask);
void sh4_handle_sar2_addr_w(sh4_state *sh4, UINT32 data, UINT32 mem_mask); void sh4_handle_sar2_addr_w(UINT32 data, UINT32 mem_mask);
void sh4_handle_sar3_addr_w(sh4_state *sh4, UINT32 data, UINT32 mem_mask); void sh4_handle_sar3_addr_w(UINT32 data, UINT32 mem_mask);
void sh4_handle_dar0_addr_w(sh4_state *sh4, UINT32 data, UINT32 mem_mask); void sh4_handle_dar0_addr_w(UINT32 data, UINT32 mem_mask);
void sh4_handle_dar1_addr_w(sh4_state *sh4, UINT32 data, UINT32 mem_mask); void sh4_handle_dar1_addr_w(UINT32 data, UINT32 mem_mask);
void sh4_handle_dar2_addr_w(sh4_state *sh4, UINT32 data, UINT32 mem_mask); void sh4_handle_dar2_addr_w(UINT32 data, UINT32 mem_mask);
void sh4_handle_dar3_addr_w(sh4_state *sh4, UINT32 data, UINT32 mem_mask); void sh4_handle_dar3_addr_w(UINT32 data, UINT32 mem_mask);
void sh4_handle_dmatcr0_addr_w(sh4_state *sh4, UINT32 data, UINT32 mem_mask); void sh4_handle_dmatcr0_addr_w(UINT32 data, UINT32 mem_mask);
void sh4_handle_dmatcr1_addr_w(sh4_state *sh4, UINT32 data, UINT32 mem_mask); void sh4_handle_dmatcr1_addr_w(UINT32 data, UINT32 mem_mask);
void sh4_handle_dmatcr2_addr_w(sh4_state *sh4, UINT32 data, UINT32 mem_mask); void sh4_handle_dmatcr2_addr_w(UINT32 data, UINT32 mem_mask);
void sh4_handle_dmatcr3_addr_w(sh4_state *sh4, UINT32 data, UINT32 mem_mask); void sh4_handle_dmatcr3_addr_w(UINT32 data, UINT32 mem_mask);
void sh4_handle_chcr0_addr_w(sh4_state *sh4, UINT32 data, UINT32 mem_mask); void sh4_handle_chcr0_addr_w(UINT32 data, UINT32 mem_mask);
void sh4_handle_chcr1_addr_w(sh4_state *sh4, UINT32 data, UINT32 mem_mask); void sh4_handle_chcr1_addr_w(UINT32 data, UINT32 mem_mask);
void sh4_handle_chcr2_addr_w(sh4_state *sh4, UINT32 data, UINT32 mem_mask); void sh4_handle_chcr2_addr_w(UINT32 data, UINT32 mem_mask);
void sh4_handle_chcr3_addr_w(sh4_state *sh4, UINT32 data, UINT32 mem_mask); void sh4_handle_chcr3_addr_w(UINT32 data, UINT32 mem_mask);
void sh4_handle_dmaor_addr_w(sh4_state *sh4, UINT32 data, UINT32 mem_mask); void sh4_handle_dmaor_addr_w(UINT32 data, UINT32 mem_mask);
UINT32 sh4_handle_sar0_addr_r(sh4_state *sh4, UINT32 mem_mask); UINT32 sh4_handle_sar0_addr_r(UINT32 mem_mask);
UINT32 sh4_handle_sar1_addr_r(sh4_state *sh4, UINT32 mem_mask); UINT32 sh4_handle_sar1_addr_r(UINT32 mem_mask);
UINT32 sh4_handle_sar2_addr_r(sh4_state *sh4, UINT32 mem_mask); UINT32 sh4_handle_sar2_addr_r(UINT32 mem_mask);
UINT32 sh4_handle_sar3_addr_r(sh4_state *sh4, UINT32 mem_mask); UINT32 sh4_handle_sar3_addr_r(UINT32 mem_mask);
UINT32 sh4_handle_dar0_addr_r(sh4_state *sh4, UINT32 mem_mask); UINT32 sh4_handle_dar0_addr_r(UINT32 mem_mask);
UINT32 sh4_handle_dar1_addr_r(sh4_state *sh4, UINT32 mem_mask); UINT32 sh4_handle_dar1_addr_r(UINT32 mem_mask);
UINT32 sh4_handle_dar2_addr_r(sh4_state *sh4, UINT32 mem_mask); UINT32 sh4_handle_dar2_addr_r(UINT32 mem_mask);
UINT32 sh4_handle_dar3_addr_r(sh4_state *sh4, UINT32 mem_mask); UINT32 sh4_handle_dar3_addr_r(UINT32 mem_mask);
UINT32 sh4_handle_dmatcr0_addr_r(sh4_state *sh4, UINT32 mem_mask); UINT32 sh4_handle_dmatcr0_addr_r(UINT32 mem_mask);
UINT32 sh4_handle_dmatcr1_addr_r(sh4_state *sh4, UINT32 mem_mask); UINT32 sh4_handle_dmatcr1_addr_r(UINT32 mem_mask);
UINT32 sh4_handle_dmatcr2_addr_r(sh4_state *sh4, UINT32 mem_mask); UINT32 sh4_handle_dmatcr2_addr_r(UINT32 mem_mask);
UINT32 sh4_handle_dmatcr3_addr_r(sh4_state *sh4, UINT32 mem_mask); UINT32 sh4_handle_dmatcr3_addr_r(UINT32 mem_mask);
UINT32 sh4_handle_chcr0_addr_r(sh4_state *sh4, UINT32 mem_mask); UINT32 sh4_handle_chcr0_addr_r(UINT32 mem_mask);
UINT32 sh4_handle_chcr1_addr_r(sh4_state *sh4, UINT32 mem_mask); UINT32 sh4_handle_chcr1_addr_r(UINT32 mem_mask);
UINT32 sh4_handle_chcr2_addr_r(sh4_state *sh4, UINT32 mem_mask); UINT32 sh4_handle_chcr2_addr_r(UINT32 mem_mask);
UINT32 sh4_handle_chcr3_addr_r(sh4_state *sh4, UINT32 mem_mask); UINT32 sh4_handle_chcr3_addr_r(UINT32 mem_mask);
UINT32 sh4_handle_dmaor_addr_r(sh4_state *sh4, UINT32 mem_mask); UINT32 sh4_handle_dmaor_addr_r(UINT32 mem_mask);

245
src/emu/cpu/sh4/sh4tmu.c
View File

@ -27,7 +27,7 @@ static UINT32 compute_ticks_timer(emu_timer *timer, int hertz, int divisor)
return (UINT32)ret; return (UINT32)ret;
} }
static void sh4_timer_recompute(sh4_state *sh4, int which) void sh34_base_device::sh4_timer_recompute(int which)
{ {
double ticks; double ticks;
@ -36,61 +36,60 @@ static void sh4_timer_recompute(sh4_state *sh4, int which)
switch (which) switch (which)
{ {
case 0: case 0:
tcr = sh4->SH4_TCR0; tcr = m_SH4_TCR0;
tcnt = sh4->SH4_TCNT0; tcnt = m_SH4_TCNT0;
break; break;
case 1: case 1:
tcr = sh4->SH4_TCR1; tcr = m_SH4_TCR1;
tcnt = sh4->SH4_TCNT1; tcnt = m_SH4_TCNT1;
break; break;
case 2: case 2:
tcr = sh4->SH4_TCR2; tcr = m_SH4_TCR2;
tcnt = sh4->SH4_TCNT2; tcnt = m_SH4_TCNT2;
break; break;
} }
ticks = tcnt; ticks = tcnt;
sh4->timer[which]->adjust(sh4_scale_up_mame_time(attotime::from_hz(sh4->pm_clock) * tcnt_div[tcr & 7], ticks), which); m_timer[which]->adjust(sh4_scale_up_mame_time(attotime::from_hz(m_pm_clock) * tcnt_div[tcr & 7], ticks), which);
} }
TIMER_CALLBACK( sh4_timer_callback ) TIMER_CALLBACK_MEMBER( sh34_base_device::sh4_timer_callback )
{ {
sh4_state *sh4 = (sh4_state *)ptr;
int which = param; int which = param;
switch (which) switch (which)
{ {
case 0: case 0:
sh4->SH4_TCNT0 = sh4->SH4_TCOR0; m_SH4_TCNT0 = m_SH4_TCOR0;
break; break;
case 1: case 1:
sh4->SH4_TCNT1 = sh4->SH4_TCOR1; m_SH4_TCNT1 = m_SH4_TCOR1;
break; break;
case 2: case 2:
sh4->SH4_TCNT2 = sh4->SH4_TCOR2; m_SH4_TCNT2 = m_SH4_TCOR2;
break; break;
} }
sh4_timer_recompute(sh4, which); sh4_timer_recompute(which);
switch (which) switch (which)
{ {
case 0: case 0:
sh4->SH4_TCR0 |= 0x100; m_SH4_TCR0 |= 0x100;
break; break;
case 1: case 1:
sh4->SH4_TCR1 |= 0x100; m_SH4_TCR1 |= 0x100;
break; break;
case 2: case 2:
sh4->SH4_TCR2 |= 0x100; m_SH4_TCR2 |= 0x100;
break; break;
} }
@ -98,25 +97,25 @@ TIMER_CALLBACK( sh4_timer_callback )
switch (which) switch (which)
{ {
case 0: case 0:
if (sh4->SH4_TCR0 & 0x20) if (m_SH4_TCR0 & 0x20)
{ {
sh4_exception_request(sh4, SH4_INTC_TUNI0); sh4_exception_request(SH4_INTC_TUNI0);
// logerror("SH4_INTC_TUNI0 requested\n"); // logerror("SH4_INTC_TUNI0 requested\n");
} }
break; break;
case 1: case 1:
if (sh4->SH4_TCR1 & 0x20) if (m_SH4_TCR1 & 0x20)
{ {
sh4_exception_request(sh4, SH4_INTC_TUNI1); sh4_exception_request(SH4_INTC_TUNI1);
// logerror("SH4_INTC_TUNI1 requested\n"); // logerror("SH4_INTC_TUNI1 requested\n");
} }
break; break;
case 2: case 2:
if (sh4->SH4_TCR2 & 0x20) if (m_SH4_TCR2 & 0x20)
{ {
sh4_exception_request(sh4, SH4_INTC_TUNI2); sh4_exception_request(SH4_INTC_TUNI2);
// logerror("SH4_INTC_TUNI2 requested\n"); // logerror("SH4_INTC_TUNI2 requested\n");
} }
break; break;
@ -125,199 +124,199 @@ TIMER_CALLBACK( sh4_timer_callback )
} }
UINT32 sh4_handle_tcnt0_addr_r(sh4_state *sh4, UINT32 mem_mask) UINT32 sh34_base_device::sh4_handle_tcnt0_addr_r(UINT32 mem_mask)
{ {
if (sh4->SH4_TSTR & 1) if (m_SH4_TSTR & 1)
return compute_ticks_timer(sh4->timer[0], sh4->pm_clock, tcnt_div[sh4->SH4_TCR0 & 7]); return compute_ticks_timer(m_timer[0], m_pm_clock, tcnt_div[m_SH4_TCR0 & 7]);
else else
return sh4->SH4_TCNT0; return m_SH4_TCNT0;
} }
UINT32 sh4_handle_tcnt1_addr_r(sh4_state *sh4, UINT32 mem_mask) UINT32 sh34_base_device::sh4_handle_tcnt1_addr_r(UINT32 mem_mask)
{ {
if (sh4->SH4_TSTR & 2) if (m_SH4_TSTR & 2)
return compute_ticks_timer(sh4->timer[1], sh4->pm_clock, tcnt_div[sh4->SH4_TCR1 & 7]); return compute_ticks_timer(m_timer[1], m_pm_clock, tcnt_div[m_SH4_TCR1 & 7]);
else else
return sh4->SH4_TCNT1; return m_SH4_TCNT1;
} }
UINT32 sh4_handle_tcnt2_addr_r(sh4_state *sh4, UINT32 mem_mask) UINT32 sh34_base_device::sh4_handle_tcnt2_addr_r(UINT32 mem_mask)
{ {
if (sh4->SH4_TSTR & 4) if (m_SH4_TSTR & 4)
return compute_ticks_timer(sh4->timer[2], sh4->pm_clock, tcnt_div[sh4->SH4_TCR2 & 7]); return compute_ticks_timer(m_timer[2], m_pm_clock, tcnt_div[m_SH4_TCR2 & 7]);
else else
return sh4->SH4_TCNT2; return m_SH4_TCNT2;
} }
UINT32 sh4_handle_tcor0_addr_r(sh4_state *sh4, UINT32 mem_mask) UINT32 sh34_base_device::sh4_handle_tcor0_addr_r(UINT32 mem_mask)
{ {
return sh4->SH4_TCOR0; return m_SH4_TCOR0;
} }
UINT32 sh4_handle_tcor1_addr_r(sh4_state *sh4, UINT32 mem_mask) UINT32 sh34_base_device::sh4_handle_tcor1_addr_r(UINT32 mem_mask)
{ {
return sh4->SH4_TCOR1; return m_SH4_TCOR1;
} }
UINT32 sh4_handle_tcor2_addr_r(sh4_state *sh4, UINT32 mem_mask) UINT32 sh34_base_device::sh4_handle_tcor2_addr_r(UINT32 mem_mask)
{ {
return sh4->SH4_TCOR2; return m_SH4_TCOR2;
} }
UINT32 sh4_handle_tcr0_addr_r(sh4_state *sh4, UINT32 mem_mask) UINT32 sh34_base_device::sh4_handle_tcr0_addr_r(UINT32 mem_mask)
{ {
return sh4->SH4_TCR0; return m_SH4_TCR0;
} }
UINT32 sh4_handle_tcr1_addr_r(sh4_state *sh4, UINT32 mem_mask) UINT32 sh34_base_device::sh4_handle_tcr1_addr_r(UINT32 mem_mask)
{ {
return sh4->SH4_TCR1; return m_SH4_TCR1;
} }
UINT32 sh4_handle_tcr2_addr_r(sh4_state *sh4, UINT32 mem_mask) UINT32 sh34_base_device::sh4_handle_tcr2_addr_r(UINT32 mem_mask)
{ {
return sh4->SH4_TCR2; return m_SH4_TCR2;
} }
UINT32 sh4_handle_tstr_addr_r(sh4_state *sh4, UINT32 mem_mask) UINT32 sh34_base_device::sh4_handle_tstr_addr_r(UINT32 mem_mask)
{ {
return sh4->SH4_TSTR; return m_SH4_TSTR;
} }
UINT32 sh4_handle_tocr_addr_r(sh4_state *sh4, UINT32 mem_mask) UINT32 sh34_base_device::sh4_handle_tocr_addr_r(UINT32 mem_mask)
{ {
return sh4->SH4_TOCR; return m_SH4_TOCR;
} }
UINT32 sh4_handle_tcpr2_addr_r(sh4_state *sh4, UINT32 mem_mask) UINT32 sh34_base_device::sh4_handle_tcpr2_addr_r(UINT32 mem_mask)
{ {
return sh4->SH4_TCPR2; return m_SH4_TCPR2;
} }
void sh4_handle_tstr_addr_w(sh4_state *sh4, UINT32 data, UINT32 mem_mask) void sh34_base_device::sh4_handle_tstr_addr_w(UINT32 data, UINT32 mem_mask)
{ {
UINT32 old2 = sh4->SH4_TSTR; UINT32 old2 = m_SH4_TSTR;
COMBINE_DATA(&sh4->SH4_TSTR); COMBINE_DATA(&m_SH4_TSTR);
if (old2 & 1) if (old2 & 1)
sh4->SH4_TCNT0 = compute_ticks_timer(sh4->timer[0], sh4->pm_clock, tcnt_div[sh4->SH4_TCR0 & 7]); m_SH4_TCNT0 = compute_ticks_timer(m_timer[0], m_pm_clock, tcnt_div[m_SH4_TCR0 & 7]);
if ((sh4->SH4_TSTR & 1) == 0) { if ((m_SH4_TSTR & 1) == 0) {
sh4->timer[0]->adjust(attotime::never); m_timer[0]->adjust(attotime::never);
} else } else
sh4_timer_recompute(sh4, 0); sh4_timer_recompute(0);
if (old2 & 2) if (old2 & 2)
sh4->SH4_TCNT1 = compute_ticks_timer(sh4->timer[1], sh4->pm_clock, tcnt_div[sh4->SH4_TCR1 & 7]); m_SH4_TCNT1 = compute_ticks_timer(m_timer[1], m_pm_clock, tcnt_div[m_SH4_TCR1 & 7]);
if ((sh4->SH4_TSTR & 2) == 0) { if ((m_SH4_TSTR & 2) == 0) {
sh4->timer[1]->adjust(attotime::never); m_timer[1]->adjust(attotime::never);
} else } else
sh4_timer_recompute(sh4, 1); sh4_timer_recompute(1);
if (old2 & 4) if (old2 & 4)
sh4->SH4_TCNT2 = compute_ticks_timer(sh4->timer[2], sh4->pm_clock, tcnt_div[sh4->SH4_TCR2 & 7]); m_SH4_TCNT2 = compute_ticks_timer(m_timer[2], m_pm_clock, tcnt_div[m_SH4_TCR2 & 7]);
if ((sh4->SH4_TSTR & 4) == 0) { if ((m_SH4_TSTR & 4) == 0) {
sh4->timer[2]->adjust(attotime::never); m_timer[2]->adjust(attotime::never);
} else } else
sh4_timer_recompute(sh4, 2); sh4_timer_recompute(2);
} }
void sh4_handle_tcr0_addr_w(sh4_state *sh4, UINT32 data, UINT32 mem_mask) void sh34_base_device::sh4_handle_tcr0_addr_w(UINT32 data, UINT32 mem_mask)
{ {
UINT32 old2 = sh4->SH4_TCR0; UINT32 old2 = m_SH4_TCR0;
COMBINE_DATA(&sh4->SH4_TCR0); COMBINE_DATA(&m_SH4_TCR0);
if (sh4->SH4_TSTR & 1) if (m_SH4_TSTR & 1)
{ {
sh4->SH4_TCNT0 = compute_ticks_timer(sh4->timer[0], sh4->pm_clock, tcnt_div[old2 & 7]); m_SH4_TCNT0 = compute_ticks_timer(m_timer[0], m_pm_clock, tcnt_div[old2 & 7]);
sh4_timer_recompute(sh4, 0); sh4_timer_recompute(0);
} }
if (!(sh4->SH4_TCR0 & 0x20) || !(sh4->SH4_TCR0 & 0x100)) if (!(m_SH4_TCR0 & 0x20) || !(m_SH4_TCR0 & 0x100))
sh4_exception_unrequest(sh4, SH4_INTC_TUNI0); sh4_exception_unrequest(SH4_INTC_TUNI0);
} }
void sh4_handle_tcr1_addr_w(sh4_state *sh4, UINT32 data, UINT32 mem_mask) void sh34_base_device::sh4_handle_tcr1_addr_w(UINT32 data, UINT32 mem_mask)
{ {
UINT32 old2 = sh4->SH4_TCR1; UINT32 old2 = m_SH4_TCR1;
COMBINE_DATA(&sh4->SH4_TCR1); COMBINE_DATA(&m_SH4_TCR1);
if (sh4->SH4_TSTR & 2) if (m_SH4_TSTR & 2)
{ {
sh4->SH4_TCNT1 = compute_ticks_timer(sh4->timer[1], sh4->pm_clock, tcnt_div[old2 & 7]); m_SH4_TCNT1 = compute_ticks_timer(m_timer[1], m_pm_clock, tcnt_div[old2 & 7]);
sh4_timer_recompute(sh4, 1); sh4_timer_recompute(1);
} }
if (!(sh4->SH4_TCR1 & 0x20) || !(sh4->SH4_TCR1 & 0x100)) if (!(m_SH4_TCR1 & 0x20) || !(m_SH4_TCR1 & 0x100))
sh4_exception_unrequest(sh4, SH4_INTC_TUNI1); sh4_exception_unrequest(SH4_INTC_TUNI1);
} }
void sh4_handle_tcr2_addr_w(sh4_state *sh4, UINT32 data, UINT32 mem_mask) void sh34_base_device::sh4_handle_tcr2_addr_w(UINT32 data, UINT32 mem_mask)
{ {
UINT32 old2 = sh4->SH4_TCR2; UINT32 old2 = m_SH4_TCR2;
COMBINE_DATA(&sh4->SH4_TCR2); COMBINE_DATA(&m_SH4_TCR2);
if (sh4->SH4_TSTR & 4) if (m_SH4_TSTR & 4)
{ {
sh4->SH4_TCNT2 = compute_ticks_timer(sh4->timer[2], sh4->pm_clock, tcnt_div[old2 & 7]); m_SH4_TCNT2 = compute_ticks_timer(m_timer[2], m_pm_clock, tcnt_div[old2 & 7]);
sh4_timer_recompute(sh4, 2); sh4_timer_recompute(2);
} }
if (!(sh4->SH4_TCR2 & 0x20) || !(sh4->SH4_TCR2 & 0x100)) if (!(m_SH4_TCR2 & 0x20) || !(m_SH4_TCR2 & 0x100))
sh4_exception_unrequest(sh4, SH4_INTC_TUNI2); sh4_exception_unrequest(SH4_INTC_TUNI2);
} }
void sh4_handle_tcor0_addr_w(sh4_state *sh4, UINT32 data, UINT32 mem_mask) void sh34_base_device::sh4_handle_tcor0_addr_w(UINT32 data, UINT32 mem_mask)
{ {
COMBINE_DATA(&sh4->SH4_TCOR0); COMBINE_DATA(&m_SH4_TCOR0);
if (sh4->SH4_TSTR & 1) if (m_SH4_TSTR & 1)
{ {
sh4->SH4_TCNT0 = compute_ticks_timer(sh4->timer[0], sh4->pm_clock, tcnt_div[sh4->SH4_TCR0 & 7]); m_SH4_TCNT0 = compute_ticks_timer(m_timer[0], m_pm_clock, tcnt_div[m_SH4_TCR0 & 7]);
sh4_timer_recompute(sh4, 0); sh4_timer_recompute(0);
} }
} }
void sh4_handle_tcor1_addr_w(sh4_state *sh4, UINT32 data, UINT32 mem_mask) void sh34_base_device::sh4_handle_tcor1_addr_w(UINT32 data, UINT32 mem_mask)
{ {
COMBINE_DATA(&sh4->SH4_TCOR1); COMBINE_DATA(&m_SH4_TCOR1);
if (sh4->SH4_TSTR & 2) if (m_SH4_TSTR & 2)
{ {
sh4->SH4_TCNT1 = compute_ticks_timer(sh4->timer[1], sh4->pm_clock, tcnt_div[sh4->SH4_TCR1 & 7]); m_SH4_TCNT1 = compute_ticks_timer(m_timer[1], m_pm_clock, tcnt_div[m_SH4_TCR1 & 7]);
sh4_timer_recompute(sh4, 1); sh4_timer_recompute(1);
} }
} }
void sh4_handle_tcor2_addr_w(sh4_state *sh4, UINT32 data, UINT32 mem_mask) void sh34_base_device::sh4_handle_tcor2_addr_w(UINT32 data, UINT32 mem_mask)
{ {
COMBINE_DATA(&sh4->SH4_TCOR2); COMBINE_DATA(&m_SH4_TCOR2);
if (sh4->SH4_TSTR & 4) if (m_SH4_TSTR & 4)
{ {
sh4->SH4_TCNT2 = compute_ticks_timer(sh4->timer[2], sh4->pm_clock, tcnt_div[sh4->SH4_TCR2 & 7]); m_SH4_TCNT2 = compute_ticks_timer(m_timer[2], m_pm_clock, tcnt_div[m_SH4_TCR2 & 7]);
sh4_timer_recompute(sh4, 2); sh4_timer_recompute(2);
} }
} }
void sh4_handle_tcnt0_addr_w(sh4_state *sh4, UINT32 data, UINT32 mem_mask) void sh34_base_device::sh4_handle_tcnt0_addr_w(UINT32 data, UINT32 mem_mask)
{ {
COMBINE_DATA(&sh4->SH4_TCNT0); COMBINE_DATA(&m_SH4_TCNT0);
if (sh4->SH4_TSTR & 1) if (m_SH4_TSTR & 1)
sh4_timer_recompute(sh4, 0); sh4_timer_recompute(0);
} }
void sh4_handle_tcnt1_addr_w(sh4_state *sh4, UINT32 data, UINT32 mem_mask) void sh34_base_device::sh4_handle_tcnt1_addr_w(UINT32 data, UINT32 mem_mask)
{ {
COMBINE_DATA(&sh4->SH4_TCNT1); COMBINE_DATA(&m_SH4_TCNT1);
if (sh4->SH4_TSTR & 2) if (m_SH4_TSTR & 2)
sh4_timer_recompute(sh4, 1); sh4_timer_recompute(1);
} }
void sh4_handle_tcnt2_addr_w(sh4_state *sh4, UINT32 data, UINT32 mem_mask) void sh34_base_device::sh4_handle_tcnt2_addr_w(UINT32 data, UINT32 mem_mask)
{ {
COMBINE_DATA(&sh4->SH4_TCNT2); COMBINE_DATA(&m_SH4_TCNT2);
if (sh4->SH4_TSTR & 4) if (m_SH4_TSTR & 4)
sh4_timer_recompute(sh4, 2); sh4_timer_recompute(2);
} }
void sh4_handle_tocr_addr_w(sh4_state *sh4, UINT32 data, UINT32 mem_mask) void sh34_base_device::sh4_handle_tocr_addr_w(UINT32 data, UINT32 mem_mask)
{ {
COMBINE_DATA(&sh4->SH4_TOCR); COMBINE_DATA(&m_SH4_TOCR);
} }
void sh4_handle_tcpr2_addr_w(sh4_state *sh4, UINT32 data, UINT32 mem_mask) void sh34_base_device::sh4_handle_tcpr2_addr_w(UINT32 data, UINT32 mem_mask)
{ {
COMBINE_DATA(&sh4->SH4_TCPR2); COMBINE_DATA(&m_SH4_TCPR2);
} }

28
src/emu/cpu/sh4/sh4tmu.h
View File

@ -1,29 +1 @@
/* SH3/4 Timer Unit */ /* SH3/4 Timer Unit */
TIMER_CALLBACK( sh4_timer_callback );
UINT32 sh4_handle_tcnt0_addr_r(sh4_state *sh4, UINT32 mem_mask);
UINT32 sh4_handle_tcnt1_addr_r(sh4_state *sh4, UINT32 mem_mask);
UINT32 sh4_handle_tcnt2_addr_r(sh4_state *sh4, UINT32 mem_mask);
UINT32 sh4_handle_tcor0_addr_r(sh4_state *sh4, UINT32 mem_mask);
UINT32 sh4_handle_tcor1_addr_r(sh4_state *sh4, UINT32 mem_mask);
UINT32 sh4_handle_tcor2_addr_r(sh4_state *sh4, UINT32 mem_mask);
UINT32 sh4_handle_tcr0_addr_r(sh4_state *sh4, UINT32 mem_mask);
UINT32 sh4_handle_tcr1_addr_r(sh4_state *sh4, UINT32 mem_mask);
UINT32 sh4_handle_tcr2_addr_r(sh4_state *sh4, UINT32 mem_mask);
UINT32 sh4_handle_tstr_addr_r(sh4_state *sh4, UINT32 mem_mask);
UINT32 sh4_handle_tocr_addr_r(sh4_state *sh4, UINT32 mem_mask);
UINT32 sh4_handle_tcpr2_addr_r(sh4_state *sh4, UINT32 mem_mask);
void sh4_handle_tstr_addr_w(sh4_state *sh4, UINT32 data, UINT32 mem_mask);
void sh4_handle_tcr0_addr_w(sh4_state *sh4, UINT32 data, UINT32 mem_mask);
void sh4_handle_tcr1_addr_w(sh4_state *sh4, UINT32 data, UINT32 mem_mask);
void sh4_handle_tcr2_addr_w(sh4_state *sh4, UINT32 data, UINT32 mem_mask);
void sh4_handle_tcor0_addr_w(sh4_state *sh4, UINT32 data, UINT32 mem_mask);
void sh4_handle_tcor1_addr_w(sh4_state *sh4, UINT32 data, UINT32 mem_mask);
void sh4_handle_tcor2_addr_w(sh4_state *sh4, UINT32 data, UINT32 mem_mask);
void sh4_handle_tcnt0_addr_w(sh4_state *sh4, UINT32 data, UINT32 mem_mask);
void sh4_handle_tcnt1_addr_w(sh4_state *sh4, UINT32 data, UINT32 mem_mask);
void sh4_handle_tcnt2_addr_w(sh4_state *sh4, UINT32 data, UINT32 mem_mask);
void sh4_handle_tocr_addr_w(sh4_state *sh4, UINT32 data, UINT32 mem_mask);
void sh4_handle_tcpr2_addr_w(sh4_state *sh4, UINT32 data, UINT32 mem_mask);

12
src/mame/drivers/aristmk6.c
View File

@ -130,12 +130,20 @@ INPUT_PORTS_END
// ? // ?
#define ARISTMK6_CPU_CLOCK XTAL_200MHz #define ARISTMK6_CPU_CLOCK XTAL_200MHz
// ? // ?
static const struct sh4_config sh4cpu_config = { 1, 0, 1, 0, 0, 0, 1, 1, 0, ARISTMK6_CPU_CLOCK };
static MACHINE_CONFIG_START( aristmk6, aristmk6_state ) static MACHINE_CONFIG_START( aristmk6, aristmk6_state )
/* basic machine hardware */ /* basic machine hardware */
MCFG_CPU_ADD("maincpu", SH4LE, ARISTMK6_CPU_CLOCK) MCFG_CPU_ADD("maincpu", SH4LE, ARISTMK6_CPU_CLOCK)
MCFG_CPU_CONFIG(sh4cpu_config) MCFG_SH4_MD0(1)
MCFG_SH4_MD1(0)
MCFG_SH4_MD2(1)
MCFG_SH4_MD3(0)
MCFG_SH4_MD4(0)
MCFG_SH4_MD5(1)
MCFG_SH4_MD6(0)
MCFG_SH4_MD7(1)
MCFG_SH4_MD8(0)
MCFG_SH4_CLOCK(ARISTMK6_CPU_CLOCK)
MCFG_CPU_PROGRAM_MAP(aristmk6_map) MCFG_CPU_PROGRAM_MAP(aristmk6_map)
MCFG_CPU_IO_MAP(aristmk6_port) MCFG_CPU_IO_MAP(aristmk6_port)
// MCFG_DEVICE_DISABLE() // MCFG_DEVICE_DISABLE()

23
src/mame/drivers/atvtrack.c
View File

@ -387,17 +387,34 @@ INPUT_PORTS_END
// ? // ?
#define ATV_CPU_CLOCK 200000000 #define ATV_CPU_CLOCK 200000000
// ? // ?
static const struct sh4_config sh4cpu_config = { 1, 0, 1, 0, 0, 0, 1, 1, 0, ATV_CPU_CLOCK };
static MACHINE_CONFIG_START( atvtrack, atvtrack_state ) static MACHINE_CONFIG_START( atvtrack, atvtrack_state )
/* basic machine hardware */ /* basic machine hardware */
MCFG_CPU_ADD("maincpu", SH4LE, ATV_CPU_CLOCK) MCFG_CPU_ADD("maincpu", SH4LE, ATV_CPU_CLOCK)
MCFG_CPU_CONFIG(sh4cpu_config) MCFG_SH4_MD0(1)
MCFG_SH4_MD1(0)
MCFG_SH4_MD2(1)
MCFG_SH4_MD3(0)
MCFG_SH4_MD4(0)
MCFG_SH4_MD5(1)
MCFG_SH4_MD6(0)
MCFG_SH4_MD7(1)
MCFG_SH4_MD8(0)
MCFG_SH4_CLOCK(ATV_CPU_CLOCK)
MCFG_CPU_PROGRAM_MAP(atvtrack_main_map) MCFG_CPU_PROGRAM_MAP(atvtrack_main_map)
MCFG_CPU_IO_MAP(atvtrack_main_port) MCFG_CPU_IO_MAP(atvtrack_main_port)
MCFG_CPU_ADD("subcpu", SH4LE, ATV_CPU_CLOCK) MCFG_CPU_ADD("subcpu", SH4LE, ATV_CPU_CLOCK)
MCFG_CPU_CONFIG(sh4cpu_config) MCFG_SH4_MD0(1)
MCFG_SH4_MD1(0)
MCFG_SH4_MD2(1)
MCFG_SH4_MD3(0)
MCFG_SH4_MD4(0)
MCFG_SH4_MD5(1)
MCFG_SH4_MD6(0)
MCFG_SH4_MD7(1)
MCFG_SH4_MD8(0)
MCFG_SH4_CLOCK(ATV_CPU_CLOCK)
MCFG_CPU_PROGRAM_MAP(atvtrack_sub_map) MCFG_CPU_PROGRAM_MAP(atvtrack_sub_map)
MCFG_CPU_IO_MAP(atvtrack_sub_port) MCFG_CPU_IO_MAP(atvtrack_sub_port)

40
src/mame/drivers/cv1k.c
View File

@ -404,24 +404,6 @@ static INPUT_PORTS_START( cv1k )
INPUT_PORTS_END INPUT_PORTS_END
// none of this is verified
// (the sh3 is different to the sh4 anyway, should be changed)
static const struct sh4_config sh4cpu_config = {
0, // md2 (clock divders)
0, // md1 (clock divders)
0, // md0 (clock divders)
0,
0,
0,
1,
1, // md7 (master?)
0,
CPU_CLOCK // influences music sequencing in ddpdfk at least
};
INTERRUPT_GEN_MEMBER(cv1k_state::cv1k_interrupt) INTERRUPT_GEN_MEMBER(cv1k_state::cv1k_interrupt)
{ {
m_maincpu->set_input_line(2, HOLD_LINE); m_maincpu->set_input_line(2, HOLD_LINE);
@ -439,7 +421,16 @@ MACHINE_RESET_MEMBER( cv1k_state, cv1k )
static MACHINE_CONFIG_START( cv1k, cv1k_state ) static MACHINE_CONFIG_START( cv1k, cv1k_state )
/* basic machine hardware */ /* basic machine hardware */
MCFG_CPU_ADD("maincpu", SH3BE, CPU_CLOCK) MCFG_CPU_ADD("maincpu", SH3BE, CPU_CLOCK)
MCFG_CPU_CONFIG(sh4cpu_config) MCFG_SH4_MD0(0) // none of this is verified
MCFG_SH4_MD1(0) // (the sh3 is different to the sh4 anyway, should be changed)
MCFG_SH4_MD2(0)
MCFG_SH4_MD3(0)
MCFG_SH4_MD4(0)
MCFG_SH4_MD5(1)
MCFG_SH4_MD6(0)
MCFG_SH4_MD7(1)
MCFG_SH4_MD8(0)
MCFG_SH4_CLOCK(CPU_CLOCK)
MCFG_CPU_PROGRAM_MAP(cv1k_map) MCFG_CPU_PROGRAM_MAP(cv1k_map)
MCFG_CPU_IO_MAP(cv1k_port) MCFG_CPU_IO_MAP(cv1k_port)
MCFG_DEVICE_VBLANK_INT_DRIVER("screen", cv1k_state, cv1k_interrupt) MCFG_DEVICE_VBLANK_INT_DRIVER("screen", cv1k_state, cv1k_interrupt)
@ -473,7 +464,16 @@ static MACHINE_CONFIG_DERIVED( cv1k_d, cv1k )
MCFG_DEVICE_REMOVE("maincpu") MCFG_DEVICE_REMOVE("maincpu")
MCFG_CPU_ADD("maincpu", SH3BE, CPU_CLOCK) MCFG_CPU_ADD("maincpu", SH3BE, CPU_CLOCK)
MCFG_CPU_CONFIG(sh4cpu_config) MCFG_SH4_MD0(0) // none of this is verified
MCFG_SH4_MD1(0) // (the sh3 is different to the sh4 anyway, should be changed)
MCFG_SH4_MD2(0)
MCFG_SH4_MD3(0)
MCFG_SH4_MD4(0)
MCFG_SH4_MD5(1)
MCFG_SH4_MD6(0)
MCFG_SH4_MD7(1)
MCFG_SH4_MD8(0)
MCFG_SH4_CLOCK(CPU_CLOCK)
MCFG_CPU_PROGRAM_MAP(cv1k_d_map) MCFG_CPU_PROGRAM_MAP(cv1k_d_map)
MCFG_CPU_IO_MAP(cv1k_port) MCFG_CPU_IO_MAP(cv1k_port)
MCFG_DEVICE_VBLANK_INT_DRIVER("screen", cv1k_state, cv1k_interrupt) MCFG_DEVICE_VBLANK_INT_DRIVER("screen", cv1k_state, cv1k_interrupt)

13
src/mame/drivers/naomi.c
View File

@ -1491,8 +1491,6 @@ Sushi Bar
#include "includes/naomi.h" #include "includes/naomi.h"
#define CPU_CLOCK (200000000) #define CPU_CLOCK (200000000)
/* MD2 MD1 MD0 MD6 MD4 MD3 MD5 MD7 MD8 */
static const struct sh4_config sh4cpu_config = { 1, 0, 1, 0, 0, 0, 1, 1, 0, CPU_CLOCK };
READ64_MEMBER(naomi_state::naomi_arm_r ) READ64_MEMBER(naomi_state::naomi_arm_r )
{ {
@ -2547,7 +2545,16 @@ MACHINE_RESET_MEMBER(naomi_state,naomi)
static MACHINE_CONFIG_START( naomi_aw_base, naomi_state ) static MACHINE_CONFIG_START( naomi_aw_base, naomi_state )
/* basic machine hardware */ /* basic machine hardware */
MCFG_CPU_ADD("maincpu", SH4LE, CPU_CLOCK) // SH4!!! MCFG_CPU_ADD("maincpu", SH4LE, CPU_CLOCK) // SH4!!!
MCFG_CPU_CONFIG(sh4cpu_config) MCFG_SH4_MD0(1)
MCFG_SH4_MD1(0)
MCFG_SH4_MD2(1)
MCFG_SH4_MD3(0)
MCFG_SH4_MD4(0)
MCFG_SH4_MD5(1)
MCFG_SH4_MD6(0)
MCFG_SH4_MD7(1)
MCFG_SH4_MD8(0)
MCFG_SH4_CLOCK(CPU_CLOCK)
MCFG_CPU_PROGRAM_MAP(naomi_map) MCFG_CPU_PROGRAM_MAP(naomi_map)
MCFG_CPU_IO_MAP(naomi_port) MCFG_CPU_IO_MAP(naomi_port)
MCFG_TIMER_DRIVER_ADD_SCANLINE("scantimer", dc_state, dc_scanline, "screen", 0, 1) MCFG_TIMER_DRIVER_ADD_SCANLINE("scantimer", dc_state, dc_scanline, "screen", 0, 1)

2
src/mame/includes/dc.h
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@ -77,7 +77,7 @@ class dc_state : public driver_device
DECLARE_WRITE8_MEMBER( g1_irq ); DECLARE_WRITE8_MEMBER( g1_irq );
DECLARE_WRITE8_MEMBER( pvr_irq ); DECLARE_WRITE8_MEMBER( pvr_irq );
required_device<cpu_device> m_maincpu; required_device<sh4_base_device> m_maincpu;
required_device<cpu_device> m_soundcpu; required_device<cpu_device> m_soundcpu;
required_device<powervr2_device> m_powervr2; required_device<powervr2_device> m_powervr2;
required_device<maple_dc_device> m_maple; required_device<maple_dc_device> m_maple;

6
src/mame/machine/dc.c
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@ -88,7 +88,7 @@ void dc_state::generic_dma(UINT32 main_adr, void *dma_ptr, UINT32 length, UINT32
ddt.direction = to_mainram; ddt.direction = to_mainram;
ddt.channel = 0; ddt.channel = 0;
ddt.mode = -1; ddt.mode = -1;
sh4_dma_ddt(m_maincpu, &ddt); m_maincpu->sh4_dma_ddt(&ddt);
} }
TIMER_CALLBACK_MEMBER(dc_state::aica_dma_irq) TIMER_CALLBACK_MEMBER(dc_state::aica_dma_irq)
@ -332,7 +332,7 @@ void dc_state::dc_update_interrupt_status()
} }
level=dc_compute_interrupt_level(); level=dc_compute_interrupt_level();
sh4_set_irln_input(m_maincpu, 15-level); m_maincpu->sh4_set_irln_input(15-level);
/* Wave DMA HW trigger */ /* Wave DMA HW trigger */
if(m_wave_dma.flag && ((m_wave_dma.sel & 2) == 2)) if(m_wave_dma.flag && ((m_wave_dma.sel & 2) == 2))
@ -407,7 +407,7 @@ WRITE64_MEMBER(dc_state::dc_sysctrl_w )
ddtdata.direction=0; ddtdata.direction=0;
ddtdata.channel=2; ddtdata.channel=2;
ddtdata.mode=25; //011001 ddtdata.mode=25; //011001
sh4_dma_ddt(m_maincpu,&ddtdata); m_maincpu->sh4_dma_ddt(&ddtdata);
#if DEBUG_SYSCTRL #if DEBUG_SYSCTRL
if ((address >= 0x11000000) && (address <= 0x11FFFFFF)) if ((address >= 0x11000000) && (address <= 0x11FFFFFF))
if (dc_sysctrl_regs[SB_LMMODE0]) if (dc_sysctrl_regs[SB_LMMODE0])

8
src/mame/machine/maple-dc.c
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@ -120,7 +120,7 @@ void maple_dc_device::dma_step()
ddtdata.direction = 0; // 0 source to buffer, 1 buffer to source ddtdata.direction = 0; // 0 source to buffer, 1 buffer to source
ddtdata.channel = 0; ddtdata.channel = 0;
ddtdata.mode = -1; // copy from/to buffer ddtdata.mode = -1; // copy from/to buffer
sh4_dma_ddt(cpu, &ddtdata); cpu->sh4_dma_ddt(&ddtdata);
dma_adr += 8; dma_adr += 8;
dma_endflag = header[0] & 0x80000000; dma_endflag = header[0] & 0x80000000;
@ -136,7 +136,7 @@ void maple_dc_device::dma_step()
ddtdata.direction = 0; // 0 source to buffer, 1 buffer to source ddtdata.direction = 0; // 0 source to buffer, 1 buffer to source
ddtdata.channel = 0; ddtdata.channel = 0;
ddtdata.mode = -1; // copy from/to buffer ddtdata.mode = -1; // copy from/to buffer
sh4_dma_ddt(cpu, &ddtdata); cpu->sh4_dma_ddt(&ddtdata);
dma_adr += length*4; dma_adr += length*4;
switch(pattern) { switch(pattern) {
@ -191,7 +191,7 @@ void maple_dc_device::dma_step()
ddtdata.direction = 1; // 0 source to buffer, 1 buffer to source ddtdata.direction = 1; // 0 source to buffer, 1 buffer to source
ddtdata.channel = 0; ddtdata.channel = 0;
ddtdata.mode = -1; // copy from/to buffer ddtdata.mode = -1; // copy from/to buffer
sh4_dma_ddt(cpu, &ddtdata); cpu->sh4_dma_ddt(&ddtdata);
dma_state = dma_endflag ? DMA_DONE : DMA_SEND; dma_state = dma_endflag ? DMA_DONE : DMA_SEND;
break; break;
} }
@ -216,7 +216,7 @@ void maple_dc_device::dma_step()
ddtdata.direction = 1; // 0 source to buffer, 1 buffer to source ddtdata.direction = 1; // 0 source to buffer, 1 buffer to source
ddtdata.channel = 0; ddtdata.channel = 0;
ddtdata.mode = -1; // copy from/to buffer ddtdata.mode = -1; // copy from/to buffer
sh4_dma_ddt(cpu, &ddtdata); cpu->sh4_dma_ddt(&ddtdata);
dma_dest += length*4; dma_dest += length*4;
} }

13
src/mess/drivers/dccons.c
View File

@ -595,8 +595,6 @@ WRITE_LINE_MEMBER(dc_cons_state::sh4_aica_irq)
dc_update_interrupt_status(); dc_update_interrupt_status();
} }
static const struct sh4_config sh4cpu_config = { 1, 0, 1, 0, 0, 0, 1, 1, 0, CPU_CLOCK };
static MACHINE_CONFIG_FRAGMENT( gdrom_config ) static MACHINE_CONFIG_FRAGMENT( gdrom_config )
MCFG_DEVICE_MODIFY("cdda") MCFG_DEVICE_MODIFY("cdda")
MCFG_SOUND_ROUTE(0, "^^^^lspeaker", 1.0) MCFG_SOUND_ROUTE(0, "^^^^lspeaker", 1.0)
@ -606,7 +604,16 @@ MACHINE_CONFIG_END
static MACHINE_CONFIG_START( dc, dc_cons_state ) static MACHINE_CONFIG_START( dc, dc_cons_state )
/* basic machine hardware */ /* basic machine hardware */
MCFG_CPU_ADD("maincpu", SH4LE, CPU_CLOCK) MCFG_CPU_ADD("maincpu", SH4LE, CPU_CLOCK)
MCFG_CPU_CONFIG(sh4cpu_config) MCFG_SH4_MD0(1)
MCFG_SH4_MD1(0)
MCFG_SH4_MD2(1)
MCFG_SH4_MD3(0)
MCFG_SH4_MD4(0)
MCFG_SH4_MD5(1)
MCFG_SH4_MD6(0)
MCFG_SH4_MD7(1)
MCFG_SH4_MD8(0)
MCFG_SH4_CLOCK(CPU_CLOCK)
MCFG_CPU_PROGRAM_MAP(dc_map) MCFG_CPU_PROGRAM_MAP(dc_map)
MCFG_CPU_IO_MAP(dc_port) MCFG_CPU_IO_MAP(dc_port)
MCFG_TIMER_DRIVER_ADD_SCANLINE("scantimer", dc_state, dc_scanline, "screen", 0, 1) MCFG_TIMER_DRIVER_ADD_SCANLINE("scantimer", dc_state, dc_scanline, "screen", 0, 1)

12
src/mess/drivers/sh4robot.c
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@ -54,12 +54,20 @@ ADDRESS_MAP_END
static INPUT_PORTS_START( sh4robot ) static INPUT_PORTS_START( sh4robot )
INPUT_PORTS_END INPUT_PORTS_END
static const struct sh4_config sh4cpu_config = { 1, 0, 1, 0, 0, 0, 1, 1, 0, 200000000 };
static MACHINE_CONFIG_START( sh4robot, sh4robot_state ) static MACHINE_CONFIG_START( sh4robot, sh4robot_state )
/* basic machine hardware */ /* basic machine hardware */
MCFG_CPU_ADD("maincpu", SH4LE, 200000000) // SH7750 MCFG_CPU_ADD("maincpu", SH4LE, 200000000) // SH7750
MCFG_CPU_CONFIG(sh4cpu_config) MCFG_SH4_MD0(1)
MCFG_SH4_MD1(0)
MCFG_SH4_MD2(1)
MCFG_SH4_MD3(0)
MCFG_SH4_MD4(0)
MCFG_SH4_MD5(1)
MCFG_SH4_MD6(0)
MCFG_SH4_MD7(1)
MCFG_SH4_MD8(0)
MCFG_SH4_CLOCK(200000000)
MCFG_CPU_PROGRAM_MAP(sh4robot_mem) MCFG_CPU_PROGRAM_MAP(sh4robot_mem)
MCFG_CPU_IO_MAP(sh4robot_io) MCFG_CPU_IO_MAP(sh4robot_io)

2
src/mess/machine/dccons.c
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@ -71,7 +71,7 @@ TIMER_CALLBACK_MEMBER(dc_cons_state::atapi_xfer_end )
ddtdata.channel= 0; ddtdata.channel= 0;
ddtdata.mode= -1; // copy from/to buffer ddtdata.mode= -1; // copy from/to buffer
printf("ATAPI: DMA one sector to %x, %x remaining\n", atapi_xferbase, atapi_xferlen); printf("ATAPI: DMA one sector to %x, %x remaining\n", atapi_xferbase, atapi_xferlen);
sh4_dma_ddt(m_maincpu, &ddtdata); m_maincpu->sh4_dma_ddt(&ddtdata);
atapi_xferbase += 2048; atapi_xferbase += 2048;
} }