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https://github.com/holub/mame
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(MESS) mbee128: improvements; mbee256: fixed some of the paste problems (nw)
This commit is contained in:
Robbbert
parent
2cd878633a
commit
be6304da89
@ -90,8 +90,6 @@
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work.
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- various fdc issues:
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- only some ds40 disks can be used. All 80-track disks fail.
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- some disks show no or partial directory listing.
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- some disks cause MESS to freeze.
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- ENMF pin missing from wd_fdc.
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- incorrect timing for track register causes 256tc failure to boot a disk.
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@ -101,7 +99,7 @@
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crashes due to a bug in z80pio emulation.
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- 256tc: Keyboard ROM U60 needs to be dumped.
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- 128k: PROM PAL needs to be dumped, so that the bankswitching can be fixed.
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- 128k: PROM PAL needs to be dumped for the bankswitching.
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- Teleterm: keyboard is problematic, and cursor doesn't show.
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@ -115,11 +113,7 @@
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and intrq/drq on read.
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intrq and drq are OR'd together, then gated to bit 7 of the
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data bus whenever port 48 is activated on read. There are
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no interrupts used in the disk system.
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Despite the simplicity of this design, disks have not worked
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in the emulator for some years. Conversion to the new modern
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implementation (2013-07-05) has not resolved the issue.
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no interrupts used.
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****************************************************************************/
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@ -203,16 +197,6 @@ static ADDRESS_MAP_START(mbee64_mem, AS_PROGRAM, 8, mbee_state)
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AM_RANGE(0xf800, 0xffff) AM_READWRITE(mbeeic_high_r, mbeeic_high_w)
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ADDRESS_MAP_END
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static ADDRESS_MAP_START(mbee128_mem, AS_PROGRAM, 8, mbee_state)
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AM_RANGE(0x0000, 0x0fff) AM_RAMBANK("boot")
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AM_RANGE(0x1000, 0x7fff) AM_RAMBANK("bank1")
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AM_RANGE(0x8000, 0x87ff) AM_RAMBANK("bank8l")
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AM_RANGE(0x8800, 0x8fff) AM_RAMBANK("bank8h")
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AM_RANGE(0x9000, 0xefff) AM_RAMBANK("bank9")
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AM_RANGE(0xf000, 0xf7ff) AM_RAMBANK("bankfl")
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AM_RANGE(0xf800, 0xffff) AM_RAMBANK("bankfh")
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ADDRESS_MAP_END
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static ADDRESS_MAP_START(mbee256_mem, AS_PROGRAM, 8, mbee_state)
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AM_RANGE(0x0000, 0x0fff) AM_READ_BANK("bankr0") AM_WRITE_BANK("bankw0")
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AM_RANGE(0x1000, 0x1fff) AM_READ_BANK("bankr1") AM_WRITE_BANK("bankw1")
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@ -535,7 +519,7 @@ static INPUT_PORTS_START( mbee256 )
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PORT_START("X6") /* IN6 KEY ROW 6 [+30] */
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PORT_BIT( 0x01, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_NAME("F7") PORT_CODE(KEYCODE_F7)
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PORT_BIT( 0x02, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_NAME("6 &") PORT_CODE(KEYCODE_6) PORT_CHAR('6') PORT_CHAR('&')
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PORT_BIT( 0x04, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_NAME("Y") PORT_CODE(KEYCODE_Y) PORT_CHAR('u') PORT_CHAR('Y') PORT_CHAR(0x19)
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PORT_BIT( 0x04, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_NAME("Y") PORT_CODE(KEYCODE_Y) PORT_CHAR('y') PORT_CHAR('Y') PORT_CHAR(0x19)
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PORT_BIT( 0x08, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_NAME("H") PORT_CODE(KEYCODE_H) PORT_CHAR('h') PORT_CHAR('H') PORT_CHAR(0x08)
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PORT_BIT( 0x10, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_NAME("/ (num)") PORT_CODE(KEYCODE_SLASH_PAD)
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PORT_BIT( 0x20, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_NAME("(Down)") PORT_CODE(KEYCODE_DOWN) PORT_CHAR(UCHAR_MAMEKEY(DOWN))
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@ -587,10 +571,10 @@ static INPUT_PORTS_START( mbee256 )
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PORT_BIT( 0x80, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_NAME("/ ?") PORT_CODE(KEYCODE_SLASH) PORT_CHAR('/') PORT_CHAR('?')
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PORT_START("X12") /* IN4 KEY ROW 4 [+60] */
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PORT_BIT( 0x80, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_NAME("Shift") PORT_CODE(KEYCODE_LSHIFT) PORT_CODE(KEYCODE_RSHIFT)
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PORT_BIT( 0x80, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_NAME("Shift") PORT_CODE(KEYCODE_LSHIFT) PORT_CODE(KEYCODE_RSHIFT) PORT_CHAR(UCHAR_SHIFT_1)
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PORT_START("X13") /* IN5 KEY ROW 5 [+68] */
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PORT_BIT( 0x80, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_NAME("Ctrl") PORT_CODE(KEYCODE_LCONTROL) PORT_CODE(KEYCODE_RCONTROL)
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PORT_BIT( 0x80, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_NAME("Ctrl") PORT_CODE(KEYCODE_LCONTROL) PORT_CODE(KEYCODE_RCONTROL) PORT_CHAR(UCHAR_SHIFT_2)
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PORT_START("X14") /* IN6 KEY ROW 6 [+70] */
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PORT_BIT( 0x80, IP_ACTIVE_HIGH, IPT_KEYBOARD ) PORT_NAME("Alt") PORT_CODE(KEYCODE_LALT) PORT_CODE(KEYCODE_RALT)
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@ -643,7 +627,7 @@ static MACHINE_CONFIG_START( mbee, mbee_state )
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MCFG_CPU_IO_MAP(mbee_io)
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MCFG_CPU_CONFIG(mbee_daisy_chain)
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MCFG_MACHINE_RESET_OVERRIDE(mbee_state, mbee )
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MCFG_MACHINE_RESET_OVERRIDE(mbee_state, mbee)
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MCFG_DEVICE_ADD("z80pio", Z80PIO, XTAL_12MHz / 6)
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MCFG_Z80PIO_OUT_INT_CB(INPUTLINE("maincpu", INPUT_LINE_IRQ0))
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@ -699,7 +683,7 @@ static MACHINE_CONFIG_START( mbeeic, mbee_state )
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MCFG_CPU_CONFIG(mbee_daisy_chain)
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//MCFG_CPU_VBLANK_INT_DRIVER("screen", mbee_state, mbee_interrupt)
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MCFG_MACHINE_RESET_OVERRIDE(mbee_state, mbee )
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MCFG_MACHINE_RESET_OVERRIDE(mbee_state, mbee)
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MCFG_DEVICE_ADD("z80pio", Z80PIO, 3375000)
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MCFG_Z80PIO_OUT_INT_CB(INPUTLINE("maincpu", INPUT_LINE_IRQ0))
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@ -787,7 +771,7 @@ static MACHINE_CONFIG_DERIVED( mbee56, mbeeic )
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MCFG_CPU_MODIFY( "maincpu" )
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MCFG_CPU_PROGRAM_MAP(mbee56_mem)
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MCFG_CPU_IO_MAP(mbee56_io)
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MCFG_MACHINE_RESET_OVERRIDE(mbee_state, mbee56 )
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MCFG_MACHINE_RESET_OVERRIDE(mbee_state, mbee56)
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MCFG_WD2793x_ADD("fdc", XTAL_4MHz / 4) // divided by 2 externally, then divided by 2 internally (/ENMF pin not emulated)
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MCFG_WD_FDC_INTRQ_CALLBACK(WRITELINE(mbee_state, fdc_intrq_w))
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MCFG_WD_FDC_DRQ_CALLBACK(WRITELINE(mbee_state, fdc_drq_w))
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@ -799,14 +783,14 @@ static MACHINE_CONFIG_DERIVED( mbee64, mbee56 )
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MCFG_CPU_MODIFY( "maincpu" )
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MCFG_CPU_PROGRAM_MAP(mbee64_mem)
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MCFG_CPU_IO_MAP(mbee64_io)
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MCFG_MACHINE_RESET_OVERRIDE(mbee_state, mbee64 )
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MCFG_MACHINE_RESET_OVERRIDE(mbee_state, mbee64)
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MACHINE_CONFIG_END
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static MACHINE_CONFIG_DERIVED( mbee128, mbeeppc )
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MCFG_CPU_MODIFY( "maincpu" )
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MCFG_CPU_PROGRAM_MAP(mbee128_mem)
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MCFG_CPU_PROGRAM_MAP(mbee256_mem)
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MCFG_CPU_IO_MAP(mbee128_io)
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MCFG_MACHINE_RESET_OVERRIDE(mbee_state, mbee128 )
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MCFG_MACHINE_RESET_OVERRIDE(mbee_state, mbee128)
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MCFG_WD2793x_ADD("fdc", XTAL_4MHz / 4)
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MCFG_WD_FDC_INTRQ_CALLBACK(WRITELINE(mbee_state, fdc_intrq_w))
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MCFG_WD_FDC_DRQ_CALLBACK(WRITELINE(mbee_state, fdc_drq_w))
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@ -818,7 +802,7 @@ static MACHINE_CONFIG_DERIVED( mbee256, mbee128 )
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MCFG_CPU_MODIFY( "maincpu" )
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MCFG_CPU_PROGRAM_MAP(mbee256_mem)
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MCFG_CPU_IO_MAP(mbee256_io)
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MCFG_MACHINE_RESET_OVERRIDE(mbee_state, mbee256 )
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MCFG_MACHINE_RESET_OVERRIDE(mbee_state, mbee256)
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MCFG_MC146818_ADD( "rtc", XTAL_32_768kHz )
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MCFG_DEVICE_REMOVE("crtc")
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@ -892,7 +876,6 @@ ROM_START( mbeeic )
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ROM_REGION(0x10000,"maincpu", ROMREGION_ERASEFF)
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ROM_LOAD("bas522a.rom", 0x8000, 0x2000, CRC(7896a696) SHA1(a158f7803296766160e1f258dfc46134735a9477) )
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ROM_LOAD("bas522b.rom", 0xa000, 0x2000, CRC(b21d9679) SHA1(332844433763331e9483409cd7da3f90ac58259d) )
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ROM_LOAD_OPTIONAL("telcom12.rom", 0xe000, 0x1000, CRC(0231bda3) SHA1(be7b32499034f985cc8f7865f2bc2b78c485585c) )
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/* PAK option roms */
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@ -1119,9 +1102,9 @@ ROM_START( mbee64 ) // CIAB (Computer-In-A-Book)
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ROM_END
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ROM_START( mbee128 ) // 128K
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ROM_REGION(0x20000,"maincpu", ROMREGION_ERASEFF)
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ROM_REGION(0x20000, "rams", ROMREGION_ERASEFF)
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ROM_REGION(0x7000,"bootrom", ROMREGION_ERASEFF)
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ROM_REGION(0x8000, "roms", 0) // rom plus optional undumped roms plus dummy area
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ROM_SYSTEM_BIOS( 0, "bn60", "Version 2.03" )
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ROMX_LOAD("bn60.rom", 0x0000, 0x2000, CRC(ed15d4ee) SHA1(3ea42b63d42b9a4c5402676dee8912ad1f906bda), ROM_BIOS(1) )
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ROM_SYSTEM_BIOS( 1, "bn59", "Version 2.02" )
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@ -1135,6 +1118,9 @@ ROM_START( mbee128 ) // 128K
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ROM_SYSTEM_BIOS( 5, "hd18", "Hard Disk System" )
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ROMX_LOAD("hd18.rom", 0x0000, 0x2000, CRC(ed53ace7) SHA1(534e2e00cc527197c76b3c106b3c9ff7f1328487), ROM_BIOS(6) )
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ROM_REGION(0x4000, "proms", 0) // undumped; using prom from 256tc for now
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ROM_LOAD( "silver.u39", 0x0000, 0x4000, BAD_DUMP CRC(c34aab64) SHA1(781fe648488dec90185760f8e081e488b73b68bf) )
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ROM_REGION(0x9800, "gfx", 0)
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ROM_LOAD("charrom.bin", 0x1000, 0x1000, CRC(1f9fcee4) SHA1(e57ac94e03638075dde68a0a8c834a4f84ba47b0) )
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ROM_RELOAD( 0x0000, 0x1000 )
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@ -276,7 +276,7 @@ TIMER_CALLBACK_MEMBER(mbee_state::mbee_rtc_irq)
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void mbee_state::mbee256_setup_banks(UINT8 data)
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{
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data &= 0x3f; // U28 (bits 0-5 are referred to as S0-S5)
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// (bits 0-5 are referred to as S0-S5)
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address_space &mem = m_maincpu->space(AS_PROGRAM);
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UINT8 *prom = memregion("proms")->base();
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UINT8 b_data = BITSWAP8(data, 7,5,3,2,4,6,1,0) & 0x3b; // arrange data bits to S0,S1,-,S4,S2,S3
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@ -338,7 +338,7 @@ void mbee_state::mbee256_setup_banks(UINT8 data)
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WRITE8_MEMBER( mbee_state::mbee256_50_w )
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{
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mbee256_setup_banks(data);
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mbee256_setup_banks(data & 0x3f);
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}
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/***********************************************************
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@ -356,72 +356,7 @@ WRITE8_MEMBER( mbee_state::mbee256_50_w )
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WRITE8_MEMBER( mbee_state::mbee128_50_w )
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{
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address_space &mem = m_maincpu->space(AS_PROGRAM);
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// primary low banks
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m_boot->set_entry((data & 3));
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m_bank1->set_entry((data & 3));
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// 9000-EFFF
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m_bank9->set_entry((data & 4) ? 1 : 0);
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// 8000-8FFF, F000-FFFF
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mem.unmap_readwrite (0x8000, 0x87ff);
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mem.unmap_readwrite (0x8800, 0x8fff);
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mem.unmap_readwrite (0xf000, 0xf7ff);
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mem.unmap_readwrite (0xf800, 0xffff);
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switch (data & 0x1c)
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{
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case 0x00:
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mem.install_read_bank (0x8000, 0x87ff, "bank8l");
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mem.install_read_bank (0x8800, 0x8fff, "bank8h");
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mem.install_readwrite_handler (0xf000, 0xf7ff, read8_delegate(FUNC(mbee_state::mbeeppc_low_r),this), write8_delegate(FUNC(mbee_state::mbeeppc_low_w),this));
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mem.install_readwrite_handler (0xf800, 0xffff, read8_delegate(FUNC(mbee_state::mbeeppc_high_r),this), write8_delegate(FUNC(mbee_state::mbeeppc_high_w),this));
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m_bank8l->set_entry(0); // rom
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m_bank8h->set_entry(0); // rom
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break;
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case 0x04:
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// these 2 lines were read_bank but readwrite is needed for bios 2,3,4,5 to boot
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mem.install_readwrite_bank (0x8000, 0x87ff, "bank8l");
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mem.install_readwrite_bank (0x8800, 0x8fff, "bank8h");
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mem.install_readwrite_handler (0xf000, 0xf7ff, read8_delegate(FUNC(mbee_state::mbeeppc_low_r),this), write8_delegate(FUNC(mbee_state::mbeeppc_low_w),this));
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mem.install_readwrite_handler (0xf800, 0xffff, read8_delegate(FUNC(mbee_state::mbeeppc_high_r),this), write8_delegate(FUNC(mbee_state::mbeeppc_high_w),this));
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m_bank8l->set_entry(1); // ram
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m_bank8h->set_entry(1); // ram
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break;
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case 0x08:
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case 0x18:
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mem.install_read_bank (0x8000, 0x87ff, "bank8l");
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mem.install_read_bank (0x8800, 0x8fff, "bank8h");
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mem.install_read_bank (0xf000, 0xf7ff, "bankfl");
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mem.install_read_bank (0xf800, 0xffff, "bankfh");
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m_bank8l->set_entry(0); // rom
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m_bank8h->set_entry(0); // rom
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m_bankfl->set_entry(0); // ram
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m_bankfh->set_entry(0); // ram
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break;
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case 0x0c:
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case 0x1c:
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mem.install_read_bank (0x8000, 0x87ff, "bank8l");
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mem.install_read_bank (0x8800, 0x8fff, "bank8h");
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mem.install_read_bank (0xf000, 0xf7ff, "bankfl");
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mem.install_read_bank (0xf800, 0xffff, "bankfh");
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m_bank8l->set_entry(1); // ram
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m_bank8h->set_entry(1); // ram
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m_bankfl->set_entry(0); // ram
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m_bankfh->set_entry(0); // ram
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break;
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case 0x10:
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case 0x14:
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mem.install_readwrite_handler (0x8000, 0x87ff, read8_delegate(FUNC(mbee_state::mbeeppc_low_r),this), write8_delegate(FUNC(mbee_state::mbeeppc_low_w),this));
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mem.install_readwrite_handler (0x8800, 0x8fff, read8_delegate(FUNC(mbee_state::mbeeppc_high_r),this), write8_delegate(FUNC(mbee_state::mbeeppc_high_w),this));
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mem.install_read_bank (0xf000, 0xf7ff, "bankfl");
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mem.install_read_bank (0xf800, 0xffff, "bankfh");
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m_bankfl->set_entry(0); // ram
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m_bankfh->set_entry(0); // ram
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break;
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}
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mbee256_setup_banks(data & 0x1f); // S5 not used
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}
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@ -507,7 +442,7 @@ READ8_MEMBER( mbee_state::mbeepc_telcom_high_r )
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/* after the first 4 bytes have been read from ROM, switch the ram back in */
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TIMER_CALLBACK_MEMBER(mbee_state::mbee_reset)
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TIMER_CALLBACK_MEMBER( mbee_state::mbee_reset )
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{
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m_boot->set_entry(0);
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}
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@ -517,20 +452,20 @@ void mbee_state::machine_reset_common_disk()
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m_fdc_rq = 0;
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}
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MACHINE_RESET_MEMBER(mbee_state,mbee)
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MACHINE_RESET_MEMBER( mbee_state, mbee )
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{
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m_boot->set_entry(1);
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timer_set(attotime::from_usec(4), TIMER_MBEE_RESET);
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}
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MACHINE_RESET_MEMBER(mbee_state,mbee56)
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MACHINE_RESET_MEMBER( mbee_state, mbee56 )
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{
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machine_reset_common_disk();
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m_boot->set_entry(1);
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timer_set(attotime::from_usec(4), TIMER_MBEE_RESET);
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}
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MACHINE_RESET_MEMBER(mbee_state,mbee64)
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MACHINE_RESET_MEMBER( mbee_state, mbee64 )
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{
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machine_reset_common_disk();
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m_boot->set_entry(1);
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@ -538,25 +473,24 @@ MACHINE_RESET_MEMBER(mbee_state,mbee64)
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m_bankh->set_entry(1);
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}
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MACHINE_RESET_MEMBER(mbee_state,mbee128)
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MACHINE_RESET_MEMBER( mbee_state, mbee128 )
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{
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address_space &mem = m_maincpu->space(AS_IO);
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machine_reset_common_disk();
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mbee128_50_w(mem,0,0); // set banks to default
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m_boot->set_entry(8); // boot time
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}
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MACHINE_RESET_MEMBER(mbee_state,mbee256)
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{
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UINT8 i;
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machine_reset_common_disk();
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for (i = 0; i < 15; i++) m_mbee256_was_pressed[i] = 0;
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m_mbee256_q_pos = 0;
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mbee256_setup_banks(0); // set banks to default
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m_maincpu->set_pc(0x8000);
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}
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MACHINE_RESET_MEMBER(mbee_state,mbeett)
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MACHINE_RESET_MEMBER( mbee_state, mbee256 )
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{
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UINT8 i;
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for (i = 0; i < 15; i++) m_mbee256_was_pressed[i] = 0;
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m_mbee256_q_pos = 0;
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machine_reset_common_disk();
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mbee256_setup_banks(0); // set banks to default
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m_maincpu->set_pc(0x8000);
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}
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MACHINE_RESET_MEMBER( mbee_state, mbeett )
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{
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UINT8 i;
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||||
for (i = 0; i < 15; i++) m_mbee256_was_pressed[i] = 0;
|
||||
@ -565,7 +499,7 @@ MACHINE_RESET_MEMBER(mbee_state,mbeett)
|
||||
timer_set(attotime::from_usec(4), TIMER_MBEE_RESET);
|
||||
}
|
||||
|
||||
INTERRUPT_GEN_MEMBER(mbee_state::mbee_interrupt)
|
||||
INTERRUPT_GEN_MEMBER( mbee_state::mbee_interrupt )
|
||||
{
|
||||
// Due to the uncertainly and hackage here, this is commented out for now - Robbbert - 05-Oct-2010
|
||||
#if 0
|
||||
@ -588,14 +522,14 @@ INTERRUPT_GEN_MEMBER(mbee_state::mbee_interrupt)
|
||||
#endif
|
||||
}
|
||||
|
||||
DRIVER_INIT_MEMBER(mbee_state,mbee)
|
||||
DRIVER_INIT_MEMBER( mbee_state, mbee )
|
||||
{
|
||||
UINT8 *RAM = memregion("maincpu")->base();
|
||||
m_boot->configure_entries(0, 2, &RAM[0x0000], 0x8000);
|
||||
m_size = 0x4000;
|
||||
}
|
||||
|
||||
DRIVER_INIT_MEMBER(mbee_state,mbeeic)
|
||||
DRIVER_INIT_MEMBER( mbee_state, mbeeic )
|
||||
{
|
||||
UINT8 *RAM = memregion("maincpu")->base();
|
||||
m_boot->configure_entries(0, 2, &RAM[0x0000], 0x8000);
|
||||
@ -607,7 +541,7 @@ DRIVER_INIT_MEMBER(mbee_state,mbeeic)
|
||||
m_size = 0x8000;
|
||||
}
|
||||
|
||||
DRIVER_INIT_MEMBER(mbee_state,mbeepc)
|
||||
DRIVER_INIT_MEMBER( mbee_state, mbeepc )
|
||||
{
|
||||
UINT8 *RAM = memregion("maincpu")->base();
|
||||
m_boot->configure_entries(0, 2, &RAM[0x0000], 0x8000);
|
||||
@ -623,7 +557,7 @@ DRIVER_INIT_MEMBER(mbee_state,mbeepc)
|
||||
m_size = 0x8000;
|
||||
}
|
||||
|
||||
DRIVER_INIT_MEMBER(mbee_state,mbeepc85)
|
||||
DRIVER_INIT_MEMBER( mbee_state, mbeepc85 )
|
||||
{
|
||||
UINT8 *RAM = memregion("maincpu")->base();
|
||||
m_boot->configure_entries(0, 2, &RAM[0x0000], 0x8000);
|
||||
@ -639,7 +573,7 @@ DRIVER_INIT_MEMBER(mbee_state,mbeepc85)
|
||||
m_size = 0x8000;
|
||||
}
|
||||
|
||||
DRIVER_INIT_MEMBER(mbee_state,mbeeppc)
|
||||
DRIVER_INIT_MEMBER( mbee_state, mbeeppc )
|
||||
{
|
||||
UINT8 *RAM = memregion("maincpu")->base();
|
||||
m_boot->configure_entry(0, &RAM[0x0000]);
|
||||
@ -660,14 +594,14 @@ DRIVER_INIT_MEMBER(mbee_state,mbeeppc)
|
||||
m_size = 0x8000;
|
||||
}
|
||||
|
||||
DRIVER_INIT_MEMBER(mbee_state,mbee56)
|
||||
DRIVER_INIT_MEMBER( mbee_state, mbee56 )
|
||||
{
|
||||
UINT8 *RAM = memregion("maincpu")->base();
|
||||
m_boot->configure_entries(0, 2, &RAM[0x0000], 0xe000);
|
||||
m_size = 0xe000;
|
||||
}
|
||||
|
||||
DRIVER_INIT_MEMBER(mbee_state,mbee64)
|
||||
DRIVER_INIT_MEMBER( mbee_state, mbee64 )
|
||||
{
|
||||
UINT8 *RAM = memregion("maincpu")->base();
|
||||
m_boot->configure_entry(0, &RAM[0x0000]);
|
||||
@ -682,27 +616,27 @@ DRIVER_INIT_MEMBER(mbee_state,mbee64)
|
||||
m_size = 0xf000;
|
||||
}
|
||||
|
||||
DRIVER_INIT_MEMBER(mbee_state,mbee128)
|
||||
DRIVER_INIT_MEMBER( mbee_state, mbee128 )
|
||||
{
|
||||
UINT8 *RAM = memregion("maincpu")->base();
|
||||
m_boot->configure_entries(0, 4, &RAM[0x0000], 0x8000); // standard banks 0000
|
||||
m_bank1->configure_entries(0, 4, &RAM[0x1000], 0x8000); // standard banks 1000
|
||||
m_bank8l->configure_entry(1, &RAM[0x0000]); // shadow ram
|
||||
m_bank8h->configure_entry(1, &RAM[0x0800]); // shadow ram
|
||||
m_bank9->configure_entry(1, &RAM[0x1000]); // shadow ram
|
||||
m_bankfl->configure_entry(0, &RAM[0xf000]); // shadow ram
|
||||
m_bankfh->configure_entry(0, &RAM[0xf800]); // shadow ram
|
||||
UINT8 *RAM = memregion("rams")->base();
|
||||
UINT8 *ROM = memregion("roms")->base();
|
||||
char banktag[10];
|
||||
|
||||
RAM = memregion("bootrom")->base();
|
||||
m_bank9->configure_entry(0, &RAM[0x1000]); // rom
|
||||
m_boot->configure_entry(8, &RAM[0x0000]); // rom at boot for 4usec
|
||||
m_bank8l->configure_entry(0, &RAM[0x0000]); // rom
|
||||
m_bank8h->configure_entry(0, &RAM[0x0800]); // rom
|
||||
for (UINT8 b_bank = 0; b_bank < 16; b_bank++)
|
||||
{
|
||||
sprintf(banktag, "bankr%d", b_bank);
|
||||
membank(banktag)->configure_entries(0, 32, &RAM[0x0000], 0x1000); // RAM banks
|
||||
membank(banktag)->configure_entries(64, 4, &ROM[0x0000], 0x1000); // rom
|
||||
|
||||
sprintf(banktag, "bankw%d", b_bank);
|
||||
membank(banktag)->configure_entries(0, 32, &RAM[0x0000], 0x1000); // RAM banks
|
||||
membank(banktag)->configure_entries(64, 1, &ROM[0x4000], 0x1000); // dummy rom
|
||||
}
|
||||
|
||||
m_size = 0x8000;
|
||||
}
|
||||
|
||||
DRIVER_INIT_MEMBER(mbee_state,mbee256)
|
||||
DRIVER_INIT_MEMBER( mbee_state, mbee256 )
|
||||
{
|
||||
UINT8 *RAM = memregion("rams")->base();
|
||||
UINT8 *ROM = memregion("roms")->base();
|
||||
@ -725,7 +659,7 @@ DRIVER_INIT_MEMBER(mbee_state,mbee256)
|
||||
m_size = 0x8000;
|
||||
}
|
||||
|
||||
DRIVER_INIT_MEMBER(mbee_state,mbeett)
|
||||
DRIVER_INIT_MEMBER( mbee_state, mbeett )
|
||||
{
|
||||
UINT8 *RAM = memregion("maincpu")->base();
|
||||
m_boot->configure_entries(0, 2, &RAM[0x0000], 0x8000);
|
||||
|
||||
Loading…
Reference in New Issue
Block a user