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https://github.com/holub/mame
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i8089.c: implemented dma engine, apricot now successfully runs the 8089 self-test
This commit is contained in:
Dirk Best
parent
cdfce086df
commit
c1cef2a6e9
@ -11,7 +11,20 @@
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// MACROS/CONSTANTS
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//**************************************************************************
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#define VERBOSE 1
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#define VERBOSE 1
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#define VERBOSE_DMA 1
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// channel control register fields
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#define CC_TMC ((m_r[CC].w >> 0) & 0x07) // terminate on masked compare
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#define CC_TBC ((m_r[CC].w >> 3) & 0x03) // terminate on byte count
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#define CC_TX ((m_r[CC].w >> 5) & 0x03) // terminate on external signal
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#define CC_TS ((m_r[CC].w >> 7) & 0x01) // terminate on single transfer
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#define CC_CHAIN ((m_r[CC].w >> 8) & 0x01) // chaining
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#define CC_LOCK ((m_r[CC].w >> 9) & 0x01) // actuate lock
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#define CC_SOURCE ((m_r[CC].w >> 10) & 0x01) // source register
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#define CC_SYNC ((m_r[CC].w >> 11) & 0x03) // synchronization
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#define CC_TRANS ((m_r[CC].w >> 13) & 0x01) // translation
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#define CC_FUNC ((m_r[CC].w >> 14) & 0x03) // function
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//**************************************************************************
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@ -149,6 +162,27 @@ private:
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i8089_device *m_iop;
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// dma
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void terminate_dma(int offset);
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bool m_xfer_pending;
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UINT16 m_dma_value;
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int m_dma_state;
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// dma state
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enum
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{
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DMA_IDLE,
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DMA_WAIT_FOR_SOURCE_DRQ,
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DMA_FETCH,
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DMA_TRANSLATE,
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DMA_WAIT_FOR_DEST_DRQ,
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DMA_STORE,
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DMA_STORE_BYTE_HIGH,
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DMA_COMPARE,
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DMA_TERMINATE
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};
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// register
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enum
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{
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@ -179,7 +213,10 @@ i8089_channel::i8089_channel(const machine_config &mconfig, const char *tag, dev
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device_t(mconfig, I8089_CHANNEL, "Intel 8089 I/O Channel", tag, owner, clock, "i8089_channel", __FILE__),
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device_execute_interface(mconfig, *this),
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m_icount(0),
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m_write_sintr(*this)
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m_write_sintr(*this),
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m_xfer_pending(false),
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m_dma_value(0),
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m_dma_state(DMA_IDLE)
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{
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}
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@ -195,6 +232,10 @@ void i8089_channel::device_start()
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m_write_sintr.resolve_safe();
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// register for save states
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save_item(NAME(m_xfer_pending));
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save_item(NAME(m_dma_value));
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save_item(NAME(m_dma_state));
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for (int i = 0; i < ARRAY_LENGTH(m_r); i++)
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{
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save_item(NAME(m_r[i].w), i);
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@ -204,6 +245,8 @@ void i8089_channel::device_start()
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void i8089_channel::device_reset()
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{
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m_xfer_pending = false;
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// initialize registers
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for (int i = 0; i < ARRAY_LENGTH(m_r); i++)
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{
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@ -257,11 +300,21 @@ UINT8 i8089_channel::imm8()
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UINT16 i8089_channel::imm16()
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{
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UINT8 imm16 = m_iop->read_word(m_r[TP].w);
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UINT16 imm16 = m_iop->read_word(m_r[TP].w);
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m_r[TP].w += 2;
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return imm16;
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}
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// adjust task pointer and continue execution
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void i8089_channel::terminate_dma(int offset)
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{
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logerror("%s('%s'): terminating dma transfer\n", shortname(), tag());
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m_r[TP].w += offset;
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m_r[PSW].w |= 1 << 2;
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m_r[PSW].w &= ~(1 << 6);
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m_dma_state = DMA_IDLE;
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}
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void i8089_channel::execute_run()
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{
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do
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@ -269,12 +322,187 @@ void i8089_channel::execute_run()
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// active transfer?
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if (BIT(m_r[PSW].w, 6))
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{
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m_icount = 0;
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// new transfer?
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if (BIT(m_r[PSW].w, 2))
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{
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// we are no longer executing task blocks
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m_r[PSW].w &= ~(1 << 2);
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m_xfer_pending = false;
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if (VERBOSE)
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{
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logerror("%s('%s'): ---- starting dma transfer ----\n", shortname(), tag());
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logerror("%s('%s'): ga = %06x, gb = %06x, gc = %06x\n", shortname(), tag(), m_r[GA].w, m_r[GB].w, m_r[GC].w);
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logerror("%s('%s'): bc = %04x, cc = %04x, mc = %04x\n", shortname(), tag(), m_r[BC].w, m_r[CC].w, m_r[MC].w);
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}
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}
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// todo: port transfers
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if (CC_FUNC != 0x03)
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fatalerror("%s('%s'): port transfer\n", shortname(), tag());
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switch (m_dma_state)
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{
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case DMA_IDLE:
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if (VERBOSE_DMA)
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logerror("%s('%s'): entering state: DMA_IDLE (bc = %04x)\n", shortname(), tag(), m_r[BC].w);
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// synchronize on source?
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if (CC_SYNC == 0x01)
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m_dma_state = DMA_WAIT_FOR_SOURCE_DRQ;
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else
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m_dma_state = DMA_FETCH;
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break;
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case DMA_WAIT_FOR_SOURCE_DRQ:
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fatalerror("%s('%s'): wait for source drq not supported\n", shortname(), tag());
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break;
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case DMA_FETCH:
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if (VERBOSE_DMA)
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logerror("%s('%s'): entering state: DMA_FETCH", shortname(), tag());
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// source is 16-bit?
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if (BIT(m_r[PSW].w, 1))
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{
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m_dma_value = m_iop->read_word(m_r[GA + CC_SOURCE].w);
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m_r[GA + CC_SOURCE].w += 2;
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m_r[BC].w -= 2;
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}
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// destination is 16-bit, byte count is even
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else if (BIT(m_r[PSW].w, 0) && !(m_r[BC].w & 1))
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{
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m_dma_value = m_iop->read_byte(m_r[GA + CC_SOURCE].w);
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m_r[GA + CC_SOURCE].w++;
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m_r[BC].w--;
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}
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// destination is 16-bit, byte count is odd
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else if (BIT(m_r[PSW].w, 0) && (m_r[BC].w & 1))
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{
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m_dma_value |= m_iop->read_byte(m_r[GA + CC_SOURCE].w) << 8;
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m_r[GA + CC_SOURCE].w++;
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m_r[BC].w--;
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}
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// 8-bit transfer
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else
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{
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m_dma_value = m_iop->read_byte(m_r[GA + CC_SOURCE].w);
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m_r[GA + CC_SOURCE].w++;
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m_r[BC].w--;
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}
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if (VERBOSE_DMA)
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logerror("[ %04x ]\n", m_dma_value);
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if (BIT(m_r[PSW].w, 0) && (m_r[BC].w & 1))
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m_dma_state = DMA_FETCH;
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else if (CC_TRANS)
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m_dma_state = DMA_TRANSLATE;
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else if (CC_SYNC == 0x02)
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m_dma_state = DMA_WAIT_FOR_DEST_DRQ;
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else
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m_dma_state = DMA_STORE;
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break;
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case DMA_TRANSLATE:
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fatalerror("%s('%s'): dma translate requested\n", shortname(), tag());
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break;
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case DMA_WAIT_FOR_DEST_DRQ:
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fatalerror("%s('%s'): wait for destination drq not supported\n", shortname(), tag());
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break;
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case DMA_STORE:
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if (VERBOSE_DMA)
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logerror("%s('%s'): entering state: DMA_STORE", shortname(), tag());
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// destination is 16-bit?
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if (BIT(m_r[PSW].w, 0))
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{
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m_iop->write_word(m_r[GB - CC_SOURCE].w, m_dma_value);
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m_r[GB - CC_SOURCE].w += 2;
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if (VERBOSE_DMA)
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logerror("[ %04x ]\n", m_dma_value);
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}
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// destination is 8-bit
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else
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{
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m_iop->write_byte(m_r[GB - CC_SOURCE].w, m_dma_value & 0xff);
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m_r[GB - CC_SOURCE].w++;
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if (VERBOSE_DMA)
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logerror("[ %02x ]\n", m_dma_value & 0xff);
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}
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if (CC_TMC & 0x03)
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m_dma_state = DMA_COMPARE;
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else
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m_dma_state = DMA_TERMINATE;
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break;
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case DMA_COMPARE:
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fatalerror("%s('%s'): dma compare requested\n", shortname(), tag());
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break;
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case DMA_TERMINATE:
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if (VERBOSE_DMA)
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logerror("%s('%s'): entering state: DMA_TERMINATE\n", shortname(), tag());
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// terminate on masked compare?
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if (CC_TMC & 0x03)
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fatalerror("%s('%s'): terminate on masked compare not supported\n", shortname(), tag());
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// terminate on byte count?
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else if (CC_TBC && m_r[BC].w == 0)
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terminate_dma((CC_TBC - 1) * 4);
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// terminate on external signal
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else if (CC_TX)
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fatalerror("%s('%s'): terminate on external signal not supported\n", shortname(), tag());
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// terminate on single transfer
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else if (CC_TS)
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fatalerror("%s('%s'): terminate on single transfer not supported\n", shortname(), tag());
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// not terminated, continue transfer
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else
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// do we need to read another byte?
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if (BIT(m_r[PSW].w, 1) && !BIT(m_r[PSW].w, 0))
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if (CC_SYNC == 0x02)
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m_dma_state = DMA_WAIT_FOR_DEST_DRQ;
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else
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m_dma_state = DMA_STORE_BYTE_HIGH;
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// transfer done
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else
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m_dma_state = DMA_IDLE;
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break;
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case DMA_STORE_BYTE_HIGH:
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if (VERBOSE_DMA)
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logerror("%s('%s'): entering state: DMA_STORE_BYTE_HIGH[ %02x ]\n", shortname(), tag(), (m_dma_value >> 8) & 0xff);
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m_iop->write_byte(m_r[GB - CC_SOURCE].w, (m_dma_value >> 8) & 0xff);
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m_r[GB - CC_SOURCE].w++;
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m_dma_state = DMA_TERMINATE;
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break;
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}
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m_icount--;
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}
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// executing task block instructions?
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else if (BIT(m_r[PSW].w, 2))
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{
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// dma transfer pending?
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if (m_xfer_pending)
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m_r[PSW].w |= 1 << 6;
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// fetch first two instruction bytes
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UINT16 op = m_iop->read_word(m_r[TP].w);
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m_r[TP].w += 2;
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@ -296,6 +524,8 @@ void i8089_channel::execute_run()
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UINT8 o;
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UINT16 off, seg;
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logerror("%s('%s'): executing %x %x %x %x %02x %x\n", shortname(), tag(), brp, wb, aa, w, opc, mm);
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switch (opc)
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{
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case 0x00: // control
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@ -305,9 +535,7 @@ void i8089_channel::execute_run()
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case 1: invalid(opc); break;
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case 2: sintr(); break;
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case 3: xfer(); break;
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default:
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if (BIT(brp, 2))
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wid(BIT(brp, 1), BIT(brp, 0));
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default: wid(BIT(brp, 1), BIT(brp, 0));
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}
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break;
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@ -659,7 +887,7 @@ void i8089_channel::movb_mr(int m, int r, int o)
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void i8089_channel::movb_rm(int r, int m, int o)
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{
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UINT8 byte = m_iop->read_byte(m_r[m].w + o);
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m_r[r].w = (BIT(byte, 7) ? 0xffff0 : 0x00000) | byte;
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m_r[r].w = (BIT(byte, 7) ? 0xfff00 : 0x00000) | byte;
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m_r[r].t = 1;
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}
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@ -673,7 +901,7 @@ void i8089_channel::movb_mm(int m1, int m2, int o1, int o2)
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// move immediate byte to register
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void i8089_channel::movbi_ri(int r, int i)
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{
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m_r[r].w = (BIT(i, 7) ? 0xffff0 : 0x00000) | (i & 0xff);
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m_r[r].w = (BIT(i, 7) ? 0xfff00 : 0x00000) | (i & 0xff);
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m_r[r].t = 1;
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}
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@ -686,14 +914,14 @@ void i8089_channel::movbi_mi(int m, int i, int o)
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// move immediate word to register
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void i8089_channel::movi_ri(int r, int i)
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{
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m_r[r].w = (BIT(i, 15) ? 0xffff0 : 0x00000) | (i & 0xffff);
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m_r[r].w = (BIT(i, 15) ? 0xf0000 : 0x00000) | (i & 0xffff);
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m_r[r].t = 1;
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}
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// move immediate word to memory word
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void i8089_channel::movi_mi(int m, int i, int o)
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{
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m_iop->write_word(m_r[m].w + o, (BIT(i, 15) ? 0xffff0 : 0x00000) | (i & 0xffff));
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m_iop->write_word(m_r[m].w + o, (BIT(i, 15) ? 0xf0000 : 0x00000) | (i & 0xffff));
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}
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// move pointer to memory (store)
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@ -753,7 +981,11 @@ void i8089_channel::wid(int s, int d)
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m_r[PSW].w |= s << 1;
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}
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void i8089_channel::xfer() { UNIMPLEMENTED }
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// enter dma transfer mode after next instruction
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void i8089_channel::xfer()
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{
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m_xfer_pending = true;
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}
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void i8089_channel::invalid(int opc)
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{
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