mirror of
https://github.com/holub/mame
synced 2025-04-23 17:00:53 +03:00
midwayic: Added hooks for serial communication. (nw)
atlantis: Renamed uart ports. (nw) iteagle: Remapped service buttons to standard location. iteagle: Connected cdrom and started adding rs232 communication ports. (nw)
This commit is contained in:
Ted Green
parent
e6227e1896
commit
c3cefee1b2
@ -41,11 +41,11 @@ DEVICE_ADDRESS_MAP_START(bus_master_map, 32, ide_pci_device)
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ADDRESS_MAP_END
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static MACHINE_CONFIG_FRAGMENT(pci_ide)
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MCFG_BUS_MASTER_IDE_CONTROLLER_ADD("ide", ata_devices, "hdd", nullptr, true)
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MCFG_BUS_MASTER_IDE_CONTROLLER_ADD("ide", ata_devices, "hdd", "cdrom", true)
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MCFG_ATA_INTERFACE_IRQ_HANDLER(WRITELINE(ide_pci_device, ide_interrupt))
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//MCFG_BUS_MASTER_IDE_CONTROLLER_SPACE(":maincpu", AS_PROGRAM)
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MCFG_BUS_MASTER_IDE_CONTROLLER_SPACE(":pci:00.0", AS_DATA)
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MCFG_BUS_MASTER_IDE_CONTROLLER_ADD("ide2", ata_devices, nullptr, "cdrom", true)
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MCFG_BUS_MASTER_IDE_CONTROLLER_ADD("ide2", ata_devices, "hdd", "cdrom", true)
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MCFG_ATA_INTERFACE_IRQ_HANDLER(WRITELINE(ide_pci_device, ide_interrupt))
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//MCFG_BUS_MASTER_IDE_CONTROLLER_SPACE(":maincpu", AS_PROGRAM)
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MCFG_BUS_MASTER_IDE_CONTROLLER_SPACE(":pci:00.0", AS_DATA)
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@ -298,6 +298,11 @@ public:
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return ((color & 0x7c00) << 9) | ((color & 0x3e0) << 6) | ((color & 0x1f) << 3);
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}
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inline uint32_t conv_rgb565_to_rgb32(uint16_t color)
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{
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return ((color & 0x7c00) << 9) | ((color & 0x3e0) << 6) | ((color & 0x8000) >> 5) | ((color & 0x1f) << 3);
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}
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#ifdef UNUSED_FUNCTION
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inline void WAVERAM_plot(int y, int x, uint32_t color)
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{
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@ -38,6 +38,8 @@
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#include "machine/idectrl.h"
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#include "machine/midwayic.h"
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#include "machine/ins8250.h"
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#include "bus/rs232/rs232.h"
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#include "machine/terminal.h"
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#include "audio/dcs.h"
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#include "machine/pci.h"
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#include "machine/vrc4373.h"
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@ -64,8 +66,8 @@
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#define GALILEO_IRQ_SHIFT 1
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#define ZEUS_IRQ_SHIFT 2
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#define PARALLEL_IRQ_SHIFT 3
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#define UART0_SHIFT 4
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#define UART1_SHIFT 5
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#define UART1_SHIFT 4
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#define UART2_SHIFT 5
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#define VBLANK_IRQ_SHIFT 7
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/* static interrupts */
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@ -73,6 +75,7 @@
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#define VBLANK_IRQ_NUM MIPS3_IRQ3
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#define IDE_IRQ_NUM MIPS3_IRQ4
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#define DEBUG_CONSOLE (0)
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#define LOG_RTC (0)
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#define LOG_PORT (0)
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#define LOG_IRQ (0)
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@ -90,6 +93,7 @@ public:
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m_ioasic(*this, "ioasic"),
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m_uart0(*this, "uart0"),
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m_uart1(*this, "uart1"),
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m_uart2(*this, "uart2"),
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m_rtc(*this, "rtc")
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{ }
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DECLARE_DRIVER_INIT(mwskins);
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@ -102,8 +106,9 @@ public:
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required_device<zeus2_device> m_zeus;
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required_device<dcs_audio_device> m_dcs;
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required_device<midway_ioasic_device> m_ioasic;
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required_device<ns16550_device> m_uart0;
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optional_device<generic_terminal_device> m_uart0;
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required_device<ns16550_device> m_uart1;
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required_device<ns16550_device> m_uart2;
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required_device<nvram_device> m_rtc;
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uint8_t m_rtc_data[0x8000];
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@ -142,8 +147,8 @@ public:
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DECLARE_WRITE_LINE_MEMBER(ide_irq);
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DECLARE_WRITE_LINE_MEMBER(ioasic_irq);
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DECLARE_WRITE_LINE_MEMBER(uart0_irq_callback);
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DECLARE_WRITE_LINE_MEMBER(uart1_irq_callback);
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DECLARE_WRITE_LINE_MEMBER(uart2_irq_callback);
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DECLARE_CUSTOM_INPUT_MEMBER(port_mod_r);
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DECLARE_READ32_MEMBER(port_ctrl_r);
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@ -186,7 +191,7 @@ READ32_MEMBER(atlantis_state::board_ctrl_r)
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switch (newOffset) {
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case CTRL_STATUS:
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if (1 && m_screen->vblank())
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data |= 0x80;
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data |= 1 << VBLANK_IRQ_SHIFT;
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if (m_last_offset != (newOffset | 0x40000))
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if (LOG_IRQ)
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logerror("%s:board_ctrl_r read from CTRL_STATUS offset %04X = %08X & %08X bus offset = %08X\n", machine().describe_context(), newOffset, data, mem_mask, offset);
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@ -413,24 +418,6 @@ READ32_MEMBER(atlantis_state::user_io_input)
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return m_user_io_state;
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}
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/*************************************
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* UART0 interrupt handler
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*************************************/
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WRITE_LINE_MEMBER(atlantis_state::uart0_irq_callback)
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{
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uint32_t status_bit = (1 << UART0_SHIFT);
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if (state && !(board_ctrl[CTRL_STATUS] & status_bit)) {
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board_ctrl[CTRL_STATUS] |= status_bit;
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update_asic_irq();
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}
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else if (!state && (board_ctrl[CTRL_STATUS] & status_bit)) {
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board_ctrl[CTRL_STATUS] &= ~status_bit;
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board_ctrl[CTRL_CAUSE] &= ~status_bit;
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update_asic_irq();
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}
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logerror("atlantis_state::uart0_irq_callback state = %1x\n", state);
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}
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/*************************************
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* UART1 interrupt handler
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*************************************/
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@ -449,6 +436,24 @@ WRITE_LINE_MEMBER(atlantis_state::uart1_irq_callback)
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logerror("atlantis_state::uart1_irq_callback state = %1x\n", state);
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}
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/*************************************
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* UART2 interrupt handler
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*************************************/
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WRITE_LINE_MEMBER(atlantis_state::uart2_irq_callback)
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{
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uint32_t status_bit = (1 << UART2_SHIFT);
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if (state && !(board_ctrl[CTRL_STATUS] & status_bit)) {
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board_ctrl[CTRL_STATUS] |= status_bit;
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update_asic_irq();
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}
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else if (!state && (board_ctrl[CTRL_STATUS] & status_bit)) {
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board_ctrl[CTRL_STATUS] &= ~status_bit;
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board_ctrl[CTRL_CAUSE] &= ~status_bit;
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update_asic_irq();
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}
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logerror("atlantis_state::uart2_irq_callback state = %1x\n", state);
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}
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/*************************************
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* Video interrupts
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*************************************/
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@ -639,8 +644,8 @@ void atlantis_state::machine_reset()
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*************************************/
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static ADDRESS_MAP_START( map0, AS_PROGRAM, 32, atlantis_state )
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AM_RANGE(0x00000000, 0x0001ffff) AM_READWRITE8(cmos_r, cmos_w, 0xff)
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AM_RANGE(0x00100000, 0x0010001f) AM_DEVREADWRITE8("uart0", ns16550_device, ins8250_r, ins8250_w, 0xff) // Serial UART0 (TL16C552 CS0)
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AM_RANGE(0x00180000, 0x0018001f) AM_DEVREADWRITE8("uart1", ns16550_device, ins8250_r, ins8250_w, 0xff) // Serial UART1 (TL16C552 CS1)
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AM_RANGE(0x00100000, 0x0010001f) AM_DEVREADWRITE8("uart1", ns16550_device, ins8250_r, ins8250_w, 0xff) // Serial UART1 (TL16C552 CS0)
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AM_RANGE(0x00180000, 0x0018001f) AM_DEVREADWRITE8("uart2", ns16550_device, ins8250_r, ins8250_w, 0xff) // Serial UART2 (TL16C552 CS1)
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//AM_RANGE(0x00200000, 0x0020001f) // Parallel UART (TL16C552 CS2)
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AM_RANGE(0x00400000, 0x004000bf) AM_READWRITE8(blue_r, blue_w, 0xff)
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AM_RANGE(0x00880000, 0x00c80003) AM_READWRITE(board_ctrl_r, board_ctrl_w)
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@ -799,6 +804,15 @@ static INPUT_PORTS_START( mwskins )
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INPUT_PORTS_END
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static DEVICE_INPUT_DEFAULTS_START(mwskins_comm)
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DEVICE_INPUT_DEFAULTS("RS232_TXBAUD", 0xff, RS232_BAUD_14400)
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DEVICE_INPUT_DEFAULTS("RS232_RXBAUD", 0xff, RS232_BAUD_14400)
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DEVICE_INPUT_DEFAULTS("RS232_STARTBITS", 0xff, RS232_STARTBITS_1)
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DEVICE_INPUT_DEFAULTS("RS232_DATABITS", 0xff, RS232_DATABITS_8)
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DEVICE_INPUT_DEFAULTS("RS232_PARITY", 0xff, RS232_PARITY_NONE)
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DEVICE_INPUT_DEFAULTS("RS232_STOPBITS", 0xff, RS232_STOPBITS_1)
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DEVICE_INPUT_DEFAULTS_END
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/*************************************
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*
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* Machine driver
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@ -843,8 +857,8 @@ static MACHINE_CONFIG_START( mwskins, atlantis_state )
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/* sound hardware */
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//MCFG_DEVICE_ADD("dcs", DCS2_AUDIO_DSIO, 0)
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MCFG_DEVICE_ADD("dcs", DCS2_AUDIO_DENVER, 0)
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MCFG_DCS2_AUDIO_DRAM_IN_MB(4)
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MCFG_DCS2_AUDIO_POLLING_OFFSET(0) /* no place to hook :-( */
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MCFG_DCS2_AUDIO_DRAM_IN_MB(8)
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//MCFG_DCS2_AUDIO_POLLING_OFFSET(0) /* no place to hook :-( */
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MCFG_DEVICE_ADD("ioasic", MIDWAY_IOASIC, 0)
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MCFG_MIDWAY_IOASIC_SHUFFLE(MIDWAY_IOASIC_STANDARD)
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@ -852,17 +866,42 @@ static MACHINE_CONFIG_START( mwskins, atlantis_state )
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MCFG_MIDWAY_IOASIC_UPPER(325)
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MCFG_MIDWAY_IOASIC_IRQ_CALLBACK(WRITELINE(atlantis_state, ioasic_irq))
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MCFG_MIDWAY_IOASIC_AUTO_ACK(1)
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if DEBUG_CONSOLE {
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MCFG_MIDWAY_IOASIC_OUT_TX_CB(DEVWRITE8("uart0", generic_terminal_device, write))
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MCFG_DEVICE_ADD("uart0", GENERIC_TERMINAL, 0)
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MCFG_GENERIC_TERMINAL_KEYBOARD_CB(DEVWRITE8("ioasic", midway_ioasic_device, serial_rx_w))
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}
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// TL16C552 UART
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MCFG_DEVICE_ADD("uart0", NS16550, XTAL_24MHz)
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MCFG_INS8250_OUT_INT_CB(DEVWRITELINE(":", atlantis_state, uart0_irq_callback))
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MCFG_DEVICE_ADD("uart1", NS16550, XTAL_24MHz)
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MCFG_INS8250_OUT_INT_CB(DEVWRITELINE(":", atlantis_state, uart1_irq_callback))
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//MCFG_INS8250_OUT_TX_CB(DEVWRITELINE("com1", rs232_port_device, write_txd))
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//MCFG_INS8250_OUT_DTR_CB(DEVWRITELINE("com1", rs232_port_device, write_dtr))
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//MCFG_INS8250_OUT_RTS_CB(DEVWRITELINE("com1", rs232_port_device, write_rts))
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//MCFG_INS8250_OUT_INT_CB(DEVWRITELINE(":", atlantis_state, uart1_irq_callback))
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MCFG_DEVICE_ADD("uart2", NS16550, XTAL_24MHz)
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//MCFG_INS8250_OUT_TX_CB(DEVWRITELINE("com2", rs232_port_device, write_txd))
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//MCFG_INS8250_OUT_DTR_CB(DEVWRITELINE("com2", rs232_port_device, write_dtr))
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//MCFG_INS8250_OUT_RTS_CB(DEVWRITELINE("com2", rs232_port_device, write_rts))
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//MCFG_INS8250_OUT_INT_CB(DEVWRITELINE(":", atlantis_state, uart2_irq_callback))
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//MCFG_RS232_PORT_ADD("com1", default_rs232_devices, nullptr)
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//MCFG_RS232_RXD_HANDLER(DEVWRITELINE("uart1", ins8250_uart_device, rx_w))
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//MCFG_RS232_DCD_HANDLER(DEVWRITELINE("uart1", ins8250_uart_device, dcd_w))
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//MCFG_RS232_DSR_HANDLER(DEVWRITELINE("uart1", ins8250_uart_device, dsr_w))
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//MCFG_RS232_RI_HANDLER(DEVWRITELINE("uart1", ins8250_uart_device, ri_w))
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//MCFG_RS232_CTS_HANDLER(DEVWRITELINE("uart1", ins8250_uart_device, cts_w))
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//MCFG_DEVICE_CARD_DEVICE_INPUT_DEFAULTS("com1", mwskins_comm)
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//MCFG_RS232_PORT_ADD("com2", default_rs232_devices, nullptr)
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//MCFG_RS232_RXD_HANDLER(DEVWRITELINE("uart2", ins8250_uart_device, rx_w))
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//MCFG_RS232_DCD_HANDLER(DEVWRITELINE("uart2", ins8250_uart_device, dcd_w))
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//MCFG_RS232_DSR_HANDLER(DEVWRITELINE("uart2", ins8250_uart_device, dsr_w))
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//MCFG_RS232_RI_HANDLER(DEVWRITELINE("uart2", ins8250_uart_device, ri_w))
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//MCFG_RS232_CTS_HANDLER(DEVWRITELINE("uart2", ins8250_uart_device, cts_w))
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MACHINE_CONFIG_END
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/*************************************
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*
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* ROM definition(s)
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@ -183,7 +183,7 @@ MACHINE_CONFIG_END
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static MACHINE_CONFIG_DERIVED( gtfore01, iteagle )
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MCFG_DEVICE_MODIFY(PCI_ID_FPGA)
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MCFG_ITEAGLE_FPGA_INIT(0x00000401, 0x0b0b0b)
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MCFG_ITEAGLE_FPGA_INIT(0x01000401, 0x0b0b0b)
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MCFG_DEVICE_MODIFY(PCI_ID_EEPROM)
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MCFG_ITEAGLE_EEPROM_INIT(0x0401, 0x7)
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MACHINE_CONFIG_END
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@ -290,8 +290,8 @@ static INPUT_PORTS_START( iteagle )
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PORT_BIT( 0xfe00, IP_ACTIVE_LOW, IPT_UNKNOWN )
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PORT_START("SYSTEM")
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PORT_BIT( 0x0001, IP_ACTIVE_LOW, IPT_TILT ) PORT_NAME( "Test" )
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PORT_BIT( 0x0002, IP_ACTIVE_LOW, IPT_SERVICE )
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PORT_BIT( 0x0001, IP_ACTIVE_LOW, IPT_SERVICE ) PORT_NAME( "Service" )
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PORT_BIT( 0x0002, IP_ACTIVE_LOW, IPT_SERVICE1 )
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PORT_BIT( 0x000c, IP_ACTIVE_LOW, IPT_UNKNOWN )
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PORT_DIPNAME( 0x0010, 0x00, "SW51-1" )
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PORT_DIPSETTING(0x00, "Normal" )
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@ -1244,7 +1244,7 @@ WRITE32_MEMBER( vegas_state::nile_w )
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break;
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case NREG_UARTTHR: /* serial port output */
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if (PRINTF_SERIAL) osd_printf_debug("%c", data & 0xff);
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if (PRINTF_SERIAL) osd_printf_info("%c", data & 0xff);
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logit = 0;
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break;
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case NREG_UARTIER: /* serial interrupt enable */
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@ -10,10 +10,30 @@
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#define LOG_EEPROM (0)
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#define LOG_PERIPH (0)
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#define AM85C30_TAG "am85c30_0"
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#define COM1_TAG "com1"
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#define COM2_TAG "com2"
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const device_type ITEAGLE_FPGA = &device_creator<iteagle_fpga_device>;
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MACHINE_CONFIG_FRAGMENT(iteagle_fpga)
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MCFG_NVRAM_ADD_0FILL("eagle2_rtc")
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// RS232 serial ports
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//MCFG_SCC85C30_ADD(AM85C30_TAG, XTAL_7_3728MHz, XTAL_1_8432MHz, 0, XTAL_1_8432MHz, 0)
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MCFG_SCC85C30_ADD(AM85C30_TAG, XTAL_1_8432MHz, XTAL_1_8432MHz, 0, XTAL_1_8432MHz, 0)
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MCFG_Z80SCC_OUT_INT_CB(WRITELINE(iteagle_fpga_device, serial_interrupt))
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MCFG_Z80SCC_OUT_TXDA_CB(DEVWRITELINE(COM2_TAG, rs232_port_device, write_txd))
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MCFG_Z80SCC_OUT_TXDB_CB(DEVWRITELINE(COM1_TAG, rs232_port_device, write_txd))
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MCFG_RS232_PORT_ADD(COM1_TAG, default_rs232_devices, nullptr)
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MCFG_RS232_RXD_HANDLER(DEVWRITELINE(AM85C30_TAG, scc85C30_device, rxb_w))
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MCFG_RS232_DCD_HANDLER(DEVWRITELINE(AM85C30_TAG, scc85C30_device, dcdb_w))
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MCFG_RS232_CTS_HANDLER(DEVWRITELINE(AM85C30_TAG, scc85C30_device, ctsb_w))
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MCFG_RS232_PORT_ADD(COM2_TAG, default_rs232_devices, nullptr)
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MCFG_RS232_RXD_HANDLER(DEVWRITELINE(AM85C30_TAG, scc85C30_device, rxa_w))
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MCFG_RS232_DCD_HANDLER(DEVWRITELINE(AM85C30_TAG, scc85C30_device, dcda_w))
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MCFG_RS232_CTS_HANDLER(DEVWRITELINE(AM85C30_TAG, scc85C30_device, ctsa_w))
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MACHINE_CONFIG_END
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DEVICE_ADDRESS_MAP_START(fpga_map, 32, iteagle_fpga_device)
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@ -30,7 +50,7 @@ ADDRESS_MAP_END
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iteagle_fpga_device::iteagle_fpga_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock)
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: pci_device(mconfig, ITEAGLE_FPGA, "ITEagle FPGA", tag, owner, clock, "iteagle_fpga", __FILE__),
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m_rtc(*this, "eagle2_rtc"), m_version(0), m_seq_init(0)
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m_rtc(*this, "eagle2_rtc"), m_scc1(*this, AM85C30_TAG), m_version(0), m_seq_init(0)
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{
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}
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@ -167,6 +187,24 @@ void iteagle_fpga_device::device_timer(emu_timer &timer, device_timer_id tid, in
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}
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WRITE_LINE_MEMBER(iteagle_fpga_device::serial_interrupt)
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{
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osd_printf_info("serial_interrupt: intr(%i) = %i\n", m_serial_irq_num, state);
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m_cpu->set_input_line(m_serial_irq_num, state);
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}
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WRITE8_MEMBER(iteagle_fpga_device::serial_rx_w)
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{
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std::string tmpStr;
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tmpStr += data;
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//osd_printf_info("serial_rx_w: %02x\n", data);
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m_serial0_1.write_rx_str(1, tmpStr);
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if (0 && m_serial0_1.check_interrupt()) {
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osd_printf_info("serial_rx_w: %02x\n", data);
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m_cpu->set_input_line(m_serial_irq_num, ASSERT_LINE);
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}
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}
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READ32_MEMBER( iteagle_fpga_device::fpga_r )
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{
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uint32_t result = m_fpga_regs[offset];
|
||||
@ -179,7 +217,7 @@ READ32_MEMBER( iteagle_fpga_device::fpga_r )
|
||||
break;
|
||||
case 0x04/4:
|
||||
result = (result & 0xFF0FFFFF) | ((machine().root_device().ioport("SW5")->read()&0xf)<<20);
|
||||
if (LOG_FPGA && !ACCESSING_BITS_0_7)
|
||||
if (0 && LOG_FPGA && !ACCESSING_BITS_0_7)
|
||||
logerror("%s:fpga_r offset %04X = %08X & %08X\n", machine().describe_context(), offset*4, result, mem_mask);
|
||||
break;
|
||||
case 0x08/4:
|
||||
@ -200,21 +238,25 @@ READ32_MEMBER( iteagle_fpga_device::fpga_r )
|
||||
case 0x0c/4: //
|
||||
result = 0;
|
||||
if (ACCESSING_BITS_0_7) {
|
||||
result |= m_serial0_1.read_control(1) << 0;
|
||||
result |= m_scc1->cb_r(space, offset) << 0;
|
||||
if (LOG_SERIAL) m_serial0_1.read_control(1);
|
||||
}
|
||||
if (ACCESSING_BITS_8_15) {
|
||||
result |= m_serial0_1.read_control(0) << 8;
|
||||
result |= m_scc1->ca_r(space, offset) << 8;
|
||||
if (LOG_SERIAL) m_serial0_1.read_control(0);
|
||||
}
|
||||
if (ACCESSING_BITS_16_23) {
|
||||
result |= m_serial0_1.read_data(1) << 16;
|
||||
result |= m_scc1->db_r(space, offset) <<16;
|
||||
if (LOG_SERIAL) m_serial0_1.read_data(1);
|
||||
}
|
||||
if (ACCESSING_BITS_24_31) {
|
||||
result |= m_serial0_1.read_data(0) << 24;
|
||||
result |= m_scc1->da_r(space, offset) << 24;
|
||||
if (LOG_SERIAL) m_serial0_1.read_data(0);
|
||||
}
|
||||
if (1 && LOG_FPGA)
|
||||
logerror("%s:fpga_r offset %04X = %08X & %08X\n", machine().describe_context(), offset*4, result, mem_mask);
|
||||
break;
|
||||
case 0x1c/4: // 1d = modem byte
|
||||
case 0x1c/4:
|
||||
result = 0;
|
||||
if (ACCESSING_BITS_0_7) {
|
||||
result |= m_serial2_3.read_control(1) << 0;
|
||||
@ -224,12 +266,10 @@ READ32_MEMBER( iteagle_fpga_device::fpga_r )
|
||||
}
|
||||
if (ACCESSING_BITS_16_23) {
|
||||
result |= m_serial2_3.read_data(1) << 16;
|
||||
// MODEM
|
||||
logerror("fpga_r: LEDSIGN read byte: %c\n", (result >> 16) & 0xff);
|
||||
logerror("fpga_r: LEDSIGN read byte: %02X\n", uint8_t(result >> 16));
|
||||
}
|
||||
if (ACCESSING_BITS_24_31) {
|
||||
result |= m_serial2_3.read_data(0) << 24;
|
||||
// LED Sign
|
||||
logerror("fpga_r: MODEM read byte: %c\n", (result >> 24) & 0xff);
|
||||
}
|
||||
// Clear interrupts
|
||||
@ -297,23 +337,34 @@ WRITE32_MEMBER( iteagle_fpga_device::fpga_w )
|
||||
break;
|
||||
case 0x0c/4:
|
||||
if (ACCESSING_BITS_0_7) {
|
||||
m_serial0_1.write_control((data >> 0) & 0xff, 1);
|
||||
m_scc1->cb_w(space, offset, (data >> 0) & 0xff);
|
||||
if (LOG_SERIAL) m_serial0_1.write_control((data >> 0) & 0xff, 1);
|
||||
}
|
||||
if (ACCESSING_BITS_8_15) {
|
||||
m_serial0_1.write_control((data >> 8) & 0xff, 0);
|
||||
m_scc1->ca_w(space, offset, (data >> 8) & 0xff);
|
||||
if (LOG_SERIAL) m_serial0_1.write_control((data >> 8) & 0xff, 0);
|
||||
}
|
||||
if (ACCESSING_BITS_16_23) {
|
||||
m_serial0_1.write_data((data >> 16) & 0xff, 1);
|
||||
if (m_serial0_1.get_tx_str(1).back() == 0xd) {
|
||||
if (LOG_SERIAL) logerror("com0: %s\n", m_serial0_1.get_tx_str(1).c_str());
|
||||
osd_printf_debug("com0: %s\n", m_serial0_1.get_tx_str(1).c_str());
|
||||
m_serial0_1.clear_tx_str(1);
|
||||
// Convert 0xd to 0xa
|
||||
uint8_t byte = data >> 16;
|
||||
if (byte==0xd)
|
||||
m_scc1->db_w(space, offset, 0xa);
|
||||
else
|
||||
m_scc1->db_w(space, offset, byte);
|
||||
if (LOG_SERIAL) {
|
||||
m_serial0_1.write_data((data >> 16) & 0xff, 1);
|
||||
if (m_serial0_1.get_tx_str(1).back() == 0xd) {
|
||||
logerror("com0: %s", m_serial0_1.get_tx_str(1).c_str());
|
||||
osd_printf_info("com0: %s\n", m_serial0_1.get_tx_str(1).c_str());
|
||||
m_serial0_1.clear_tx_str(1);
|
||||
}
|
||||
}
|
||||
}
|
||||
if (ACCESSING_BITS_24_31) {
|
||||
m_serial0_1.write_data((data >> 24) & 0xff, 0);
|
||||
m_scc1->da_w(space, offset, (data >> 24) & 0xff);
|
||||
if (LOG_SERIAL) m_serial0_1.write_data((data >> 24) & 0xff, 0);
|
||||
}
|
||||
if (0 && LOG_FPGA)
|
||||
if (1 && LOG_FPGA)
|
||||
logerror("%s:fpga_w offset %04X = %08X & %08X\n", machine().describe_context(), offset*4, data, mem_mask);
|
||||
break;
|
||||
case 0x1c/4:
|
||||
@ -326,12 +377,28 @@ WRITE32_MEMBER( iteagle_fpga_device::fpga_w )
|
||||
if (ACCESSING_BITS_16_23) {
|
||||
int chan = 1;
|
||||
m_serial2_3.write_data((data >> 16) & 0xff, chan);
|
||||
if (m_serial2_3.get_tx_str(chan).length() == 8) {
|
||||
if (LOG_SERIAL) logerror("com2: %s\n", m_serial2_3.get_tx_str(chan).c_str());
|
||||
osd_printf_debug("com2: %s\n", m_serial2_3.get_tx_str(chan).c_str());
|
||||
m_serial2_3.clear_tx_str(chan);
|
||||
// Set Response
|
||||
m_serial2_3.write_rx_str(chan, "\x08");
|
||||
std::string txString = m_serial2_3.get_tx_str(chan);
|
||||
if (txString.length() >= 8) {
|
||||
int length = (uint8_t(txString[4]) << 8) | uint8_t(txString[5]);
|
||||
if (txString.length() >= length) {
|
||||
osd_printf_debug("com2:");
|
||||
if (LOG_SERIAL) logerror("com2:\n");
|
||||
for (int i = 0; i < txString.length(); i++) {
|
||||
if (LOG_SERIAL) logerror(" %02x", uint8_t(txString[i]));
|
||||
osd_printf_debug(" %02x", uint8_t(txString[i]));
|
||||
if ((i + 1) % 16 == 0 || i==length-1) {
|
||||
osd_printf_debug("\n");
|
||||
if (LOG_SERIAL) logerror("\n");
|
||||
}
|
||||
}
|
||||
osd_printf_debug("\n");
|
||||
// Set Sign Response ACK
|
||||
//if (txString[0]==0x01 || txString[0] == 0x23)
|
||||
m_serial2_3.write_rx_str(chan, "\x10");
|
||||
// Clear string
|
||||
m_serial2_3.clear_tx_str(chan);
|
||||
txString.clear();
|
||||
}
|
||||
}
|
||||
}
|
||||
if (ACCESSING_BITS_24_31) {
|
||||
@ -386,8 +453,8 @@ void iteagle_am85c30::write_control(uint8_t data, int channel)
|
||||
// Reset address pointer to 0
|
||||
if (addr != 0) {
|
||||
m_wr_regs[channel][0] = 0;
|
||||
// Mirror wr2 to rr2
|
||||
m_rr_regs[channel][2] = m_wr_regs[channel][2];
|
||||
// Mirror wr2 to rr2[chan0]
|
||||
m_rr_regs[0][2] = m_wr_regs[channel][2];
|
||||
}
|
||||
}
|
||||
|
||||
@ -413,7 +480,7 @@ void iteagle_am85c30::write_data(uint8_t data, int channel)
|
||||
m_rr_regs[1][3] = m_rr_regs[0][3];
|
||||
}
|
||||
// Limit length
|
||||
if (m_serial_tx[channel].size() >= 160) {
|
||||
if (m_serial_tx[channel].size() >= 4000) {
|
||||
if (LOG_SERIAL) printf("%s\n", m_serial_tx[channel].c_str());
|
||||
osd_printf_debug("%s\n", m_serial_tx[channel].c_str());
|
||||
m_serial_tx[channel].clear();
|
||||
@ -547,6 +614,7 @@ iteagle_eeprom_device::iteagle_eeprom_device(const machine_config &mconfig, cons
|
||||
// 0x4 = HW Version - 6-8 is GREEN board PCB, 9 is RED board PCB
|
||||
// 0x5 = Serial Num + top byte of 0x4
|
||||
// 0x6 = OperID
|
||||
// 0xd = GT Fore Tournament Board
|
||||
// 0xe = SW Version
|
||||
// 0xf = 0x01 for extra courses
|
||||
// 0x3e = 0x0002 for good nvram
|
||||
@ -554,7 +622,7 @@ iteagle_eeprom_device::iteagle_eeprom_device(const machine_config &mconfig, cons
|
||||
m_iteagle_default_eeprom =
|
||||
{ {
|
||||
0xd000,0x0022,0x0000,0x0003,0x1209,0x1111,0x2222,0x1234,
|
||||
0x0000,0x0000,0x0000,0x0000,0xcd00,0x0000,0x0000,0x0001,
|
||||
0x0000,0x0000,0x0000,0x0000,0xcd00,0x0001,0x0000,0x0001,
|
||||
0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,
|
||||
0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,
|
||||
0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,0x0000,
|
||||
|
||||
@ -9,6 +9,8 @@
|
||||
#include "machine/pci.h"
|
||||
#include "machine/nvram.h"
|
||||
#include "machine/eepromser.h"
|
||||
#include "machine/z80scc.h"
|
||||
#include "bus/rs232/rs232.h"
|
||||
|
||||
//MCFG_PCI_DEVICE_ADD(_tag, _type, _main_id, _revision, _pclass, _subsystem_id)
|
||||
|
||||
@ -57,11 +59,15 @@ public:
|
||||
virtual machine_config_constructor device_mconfig_additions() const override;
|
||||
|
||||
required_device<nvram_device> m_rtc;
|
||||
required_device<scc85C30_device> m_scc1;
|
||||
|
||||
void set_init_info(int version, int seq_init) {m_version=version; m_seq_init=seq_init;}
|
||||
void set_irq_info(const char *tag, const int irq_num, const int serial_num) {
|
||||
m_cpu_tag = tag; m_irq_num = irq_num; m_serial_irq_num = serial_num;}
|
||||
|
||||
DECLARE_WRITE_LINE_MEMBER(serial_interrupt);
|
||||
DECLARE_WRITE8_MEMBER(serial_rx_w);
|
||||
|
||||
protected:
|
||||
virtual void device_start() override;
|
||||
virtual void device_reset() override;
|
||||
|
||||
@ -593,6 +593,7 @@ const device_type MIDWAY_IOASIC = &device_creator<midway_ioasic_device>;
|
||||
|
||||
midway_ioasic_device::midway_ioasic_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock) :
|
||||
midway_serial_pic2_device(mconfig, MIDWAY_IOASIC, "Midway IOASIC", tag, owner, clock, "midway_ioasic", __FILE__),
|
||||
m_serial_tx_cb(*this),
|
||||
m_has_dcs(0),
|
||||
m_has_cage(0),
|
||||
m_dcs_cpu(nullptr),
|
||||
@ -657,6 +658,7 @@ void midway_ioasic_device::device_start()
|
||||
m_shuffle_map = &shuffle_maps[m_shuffle_type][0];
|
||||
// resolve callbacks
|
||||
m_irq_callback.resolve_safe();
|
||||
m_serial_tx_cb.resolve_safe();
|
||||
|
||||
/* initialize the PIC */
|
||||
midway_serial_pic2_device::device_start();
|
||||
@ -1028,6 +1030,12 @@ WRITE32_MEMBER( midway_ioasic_device::packed_w )
|
||||
write(space, offset*2+1, data >> 16, 0x0000ffff);
|
||||
}
|
||||
|
||||
WRITE8_MEMBER(midway_ioasic_device::serial_rx_w)
|
||||
{
|
||||
m_reg[IOASIC_UARTIN] = data | 0x1000;
|
||||
update_ioasic_irq();
|
||||
|
||||
}
|
||||
|
||||
WRITE32_MEMBER( midway_ioasic_device::write )
|
||||
{
|
||||
@ -1068,8 +1076,13 @@ WRITE32_MEMBER( midway_ioasic_device::write )
|
||||
m_reg[IOASIC_UARTIN] = (newreg & 0x00ff) | 0x1000;
|
||||
update_ioasic_irq();
|
||||
}
|
||||
else if (PRINTF_DEBUG)
|
||||
osd_printf_debug("%c", data & 0xff);
|
||||
else {
|
||||
m_serial_tx_cb(data & 0xff);
|
||||
if (PRINTF_DEBUG) {
|
||||
osd_printf_info("%c", data & 0xff);
|
||||
logerror("%c", data & 0xff);
|
||||
}
|
||||
}
|
||||
break;
|
||||
|
||||
case IOASIC_SOUNDCTL:
|
||||
|
||||
@ -125,6 +125,7 @@ public:
|
||||
static void static_set_shuffle_default(device_t &device, uint8_t shuffle) { downcast<midway_ioasic_device &>(device).m_shuffle_default = shuffle; }
|
||||
static void static_set_auto_ack(device_t &device, uint8_t auto_ack) { downcast<midway_ioasic_device &>(device).m_auto_ack = auto_ack; }
|
||||
template<class _Object> static devcb_base &set_irqhandler_callback(device_t &device, _Object object) { return downcast<midway_ioasic_device &>(device).m_irq_callback.set_callback(object); }
|
||||
template<class _Object> static devcb_base &set_serial_tx_callback(device_t &device, _Object object) { return downcast<midway_ioasic_device &>(device).m_serial_tx_cb.set_callback(object); }
|
||||
|
||||
void set_shuffle_state(int state);
|
||||
void fifo_w(uint16_t data);
|
||||
@ -145,6 +146,8 @@ public:
|
||||
|
||||
DECLARE_WRITE8_MEMBER(cage_irq_handler);
|
||||
|
||||
DECLARE_WRITE8_MEMBER(serial_rx_w);
|
||||
|
||||
void ioasic_reset();
|
||||
|
||||
protected:
|
||||
@ -155,6 +158,7 @@ private:
|
||||
void ioasic_register_state();
|
||||
void update_ioasic_irq();
|
||||
|
||||
devcb_write8 m_serial_tx_cb;
|
||||
|
||||
uint32_t m_reg[16];
|
||||
uint8_t m_has_dcs;
|
||||
@ -200,6 +204,9 @@ extern const device_type MIDWAY_IOASIC;
|
||||
#define MCFG_MIDWAY_IOASIC_AUTO_ACK(_ack) \
|
||||
midway_ioasic_device::static_set_auto_ack(*device, _ack);
|
||||
|
||||
#define MCFG_MIDWAY_IOASIC_OUT_TX_CB(_devcb) \
|
||||
devcb = &midway_ioasic_device::set_serial_tx_callback(*device, DEVCB_##_devcb);
|
||||
|
||||
|
||||
enum
|
||||
{
|
||||
|
||||
Loading…
Reference in New Issue
Block a user