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Port from MESS, nw

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This commit is contained in:
Angelo Salese 2011-06-14 00:53:46 +00:00
parent 23976ade94
commit c422a1a72e
4 changed files with 139 additions and 86 deletions
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84
src/mame/drivers/saturn.c
View File

@ -149,6 +149,7 @@ static struct
UINT8 abus; UINT8 abus;
}stv_irq; }stv_irq;
static void scu_do_transfer(running_machine &machine,UINT8 event);
static void scu_dma_direct(address_space *space, UINT8 dma_ch); /*DMA level 0 direct transfer function*/ static void scu_dma_direct(address_space *space, UINT8 dma_ch); /*DMA level 0 direct transfer function*/
static void scu_dma_indirect(address_space *space, UINT8 dma_ch); /*DMA level 0 indirect transfer function*/ static void scu_dma_indirect(address_space *space, UINT8 dma_ch); /*DMA level 0 indirect transfer function*/
@ -1189,11 +1190,8 @@ xxxx xxxx x--- xx-- xx-- xx-- xx-- xx-- UNUSED
**********************************************************************************/ **********************************************************************************/
/* /*
DMA TODO: DMA TODO:
-Verify if there are any kind of bugs,do clean-ups,use better comments
and macroize for better reading...
-Add timings(but how fast are each DMA?). -Add timings(but how fast are each DMA?).
-Add level priority & DMA status register. -Add level priority & DMA status register.
-Add DMA start factor conditions that are different than 7.
-Add byte data type transfer. -Add byte data type transfer.
-Set boundaries. -Set boundaries.
*/ */
@ -1219,6 +1217,22 @@ static UINT32 scu_add_tmp;
#define WORK_RAM_H(_lv_) ((scu_##_lv_ & 0x07ffffff) >= 0x06000000) && ((scu_##_lv_ & 0x07ffffff) <= 0x060fffff) #define WORK_RAM_H(_lv_) ((scu_##_lv_ & 0x07ffffff) >= 0x06000000) && ((scu_##_lv_ & 0x07ffffff) <= 0x060fffff)
#define SOUND_RAM(_lv_) ((scu_##_lv_ & 0x07ffffff) >= 0x05a00000) && ((scu_##_lv_ & 0x07ffffff) <= 0x05afffff) #define SOUND_RAM(_lv_) ((scu_##_lv_ & 0x07ffffff) >= 0x05a00000) && ((scu_##_lv_ & 0x07ffffff) <= 0x05afffff)
static void scu_do_transfer(running_machine &machine,UINT8 event)
{
saturn_state *state = machine.driver_data<saturn_state>();
address_space *space = machine.device("maincpu")->memory().space(AS_PROGRAM);
int i;
for(i=0;i<3;i++)
{
if(state->m_scu.enable_mask[i] && state->m_scu.start_factor[i] == event)
{
if(DIRECT_MODE(i)) { scu_dma_direct(space,i); }
else { scu_dma_indirect(space,i); }
}
}
}
static READ32_HANDLER( saturn_scu_r ) static READ32_HANDLER( saturn_scu_r )
{ {
saturn_state *state = space->machine().driver_data<saturn_state>(); saturn_state *state = space->machine().driver_data<saturn_state>();
@ -1304,11 +1318,11 @@ static WRITE32_HANDLER( saturn_scu_w )
It must be 7 for this specific condition. It must be 7 for this specific condition.
-state->m_scu_regs[5] bit 24 is Indirect Mode/Direct Mode (0/1). -state->m_scu_regs[5] bit 24 is Indirect Mode/Direct Mode (0/1).
*/ */
if(state->m_scu_regs[offset] & 1 && ((state->m_scu_regs[offset+1] & 7) == 7) && state->m_scu_regs[offset] & 0x100) state->m_scu.enable_mask[DMA_CH] = (data & 0x100) >> 8;
if(state->m_scu.enable_mask[DMA_CH] && state->m_scu.start_factor[DMA_CH] == 7 && state->m_scu_regs[offset] & 1)
{ {
if(DIRECT_MODE(DMA_CH)) { scu_dma_direct(space,DMA_CH); } if(DIRECT_MODE(DMA_CH)) { scu_dma_direct(space,DMA_CH); }
else { scu_dma_indirect(space,DMA_CH); } else { scu_dma_indirect(space,DMA_CH); }
state->m_scu_regs[offset]&=~1;//disable starting bit. state->m_scu_regs[offset]&=~1;//disable starting bit.
} }
break; break;
@ -1320,8 +1334,7 @@ static WRITE32_HANDLER( saturn_scu_w )
} }
/*Start factor enable bits,bit 2,bit 1 and bit 0*/ /*Start factor enable bits,bit 2,bit 1 and bit 0*/
if((state->m_scu_regs[offset] & 7) != 7) state->m_scu.start_factor[DMA_CH] = state->m_scu_regs[offset] & 7;
if(LOG_SCU) logerror("Start factor chosen for lv %d = %d\n",state->m_scu_regs[offset+1] & 7,DMA_CH);
break; break;
case 24: case 24:
@ -1753,7 +1766,7 @@ static ADDRESS_MAP_START( saturn_mem, AS_PROGRAM, 32 )
/* VDP1 */ /* VDP1 */
AM_RANGE(0x05c00000, 0x05c7ffff) AM_READWRITE(saturn_vdp1_vram_r, saturn_vdp1_vram_w) AM_RANGE(0x05c00000, 0x05c7ffff) AM_READWRITE(saturn_vdp1_vram_r, saturn_vdp1_vram_w)
AM_RANGE(0x05c80000, 0x05cbffff) AM_READWRITE(saturn_vdp1_framebuffer0_r, saturn_vdp1_framebuffer0_w) AM_RANGE(0x05c80000, 0x05cbffff) AM_READWRITE(saturn_vdp1_framebuffer0_r, saturn_vdp1_framebuffer0_w)
AM_RANGE(0x05d00000, 0x05d0001f) AM_READWRITE(saturn_vdp1_regs_r, saturn_vdp1_regs_w) AM_RANGE(0x05d00000, 0x05d0001f) AM_READWRITE16(saturn_vdp1_regs_r, saturn_vdp1_regs_w,0xffffffff)
AM_RANGE(0x05e00000, 0x05efffff) AM_READWRITE(saturn_vdp2_vram_r, saturn_vdp2_vram_w) AM_RANGE(0x05e00000, 0x05efffff) AM_READWRITE(saturn_vdp2_vram_r, saturn_vdp2_vram_w)
AM_RANGE(0x05f00000, 0x05f7ffff) AM_READWRITE(saturn_vdp2_cram_r, saturn_vdp2_cram_w) AM_RANGE(0x05f00000, 0x05f7ffff) AM_READWRITE(saturn_vdp2_cram_r, saturn_vdp2_cram_w)
AM_RANGE(0x05f80000, 0x05fbffff) AM_READWRITE(saturn_vdp2_regs_r, saturn_vdp2_regs_w) AM_RANGE(0x05f80000, 0x05fbffff) AM_READWRITE(saturn_vdp2_regs_r, saturn_vdp2_regs_w)
@ -1781,7 +1794,7 @@ static ADDRESS_MAP_START( stv_mem, AS_PROGRAM, 32 )
/* VDP1 */ /* VDP1 */
AM_RANGE(0x05c00000, 0x05c7ffff) AM_READWRITE(saturn_vdp1_vram_r, saturn_vdp1_vram_w) AM_RANGE(0x05c00000, 0x05c7ffff) AM_READWRITE(saturn_vdp1_vram_r, saturn_vdp1_vram_w)
AM_RANGE(0x05c80000, 0x05cbffff) AM_READWRITE(saturn_vdp1_framebuffer0_r, saturn_vdp1_framebuffer0_w) AM_RANGE(0x05c80000, 0x05cbffff) AM_READWRITE(saturn_vdp1_framebuffer0_r, saturn_vdp1_framebuffer0_w)
AM_RANGE(0x05d00000, 0x05d0001f) AM_READWRITE(saturn_vdp1_regs_r, saturn_vdp1_regs_w) AM_RANGE(0x05d00000, 0x05d0001f) AM_READWRITE16(saturn_vdp1_regs_r, saturn_vdp1_regs_w,0xffffffff)
AM_RANGE(0x05e00000, 0x05efffff) AM_READWRITE(saturn_vdp2_vram_r, saturn_vdp2_vram_w) AM_RANGE(0x05e00000, 0x05efffff) AM_READWRITE(saturn_vdp2_vram_r, saturn_vdp2_vram_w)
AM_RANGE(0x05f00000, 0x05f7ffff) AM_READWRITE(saturn_vdp2_cram_r, saturn_vdp2_cram_w) AM_RANGE(0x05f00000, 0x05f7ffff) AM_READWRITE(saturn_vdp2_cram_r, saturn_vdp2_cram_w)
AM_RANGE(0x05f80000, 0x05fbffff) AM_READWRITE(saturn_vdp2_regs_r, saturn_vdp2_regs_w) AM_RANGE(0x05f80000, 0x05fbffff) AM_READWRITE(saturn_vdp2_regs_r, saturn_vdp2_regs_w)
@ -2364,7 +2377,11 @@ static WRITE_LINE_DEVICE_HANDLER( scsp_to_main_irq )
{ {
saturn_state *drvstate = device->machine().driver_data<saturn_state>(); saturn_state *drvstate = device->machine().driver_data<saturn_state>();
device_set_input_line_and_vector(drvstate->m_maincpu, 9, (stv_irq.sound_req) ? HOLD_LINE : CLEAR_LINE, 0x46); if(stv_irq.sound_req)
{
device_set_input_line_and_vector(drvstate->m_maincpu, 9, HOLD_LINE, 0x46);
scu_do_transfer(device->machine(),5);
}
} }
static const scsp_interface scsp_config = static const scsp_interface scsp_config =
@ -2568,28 +2585,55 @@ static TIMER_DEVICE_CALLBACK( saturn_scanline )
//popmessage("%08x %d %08x %08x",state->m_scu_regs[40] ^ 0xffffffff,max_y,state->m_scu_regs[36],state->m_scu_regs[38]); //popmessage("%08x %d %08x %08x",state->m_scu_regs[40] ^ 0xffffffff,max_y,state->m_scu_regs[36],state->m_scu_regs[38]);
if(scanline == 0*y_step) if(scanline == 0*y_step)
{
if(stv_irq.vblank_out)
{ {
device_set_input_line_and_vector(state->m_maincpu, 0xe, (stv_irq.vblank_out) ? HOLD_LINE : CLEAR_LINE , 0x41); device_set_input_line_and_vector(state->m_maincpu, 0xe, (stv_irq.vblank_out) ? HOLD_LINE : CLEAR_LINE , 0x41);
//CEF_0; //TODO scu_do_transfer(timer.machine(),1);
}
} }
else if(scanline == vblank_line*y_step) else if(scanline == vblank_line*y_step)
{ {
device_set_input_line_and_vector(state->m_maincpu, 0xf, (stv_irq.vblank_in) ? HOLD_LINE : CLEAR_LINE , 0x40); if(stv_irq.vblank_in)
video_update_vdp1(timer.machine()); {
device_set_input_line_and_vector(state->m_maincpu, 0xf, HOLD_LINE ,0x40);
scu_do_transfer(timer.machine(),0);
}
if(stv_irq.vdp1_end) if(stv_irq.vdp1_end)
{
device_set_input_line_and_vector(state->m_maincpu, 0x2, HOLD_LINE, 0x4d); device_set_input_line_and_vector(state->m_maincpu, 0x2, HOLD_LINE, 0x4d);
CEF_1; scu_do_transfer(timer.machine(),6);
}
video_update_vdp1(timer.machine());
} }
else if((scanline % y_step) == 0 && scanline < vblank_line*y_step) else if((scanline % y_step) == 0 && scanline < vblank_line*y_step)
device_set_input_line_and_vector(state->m_maincpu, 0xd, (stv_irq.hblank_in) ? HOLD_LINE : CLEAR_LINE, 0x42); {
if(stv_irq.hblank_in)
{
device_set_input_line_and_vector(state->m_maincpu, 0xd, HOLD_LINE, 0x42);
scu_do_transfer(timer.machine(),2);
}
}
if(scanline == (state->m_scu_regs[36] & 0x3ff)*y_step)
{
if(stv_irq.timer_0)
{
device_set_input_line_and_vector(state->m_maincpu, 0xc, HOLD_LINE, 0x43 );
scu_do_transfer(timer.machine(),3);
}
}
/* TODO: this isn't completely correct */ /* TODO: this isn't completely correct */
if((state->m_scu_regs[38] & 0x81) == 0x01 && ((scanline % y_step) == 0)) if((state->m_scu_regs[38] & 0x81) == 0x01 && ((scanline % y_step) == 0))
device_set_input_line_and_vector(state->m_maincpu, 0xb, (stv_irq.timer_1) ? HOLD_LINE : CLEAR_LINE, 0x44 ); {
if(stv_irq.timer_1)
if(scanline == (state->m_scu_regs[36] & 0x3ff)*y_step) {
device_set_input_line_and_vector(state->m_maincpu, 0xc, (stv_irq.timer_0) ? HOLD_LINE : CLEAR_LINE, 0x43 ); device_set_input_line_and_vector(state->m_maincpu, 0xb, HOLD_LINE, 0x44 );
scu_do_transfer(timer.machine(),4);
}
}
} }
static READ32_HANDLER( saturn_cart_dram0_r ) static READ32_HANDLER( saturn_cart_dram0_r )

20
src/mame/includes/stv.h
View File

@ -17,7 +17,7 @@ public:
UINT32 *m_vdp2_vram; UINT32 *m_vdp2_vram;
UINT32 *m_vdp2_cram; UINT32 *m_vdp2_cram;
UINT32 *m_vdp1_vram; UINT32 *m_vdp1_vram;
UINT32 *m_vdp1_regs; UINT16 *m_vdp1_regs;
UINT8 m_NMI_reset; UINT8 m_NMI_reset;
UINT8 m_en_68k; UINT8 m_en_68k;
@ -29,6 +29,8 @@ public:
UINT32 dst_add[3]; /* Destination Addition for DMA lv n*/ UINT32 dst_add[3]; /* Destination Addition for DMA lv n*/
INT32 size[3]; /* Transfer DMA size lv n*/ INT32 size[3]; /* Transfer DMA size lv n*/
UINT32 index[3]; UINT32 index[3];
UINT8 start_factor[3];
UINT8 enable_mask[3];
}m_scu; }m_scu;
int m_minit_boost; int m_minit_boost;
@ -96,10 +98,14 @@ public:
#define MASTER_CLOCK_352 57272800 #define MASTER_CLOCK_352 57272800
#define MASTER_CLOCK_320 53748200 #define MASTER_CLOCK_320 53748200
#define CEF_1 state->m_vdp1_regs[0x010/4]|=0x00020000 #define CEF_1 state->m_vdp1_regs[0x010/2]|=0x0002
#define CEF_0 state->m_vdp1_regs[0x010/4]&=~0x00020000 #define CEF_0 state->m_vdp1_regs[0x010/2]&=~0x0002
#define BEF_1 state->m_vdp1_regs[0x010/4]|=0x00010000 #define BEF_1 state->m_vdp1_regs[0x010/2]|=0x0001
#define BEF_0 state->m_vdp1_regs[0x010/4]&=~0x00010000 #define BEF_0 state->m_vdp1_regs[0x010/2]&=~0x0001
#define STV_VDP1_TVMR ((state->m_vdp1_regs[0x000/2])&0xffff)
#define STV_VDP1_VBE ((STV_VDP1_TVMR & 0x0008) >> 3)
#define STV_VDP1_TVM ((STV_VDP1_TVMR & 0x0007) >> 0)
DRIVER_INIT ( stv ); DRIVER_INIT ( stv );
@ -159,11 +165,11 @@ int stv_vdp1_start ( running_machine &machine );
void video_update_vdp1(running_machine &machine); void video_update_vdp1(running_machine &machine);
void stv_vdp2_dynamic_res_change(running_machine &machine); void stv_vdp2_dynamic_res_change(running_machine &machine);
READ32_HANDLER ( saturn_vdp1_regs_r ); READ16_HANDLER ( saturn_vdp1_regs_r );
READ32_HANDLER ( saturn_vdp1_vram_r ); READ32_HANDLER ( saturn_vdp1_vram_r );
READ32_HANDLER ( saturn_vdp1_framebuffer0_r ); READ32_HANDLER ( saturn_vdp1_framebuffer0_r );
WRITE32_HANDLER ( saturn_vdp1_regs_w ); WRITE16_HANDLER ( saturn_vdp1_regs_w );
WRITE32_HANDLER ( saturn_vdp1_vram_w ); WRITE32_HANDLER ( saturn_vdp1_vram_w );
WRITE32_HANDLER ( saturn_vdp1_framebuffer0_w ); WRITE32_HANDLER ( saturn_vdp1_framebuffer0_w );

112
src/mame/video/stvvdp1.c
View File

@ -90,9 +90,6 @@ struct shaded_point
1 1024x256 1 1024x256
0 512x256 0 512x256
*/ */
#define STV_VDP1_TVMR ((state->m_vdp1_regs[0x000/4] >> 16)&0x0000ffff)
#define STV_VDP1_VBE ((STV_VDP1_TVMR & 0x0008) >> 3)
#define STV_VDP1_TVM ((STV_VDP1_TVMR & 0x0007) >> 0)
/*Frame Buffer Change Mode Register*/ /*Frame Buffer Change Mode Register*/
/* /*
@ -103,7 +100,7 @@ struct shaded_point
---- ---- ---- --x- | Frame Buffer Change Trigger (FCM) ---- ---- ---- --x- | Frame Buffer Change Trigger (FCM)
---- ---- ---- ---x | Frame Buffer Change Mode (FCT) ---- ---- ---- ---x | Frame Buffer Change Mode (FCT)
*/ */
#define STV_VDP1_FBCR ((state->m_vdp1_regs[0x000/4] >> 0)&0x0000ffff) #define STV_VDP1_FBCR ((state->m_vdp1_regs[0x002/2] >> 0)&0xffff)
#define STV_VDP1_EOS ((STV_VDP1_FBCR & 0x0010) >> 4) #define STV_VDP1_EOS ((STV_VDP1_FBCR & 0x0010) >> 4)
#define STV_VDP1_DIE ((STV_VDP1_FBCR & 0x0008) >> 3) #define STV_VDP1_DIE ((STV_VDP1_FBCR & 0x0008) >> 3)
#define STV_VDP1_DIL ((STV_VDP1_FBCR & 0x0004) >> 2) #define STV_VDP1_DIL ((STV_VDP1_FBCR & 0x0004) >> 2)
@ -121,9 +118,17 @@ struct shaded_point
1 VDP1 draw by request 1 VDP1 draw by request
0 VDP1 Idle (no access) 0 VDP1 Idle (no access)
*/ */
#define STV_VDP1_PTMR ((state->m_vdp1_regs[0x004/4] >> 16)&0x0000ffff) #define STV_VDP1_PTMR ((state->m_vdp1_regs[0x004/2])&0xffff)
#define STV_VDP1_PTM ((STV_VDP1_PTMR & 0x0003) >> 0) #define STV_VDP1_PTM ((STV_VDP1_PTMR & 0x0003) >> 0)
#define PTM_0 state->m_vdp1_regs[0x004/4]&=~0x00010000 #define PTM_0 state->m_vdp1_regs[0x004/2]&=~0x0001
/*
Erase/Write Data Register
16 bpp = data
8 bpp = erase/write data for even/odd X coordinates
*/
#define STV_VDP1_EWDR ((state->m_vdp1_regs[0x006/2])&0xffff)
/*Erase/Write Upper-Left register*/ /*Erase/Write Upper-Left register*/
/* /*
x--- ---- ---- ---- | UNUSED x--- ---- ---- ---- | UNUSED
@ -131,7 +136,7 @@ struct shaded_point
---- ---x xxxx xxxx | Y1 register ---- ---x xxxx xxxx | Y1 register
*/ */
#define STV_VDP1_EWLR ((state->m_vdp1_regs[0x008/4] >> 16)&0x0000ffff) #define STV_VDP1_EWLR ((state->m_vdp1_regs[0x008/2])&0xffff)
#define STV_VDP1_EWLR_X1 ((STV_VDP1_EWLR & 0x7e00) >> 9) #define STV_VDP1_EWLR_X1 ((STV_VDP1_EWLR & 0x7e00) >> 9)
#define STV_VDP1_EWLR_Y1 ((STV_VDP1_EWLR & 0x01ff) >> 0) #define STV_VDP1_EWLR_Y1 ((STV_VDP1_EWLR & 0x01ff) >> 0)
/*Erase/Write Lower-Right register*/ /*Erase/Write Lower-Right register*/
@ -140,7 +145,7 @@ struct shaded_point
---- ---x xxxx xxxx | Y3 register ---- ---x xxxx xxxx | Y3 register
*/ */
#define STV_VDP1_EWRR ((state->m_vdp1_regs[0x008/4] >> 0)&0x0000ffff) #define STV_VDP1_EWRR ((state->m_vdp1_regs[0x00a/2])&0xffff)
#define STV_VDP1_EWRR_X3 ((STV_VDP1_EWRR & 0xfe00) >> 9) #define STV_VDP1_EWRR_X3 ((STV_VDP1_EWRR & 0xfe00) >> 9)
#define STV_VDP1_EWRR_Y3 ((STV_VDP1_EWRR & 0x01ff) >> 0) #define STV_VDP1_EWRR_Y3 ((STV_VDP1_EWRR & 0x01ff) >> 0)
/*Transfer End Status Register*/ /*Transfer End Status Register*/
@ -150,7 +155,7 @@ struct shaded_point
---- ---- ---- ---x | BEF ---- ---- ---- ---x | BEF
*/ */
#define STV_VDP1_EDSR ((state->m_vdp1_regs[0x010/4] >> 16)&0x0000ffff) #define STV_VDP1_EDSR ((state->m_vdp1_regs[0x010/2])&0xffff)
#define STV_VDP1_CEF (STV_VDP1_EDSR & 2) #define STV_VDP1_CEF (STV_VDP1_EDSR & 2)
#define STV_VDP1_BEF (STV_VDP1_EDSR & 1) #define STV_VDP1_BEF (STV_VDP1_EDSR & 1)
/**/ /**/
@ -159,13 +164,25 @@ struct shaded_point
static void stv_vdp1_process_list(running_machine &machine); static void stv_vdp1_process_list(running_machine &machine);
READ32_HANDLER( saturn_vdp1_regs_r ) READ16_HANDLER( saturn_vdp1_regs_r )
{ {
saturn_state *state = space->machine().driver_data<saturn_state>(); saturn_state *state = space->machine().driver_data<saturn_state>();
//logerror ("cpu %s (PC=%08X) VDP1: Read from Registers, Offset %04x\n", space->device().tag(), cpu_get_pc(&space->device()), offset); //logerror ("cpu %s (PC=%08X) VDP1: Read from Registers, Offset %04x\n", space->device().tag(), cpu_get_pc(&space->device()), offset);
return state->m_vdp1_regs[offset]; switch(offset)
{
case 0x10/2:
break;
case 0x12/2:
case 0x14/2:
case 0x16/2:
printf ("cpu %s (PC=%08X) VDP1: Read from Registers, Offset %04x\n", space->device().tag(), cpu_get_pc(&space->device()), offset);
break;
}
return state->m_vdp1_regs[offset]; //TODO: write-only regs should return open bus or zero
} }
static void stv_clear_framebuffer( running_machine &machine, int which_framebuffer ) static void stv_clear_framebuffer( running_machine &machine, int which_framebuffer )
@ -254,58 +271,46 @@ static void stv_set_framebuffer_config( running_machine &machine )
stv_prepare_framebuffers(machine); stv_prepare_framebuffers(machine);
} }
WRITE32_HANDLER( saturn_vdp1_regs_w ) WRITE16_HANDLER( saturn_vdp1_regs_w )
{ {
saturn_state *state = space->machine().driver_data<saturn_state>(); saturn_state *state = space->machine().driver_data<saturn_state>();
COMBINE_DATA(&state->m_vdp1_regs[offset]); COMBINE_DATA(&state->m_vdp1_regs[offset]);
if ( offset == 0 )
switch(offset)
{ {
case 0x00/2:
stv_set_framebuffer_config(space->machine()); stv_set_framebuffer_config(space->machine());
if ( ACCESSING_BITS_0_15 )
{
if ( VDP1_LOG ) logerror( "VDP1: Access to register FBCR = %1X\n", STV_VDP1_FBCR );
state->m_vdp1.fbcr_accessed = 1;
}
else
{
if ( VDP1_LOG ) logerror( "VDP1: Access to register TVMR = %1X\n", STV_VDP1_TVMR ); if ( VDP1_LOG ) logerror( "VDP1: Access to register TVMR = %1X\n", STV_VDP1_TVMR );
if ( STV_VDP1_VBE && get_vblank(space->machine()) ) if ( STV_VDP1_VBE && get_vblank(space->machine()) )
{
state->m_vdp1.framebuffer_clear_on_next_frame = 1; state->m_vdp1.framebuffer_clear_on_next_frame = 1;
}
/* needed by pblbeach, it doesn't clear local coordinates in its sprite list...*/ break;
//if ( !strcmp(space->machine().system().name, "pblbeach") ) case 0x02/2:
//{ stv_set_framebuffer_config(space->machine());
// state->m_vdp1.local_x = state->m_vdp1.local_y = 0; if ( VDP1_LOG ) logerror( "VDP1: Access to register FBCR = %1X\n", STV_VDP1_FBCR );
//} state->m_vdp1.fbcr_accessed = 1;
} break;
} case 0x04/2:
else if ( offset == 1 ) if ( VDP1_LOG ) logerror( "VDP1: Access to register PTMR = %1X\n", STV_VDP1_PTM );
{
if ( ACCESSING_BITS_16_31 )
{
if ( STV_VDP1_PTMR == 1 ) if ( STV_VDP1_PTMR == 1 )
{
if ( VDP1_LOG ) logerror( "VDP1: Access to register PTMR = %1X\n", STV_VDP1_PTMR );
stv_vdp1_process_list( space->machine() ); stv_vdp1_process_list( space->machine() );
}
} break;
else if ( ACCESSING_BITS_0_15 ) case 0x06/2:
{
if ( VDP1_LOG ) logerror( "VDP1: Erase data set %08X\n", data ); if ( VDP1_LOG ) logerror( "VDP1: Erase data set %08X\n", data );
}
} if(data)
else if ( offset == 2 ) popmessage("EWDR set %08x, contact MAMEdev",STV_VDP1_EWDR);
{ break;
if ( ACCESSING_BITS_16_31 ) case 0x08/2:
{
if ( VDP1_LOG ) logerror( "VDP1: Erase upper-left coord set: %08X\n", data ); if ( VDP1_LOG ) logerror( "VDP1: Erase upper-left coord set: %08X\n", data );
} break;
else if ( ACCESSING_BITS_0_15 ) case 0x0a/2:
{
if ( VDP1_LOG ) logerror( "VDP1: Erase lower-right coord set: %08X\n", data ); if ( VDP1_LOG ) logerror( "VDP1: Erase lower-right coord set: %08X\n", data );
} break;
default:
printf("Warning: write to unknown VDP1 reg %08x %08x\n",offset*2,data);
break;
} }
} }
@ -1767,7 +1772,7 @@ static void stv_vdp1_process_list(running_machine &machine)
stv_clear_gouraud_shading(); stv_clear_gouraud_shading();
/*Set CEF bit to 0*/ /*Set CEF bit to 0*/
//CEF_0; CEF_0;
while (spritecount<10000) // if its drawn this many sprites something is probably wrong or sega were crazy ;-) while (spritecount<10000) // if its drawn this many sprites something is probably wrong or sega were crazy ;-)
{ {
@ -1973,6 +1978,8 @@ static void stv_vdp1_process_list(running_machine &machine)
end: end:
/* set CEF to 1*/
CEF_1;
if (VDP1_LOG) logerror ("End of list processing!\n"); if (VDP1_LOG) logerror ("End of list processing!\n");
} }
@ -2055,7 +2062,6 @@ void video_update_vdp1(running_machine &machine)
if ( framebuffer_changed ) if ( framebuffer_changed )
{ {
/*set CEF to 1*/ /*set CEF to 1*/
//CEF_1;
stv_vdp1_process_list(machine); stv_vdp1_process_list(machine);
} }
break; break;
@ -2092,7 +2098,7 @@ static void stv_vdp1_state_save_postload(running_machine &machine)
int stv_vdp1_start ( running_machine &machine ) int stv_vdp1_start ( running_machine &machine )
{ {
saturn_state *state = machine.driver_data<saturn_state>(); saturn_state *state = machine.driver_data<saturn_state>();
state->m_vdp1_regs = auto_alloc_array_clear(machine, UINT32, 0x040000/4 ); state->m_vdp1_regs = auto_alloc_array_clear(machine, UINT16, 0x020/2 );
state->m_vdp1_vram = auto_alloc_array_clear(machine, UINT32, 0x100000/4 ); state->m_vdp1_vram = auto_alloc_array_clear(machine, UINT32, 0x100000/4 );
state->m_vdp1.gfx_decode = auto_alloc_array(machine, UINT8, 0x100000 ); state->m_vdp1.gfx_decode = auto_alloc_array(machine, UINT8, 0x100000 );
@ -2119,7 +2125,7 @@ int stv_vdp1_start ( running_machine &machine )
state->m_vdp1.user_cliprect.min_y = state->m_vdp1.user_cliprect.max_y = 0; state->m_vdp1.user_cliprect.min_y = state->m_vdp1.user_cliprect.max_y = 0;
// save state // save state
state_save_register_global_pointer(machine, state->m_vdp1_regs, 0x040000/4); state_save_register_global_pointer(machine, state->m_vdp1_regs, 0x020/2);
state_save_register_global_pointer(machine, state->m_vdp1_vram, 0x100000/4); state_save_register_global_pointer(machine, state->m_vdp1_vram, 0x100000/4);
state_save_register_global(machine, state->m_vdp1.fbcr_accessed); state_save_register_global(machine, state->m_vdp1.fbcr_accessed);
state_save_register_global(machine, state->m_vdp1.framebuffer_current_display); state_save_register_global(machine, state->m_vdp1.framebuffer_current_display);

3
src/mame/video/stvvdp2.c
View File

@ -5812,9 +5812,6 @@ static int stv_sprite_priorities_used[8];
static int stv_sprite_priorities_usage_valid; static int stv_sprite_priorities_usage_valid;
static UINT8 stv_sprite_priorities_in_fb_line[512][8]; static UINT8 stv_sprite_priorities_in_fb_line[512][8];
#define STV_VDP1_TVMR ((state->m_vdp1_regs[0x000/4] >> 16)&0x0000ffff)
#define STV_VDP1_TVM ((STV_VDP1_TVMR & 0x0007) >> 0)
static void draw_sprites(running_machine &machine, bitmap_t *bitmap, const rectangle *cliprect, UINT8 pri) static void draw_sprites(running_machine &machine, bitmap_t *bitmap, const rectangle *cliprect, UINT8 pri)
{ {
saturn_state *state = machine.driver_data<saturn_state>(); saturn_state *state = machine.driver_data<saturn_state>();