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https://github.com/holub/mame
synced 2025-05-23 06:08:48 +03:00
some cleanup
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aefabca2f9
commit
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@ -91,7 +91,7 @@ INLINE void UPDATE_AR(tms32051_state *cpustate, int ar, int step)
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if (cenb1 && ar == car1)
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{
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// update circular buffer 1
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// update circular buffer 1, note that it only checks ==
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if (cpustate->ar[ar] == cpustate->cber1)
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{
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cpustate->ar[ar] = cpustate->cbsr1;
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@ -103,7 +103,7 @@ INLINE void UPDATE_AR(tms32051_state *cpustate, int ar, int step)
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}
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else if (cenb2 && ar == car2)
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{
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// update circular buffer 2
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// update circular buffer 2, note that it only checks ==
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if (cpustate->ar[ar] == cpustate->cber2)
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{
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cpustate->ar[ar] = cpustate->cbsr2;
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@ -255,7 +255,7 @@ INLINE int GET_TP_CONDITION(tms32051_state *cpustate, int tp)
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}
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case 2: // TC = 0
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{
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return !cpustate->st1.tc;
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return cpustate->st1.tc ^ 1;
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}
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case 3: // always false
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{
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@ -431,46 +431,38 @@ static void op_bsar(tms32051_state *cpustate)
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static void op_cmpl(tms32051_state *cpustate)
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{
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cpustate->acc = ~cpustate->acc;
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cpustate->acc = ~(UINT32)(cpustate->acc);
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CYCLES(1);
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}
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static void op_crgt(tms32051_state *cpustate)
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{
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if (cpustate->acc > cpustate->accb)
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if (cpustate->acc >= cpustate->accb)
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{
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cpustate->accb = cpustate->acc;
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cpustate->st1.c = 1;
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}
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else if (cpustate->acc < cpustate->accb)
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else
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{
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cpustate->acc = cpustate->accb;
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cpustate->st1.c = 0;
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}
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else
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{
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cpustate->st1.c = 1;
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}
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CYCLES(1);
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}
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static void op_crlt(tms32051_state *cpustate)
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{
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if (cpustate->acc < cpustate->accb)
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{
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cpustate->accb = cpustate->acc;
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cpustate->st1.c = 1;
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}
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else if (cpustate->acc > cpustate->accb)
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if (cpustate->acc >= cpustate->accb)
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{
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cpustate->acc = cpustate->accb;
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cpustate->st1.c = 0;
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}
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else
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{
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cpustate->st1.c = 0;
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cpustate->accb = cpustate->acc;
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cpustate->st1.c = 1;
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}
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CYCLES(1);
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@ -530,15 +522,7 @@ static void op_lacc_limm(tms32051_state *cpustate)
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static void op_lacc_s16_mem(tms32051_state *cpustate)
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{
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UINT16 ea = GET_ADDRESS(cpustate);
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if (cpustate->st1.sxm)
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{
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cpustate->acc = (INT32)(INT16)(DM_READ16(cpustate, ea)) << 16;
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}
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else
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{
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cpustate->acc = (UINT32)(DM_READ16(cpustate, ea)) << 16;
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}
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cpustate->acc = DM_READ16(cpustate, ea) << 16;
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CYCLES(1);
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}
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@ -565,10 +549,9 @@ static void op_lact(tms32051_state *cpustate)
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static void op_lamm(tms32051_state *cpustate)
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{
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UINT16 ea = GET_ADDRESS(cpustate);
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ea &= 0x7f;
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UINT16 ea = GET_ADDRESS(cpustate) & 0x7f;
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cpustate->acc = DM_READ16(cpustate, ea) & 0xffff;
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CYCLES(1);
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}
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@ -1423,14 +1406,7 @@ static void op_cpl_imm(tms32051_state *cpustate)
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UINT16 ea = GET_ADDRESS(cpustate);
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UINT16 data = DM_READ16(cpustate, ea);
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if (data == imm)
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{
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cpustate->st1.tc = 1;
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}
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else
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{
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cpustate->st1.tc = 0;
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}
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cpustate->st1.tc = (data == imm) ? 1 : 0;
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CYCLES(1);
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}
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@ -1640,16 +1616,8 @@ static void op_bit(tms32051_state *cpustate)
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{
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UINT16 ea = GET_ADDRESS(cpustate);
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UINT16 data = DM_READ16(cpustate, ea);
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int bit = 15 - ((cpustate->op >> 8) & 0xf);
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if (data & (1 << bit))
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{
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cpustate->st1.tc = 1;
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}
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else
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{
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cpustate->st1.tc = 0;
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}
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cpustate->st1.tc = (data >> (~cpustate->op >> 8 & 0xf)) & 1;
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CYCLES(1);
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}
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@ -1658,16 +1626,8 @@ static void op_bitt(tms32051_state *cpustate)
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{
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UINT16 ea = GET_ADDRESS(cpustate);
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UINT16 data = DM_READ16(cpustate, ea);
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int bit = 15 - (cpustate->treg2 & 0xf);
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if (data & (1 << bit))
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{
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cpustate->st1.tc = 1;
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}
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else
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{
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cpustate->st1.tc = 0;
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}
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cpustate->st1.tc = (data >> (~cpustate->treg2 & 0xf)) & 1;
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CYCLES(1);
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}
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@ -27,9 +27,10 @@ class horse_state : public driver_device
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{
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public:
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horse_state(const machine_config &mconfig, device_type type, const char *tag)
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: driver_device(mconfig, type, tag) ,
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: driver_device(mconfig, type, tag),
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m_video_ram(*this, "video_ram"),
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m_color_ram(*this, "color_ram"){ }
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m_color_ram(*this, "color_ram")
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{ }
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required_shared_ptr<UINT8> m_video_ram;
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required_shared_ptr<UINT8> m_color_ram;
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@ -94,7 +95,6 @@ ADDRESS_MAP_END
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READ8_MEMBER(horse_state::horse_input_r)
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{
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switch (m_output >> 6 & 3)
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{
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case 0: return ioport("IN0")->read();
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