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cpu/powerpc: Fixed issues in POWER div (signed divide) instruction causing GitHub #13329.

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This was "working" on x86-64 due to the backend treating shift/rotate
instructions with zero immediate bit count as a no-op even if the source
and destination registaer aren't the same.  Fixing the bug in the
back-end caused it to break the same way on x86-64 as it does on the
other three back-ends that didn't have this bug.
This commit is contained in:
Vas Crabb 2025-04-08 06:50:34 +10:00
parent 63be095e58
commit cce7b01de9
1 changed files with 10 additions and 5 deletions
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15
src/devices/cpu/powerpc/ppcdrc.cpp
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@ -2739,9 +2739,10 @@ bool ppc_device::generate_instruction_1f(drcuml_block &block, compiler_state *co
case 0x14b: /* DIV (POWER) */
assert(m_cap & PPCCAP_LEGACY_POWER);
UML_SHL(block, I0, R32(G_RB(op)), 32); // I0 = RA << 32
UML_OR(block, I0, I0, SPR32(SPR601_MQ)); // I0 |= MQ
UML_CMP(block, I0, 0x0); // cmp I0, #0
UML_MOV(block, I0, R32(G_RA(op)));
UML_MOV(block, I1, SPR32(SPR601_MQ));
UML_DSHL(block, I0, I0, 32); // I0 = RA << 32
UML_DOR(block, I0, I0, I1); // I0 |= MQ
UML_JMPc(block, COND_NZ, compiler->labelnum); // bne 0:
UML_MOV(block, R32(G_RD(op)), 0x0); // mov rd, #0
@ -2759,8 +2760,12 @@ bool ppc_device::generate_instruction_1f(drcuml_block &block, compiler_state *co
UML_JMP(block, compiler->labelnum + 1); // jmp 1:
UML_LABEL(block, compiler->labelnum++); // 0:
UML_DIVS(block, R32(G_RD(op)), SPR32(SPR601_MQ), I0, R32(G_RB(op))); // divs rd,mq,I0,rb
UML_LABEL(block, compiler->labelnum++);
UML_MOV(block, I1, R32(G_RB(op)));
UML_DSEXT(block, I1, I1, SIZE_DWORD);
UML_DDIVS(block, I0, I1, I0, I1);
UML_MOV(block, R32(G_RD(op)), I0);
UML_MOV(block, SPR32(SPR601_MQ), I1);
generate_compute_flags(block, desc, op & M_RC, ((op & M_OE) ? XER_OV | XER_SO : 0), false); // <update flags>
UML_LABEL(block, compiler->labelnum++); // 1:
return true;