netlist: Fix 74ls629 implementation and some cherry-picking issues.

This commit is contained in:
couriersud 2020-08-01 18:25:22 +02:00
parent c0ecd68341
commit d876f4cd82
8 changed files with 51 additions and 38 deletions

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@ -28,8 +28,10 @@
#if !NL_AUTO_DEVICES #if !NL_AUTO_DEVICES
#if !(NL_USE_TRUTHTABLE_7448) #if !(NL_USE_TRUTHTABLE_7448)
#define TTL_7448(name) \ // usage : TTL_7448(name, pA, pB, pC, pD, pLTQ, pBIQ, pRBIQ)
NET_REGISTER_DEV(TTL_7448, name) \ // auto connect: VCC, GND
#define TTL_7448(...) \
NET_REGISTER_DEVEXT(TTL_7448, __VA_ARGS__)
#endif #endif
#endif #endif

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@ -46,24 +46,17 @@ namespace netlist
{ {
namespace devices namespace devices
{ {
NETLIB_OBJECT(SN74LS629clk)
{
NETLIB_CONSTRUCTOR(SN74LS629clk)
, m_FB(*this, "FB", NETLIB_DELEGATE(fb))
, m_Y(*this, "Y")
, m_enableq(*this, "m_enableq", 1)
, m_out(*this, "m_out", 0)
, m_inc(*this, "m_inc", netlist_time::zero())
, m_power_pins(*this)
{
connect(m_FB, m_Y);
}
NETLIB_RESETI() struct SN74LS629clk
{
SN74LS629clk(device_t &owner)
: m_FB(owner, "FB", nldelegate(&SN74LS629clk::fb, this))
, m_Y(owner, "Y")
, m_enableq(owner, "m_enableq", 0)
, m_out(owner, "m_out", 0)
, m_inc(owner, "m_inc", netlist_time::zero())
{ {
m_enableq = 0; owner.connect(m_FB, m_Y);
m_out = 0;
m_inc = netlist_time::zero();
} }
public: public:
@ -73,7 +66,6 @@ namespace netlist
state_var<netlist_sig_t> m_enableq; state_var<netlist_sig_t> m_enableq;
state_var<netlist_sig_t> m_out; state_var<netlist_sig_t> m_out;
state_var<netlist_time> m_inc; state_var<netlist_time> m_inc;
nld_power_pins m_power_pins;
private: private:
NETLIB_HANDLERI(fb) NETLIB_HANDLERI(fb)
@ -94,7 +86,7 @@ namespace netlist
NETLIB_OBJECT(SN74LS629) NETLIB_OBJECT(SN74LS629)
{ {
NETLIB_CONSTRUCTOR(SN74LS629) NETLIB_CONSTRUCTOR(SN74LS629)
, m_clock(*this, "OSC") , m_clock(*this)
, m_R_FC(*this, "R_FC") , m_R_FC(*this, "R_FC")
, m_R_RNG(*this, "R_RNG") , m_R_RNG(*this, "R_RNG")
, m_ENQ(*this, "ENQ", NETLIB_DELEGATE(inputs)) , m_ENQ(*this, "ENQ", NETLIB_DELEGATE(inputs))
@ -102,8 +94,9 @@ namespace netlist
, m_FC(*this, "FC", NETLIB_DELEGATE(inputs)) , m_FC(*this, "FC", NETLIB_DELEGATE(inputs))
, m_CAP(*this, "CAP", nlconst::magic(1e-6)) , m_CAP(*this, "CAP", nlconst::magic(1e-6))
, m_power_pins(*this) , m_power_pins(*this)
, m_power_pins_osc(*this, "OSCVCC", "OSCGND")
{ {
connect(m_power_pins.GND(), m_R_FC.N()); connect(m_power_pins_osc.GND(), m_R_FC.N());
connect(m_FC, m_R_FC.P()); connect(m_FC, m_R_FC.P());
connect(m_RNG, m_R_RNG.P()); connect(m_RNG, m_R_RNG.P());
@ -116,7 +109,6 @@ namespace netlist
{ {
m_R_FC.set_R( nlconst::magic(90000.0)); m_R_FC.set_R( nlconst::magic(90000.0));
m_R_RNG.set_R(nlconst::magic(90000.0)); m_R_RNG.set_R(nlconst::magic(90000.0));
m_clock.reset();
} }
NETLIB_UPDATE_PARAMI() NETLIB_UPDATE_PARAMI()
@ -125,7 +117,7 @@ namespace netlist
} }
public: public:
NETLIB_SUB(SN74LS629clk) m_clock; SN74LS629clk m_clock;
analog::NETLIB_SUB(R_base) m_R_FC; analog::NETLIB_SUB(R_base) m_R_FC;
analog::NETLIB_SUB(R_base) m_R_RNG; analog::NETLIB_SUB(R_base) m_R_RNG;
@ -135,6 +127,7 @@ namespace netlist
param_fp_t m_CAP; param_fp_t m_CAP;
nld_power_pins m_power_pins; nld_power_pins m_power_pins;
nld_power_pins m_power_pins_osc;
private: private:
NETLIB_HANDLERI(inputs) NETLIB_HANDLERI(inputs)
@ -179,8 +172,6 @@ namespace netlist
// FIXME: we need a possibility to remove entries from queue ... // FIXME: we need a possibility to remove entries from queue ...
// or an exact model ... // or an exact model ...
m_clock.m_inc = netlist_time::from_fp(nlconst::half() / freq); m_clock.m_inc = netlist_time::from_fp(nlconst::half() / freq);
//NL_VERBOSE_OUT(("{1} {2} {3} {4}\n", name(), v_freq, v_rng, freq));
} }
if (!m_clock.m_enableq && m_ENQ()) if (!m_clock.m_enableq && m_ENQ())
@ -199,7 +190,7 @@ namespace netlist
}; };
NETLIB_DEVICE_IMPL(SN74LS629, "SN74LS629", "CAP") NETLIB_DEVICE_IMPL(SN74LS629, "SN74LS629", "CAP,@VCC,@GND")
} //namespace devices } //namespace devices
} // namespace netlist } // namespace netlist

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@ -30,7 +30,7 @@
#include "netlist/nl_setup.h" #include "netlist/nl_setup.h"
#define SN74LS629(name, p_cap) \ #define SN74LS629(name, ...) \
NET_REGISTER_DEVEXT(SN74LS629, name, p_cap) NET_REGISTER_DEVEXT(SN74LS629, name,__VA_ARGS__)
#endif /* NLD_74LS629_H_ */ #endif /* NLD_74LS629_H_ */

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@ -678,7 +678,7 @@ namespace factory
#define ENTRY(n, s) ENTRYY(n, 1, s); ENTRYY(n, 2, s); ENTRYY(n, 3, s); \ #define ENTRY(n, s) ENTRYY(n, 1, s); ENTRYY(n, 2, s); ENTRYY(n, 3, s); \
ENTRYY(n, 4, s); ENTRYY(n, 5, s); ENTRYY(n, 6, s); \ ENTRYY(n, 4, s); ENTRYY(n, 5, s); ENTRYY(n, 6, s); \
ENTRYY(n, 7, s); ENTRYY(n, 8, s); ENTRYY(n, 9, s); \ ENTRYY(n, 7, s); ENTRYY(n, 8, s); ENTRYY(n, 9, s); \
ENTRYY(n, 10, s); ENTRYY(n, 10, s)
host_arena::unique_ptr<truthtable_base_element_t> truthtable_create(tt_desc &desc, properties &&props) host_arena::unique_ptr<truthtable_base_element_t> truthtable_create(tt_desc &desc, properties &&props)
{ {

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@ -30,6 +30,10 @@
#define EPROM_2716_DIP(name) \ #define EPROM_2716_DIP(name) \
NET_REGISTER_DEV(EPROM_2716_DIP, name) NET_REGISTER_DEV(EPROM_2716_DIP, name)
// usage : TTL_82S16_DIP(name)
#define TTL_82S16_DIP(...) \
NET_REGISTER_DEVEXT(TTL_82S16_DIP, __VA_ARGS__)
#endif // NL_AUTO_DEVICES #endif // NL_AUTO_DEVICES

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@ -1332,17 +1332,19 @@ static NETLIST_START(SN74LS629_DIP)
NET_C(A.GND, B.GND) NET_C(A.GND, B.GND)
NET_C(A.VCC, B.VCC) NET_C(A.VCC, B.VCC)
NET_C(A.OSCGND, B.OSCGND)
NET_C(A.OSCVCC, B.OSCVCC)
NC_PIN(NC) NC_PIN(NC)
DIPPINS( /* +--------------+ */ DIPPINS( /* +--------------+ */
B.FC, /* 2FC |1 ++ 16| VCC */ NC.I, B.FC, /* 2FC |1 ++ 16| VCC */ A.VCC,
A.FC, /* 1FC |2 15| OSC VCC */ A.VCC, A.FC, /* 1FC |2 15| OSC VCC */ A.OSCVCC,
A.RNG, /* 1RNG |3 14| 2RNG */ B.RNG, A.RNG, /* 1RNG |3 14| 2RNG */ B.RNG,
NC.I, /* 1CX1 |4 74LS629 13| 2CX1 */ NC.I, NC.I, /* 1CX1 |4 74LS629 13| 2CX1 */ NC.I,
NC.I, /* 1CX2 |5 12| 2CX2 */ NC.I, NC.I, /* 1CX2 |5 12| 2CX2 */ NC.I,
A.ENQ, /* 1ENQ |6 11| 2ENQ */ B.ENQ, A.ENQ, /* 1ENQ |6 11| 2ENQ */ B.ENQ,
B.Y, /* 1Y |7 10| 2Y */ B.Y, B.Y, /* 1Y |7 10| 2Y */ B.Y,
A.GND, /* OSC GND |8 9| GND */ NC.I A.OSCGND, /* OSC GND |8 9| GND */ A.GND
/* +--------------+ */ /* +--------------+ */
) )
NETLIST_END() NETLIST_END()

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@ -369,6 +369,14 @@ namespace netlist
{ {
} }
// Some devices like the 74LS629 have two pairs of supply pins.
explicit nld_power_pins(device_t &owner,
const pstring &vcc, const pstring &gnd)
: m_VCC(owner, vcc, NETLIB_DELEGATE(noop))
, m_GND(owner, gnd, NETLIB_DELEGATE(noop))
{
}
const analog_input_t &VCC() const noexcept const analog_input_t &VCC() const noexcept
{ {
return m_VCC; return m_VCC;

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@ -53,14 +53,16 @@ static NETLIST_START(nl_mario_snd0)
SN74LS629(1J_A, CAP_N(3.9)) SN74LS629(1J_A, CAP_N(3.9))
NET_C(1J_A.RNG, V5) NET_C(1J_A.RNG, V5)
NET_C(1J_A.ENQ, ttllow) NET_C(1J_A.ENQ, ttllow)
NET_C(GND, 1J_A.GND) NET_C(GND, 1J_A.OSCGND)
NET_C(VCC, 1J_A.OSCVCC)
// #define MR_C17 CAP_N(22) /* verified */ // #define MR_C17 CAP_N(22) /* verified */
SN74LS629(2J_A, CAP_N(22)) SN74LS629(2J_A, CAP_N(22))
NET_C(2J_A.RNG, V5) NET_C(2J_A.RNG, V5)
NET_C(2J_A.ENQ, ttllow) NET_C(2J_A.ENQ, ttllow)
NET_C(GND, 2J_A.GND) NET_C(GND, 2J_A.OSCGND)
NET_C(VCC, 2J_A.OSCVCC)
TTL_7486_XOR(1K_A, 1J_A.Y, 2J_A.Y) TTL_7486_XOR(1K_A, 1J_A.Y, 2J_A.Y)
TTL_7408_AND(2K_A, 2H_A.Q, 1K_A) TTL_7408_AND(2K_A, 2H_A.Q, 1K_A)
@ -99,12 +101,14 @@ static NETLIST_START(nl_mario_snd1)
SN74LS629(1J_B, CAP_N(39)) /* C5 */ SN74LS629(1J_B, CAP_N(39)) /* C5 */
NET_C(1J_B.RNG, V5) NET_C(1J_B.RNG, V5)
NET_C(1J_B.ENQ, ttllow) NET_C(1J_B.ENQ, ttllow)
NET_C(GND, 1J_B.GND) NET_C(GND, 1J_B.OSCGND)
NET_C(VCC, 1J_B.OSCVCC)
SN74LS629(2J_B, CAP_N(6.8)) /* C16 */ SN74LS629(2J_B, CAP_N(6.8)) /* C16 */
NET_C(2J_B.RNG, V5) NET_C(2J_B.RNG, V5)
NET_C(2J_B.ENQ, ttllow) NET_C(2J_B.ENQ, ttllow)
NET_C(GND, 2J_B.GND) NET_C(GND, 2J_B.OSCGND)
NET_C(VCC, 2J_B.OSCVCC)
TTL_7486_XOR(1K_B, 1J_B.Y, 2J_B.Y) TTL_7486_XOR(1K_B, 1J_B.Y, 2J_B.Y)
TTL_7408_AND(2K_B, 2H_B.Q, 1K_B) TTL_7408_AND(2K_B, 2H_B.Q, 1K_B)
@ -139,7 +143,8 @@ static NETLIST_START(nl_mario_snd7)
SN74LS629(4K_A, CAP_U(0.022)) SN74LS629(4K_A, CAP_U(0.022))
NET_C(4K_A.RNG, V5) NET_C(4K_A.RNG, V5)
NET_C(4K_A.ENQ, ttllow) NET_C(4K_A.ENQ, ttllow)
NET_C(GND, 4K_A.GND) NET_C(GND, 4K_A.OSCGND)
NET_C(VCC, 4K_A.OSCVCC)
NET_C(R65.1, 4J_A.Q) NET_C(R65.1, 4J_A.Q)
NET_C(R65.2, 4K_A.FC, C44.1) NET_C(R65.2, 4K_A.FC, C44.1)
NET_C(C44.2, GND) NET_C(C44.2, GND)
@ -153,7 +158,8 @@ static NETLIST_START(nl_mario_snd7)
SN74LS629(4K_B, CAP_U(0.0047)) SN74LS629(4K_B, CAP_U(0.0047))
NET_C(4K_B.RNG, V5) NET_C(4K_B.RNG, V5)
NET_C(4K_B.ENQ, ttllow) NET_C(4K_B.ENQ, ttllow)
NET_C(GND, 4K_B.GND) NET_C(GND, 4K_B.OSCGND)
NET_C(VCC, 4K_B.OSCVCC)
NET_C(R64.1, 4J_B.Q) NET_C(R64.1, 4J_B.Q)
NET_C(R64.2, 4K_B.FC, C43.1) NET_C(R64.2, 4K_B.FC, C43.1)
NET_C(C43.2, GND) NET_C(C43.2, GND)