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(Thanks to MooglyGuy for the pointer)

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Removed hack in setting the timer in the MIPS core, which caused missed timers on the aleck64 games.
Fixed icount management in the RSP core which caused it to report negative cycle counts.
Fixes aleck64_0120red and mtetrisc0115u1red.
This commit is contained in:
Aaron Giles 2008-01-06 07:10:12 +00:00
parent aae4b919d1
commit dae5e71408
4 changed files with 7 additions and 10 deletions
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2
src/emu/cpu/mips/mdrc64.c
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@ -3034,7 +3034,7 @@ static int compile_set_cop0_reg(drc_core *drc, compiler_state *compiler, const o
emit_mov_r32_m32(DRCTOP, REG_EDX, CPR0ADDR(COP0_Status)); // mov edx,[Status]
emit_mov_m32_r32(DRCTOP, CPR0ADDR(COP0_Status), REG_EAX); // mov [Status],eax
emit_xor_r32_r32(DRCTOP, REG_EDX, REG_EAX); // xor edx,eax
emit_test_r32_imm(DRCTOP, REG_EDX, 0x8000); // test edx,0x8000
emit_test_r32_imm(DRCTOP, REG_EDX, SR_IMEX5); // test edx,0x8000
emit_jcc_short_link(DRCTOP, COND_Z, &link1); // jz skip
emit_lea_r64_m64(DRCTOP, REG_P1, COREADDR); // lea p1,[mips3.core]
emit_call_m64(DRCTOP, MDRC(&mips3.drcdata->mips3com_update_cycle_counting)); // call mips3com_update_cycle_counting

7
src/emu/cpu/mips/mips3com.c
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@ -174,16 +174,13 @@ offs_t mips3com_dasm(mips3_state *mips, char *buffer, offs_t pc, const UINT8 *op
void mips3com_update_cycle_counting(mips3_state *mips)
{
/* modify the timer to go off */
if ((mips->cpr[0][COP0_Status] & 0x8000) && mips->cpr[0][COP0_Compare] != 0xffffffff)
if ((mips->cpr[0][COP0_Status] & SR_IMEX5) && mips->cpr[0][COP0_Compare] != 0xffffffff)
{
UINT32 count = (activecpu_gettotalcycles64() - mips->count_zero_time) / 2;
UINT32 compare = mips->cpr[0][COP0_Compare];
UINT32 cyclesleft = compare - count;
attotime newtime = ATTOTIME_IN_CYCLES(((INT64)cyclesleft * 2), cpu_getactivecpu());
/* due to accuracy issues, don't bother setting timers unless they're for less than 100msec */
if (attotime_compare(newtime, ATTOTIME_IN_MSEC(100)) < 0)
timer_adjust(mips->compare_int_timer, newtime, cpu_getactivecpu(), attotime_zero);
timer_adjust(mips->compare_int_timer, newtime, cpu_getactivecpu(), attotime_zero);
}
else
timer_adjust(mips->compare_int_timer, attotime_never, cpu_getactivecpu(), attotime_zero);

2
src/emu/cpu/mips/mips3drc.c
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@ -233,7 +233,7 @@ static int mips3_execute(int cycles)
if (mips3.cache_dirty)
drc_cache_reset(mips3.drc);
mips3.cache_dirty = FALSE;
/* execute */
mips3.core->icount = cycles;
drc_execute(mips3.drc);

6
src/emu/cpu/rsp/rsp.c
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@ -2553,7 +2553,7 @@ static int rsp_execute(int cycles)
if( rsp.sr & ( RSP_STATUS_HALT | RSP_STATUS_BROKE ) )
{
rsp_icount = 0;
rsp_icount = MIN(rsp_icount, 0);
}
while (rsp_icount > 0)
@ -2589,7 +2589,7 @@ static int rsp_execute(int cycles)
case 0x0d: /* BREAK */
{
(config->sp_set_status)(0x3);
rsp_icount = 1;
rsp_icount = MIN(rsp_icount, 1);
#if LOG_INSTRUCTION_EXECUTION
fprintf(exec_output, "\n---------- break ----------\n\n");
@ -2788,7 +2788,7 @@ static int rsp_execute(int cycles)
if( rsp.sr & ( RSP_STATUS_HALT | RSP_STATUS_BROKE ) )
{
rsp_icount = 0;
rsp_icount = MIN(rsp_icount, 0);
}
}