mirror of
https://github.com/holub/mame
synced 2025-04-24 17:30:55 +03:00
Merge branch 'master' of https://github.com/mamedev/mame
This commit is contained in:
dankan1890
commit
db58451870
@ -82,11 +82,6 @@ void a26_rom_harmony_device::device_start()
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}
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static ADDRESS_MAP_START( harmony_arm7_map, AS_PROGRAM, 32, a26_rom_harmony_device )
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// these are not listed in the ARM manual as internal areas, so probably external? what maps here?
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AM_RANGE(0x3FFFC000, 0x3FFFC003) AM_RAM
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AM_RANGE(0x3FFFC010, 0x3FFFC013) AM_RAM
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AM_RANGE(0x3FFFC014, 0x3FFFC017) AM_RAM // reads
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AM_RANGE(0x3FFFC018, 0x3FFFC01b) AM_RAM
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ADDRESS_MAP_END
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static MACHINE_CONFIG_FRAGMENT( a26_harmony )
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@ -18,9 +18,24 @@ const device_type LPC2103 = &device_creator<lpc210x_device>;
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static ADDRESS_MAP_START( lpc2103_map, AS_PROGRAM, 32, lpc210x_device )
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AM_RANGE(0x00000000, 0x00007fff) AM_READWRITE(flash_r, flash_w) // 32kb internal FLASH rom
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AM_RANGE(0x40000000, 0x40001fff) AM_RAM // 8kb internal SROM (writes should actually latch - see docs)
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AM_RANGE(0x3FFFC000, 0x3FFFC01f) AM_READWRITE( fio_r, fio_w ) // GPIO
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AM_RANGE(0xE01FC088, 0xE01FC08b) AM_READ(arm_E01FC088_r)
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AM_RANGE(0x40000000, 0x40001fff) AM_RAM // 8kb internal SROM (writes should actually latch - see docs)
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AM_RANGE(0xE0004000, 0xE000407f) AM_READWRITE( timer0_r, timer0_w)
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AM_RANGE(0xE0008000, 0xE000807f) AM_READWRITE( timer1_r, timer1_w)
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AM_RANGE(0xE002C000, 0xE002C007) AM_READWRITE( pin_r, pin_w )
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AM_RANGE(0xE01FC000, 0xE01FC007) AM_READWRITE( mam_r, mam_w )
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AM_RANGE(0xE01FC080, 0xE01FC08f) AM_READWRITE( pll_r, pll_w ) // phase locked loop
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AM_RANGE(0xE01FC100, 0xE01FC103) AM_READWRITE( apbdiv_r, apbdiv_w )
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AM_RANGE(0xE01FC1a0, 0xE01FC1a3) AM_READWRITE( scs_r, scs_w )
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AM_RANGE(0xFFFFF000, 0xFFFFF2ff) AM_READWRITE( vic_r, vic_w ) // interrupt controller
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ADDRESS_MAP_END
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@ -71,7 +86,6 @@ void lpc210x_device::device_start()
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arm7_cpu_device::device_start();
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}
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//-------------------------------------------------
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// device_reset - device-specific reset
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//-------------------------------------------------
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@ -79,8 +93,188 @@ void lpc210x_device::device_start()
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void lpc210x_device::device_reset()
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{
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arm7_cpu_device::device_reset();
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m_TxPR[0] = 0;
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m_TxPR[1] = 0;
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}
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/* VIC (Vectored Interrupt Controller) */
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READ32_MEMBER( lpc210x_device::vic_r )
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{
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switch (offset*4)
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{
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default:
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logerror("%08x unhandled read from VIC offset %08x mem_mask %08x\n", space.device().safe_pc(), offset * 4, mem_mask);
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}
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return 0x00000000;
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}
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WRITE32_MEMBER( lpc210x_device::vic_w )
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{
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switch (offset * 4)
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{
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default:
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logerror("%08x unhandled write VIC offset %02x data %08x mem_mask %08x\n", space.device().safe_pc(), offset * 4, data, mem_mask);
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}
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}
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/* PIN Select block */
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READ32_MEMBER( lpc210x_device::pin_r )
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{
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switch (offset*4)
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{
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default:
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logerror("%08x unhandled read from PINSEL offset %08x mem_mask %08x\n",space.device().safe_pc(), offset * 4, mem_mask);
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}
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return 0x00000000;
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}
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WRITE32_MEMBER( lpc210x_device::pin_w )
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{
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switch (offset * 4)
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{
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default:
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logerror("%08x unhandled write PINSEL offset %02x data %08x mem_mask %08x\n", space.device().safe_pc(), offset * 4, data, mem_mask);
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}
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}
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/* MAM block (memory conttroller) */
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READ32_MEMBER( lpc210x_device::mam_r )
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{
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switch (offset*4)
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{
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default:
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logerror("%08x unhandled read from MAM offset %08x mem_mask %08x\n", space.device().safe_pc(), offset * 4, mem_mask);
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}
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return 0x00000000;
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}
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WRITE32_MEMBER( lpc210x_device::mam_w )
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{
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switch (offset * 4)
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{
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default:
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logerror("%08x unhandled write MAM offset %02x data %08x mem_mask %08x\n", space.device().safe_pc(), offset * 4, data, mem_mask);
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}
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}
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/* FIO block */
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READ32_MEMBER( lpc210x_device::fio_r )
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{
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switch (offset*4)
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{
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default:
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logerror("%08x unhandled read from FIO offset %08x mem_mask %08x\n", space.device().safe_pc(), offset * 4, mem_mask);
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}
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return 0x00000000;
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}
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WRITE32_MEMBER( lpc210x_device::fio_w )
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{
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switch (offset * 4)
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{
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default:
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logerror("%08x unhandled write FIO offset %02x data %08x mem_mask %08x\n", space.device().safe_pc(), offset * 4, data, mem_mask);
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}
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}
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/* APB Divider */
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READ32_MEMBER( lpc210x_device::apbdiv_r )
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{
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logerror("%08x unhandled read from APBDIV offset %08x mem_mask %08x\n", space.device().safe_pc(), offset * 4, mem_mask);
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return 0x00000000;
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}
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WRITE32_MEMBER( lpc210x_device::apbdiv_w )
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{
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logerror("%08x unhandled write APBDIV offset %02x data %08x mem_mask %08x\n", space.device().safe_pc(),offset * 4, data, mem_mask);
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}
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/* Syscon misc registers */
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READ32_MEMBER( lpc210x_device::scs_r )
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{
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logerror("%08x unhandled read from SCS offset %08x mem_mask %08x\n", space.device().safe_pc(),offset * 4, mem_mask);
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return 0x00000000;
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}
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WRITE32_MEMBER( lpc210x_device::scs_w )
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{
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logerror("%08x unhandled write SCS offset %02x data %08x mem_mask %08x\n", space.device().safe_pc(),offset * 4, data, mem_mask);
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}
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/* PLL Phase Locked Loop */
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READ32_MEMBER( lpc210x_device::pll_r )
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{
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switch (offset*4)
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{
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default:
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logerror("%08x unhandled read from PLL offset %08x mem_mask %08x\n", space.device().safe_pc(),offset * 4, mem_mask);
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}
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return 0xffffffff;
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}
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WRITE32_MEMBER( lpc210x_device::pll_w )
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{
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switch (offset * 4)
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{
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default:
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logerror("%08x unhandled write PLL offset %02x data %08x mem_mask %08x\n", space.device().safe_pc(),offset * 4, data, mem_mask);
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}
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}
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/* Timers */
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UINT32 lpc210x_device::read_timer(address_space &space, int timer, int offset, UINT32 mem_mask)
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{
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switch (offset*4)
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{
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case 0x0c:
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return m_TxPR[timer];
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default:
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logerror("%08x unhandled read from timer %d offset %02x mem_mask %08x\n", space.device().safe_pc(),timer, offset * 4, mem_mask);
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}
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return 0x00000000;
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}
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void lpc210x_device::write_timer(address_space &space, int timer, int offset, UINT32 data, UINT32 mem_mask)
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{
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switch (offset * 4)
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{
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case 0x0c:
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COMBINE_DATA(&m_TxPR[timer]);
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logerror("%08x Timer %d Prescale Register set to %08x\n", space.device().safe_pc(),timer, m_TxPR[timer]);
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break;
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default:
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logerror("%08x unhandled write timer %d offset %02x data %08x mem_mask %08x\n", space.device().safe_pc(),timer, offset * 4, data, mem_mask);
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}
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}
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static MACHINE_CONFIG_FRAGMENT( lpc210x )
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MACHINE_CONFIG_END
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@ -34,6 +34,45 @@ public:
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DECLARE_READ32_MEMBER(flash_r);
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DECLARE_WRITE32_MEMBER(flash_w);
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// timer 0 / 1
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DECLARE_READ32_MEMBER(timer0_r) { return read_timer(space, 0, offset, mem_mask); }
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DECLARE_WRITE32_MEMBER(timer0_w) { write_timer(space, 0, offset, data, mem_mask); }
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DECLARE_READ32_MEMBER(timer1_r) { return read_timer(space, 1, offset, mem_mask); }
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DECLARE_WRITE32_MEMBER(timer1_w) { write_timer(space, 1, offset, data, mem_mask); }
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void write_timer(address_space &space, int timer, int offset, UINT32 data, UINT32 mem_mask);
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UINT32 read_timer(address_space &space, int timer, int offset, UINT32 mem_mask);
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UINT32 m_TxPR[2];
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// VIC
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DECLARE_READ32_MEMBER(vic_r);
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DECLARE_WRITE32_MEMBER(vic_w);
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// PIN select block
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DECLARE_READ32_MEMBER(pin_r);
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DECLARE_WRITE32_MEMBER(pin_w);
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//PLL Phase Locked Loop
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DECLARE_READ32_MEMBER(pll_r);
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DECLARE_WRITE32_MEMBER(pll_w);
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//MAM memory controller
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DECLARE_READ32_MEMBER(mam_r);
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DECLARE_WRITE32_MEMBER(mam_w);
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//APB divider
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DECLARE_READ32_MEMBER(apbdiv_r);
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DECLARE_WRITE32_MEMBER(apbdiv_w);
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//syscon misc
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DECLARE_READ32_MEMBER(scs_r);
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DECLARE_WRITE32_MEMBER(scs_w);
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// fio
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DECLARE_READ32_MEMBER(fio_r);
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DECLARE_WRITE32_MEMBER(fio_w);
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protected:
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// device-level overrides
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@ -43,9 +82,18 @@ protected:
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virtual const address_space_config *memory_space_config(address_spacenum spacenum = AS_0) const;
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private:
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address_space_config m_program_config;
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};
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