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https://github.com/holub/mame
synced 2025-04-22 16:31:49 +03:00
Various comments added and updated to add input port details, more detailed rom, pal and prom labels, and driver/device details, for multiple drivers/devices. [Lord Nightmare]
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Lord-Nightmare
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560a1ae35f
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@ -81,7 +81,7 @@ void msx_cart_sfg05_device::device_add_mconfig(machine_config &config)
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ROM_START( msx_sfg01 )
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ROM_REGION(0x4000, "sfg", 0)
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ROM_LOAD("sfg01.rom", 0x0, 0x4000, CRC(0995fb36) SHA1(434651305f92aa770a89e40b81125fb22d91603d))
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ROM_LOAD("sfg01.rom", 0x0, 0x4000, CRC(0995fb36) SHA1(434651305f92aa770a89e40b81125fb22d91603d)) // correct label is almost certainly "yamaha__ym2211-22702__48_18_89_b.ic104" though the datecode portion may vary between late 1983 and mid 1984
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ROM_END
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@ -94,9 +94,9 @@ const tiny_rom_entry *msx_cart_sfg01_device::device_rom_region() const
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ROM_START( msx_sfg05 )
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ROM_REGION(0x8000, "sfg", 0)
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ROM_SYSTEM_BIOS( 0, "sfg05", "SFG05 (original)" )
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ROMX_LOAD( "sfg05.rom", 0x0, 0x8000, CRC(2425c279) SHA1(d956167e234f60ad916120437120f86fc8c3c321), ROM_BIOS(0) )
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ROMX_LOAD( "sfg05.rom", 0x0, 0x8000, CRC(2425c279) SHA1(d956167e234f60ad916120437120f86fc8c3c321), ROM_BIOS(0) ) // correct label MIGHT be "yamaha__ym2301-23959.ic104" but this needs redump/verification
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ROM_SYSTEM_BIOS( 1, "sfg05a", "SFG05 (SFG01 upgrade)" ) // SFG01 PCB, Yamaha official upgrade, has YM2151 instead of YM2164
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ROMX_LOAD( "sfg05a.rom", 0x0, 0x8000, CRC(5bc237f8) SHA1(930338f45c08228108c0831cc4a26014c2674718), ROM_BIOS(1) )
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ROMX_LOAD( "sfg05a.rom", 0x0, 0x8000, CRC(5bc237f8) SHA1(930338f45c08228108c0831cc4a26014c2674718), ROM_BIOS(1) ) // this came on a single eprom on a daughterboard on an SFG01 board which had been factory upgraded to SFG05
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ROM_END
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@ -127,7 +127,7 @@ pinsnd88_device::pinsnd88_device(const machine_config &mconfig, const char *tag,
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0 0 0 * * * * * * * * * * * * * RW - 0x0000 - SRAM @U7
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0 0 1 0 0 0 x x x x x x x x x * RW - 0x2000 - YM2151 @U16
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0 0 1 0 0 1 x x x x x x x x x x x - 0x2400 - open bus (hypothesis: leftover from cvsd_clock_set_w circuit)
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0 0 1 0 1 0 x x x x x x x x x x W[1]- 0x2800 - ANALOG SWITCH, input sound and output stereo control; on NARC, latch to respond to main pcb
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0 0 1 0 1 0 x x x x x x x x x x W[1]- 0x2800 - ANALOG SWITCH, goes to active low inputs of an ADG201 quad analog switch; on NARC, latch to respond to main pcb
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0 0 1 0 1 1 x x x x x x x x x x x - 0x2C00 - open bus (hypothesis: leftover from cvsd_digit_clock_clear_w circuit; on NARC, secondary command_w)
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0 0 1 1 0 0 x x x x x x x x x x W - 0x3000 - 7224 DAC write
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0 0 1 1 0 1 x x x x x x x x x x R[2]- 0x3400 - Latch Read and de-assert MC68B09E /IRQ
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@ -105,7 +105,7 @@
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Capable of running all romsets.
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* The following Romsets are known, ROUGHLY from oldest to newest:
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SV01, SV02, SV03, SV04, SV05, SV06 - undumped (rev 1), If this exists at all this would be the very first Japanese release of space invaders (Andy W may call this 'SV0'?)
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SV01, SV02, SV03, SV04, SV05, SV06 - undumped, this has never been seen in the wild and may never have existed.
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SV01, SV02, SV10, SV04, SV09, SV06 - sisv2 (rev 2) (Andy W calls this 'SV1', and the midway 'invaders' set is based on this romset)
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SV0H, SV02, SV10, SV04, SV09, SV06 - sisv3 (rev 3) (Andy W calls this 'SV2')
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SV0H, SV11, SV12, SV04, SV13, SV14 - sisv (rev 4, 5-digit scoring) (Andy W calls this 'SV3') (this set is likely newer than the TV0x sets)
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@ -442,7 +442,7 @@ ROM_START( circus )
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ROM_REGION( 0x0200, "gfx2", 0 ) // clown sprite
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ROM_LOAD( "9012.14d", 0x0000, 0x0200, CRC(2fde3930) SHA1(a21e2d342f16a39a07edf4bea8d698a52216ecba) )
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ROM_REGION( 0x400, "extra_proms", 0 ) // timing? not used by the emulation, dumped for the circusb bootleg but should match
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ROM_REGION( 0x400, "extra_proms", 0 ) // timing? not used by the emulation, dumped for the circusb bootleg but might match
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ROM_LOAD( "dm74s570-d4.4d", 0x000, 0x200, BAD_DUMP CRC(aad8da33) SHA1(1d60a6b75b94f5be5bad190ef56e9e3da20bf81a) )
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ROM_LOAD( "dm74s570-d5.5d", 0x200, 0x200, BAD_DUMP CRC(ed2493fa) SHA1(57ee357b68383b0880bfa385820605bede500747) )
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ROM_END
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@ -114,7 +114,7 @@ void fungames_state::fungames(machine_config &config)
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ROM_START( biplane4 )
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ROM_REGION( 0x10000, "maincpu", ROMREGION_ERASE00 )
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ROM_REGION( 0x0400, "roms", ROMREGION_ERASE00 )
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ROM_REGION( 0x0400, "roms", ROMREGION_ERASE00 ) /* 82s115 PROMS */
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ROM_LOAD( "biplane.p", 0x0000, 0x0200, CRC(0b3af146) SHA1(de7e4bffd4ca3baf3fe6017609d1b11fa9fc356a) )
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ROM_LOAD( "biplane.r", 0x0000, 0x0200, CRC(121eee0c) SHA1(fbdbc4da94dd9dba5903a6df321a9c2319f86dbd) )
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ROM_LOAD( "biplane.s", 0x0000, 0x0200, CRC(a57a1c43) SHA1(64d8e609415bc0fe51581bfea2e777106505c761) )
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@ -1309,7 +1309,7 @@ ROM_START( rampage )
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ROM_LOAD( "fg-3_4e_6-30-86.4e", 0x30000, 0x10000, CRC(81e1de40) SHA1(7e7818792845ec3687b3202eeade60a298ef513e) )
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ROM_REGION( 0x0001, "sg:pal", 0 ) /* Sounds Good board pal */
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ROM_LOAD( "e36a31axnaxqd.u15.bin", 0x0000, 0x0001, NO_DUMP) /* PAL20L10CNS */
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ROM_LOAD( "e36a31axnaxqd.u15.bin", 0x0000, 0x0001, NO_DUMP) /* PAL20L10CNS, called "SG01R0 PAL" with part number "E36-00803-0009" on the schematics */
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ROM_END
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@ -1336,7 +1336,7 @@ ROM_START( rampage2 )
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ROM_LOAD( "fg-3_4e_6-30-86.4e", 0x30000, 0x10000, CRC(81e1de40) SHA1(7e7818792845ec3687b3202eeade60a298ef513e) )
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ROM_REGION( 0x0001, "sg:pal", 0 ) /* Sounds Good board pal */
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ROM_LOAD( "e36a31axnaxqd.u15.bin", 0x0000, 0x0001, NO_DUMP) /* PAL20L10CNS */
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ROM_LOAD( "e36a31axnaxqd.u15.bin", 0x0000, 0x0001, NO_DUMP) /* PAL20L10CNS, called "SG01R0 PAL" with part number "E36-00803-0009" on the schematics */
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ROM_END
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@ -82,7 +82,7 @@ Notes:
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Other U* - 27C020 EPROMs
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Sound PCB
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Sound PCB (see /audio/s11c_bg.cpp)
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---------
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5766-12702-00 REV. B
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@ -105,6 +105,7 @@ Notes:
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6809 - clock 2.000MHz [8/4]
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YM2151 - clock 3.579545MHz
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55536 - Harris HC-55536 Continuously Variable Slope Delta Modulator
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(some early boards use an HC-55516, later boards use an HC-55536 or HC-55564)
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6116 - 2k x8 SRAM
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U* - 27C010 EPROMs
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J4 - flat cable connector from main board J8
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@ -287,7 +288,7 @@ INPUT_PORTS_END
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static INPUT_PORTS_START( trog )
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PORT_START("IN0")
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PORT_START("IN0") // Input 0-15 on D0-D15
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PORT_BIT( 0x0001, IP_ACTIVE_LOW, IPT_JOYSTICK_UP ) PORT_4WAY PORT_PLAYER(1)
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PORT_BIT( 0x0002, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN ) PORT_4WAY PORT_PLAYER(1)
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PORT_BIT( 0x0004, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT ) PORT_4WAY PORT_PLAYER(1)
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@ -301,7 +302,7 @@ static INPUT_PORTS_START( trog )
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PORT_BIT( 0x1000, IP_ACTIVE_LOW, IPT_BUTTON1 ) PORT_NAME("P2 Punch") PORT_PLAYER(2)
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PORT_BIT( 0xe000, IP_ACTIVE_LOW, IPT_UNUSED )
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PORT_START("IN1")
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PORT_START("IN1") // coin1,coin2,start1,tilt,test,start2,service1,input23-31 on D0-D15
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PORT_BIT( 0x0001, IP_ACTIVE_LOW, IPT_COIN1 )
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PORT_BIT( 0x0002, IP_ACTIVE_LOW, IPT_COIN2 )
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PORT_BIT( 0x0004, IP_ACTIVE_LOW, IPT_START1 )
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@ -319,7 +320,7 @@ static INPUT_PORTS_START( trog )
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PORT_BIT( 0x4000, IP_ACTIVE_LOW, IPT_JOYSTICK_RIGHT ) PORT_4WAY PORT_PLAYER(3)
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PORT_BIT( 0x8000, IP_ACTIVE_LOW, IPT_BUTTON1 ) PORT_NAME("P3 Punch") PORT_PLAYER(3)
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PORT_START("IN2")
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PORT_START("IN2") // input32-input39 on D0-D7; D8-D15 unused
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PORT_BIT( 0x0001, IP_ACTIVE_LOW, IPT_JOYSTICK_UP ) PORT_4WAY PORT_PLAYER(4)
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PORT_BIT( 0x0002, IP_ACTIVE_LOW, IPT_JOYSTICK_DOWN ) PORT_4WAY PORT_PLAYER(4)
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PORT_BIT( 0x0004, IP_ACTIVE_LOW, IPT_JOYSTICK_LEFT ) PORT_4WAY PORT_PLAYER(4)
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@ -328,7 +329,7 @@ static INPUT_PORTS_START( trog )
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PORT_BIT( 0x0020, IP_ACTIVE_LOW, IPT_COIN3 )
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PORT_BIT( 0xffc0, IP_ACTIVE_LOW, IPT_UNUSED )
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PORT_START("DSW")
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PORT_START("DSW") // DSW1 and DSW2 on D0-D15
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PORT_DIPNAME( 0x0001, 0x0001, DEF_STR( Unused ))
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PORT_DIPSETTING( 0x0001, DEF_STR( Off ))
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PORT_DIPSETTING( 0x0000, DEF_STR( On ))
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@ -511,8 +511,8 @@ ROM_START( redalert )
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ROM_LOAD( "ras3", 0x2000, 0x1000, CRC(20d56f3e) SHA1(5c32ee3365407e6d3f7ab5662e9ecbac437ed4cb) )
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ROM_LOAD( "ras4", 0x3000, 0x1000, CRC(130e66db) SHA1(385b8f889fee08fddbb2f75a691af569109eacd1) )
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ROM_REGION( 0x0200, "proms", 0 ) /* color PROM */
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ROM_LOAD( "m-257sc.1a", 0x0000, 0x0200, CRC(b1aca792) SHA1(db37f99b9880cc3c434e2a55a0bbb017d9a72aa3) ) /* 512*8 74S472 or compatible BPROM like a 82s147 */
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ROM_REGION( 0x0200, "proms", 0 ) /* color PROM, on an "M-33 SUB-2" daughterpcb with 8 resistors and a prom, plugged into a 20 pin socket; the actual prom is a TBP18s22N 256x8 prom, but the pcb is silkscreened 'S472' so it can handle either a 256x8 (82s135-style) or 512x8 (82s147-style) prom */
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ROM_LOAD( "m-257sc.1a", 0x0000, 0x0200, CRC(b1aca792) SHA1(db37f99b9880cc3c434e2a55a0bbb017d9a72aa3) ) /* 256x8 data dumped from a 512*8 74S472 or compatible BPROM like a 82s147; note that since this was dumped as the 'wrong' type, A5 is tied low, and board A5 goes to prom A6, likewise BA6->A7, BA7->A8 */
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ROM_END
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@ -2,10 +2,10 @@
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// copyright-holders:Jonathan Gevaryahu
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// thanks-to:Kevin Horton
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/******************************************************************************
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*
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* Votrax/Phonic Mirror HandiVolce models HC-110 and HC-120
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*
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******************************************************************************/
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*
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* Votrax/Phonic Mirror HandiVoice models HC-110 and HC-120
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*
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*****************************************************************************/
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/*
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The HC-110 and HC-120 both consist of 3 boards:
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1. An 'embedded system' 6800 board with two output latches, one input
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@ -423,8 +423,9 @@
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three ROMs, and a smaller board with lots of ROMs,
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the CPU, the 6821 PIAs, and the two "Special Chip 2"
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custom BIT/BLT chips.
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Joust 2 has an additional music/speech board that has a
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68B09E CPU, 68B21 PIA, Harris 55564-5 CVSD, and a YM2151.
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Joust 2 has an additional D-11298 Williams System 11 background
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music/speech board (the older board version from PIN*BOT)
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that has a 68B09E CPU, 68B21 PIA, Harris 55564-5 CVSD, and a YM2151.
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Contact Michael Soderstrom (ichael@geocities.com) if you
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have any additional information or corrections.
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@ -199,16 +199,36 @@ TMS340X0_FROM_SHIFTREG_CB_MEMBER(midyunit_state::from_shiftreg)
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void midyunit_state::midyunit_control_w(offs_t offset, uint16_t data, uint16_t mem_mask)
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{
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/*
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* Narc system register
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* Narc 'Z-unit' system register, accessed via '/SEL.MISC' being asserted
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* ------------------
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*
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* | Bit | Use
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* --+-FEDCBA9876543210-+------------
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* | xxxxxxxx-------- | 7 segment led on CPU board
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* | --------xx------ | CMOS page
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* | ----------x----- | - OBJ PAL RAM select
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* | -----------x---- | - autoerase enable
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* | ---------------- | - watchdog
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* | xxxxxxxx-------- | 7 segment led on CPU board
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* | --------xx------ | CMOS page, selected by feeding the '/SPK.0' D6 and '/SPK.1' D7 through an EP800 PLD @U12
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* | ----------x----- | /OBJ PAL RAM select
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* | -----------x---- | /autoerase enable
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* | ------------x--- | /bg enable
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* | -------------x-- | /bg priority
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* | --------------x- | fg scroll 1
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* | ---------------x | fg scroll 0
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* | --------xx----xx | watchdog is triggered on any (state change? rising edge? needs testing, the EP800 @U12 controls this) of these bits, and the EP800 likely also counts pulses the /BLANK bit from the tms34010
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*
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*/
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/*
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* Y-unit system register, accessed via '/SEL.MISC' being asserted ('later' is from the super high impact schematics vs main labels are from the trog schematics)
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* ------------------
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*
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* | Bit | Use
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* --+-FEDCBA9876543210-+------------
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* | OPEN_BUS-------- | upper 8 bits are open bus
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* | " " xx------ | CMOS page, selected by feeding the '/SPK.0' (later CBANK1) D6 and '/SPK.1' (later CBANK0) D7 through an EP800 PLD @U12
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* | " " --x----- | /OBJ PAL RAM select
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* | " " ---x---- | /autoerase enable
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* | " " ----x--- | N/C (later 'EXT')
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* | " " -----x-- | /LED
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* | " " ------x- | fg scroll 1 (later 'WD.DAT')
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* | " " -------x | fg scroll 0 (later 'WD.CLK')
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*
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*/
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