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https://github.com/holub/mame
synced 2025-05-14 18:08:13 +03:00
Added CLR, starting to understand why it wasn't working before ...
This commit is contained in:
Angelo Salese
parent
57116c6699
commit
e25be75dd5
@ -5,6 +5,7 @@
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TODO:
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- 8-bit support for FIFO, parameters and command values
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- convert to C++
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- execution cycles;
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***************************************************************************/
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@ -33,8 +34,12 @@ h63484_device::h63484_device(const machine_config &mconfig, const char *tag, dev
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m_fifo_r_ptr(-1),
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m_cr(0),
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m_param_ptr(0),
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m_rwp(0),
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m_rwp_dn(0),
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m_org_dpa(0),
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m_org_dn(0),
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m_org_dpd(0),
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m_cl0(0),
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m_cl1(0),
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m_space_config("videoram", ENDIANNESS_LITTLE, 8, 20, 0, NULL, *ADDRESS_MAP_NAME(h63484_vram))
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{
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m_shortname = "h63484";
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@ -63,11 +68,6 @@ enum
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#define H63484_SR_WFE 0x01 // Write FIFO Empty
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#define CCR 0x02
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// Command Control
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#define ABT 0x8000
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static const char *const acrtc_regnames[0x100/2] =
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{
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"FIFO Entry", // 0x00
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@ -614,20 +614,89 @@ void h63484_device::command_end_seq()
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void h63484_device::command_wpr_exec()
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{
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if(LOG) printf("%s -> %02x\n",wpr_regnames[m_cr & 0x1f],m_pr[0]);
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switch(m_cr & 0x1f)
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{
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case 0x00: // color 0
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m_cl0 = m_pr[0];
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break;
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case 0x01: // color 1
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m_cl1 = m_pr[0];
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break;
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case 0x0c: // Read Write Pointer H
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m_rwp_dn = (m_pr[0] & 0xc000) >> 14;
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m_rwp = (m_rwp & 0x00fff) | ((m_pr[0] & 0x00ff) << 12);
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m_rwp[m_rwp_dn] = (m_rwp[m_rwp_dn] & 0x00fff) | ((m_pr[0] & 0x00ff) << 12);
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break;
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case 0x0d: // Read Write Pointer L
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m_rwp = (m_rwp & 0xff000) | ((m_pr[0] & 0xfff0) >> 4);
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m_rwp[m_rwp_dn] = (m_rwp[m_rwp_dn] & 0xff000) | ((m_pr[0] & 0xfff0) >> 4);
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break;
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default:
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if(LOG) printf("%s -> %02x\n",wpr_regnames[m_cr & 0x1f],m_pr[0]);
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break;
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}
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}
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void h63484_device::command_clr_exec()
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{
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INT16 ax, ay;
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UINT16 d;
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INT16 x,y;
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int inc_x,inc_y;
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UINT32 offset;
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UINT8 data_r;
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UINT8 res;
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d = m_pr[0];
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ax = m_pr[1];
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ay = m_pr[2];
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inc_x = (ax < 0) ? -1 : 1;
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inc_y = (ay < 0) ? -1 : 1;
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offset = m_rwp[m_rwp_dn] & 0xfffff;
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for(y=0;y!=ay;y+=inc_y)
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{
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for(x=0;x!=ax;x+=inc_x)
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{
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offset = (m_rwp[m_rwp_dn] + (x >> 1) + y * m_mwr[m_rwp_dn]) & 0xfffff; /* TODO: address if bpp != 4 */
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data_r = readbyte(offset);
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res = (d >> (((x & 2) << 2) ^ 8)) & 0xff;
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switch(m_cr & 3)
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{
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case 0: // replace
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if(x & 1)
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res = (res & 0x0f) | (data_r & 0xf0);
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else
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res = (res & 0xf0) | (data_r & 0x0f);
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break;
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case 1: // OR
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if(x & 1)
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res = (res & 0xff) | (data_r & 0xf0);
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else
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res = (res & 0xff) | (data_r & 0x0f);
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break;
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case 2: // AND
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if(x & 1)
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res = (res & 0x0f) | ((res & 0xf0) & (data_r & 0xf0));
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else
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res = (res & 0xf0) | ((res & 0x0f) & (data_r & 0x0f));
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break;
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case 3: // EOR
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if(x & 1)
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res = (res & 0x0f) | ((res & 0xf0) ^ (data_r & 0xf0));
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else
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res = (res & 0xf0) | ((res & 0x0f) ^ (data_r & 0x0f));
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break;
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}
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writebyte(offset,res);
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}
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}
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m_rwp[m_rwp_dn] = offset;
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}
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void h63484_device::process_fifo()
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{
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UINT8 data;
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@ -657,11 +726,20 @@ void h63484_device::process_fifo()
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m_sr |= H63484_SR_CER; // command error
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break;
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case COMMAND_ORG:
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if (m_param_ptr == 2)
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{
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m_org_dn = (m_pr[0] & 0xc000) >> 14;
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m_org_dpa = ((m_pr[0] & 0xff) << 12) | ((m_pr[1] & 0xfff0) >> 4);
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m_org_dpd = (m_pr[1] & 0xf);
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// TODO: CP = 0
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command_end_seq();
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}
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break;
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case COMMAND_WPR: // 0x0800 & ~0x1f
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if (m_param_ptr == 1)
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{
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printf("%04x\n",m_pr[0]);
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command_wpr_exec();
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command_end_seq();
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}
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@ -670,13 +748,25 @@ void h63484_device::process_fifo()
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case COMMAND_RD:
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if (m_param_ptr == 0)
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{
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queue_r(readbyte((m_rwp+0) & 0xfffff));
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queue_r(readbyte((m_rwp+1) & 0xfffff));
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m_rwp+=2;
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m_rwp&=0xfffff;
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queue_r(readbyte((m_rwp[m_rwp_dn]+0) & 0xfffff));
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queue_r(readbyte((m_rwp[m_rwp_dn]+1) & 0xfffff));
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m_rwp[m_rwp_dn]+=2;
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m_rwp[m_rwp_dn]&=0xfffff;
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command_end_seq();
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}
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break;
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case COMMAND_CLR:
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if (m_param_ptr == 3)
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{
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command_clr_exec();
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command_end_seq();
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}
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break;
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default:
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fatalerror("stop!\n");
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break;
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}
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}
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@ -697,10 +787,17 @@ void h63484_device::check_video_registers(int offset)
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{
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case 0x00: // FIFO entry, not covered there
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break;
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case CCR: // Command Entry
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if(vreg_data & ABT) // abort sequence
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case 0x02: // Command Entry
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if(vreg_data & 0x8000) // abort sequence
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exec_abort_sequence();
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break;
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case 0xc2: // Memory Width Register
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case 0xca:
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case 0xd2:
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case 0xda:
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m_mwr[(offset & 0x18) >> 3] = vreg_data & 0xfff; // pitch
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m_mwr_chr[(offset & 0x18) >> 3] = (vreg_data & 0x8000) >> 15;
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break;
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}
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}
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@ -726,7 +823,11 @@ READ16_MEMBER( h63484_device::data_r )
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}
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else
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{
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if(LOG) printf("%s R\n",acrtc_regnames[m_ar/2]);
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if(m_ar == 0x80)
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res = m_screen->vpos() & 0xfff; // Raster Count
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else
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if(LOG) printf("%s R\n",acrtc_regnames[m_ar/2]);
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}
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return res;
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@ -80,6 +80,7 @@ private:
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void command_end_seq();
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void command_wpr_exec();
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void command_clr_exec();
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void process_fifo();
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void exec_abort_sequence();
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void check_video_registers(int offset);
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@ -104,9 +105,18 @@ private:
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UINT16 m_pr[9]; /* parameter byte register */
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int m_param_ptr; /* parameter pointer */
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UINT32 m_rwp;
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UINT32 m_rwp[4];
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UINT8 m_rwp_dn;
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UINT32 m_org_dpa;
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UINT8 m_org_dn;
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UINT8 m_org_dpd;
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UINT16 m_cl0;
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UINT16 m_cl1;
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UINT16 m_mwr[4];
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UINT8 m_mwr_chr[4];
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const address_space_config m_space_config;
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};
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