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nds: fleshing out a few more things (nw)

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This commit is contained in:
arbee 2017-11-20 23:17:43 -05:00
parent a9934e830a
commit e4ef4dd0f7
2 changed files with 56 additions and 6 deletions
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57
src/mame/drivers/nds.cpp
View File

@ -28,6 +28,7 @@ static inline void ATTR_PRINTF(3,4) verboselog(device_t &device, int n_level, co
READ32_MEMBER(nds_state::arm7_io_r)
{
uint8_t temp1, temp2;
switch(offset)
{
case IPCSYNC_OFFSET:
@ -43,8 +44,9 @@ READ32_MEMBER(nds_state::arm7_io_r)
return m_arm7_postflg;
case WRAMSTAT_OFFSET:
printf("ARM7: read WRAMSTAT mask %08x\n", mem_mask);
return m_wramcnt;
temp1 = (((m_vramcntc & 3) == 2) && (m_vramcntc & 0x80)) ? 1 : 0;
temp2 = (((m_vramcntd & 3) == 2) && (m_vramcntd & 0x80)) ? 2 : 0;
return (m_wramcnt << 8) | temp1 | temp2;
default:
verboselog(*this, 0, "[ARM7] [IO] Unknown read: %08x (%08x)\n", offset*4, mem_mask);
@ -115,10 +117,55 @@ WRITE32_MEMBER(nds_state::arm9_io_w)
m_arm9_ipcsync |= (data & ~0xf);
break;
case VRAMCNT_A_OFFSET:
if (ACCESSING_BITS_0_7) // VRAMCNT_A
{
m_vramcnta = data & 0xff;
}
if (ACCESSING_BITS_8_15) // VRAMCNT_B
{
m_vramcntb = (data >> 8) & 0xff;
}
if (ACCESSING_BITS_16_23) // VRAMCNT_C
{
m_vramcntc = (data >> 16) & 0xff;
}
if (ACCESSING_BITS_24_31) // VRAMCNT_D
{
m_vramcntd = (data >> 24) & 0xff;
}
break;
case WRAMCNT_OFFSET:
m_wramcnt = (data>>24) & 0x3;
m_arm7wrambnk->set_bank(m_wramcnt);
m_arm9wrambnk->set_bank(m_wramcnt);
if (ACCESSING_BITS_0_7) // VRAMCNT_E
{
m_vramcnte = data & 0xff;
}
if (ACCESSING_BITS_8_15) // VRAMCNT_F
{
m_vramcntf = (data >> 8) & 0xff;
}
if (ACCESSING_BITS_16_23) // VRAMCNT_G
{
m_vramcntg = (data >> 16) & 0xff;
}
if (ACCESSING_BITS_24_31) // WRAMCNT
{
m_wramcnt = (data>>24) & 0x3;
m_arm7wrambnk->set_bank(m_wramcnt);
m_arm9wrambnk->set_bank(m_wramcnt);
}
break;
case VRAMCNT_H_OFFSET:
if (ACCESSING_BITS_0_7) // VRAMCNT_H
{
m_vramcnth = data & 0xff;
}
if (ACCESSING_BITS_8_15) // VRAMCNT_I
{
m_vramcnti = (data >> 8) & 0xff;
}
break;
case POSTFLG_OFFSET:

5
src/mame/includes/nds.h
View File

@ -51,7 +51,9 @@ protected:
IPCSYNC_OFFSET = 0x180/4,
GAMECARD_BUS_CTRL_OFFSET = 0x1a4/4,
WRAMSTAT_OFFSET = 0x241/4,
WRAMCNT_OFFSET = 0x247/4,
VRAMCNT_A_OFFSET = 0x240/4,
WRAMCNT_OFFSET = 0x244/4,
VRAMCNT_H_OFFSET = 0x248/4,
POSTFLG_OFFSET = 0x300/4,
POSTFLG_PBF_SHIFT = 0,
POSTFLG_RAM_SHIFT = 1,
@ -64,6 +66,7 @@ protected:
uint16_t m_arm7_ipcsync, m_arm9_ipcsync;
uint8_t m_WRAM[0x8000];
uint8_t m_wramcnt;
uint8_t m_vramcnta, m_vramcntb, m_vramcntc, m_vramcntd, m_vramcnte, m_vramcntf, m_vramcntg, m_vramcnth, m_vramcnti;
};
#endif // INCLUDES_NDS_H