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mips3.cpp: Added logging of cache opcodes, nw
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@ -80,7 +80,7 @@
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#define IS_FR1 (SR & SR_FR)
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/* size of the execution code cache */
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#define CACHE_SIZE (32 * 1024 * 1024)
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#define DRC_CACHE_SIZE (32 * 1024 * 1024)
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@ -166,7 +166,7 @@ mips3_device::mips3_device(const machine_config &mconfig, device_type type, cons
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, c_dcache_size(0)
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, m_fastram_select(0)
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, m_debugger_temp(0)
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, m_drc_cache(CACHE_SIZE + sizeof(internal_mips3_state) + 0x80000)
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, m_drc_cache(DRC_CACHE_SIZE + sizeof(internal_mips3_state) + 0x80000)
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, m_drcuml(nullptr)
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, m_drcfe(nullptr)
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, m_drcoptions(0)
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@ -5500,5 +5500,94 @@ void mips3_device::load_elf()
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void r5000be_device::handle_cache(uint32_t op)
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{
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// Handle as a no-op for now
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if ((SR & SR_KSU_MASK) != SR_KSU_KERNEL && !(SR & SR_COP0))
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{
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m_badcop_value = 0;
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generate_exception(EXCEPTION_BADCOP, 1);
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return;
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}
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const uint32_t vaddr = RSVAL32 + SIMMVAL;
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switch (CACHE_TYPE)
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{
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case 0: // Primary Instruction
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switch (CACHE_OP)
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{
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case 0: // Index Invalidate
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logerror("%s: MIPS3: Not yet implemented: cache: vaddr %08x, I-Cache Index Invalidate\n", machine().describe_context(), vaddr);
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break;
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case 1: // Index Load Tag
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logerror("%s: MIPS3: Not yet implemented: cache: vaddr %08x, I-Cache Index Load Tag\n", machine().describe_context(), vaddr);
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break;
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case 2: // Index Store Tag
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logerror("%s: MIPS3: Not yet implemented: cache: vaddr %08x, I-Cache Index Store Tag\n", machine().describe_context(), vaddr);
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break;
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case 4: // Hit Invalidate
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logerror("%s: MIPS3: Not yet implemented: cache: vaddr %08x, I-Cache Hit Invalidate\n", machine().describe_context(), vaddr);
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break;
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case 5: // Fill
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logerror("%s: MIPS3: Not yet implemented: cache: vaddr %08x, I-Cache Fill \n", machine().describe_context(), vaddr);
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break;
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case 6: // Hit WriteBack
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logerror("%s: MIPS3: Not yet implemented: cache: vaddr %08x, I-Cache Hit WriteBack\n", machine().describe_context(), vaddr);
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break;
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default:
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logerror("%s: MIPS3: %08x specifies invalid I-Cache op %d, vaddr %08x\n", machine().describe_context(), op, CACHE_OP, vaddr);
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break;
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}
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break;
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case 1: // Primary Data
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switch (CACHE_OP)
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{
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case 0: // Index WriteBack Invalidate
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logerror("%s: MIPS3: Not yet implemented: cache: vaddr %08x, D-Cache Index WriteBack Invalidate\n", machine().describe_context(), vaddr);
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break;
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case 1: // Index Load Tag
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logerror("%s: MIPS3: Not yet implemented: cache: vaddr %08x, D-Cache Index Load Tag\n", machine().describe_context(), vaddr);
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break;
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case 2: // Index Store Tag
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logerror("%s: MIPS3: Not yet implemented: cache: vaddr %08x, D-Cache Index Store Tag\n", machine().describe_context(), vaddr);
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break;
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case 3: // Create Dirty Exclusive
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logerror("%s: MIPS3: Not yet implemented: cache: vaddr %08x, D-Cache Create Dirty Exclusive\n", machine().describe_context(), vaddr);
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break;
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case 4: // Hit Invalidate
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logerror("%s: MIPS3: Not yet implemented: cache: vaddr %08x, D-Cache Hit Invalidate\n", machine().describe_context(), vaddr);
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break;
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case 5: // Hit WriteBack Invalidate
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logerror("%s: MIPS3: Not yet implemented: cache: vaddr %08x, D-Cache Hit WriteBack Invalidate\n", machine().describe_context(), vaddr);
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break;
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case 6: // Hit WriteBack
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logerror("%s: MIPS3: Not yet implemented: cache: vaddr %08x, D-Cache Hit WriteBack\n", machine().describe_context(), vaddr);
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break;
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default:
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logerror("%s: MIPS3: %08x specifies invalid D-Cache op %d, vaddr %08x\n", machine().describe_context(), op, CACHE_OP, vaddr);
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break;
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}
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break;
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case 3: // Secondary Cache
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switch (CACHE_OP)
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{
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case 0: // Cache Clear
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logerror("%s: MIPS3: Not yet implemented: cache: vaddr %08x, SC Cache Clear\n", machine().describe_context(), vaddr);
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break;
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case 1: // Index Load Tag
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logerror("%s: MIPS3: Not yet implemented: cache: vaddr %08x, SC Index Load Tag\n", machine().describe_context(), vaddr);
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break;
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case 2: // Index Store Tag
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logerror("%s: MIPS3: Not yet implemented: cache: vaddr %08x, SC Index Store Tag\n", machine().describe_context(), vaddr);
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break;
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case 5: // Cache Page Invalidate
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logerror("%s: MIPS3: Not yet implemented: cache: vaddr %08x, SC Cache Page Invalidate\n", machine().describe_context(), vaddr);
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break;
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default:
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logerror("%s: MIPS3: %08x specifies invalid SC cache op %d, vaddr %08x\n", machine().describe_context(), op, CACHE_OP, vaddr);
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break;
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}
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break;
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default:
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logerror("%s: MIPS3: %08x specifies invalid cache type %d, vaddr %08x\n", machine().describe_context(), op, CACHE_TYPE, vaddr);
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break;
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}
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}
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@ -187,5 +187,7 @@
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#define UIMMVAL ((uint16_t)op)
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#define LIMMVAL (op & 0x03ffffff)
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#define CACHE_TYPE ((op >> 16) & 3)
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#define CACHE_OP ((op >> 18) & 7)
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#endif // MAME_CPU_MIPS_MIPS3COM_H
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