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heathkit/h89.cpp: Implement more functionality, add new monitor ROMs, add more tech details (#11108)
* heathkit/h89.cpp: Implement more functionality, add new monitor ROMs, add more tech details
This commit is contained in:
Mark Garlanger
GitHub
parent
9de67ba595
commit
eb6bf1e689
@ -4,6 +4,16 @@
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Heathkit H89
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Heath Company made several very similar systems, including
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- H88 - kit, came with a cassette interface board instead of floppy controller
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- H89 - kit, came with a hard-sectored floppy disk controller
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- WH89 - was factory assembled
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Heath's parent company Zenith, also sold systems under the Zenith Data
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Systems brand. These were all factory assembled
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- Z-89 - same as Heath's H89, but assembled
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- Z-90 - came with a soft-sectored floppy disk controller
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Monitor Commands (for MTR-90):
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B Boot
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C Convert (number)
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@ -15,6 +25,20 @@
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T Test Memory
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V View
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Monitor Commands (for MTR-88)
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B Boot
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D Dump - dump a program to cassette
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G Go (address)
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L Load - load a program from cassette
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P Program Counter (address) - select an address in the PC
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S Substitute - inspect or change memory
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Monitor Commands (for MTR-89)
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B Boot
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G Go (address)
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P Program Counter (address) - select an address in the PC
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S Substitute - inspect or change memory
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****************************************************************************/
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#include "emu.h"
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@ -23,22 +47,31 @@
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#include "cpu/z80/z80.h"
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#include "machine/ins8250.h"
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#include "machine/ram.h"
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#include "machine/timer.h"
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namespace {
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#define H89_CLOCK (XTAL(12'288'000) / 6)
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#define INS8250_CLOCK (XTAL(1'843'200))
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class h89_state : public driver_device
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{
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public:
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h89_state(const machine_config &mconfig, device_type type, const char *tag) :
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driver_device(mconfig, type, tag),
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m_maincpu(*this, "maincpu"),
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m_tlb(*this, "tlb"),
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m_console(*this, "console")
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h89_state(const machine_config &mconfig, device_type type, const char *tag)
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: driver_device(mconfig, type, tag)
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, m_maincpu(*this, "maincpu")
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, m_maincpu_region(*this, "maincpu")
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, m_mem_view(*this, "rom_bank")
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, m_ram(*this, RAM_TAG)
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, m_floppy_ram(*this, "floppyram")
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, m_tlb(*this, "tlb")
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, m_console(*this, "console")
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, m_serial1(*this, "serial1")
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, m_serial2(*this, "serial2")
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, m_serial3(*this, "serial3")
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, m_gpp(0)
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, m_rom_enabled(true)
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, m_timer_intr_enabled(true)
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, m_floppy_ram_wp(true)
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{
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}
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@ -46,62 +79,167 @@ public:
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private:
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required_device<cpu_device> m_maincpu;
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required_memory_region m_maincpu_region;
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memory_view m_mem_view;
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required_device<ram_device> m_ram;
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required_shared_ptr<uint8_t> m_floppy_ram;
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required_device<heath_tlb_device> m_tlb;
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required_device<ins8250_device> m_console;
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required_device<ins8250_device> m_serial1;
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required_device<ins8250_device> m_serial2;
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required_device<ins8250_device> m_serial3;
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// General Purpose Port (GPP)
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uint8_t m_gpp;
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bool m_rom_enabled;
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bool m_timer_intr_enabled;
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bool m_floppy_ram_wp;
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// Clocks
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static constexpr XTAL H89_CLOCK = XTAL(12'288'000) / 6;
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static constexpr XTAL INS8250_CLOCK = XTAL(1'843'200);
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static constexpr uint8_t GPP_SINGLE_STEP_BIT = 0;
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static constexpr uint8_t GPP_ENABLE_TIMER_INTERRUPT_BIT = 1;
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static constexpr uint8_t GPP_DISABLE_ROM_BIT = 5;
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static constexpr uint8_t GPP_H17_SIDE_SELECT_BIT = 6;
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void update_mem_view();
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void update_gpp(uint8_t gpp);
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void port_f2_w(uint8_t data);
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uint8_t m_port_f2 = 0;
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virtual void machine_start() override;
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virtual void machine_reset() override;
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TIMER_DEVICE_CALLBACK_MEMBER(h89_irq_timer);
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void h89_io(address_map &map);
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void h89_mem(address_map &map);
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uint8_t raise_NMI_r();
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void raise_NMI_w(uint8_t data);
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};
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/*
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The H89 supported 16K, 32K, 48K, or 64K of RAM. The first 8K of address space
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is reserved for the monitor ROM, floppy ROM, and scratch pad RAM. For 16k-48K
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sizes, the upper 8k of memory is remapped to the first 8K when the ROM is disabled.
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For systems with 64K of RAM, the upper half of the expansion board is permanently
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mapped to the lower 8K. Even when ROM is mapped, any writes will still occur
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to the RAM.
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H89 Lower 8K address map
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HDOS Mode CP/M Mode
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------------------- 0x2000 (8k) ----------------
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| Floppy ROM | | |
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------------------- 0x1800 (6k) | |
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| Floppy RAM | | |
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------------------- 0x1400 (5k) | RAM |
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| Open | | |
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------------------- 0x1000 (4k) | |
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| MTR-90 ROM | | |
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-................-- 0x0800 (2k) | |
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| MTR(88/89) ROM | | |
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------------------- 0x0000 (0k) ----------------
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16K RAM Example
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HDOS CP/M
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------------- 24k
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| RAM | ------+
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------------- 16k | ------------- 16k
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| RAM | -------------> | RAM |
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------------- 8k | ------------- 8k
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| ROM | +------> | RAM |
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------------- 0k ------------- 0k
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*/
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void h89_state::h89_mem(address_map &map)
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{
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map.unmap_value_high();
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// Bank 0 - At startup has the format defined below, but software could swap it for RAM (Later H-89s and
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// Early ones with the Org-0 modification),
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// TODO - define the RAM so it can swap in/out under program control.
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map(0x0000, 0x0fff).rom(); // Page 0-4 - System ROM (at most 4k(MTR-90), early versions(MTR-88, MTR-89) only had 2k)
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map(0x1000, 0x13ff).ram(); // Page 5 - Floppy Disk RAM (Write-protectable)
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map(0x1400, 0x1fff).rom(); // Page 6-7 - Floppy Disk ROM
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// Banks 1-7
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map(0x2000, 0xffff).ram();
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map(0x0000, 0xffff).view(m_mem_view);
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// View 0 - ROM / Floppy RAM R/O
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// View 1 - ROM / Floppy RAM R/W
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// monitor ROM
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m_mem_view[0](0x0000, 0x0fff).rom().region("maincpu", 0).unmapw();
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m_mem_view[1](0x0000, 0x0fff).rom().region("maincpu", 0).unmapw();
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// Floppy RAM
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m_mem_view[0](0x1400, 0x17ff).readonly().share(m_floppy_ram);
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m_mem_view[1](0x1400, 0x17ff).ram().share(m_floppy_ram);
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// Floppy ROM
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m_mem_view[0](0x1800, 0x1fff).rom().region("maincpu", 0x1800).unmapw();
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m_mem_view[1](0x1800, 0x1fff).rom().region("maincpu", 0x1800).unmapw();
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}
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/* PORT
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Use | Hex | Octal
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--------------------------+-------+---------
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Not specified, available | 0-77 | 0-167
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Cassette I/O (if used) | 78-79 | 170-171
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Disk I/O #1 | 78-7B | 170-173
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Disk I/O #2 | 7C-7F | 174-177
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Not specified, reserved | 80-CF | 200-317
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DCE Serial I/O | D0-D7 | 320-327
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DTE Serial I/O | D8-DF | 330-337
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DCE Serial I/O | EO-E7 | 340-347
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Console I/O | E8-EF | 350-357
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NMI | F0-F1 | 360-361
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General purpose port | F2 | 362
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NMI | FA-FB | 372-373
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*/
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void h89_state::h89_io(address_map &map)
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{
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map.unmap_value_high();
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map.global_mask(0xff);
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// map(0x78, 0x7b) expansion 1 // Options - Cassette I/O (only uses 0x78 - 0x79) Requires MTR-88 ROM
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// - H37 5-1/4" Soft-sectored Controller MTR-90 ROM
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// - H47 Dual 8" Drives - Requires MTR-89 or MTR-90 ROM
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// - H67 8" Hard disk + 8" Floppy Drives - MTR-90 ROM
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// map(0x7c, 0x7f) expansion 2 // Options - 5-1/4" Hard-sectored Controller (works with ALL ROMs)
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// - H47 Dual 8" Drives - Requires MTR-89 or MTR-90 ROM
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// - H67 8" Hard disk + 8" Floppy Drives - MTR-90 ROM
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// map(0xd0, 0xd7) 8250 UART DCE
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// map(0xd8, 0xdf) 8250 UART DTE - MODEM
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// map(0xe0, 0xe7) 8250 UART DCE - LP
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map(0xe8, 0xef).rw(m_console, FUNC(ins8250_device::ins8250_r), FUNC(ins8250_device::ins8250_w)); // 8250 UART console - this
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// connects internally to a Terminal board
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// that is also used in the H19.
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// map(0xf0, 0xf1) // ports defined on the H8 - on the H89, access to these addresses causes a NMI
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// Disk I/O #1 - 0170-0173 (0x78-0x7b)
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// Options
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// - Cassette I/O (only uses 0x78 - 0x79) - Requires MTR-88 ROM
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// - H37 5-1/4" Soft-sectored Controller - Requires MTR-90 ROM
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// - H47 Dual 8" Drives - Requires MTR-89 or MTR-90 ROM
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// - H67 8" Hard disk + 8" Floppy Drives - Requires MTR-90 ROM
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// map(0x78, 0x7b)
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// Disk I/O #2 - 0174-0177 (0x7c-0x7f)
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// Options
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// - 5-1/4" Hard-sectored Controller - supported by all ROMs
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// - H47 Dual 8" Drives - Requires MTR-89 or MTR-90 ROM
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// - H67 8" Hard disk + 8" Floppy Drives - MTR-90 ROM
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// map(0x7c, 0x7f)
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// 8250 UART DCE 0320 (0xd0)
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map(0xd0, 0xd7).rw(m_serial1, FUNC(ins8250_device::ins8250_r), FUNC(ins8250_device::ins8250_w));
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// 8250 UART DTE 0330 (0xd8) - typically used for modem
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map(0xd8, 0xdf).rw(m_serial2, FUNC(ins8250_device::ins8250_r), FUNC(ins8250_device::ins8250_w));
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// 8250 UART DCE 0340 (0xe0) - typically used for printer
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map(0xe0, 0xe7).rw(m_serial3, FUNC(ins8250_device::ins8250_r), FUNC(ins8250_device::ins8250_w));
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// 8250 UART console - this connects internally to the Terminal Logic board that is also used in the H19.
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map(0xe8, 0xef).rw(m_console, FUNC(ins8250_device::ins8250_r), FUNC(ins8250_device::ins8250_w));
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// ports defined on the H8. On the H89, access to these addresses causes a NMI
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map(0xf0, 0xf1).rw(FUNC(h89_state::raise_NMI_r),FUNC(h89_state::raise_NMI_w));
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// General Purpose Port (GPP)
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map(0xf2, 0xf2).w(FUNC(h89_state::port_f2_w)).portr("SW501");
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// map(0xf3, 0xf3) // ports defined on the H8 - on the H89, access to these addresses causes a NMI
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// port defined on the H8. On the H89, access to these addresses causes a NMI
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map(0xfa, 0xfb).rw(FUNC(h89_state::raise_NMI_r), FUNC(h89_state::raise_NMI_w));
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}
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/* Input ports */
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// Input ports
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static INPUT_PORTS_START( h89 )
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// Settings with the MTR-88 ROM (#444-40)
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// Settings with the MTR-88 ROM (#444-40)
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// PORT_START("SW501")
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// PORT_DIPNAME( 0x1f, 0x00, "Unused" ) PORT_DIPLOCATION("S1:1,S1:2,S1:3,S1:4,S1:5")
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// PORT_DIPNAME( 0x1f, 0x00, "Unused" ) PORT_DIPLOCATION("S1:1,2,3,4,5")
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// PORT_DIPNAME( 0x20, 0x20, "Perform memory test at start" ) PORT_DIPLOCATION("S1:6")
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// PORT_DIPSETTING( 0x20, DEF_STR( Off ) )
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// PORT_DIPSETTING( 0x00, DEF_STR( On ) )
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@ -111,21 +249,21 @@ static INPUT_PORTS_START( h89 )
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// PORT_DIPSETTING( 0x80, "38400" )
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// PORT_DIPSETTING( 0xc0, "57600" )
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// Settings with the MTR-89 ROM (#444-62)
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// Settings with the MTR-89 ROM (#444-62)
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// PORT_START("SW501")
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// PORT_DIPNAME( 0x03, 0x00, "Expansion 1" ) PORT_DIPLOCATION("S1:1,S1:2")
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// PORT_DIPNAME( 0x03, 0x00, "Disk I/O #2" ) PORT_DIPLOCATION("S1:1,2")
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// PORT_DIPSETTING( 0x00, "H-88-1" )
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// PORT_DIPSETTING( 0x01, "H/Z-47" )
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// PORT_DIPSETTING( 0x02, "Undefined" )
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// PORT_DIPSETTING( 0x03, "Undefined" )
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// PORT_DIPNAME( 0x0c, 0x00, "Expansion 2" ) PORT_DIPLOCATION("S1:3,S1:4")
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// PORT_DIPNAME( 0x0c, 0x00, "Disk I/O #1" ) PORT_DIPLOCATION("S1:3,4")
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// PORT_DIPSETTING( 0x00, "Unused" )
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// PORT_DIPSETTING( 0x04, "H/Z-47" )
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// PORT_DIPSETTING( 0x08, "Undefined" )
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// PORT_DIPSETTING( 0x0c, "Undefined" )
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// PORT_DIPNAME( 0x10, 0x00, "Boot from" ) PORT_DIPLOCATION("S1:5")
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// PORT_DIPSETTING( 0x00, "Expansion 1" )
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// PORT_DIPSETTING( 0x10, "Expansion 2" )
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// PORT_DIPNAME( 0x10, 0x00, "Primary Boot from" ) PORT_DIPLOCATION("S1:5")
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// PORT_DIPSETTING( 0x00, "Disk I/O #2" )
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// PORT_DIPSETTING( 0x10, "Disk I/O #1" )
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// PORT_DIPNAME( 0x20, 0x20, "Perform memory test at start" ) PORT_DIPLOCATION("S1:6")
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// PORT_DIPSETTING( 0x20, DEF_STR( Off ) )
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// PORT_DIPSETTING( 0x00, DEF_STR( On ) )
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@ -138,19 +276,19 @@ static INPUT_PORTS_START( h89 )
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// Settings with the MTR-90 ROM (#444-84 or 444-142)
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PORT_START("SW501")
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PORT_DIPNAME( 0x03, 0x00, "Expansion 1" ) PORT_DIPLOCATION("S1:1,S1:2")
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PORT_DIPSETTING( 0x00, "H-88-1" )
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PORT_DIPSETTING( 0x01, "H/Z-47" )
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PORT_DIPSETTING( 0x02, "Z-67" )
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PORT_DIPNAME( 0x03, 0x00, "Disk I/O #2" ) PORT_DIPLOCATION("S1:1,2")
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PORT_DIPSETTING( 0x00, "H-88-1 (Not yet implemented)" )
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PORT_DIPSETTING( 0x01, "H/Z-47 (Not yet implemented)" )
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PORT_DIPSETTING( 0x02, "Z-67 (Not yet implemented)" )
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PORT_DIPSETTING( 0x03, "Undefined" )
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PORT_DIPNAME( 0x0c, 0x00, "Expansion 2" ) PORT_DIPLOCATION("S1:3,S1:4")
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PORT_DIPSETTING( 0x00, "H-89-37" )
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PORT_DIPSETTING( 0x04, "H/Z-47" )
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PORT_DIPSETTING( 0x08, "Z-67" )
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PORT_DIPNAME( 0x0c, 0x00, "Disk I/O #1" ) PORT_DIPLOCATION("S1:3,4")
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PORT_DIPSETTING( 0x00, "H-89-37 (Not yet implemented)" )
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PORT_DIPSETTING( 0x04, "H/Z-47 (Not yet implemented)" )
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PORT_DIPSETTING( 0x08, "Z-67 (Not yet implemented)" )
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PORT_DIPSETTING( 0x0c, "Undefined" )
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PORT_DIPNAME( 0x10, 0x00, "Boot from" ) PORT_DIPLOCATION("S1:5")
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PORT_DIPSETTING( 0x00, "Expansion 1" )
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PORT_DIPSETTING( 0x10, "Expansion 2" )
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PORT_DIPNAME( 0x10, 0x00, "Primary Boot from" ) PORT_DIPLOCATION("S1:5")
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PORT_DIPSETTING( 0x00, "Disk I/O #2" )
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PORT_DIPSETTING( 0x10, "Disk I/O #1" )
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PORT_DIPNAME( 0x20, 0x20, "Perform memory test at start" ) PORT_DIPLOCATION("S1:6")
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PORT_DIPSETTING( 0x20, DEF_STR( Off ) )
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PORT_DIPSETTING( 0x00, DEF_STR( On ) )
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@ -163,23 +301,102 @@ static INPUT_PORTS_START( h89 )
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INPUT_PORTS_END
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void h89_state::machine_start()
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{
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save_item(NAME(m_gpp));
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save_item(NAME(m_rom_enabled));
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save_item(NAME(m_timer_intr_enabled));
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save_item(NAME(m_floppy_ram_wp));
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// update RAM mappings based on RAM size
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u8 *m_ram_ptr = m_ram->pointer();
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u32 ram_size = m_ram->size();
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if (ram_size == 0x10000)
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{
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// system has a full 64k
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m_maincpu->space(AS_PROGRAM).install_ram(0x2000, 0xffff, m_ram_ptr);
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// TODO: install shadow writing to RAM when in ROM mode
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// Only the CP/M - Org 0 view will have RAM at the lower 8k
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m_mem_view[2].install_ram(0x0000, 0x1fff, m_ram_ptr + 0xe000);
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}
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else
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{
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// less than 64k
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// for views with ROM visible, the top of memory is 8k higher than
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// the memory size, since the base starts at 8k.
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u32 ram_top = ram_size + 0x1fff;
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m_mem_view[0].install_ram(0x2000, ram_top, m_ram_ptr);
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m_mem_view[1].install_ram(0x2000, ram_top, m_ram_ptr);
|
||||
|
||||
// when ROM is not active, memory still starts at 8k, but is 8k smaller
|
||||
m_mem_view[2].install_ram(0x2000, ram_size - 1, m_ram_ptr);
|
||||
|
||||
// remap the top 8k down to addr 0
|
||||
m_mem_view[2].install_ram(0x0000, 0x1fff, m_ram_ptr + ram_size - 0x2000);
|
||||
}
|
||||
|
||||
update_gpp(0);
|
||||
}
|
||||
|
||||
|
||||
void h89_state::machine_reset()
|
||||
{
|
||||
update_gpp(0);
|
||||
}
|
||||
|
||||
|
||||
uint8_t h89_state::raise_NMI_r()
|
||||
{
|
||||
m_maincpu->pulse_input_line(INPUT_LINE_NMI, attotime::from_usec(2));
|
||||
|
||||
return 0x00;
|
||||
}
|
||||
|
||||
void h89_state::raise_NMI_w(uint8_t)
|
||||
{
|
||||
m_maincpu->pulse_input_line(INPUT_LINE_NMI, attotime::from_usec(2));
|
||||
}
|
||||
|
||||
TIMER_DEVICE_CALLBACK_MEMBER(h89_state::h89_irq_timer)
|
||||
{
|
||||
if (m_port_f2 & 0x02)
|
||||
if (m_timer_intr_enabled)
|
||||
{
|
||||
m_maincpu->set_input_line_and_vector(0, HOLD_LINE, 0xcf); // Z80
|
||||
m_maincpu->set_input_line_and_vector(0, HOLD_LINE, 0xcf);
|
||||
}
|
||||
}
|
||||
|
||||
void h89_state::update_mem_view()
|
||||
{
|
||||
if (m_rom_enabled)
|
||||
{
|
||||
m_mem_view.select(m_floppy_ram_wp ? 0 : 1);
|
||||
}
|
||||
else
|
||||
{
|
||||
m_mem_view.select(2);
|
||||
}
|
||||
}
|
||||
|
||||
void h89_state::update_gpp(uint8_t gpp)
|
||||
{
|
||||
m_gpp = gpp;
|
||||
|
||||
m_rom_enabled = BIT(m_gpp, GPP_DISABLE_ROM_BIT) == 0;
|
||||
|
||||
update_mem_view();
|
||||
|
||||
m_timer_intr_enabled = BIT(m_gpp, GPP_ENABLE_TIMER_INTERRUPT_BIT) == 1;
|
||||
}
|
||||
|
||||
// General Purpose Port
|
||||
void h89_state::port_f2_w(uint8_t data)
|
||||
{
|
||||
// Bit 0 - Single-step
|
||||
// Bit 1 - Enable timer interrupt (2mSec Clock)
|
||||
m_port_f2 = data;
|
||||
update_gpp(data);
|
||||
}
|
||||
|
||||
void h89_state::h89(machine_config & config)
|
||||
@ -189,6 +406,8 @@ void h89_state::h89(machine_config & config)
|
||||
m_maincpu->set_addrmap(AS_PROGRAM, &h89_state::h89_mem);
|
||||
m_maincpu->set_addrmap(AS_IO, &h89_state::h89_io);
|
||||
|
||||
RAM(config, m_ram).set_default_size("64K").set_extra_options("16K,32K,48K").set_default_value(0x00);
|
||||
|
||||
INS8250(config, m_console, INS8250_CLOCK);
|
||||
HEATH_TLB(config, m_tlb);
|
||||
|
||||
@ -196,25 +415,42 @@ void h89_state::h89(machine_config & config)
|
||||
m_console->out_tx_callback().set(m_tlb, FUNC(heath_tlb_device::cb1_w));
|
||||
m_tlb->serial_data_callback().set(m_console, FUNC(ins8250_uart_device::rx_w));
|
||||
|
||||
// H-88-3 3-port serial board
|
||||
INS8250(config, m_serial1, INS8250_CLOCK);
|
||||
INS8250(config, m_serial2, INS8250_CLOCK);
|
||||
INS8250(config, m_serial3, INS8250_CLOCK);
|
||||
|
||||
// H89 interrupt interval is 2mSec
|
||||
TIMER(config, "irq_timer", 0).configure_periodic(FUNC(h89_state::h89_irq_timer), attotime::from_msec(2));
|
||||
}
|
||||
|
||||
/* ROM definition */
|
||||
// ROM definition
|
||||
ROM_START( h89 )
|
||||
ROM_REGION( 0x10000, "maincpu", ROMREGION_ERASEFF )
|
||||
ROM_LOAD( "2732_444-142_mtr90.rom", 0x0000, 0x1000, CRC(c4ff47c5) SHA1(d6f3d71ff270a663003ec18a3ed1fa49f627123a))
|
||||
ROM_REGION( 0x2000, "maincpu", ROMREGION_ERASEFF )
|
||||
ROM_DEFAULT_BIOS("mtr90")
|
||||
|
||||
ROM_LOAD( "2716_444-19_h17.rom", 0x1800, 0x0800, CRC(26e80ae3) SHA1(0c0ee95d7cb1a760f924769e10c0db1678f2435c))
|
||||
|
||||
ROM_REGION( 0x10000, "otherroms", ROMREGION_ERASEFF )
|
||||
ROM_LOAD( "2732_444-84_mtr84.rom", 0x0000, 0x1000, CRC(c98e5f4c) SHA1(03347206dca145ff69ca08435db822b70ce106af))
|
||||
ROM_LOAD( "2732_mms84a_magnoliamms.bin", 0x0000, 0x1000, CRC(5563f42a) SHA1(1b74cafca8213d5c083f16d8a848933ab56eb43b))
|
||||
ROM_SYSTEM_BIOS(0, "mtr90", "MTR-90 (444-142)")
|
||||
ROMX_LOAD("2732_444-142_mtr90.rom", 0x0000, 0x1000, CRC(c4ff47c5) SHA1(d6f3d71ff270a663003ec18a3ed1fa49f627123a), ROM_BIOS(0))
|
||||
|
||||
ROM_SYSTEM_BIOS(1, "mtr88", "MTR-88 (444-40)")
|
||||
ROMX_LOAD("2716_444-40_mtr88.bin", 0x0000, 0x0800, CRC(093afb79) SHA1(bcc1569ad9da7babf0a4199cab96d8cd59b2dd78), ROM_BIOS(1))
|
||||
|
||||
ROM_SYSTEM_BIOS(2, "mtr89", "MTR-89 (444-62)")
|
||||
ROMX_LOAD("2716_444-62_mtr89.bin", 0x0000, 0x0800, CRC(8f507972) SHA1(ac6c6c1344ee4e09fb60d53c85c9b761217fe9dc), ROM_BIOS(2))
|
||||
|
||||
ROM_SYSTEM_BIOS(3, "mms84a", "MMS 84a (not working)")
|
||||
ROMX_LOAD("2732_mms84a_magnoliamms.bin", 0x0000, 0x1000, CRC(5563f42a) SHA1(1b74cafca8213d5c083f16d8a848933ab56eb43b), ROM_BIOS(3))
|
||||
|
||||
ROM_SYSTEM_BIOS(4, "mtr90a", "MTR-90 (444-84 - not working)")
|
||||
ROMX_LOAD("2732_444-84_mtr84.rom", 0x0000, 0x1000, CRC(c98e5f4c) SHA1(03347206dca145ff69ca08435db822b70ce106af), ROM_BIOS(4))
|
||||
ROM_END
|
||||
|
||||
} // anonymous namespace
|
||||
|
||||
|
||||
/* Driver */
|
||||
// Driver
|
||||
|
||||
/* YEAR NAME PARENT COMPAT MACHINE INPUT CLASS INIT COMPANY FULLNAME FLAGS */
|
||||
// YEAR NAME PARENT COMPAT MACHINE INPUT CLASS INIT COMPANY FULLNAME FLAGS
|
||||
COMP( 1979, h89, 0, 0, h89, h89, h89_state, empty_init, "Heath Company", "Heathkit H89", MACHINE_NOT_WORKING)
|
||||
|
||||
Loading…
Reference in New Issue
Block a user